dts: renesas_ra: Referencing clocks change to DeviceTree's standard.
DeviceTree typically references the clock source using the `clocks`
property defined in `base.yaml`, so we'll change it to this.
Also delete the custom clock source definitions in
`renesas,ra-cgc-pclk-block.yaml`, `renesas,ra-cgc-pclk.yaml`, and
`renesas,ra-cgc-pll.yaml`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.dts b/boards/renesas/ek_ra4e2/ek_ra4e2.dts
index e371198..2bf7a9d 100644
--- a/boards/renesas/ek_ra4e2/ek_ra4e2.dts
+++ b/boards/renesas/ek_ra4e2/ek_ra4e2.dts
@@ -53,7 +53,7 @@
};
&pll {
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
mul = <10 0>;
status = "okay";
diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.dts b/boards/renesas/ek_ra4m2/ek_ra4m2.dts
index 49f35db..9cb8d8b 100644
--- a/boards/renesas/ek_ra4m2/ek_ra4m2.dts
+++ b/boards/renesas/ek_ra4m2/ek_ra4m2.dts
@@ -53,7 +53,7 @@
};
&pll {
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
mul = <25 0>;
status = "okay";
diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.dts b/boards/renesas/ek_ra4m3/ek_ra4m3.dts
index f076510..09701ac 100644
--- a/boards/renesas/ek_ra4m3/ek_ra4m3.dts
+++ b/boards/renesas/ek_ra4m3/ek_ra4m3.dts
@@ -53,7 +53,7 @@
};
&pll {
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
mul = <25 0>;
status = "okay";
diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.dts b/boards/renesas/ek_ra6e2/ek_ra6e2.dts
index 682aafc..29571eb 100644
--- a/boards/renesas/ek_ra6e2/ek_ra6e2.dts
+++ b/boards/renesas/ek_ra6e2/ek_ra6e2.dts
@@ -94,7 +94,7 @@
};
&pll {
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
mul = <10 0>;
status = "okay";
diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.dts b/boards/renesas/ek_ra6m1/ek_ra6m1.dts
index f82d065..631f2d1 100644
--- a/boards/renesas/ek_ra6m1/ek_ra6m1.dts
+++ b/boards/renesas/ek_ra6m1/ek_ra6m1.dts
@@ -60,7 +60,7 @@
};
&pll {
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
mul = <20 0>;
status = "okay";
diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.dts b/boards/renesas/ek_ra6m2/ek_ra6m2.dts
index 7840735..19721a4 100644
--- a/boards/renesas/ek_ra6m2/ek_ra6m2.dts
+++ b/boards/renesas/ek_ra6m2/ek_ra6m2.dts
@@ -60,7 +60,7 @@
};
&pll {
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
mul = <20 0>;
status = "okay";
diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.dts b/boards/renesas/ek_ra6m3/ek_ra6m3.dts
index 0cd4de2..db90313 100644
--- a/boards/renesas/ek_ra6m3/ek_ra6m3.dts
+++ b/boards/renesas/ek_ra6m3/ek_ra6m3.dts
@@ -72,7 +72,7 @@
};
&pll {
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
mul = <20 0>;
status = "okay";
diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts
index f0f447e..b156f6f 100644
--- a/boards/renesas/ek_ra6m4/ek_ra6m4.dts
+++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts
@@ -68,14 +68,14 @@
};
&pll {
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
mul = <25 0>;
status = "okay";
};
&pclka {
- clk-src = <RA_CLOCK_SOURCE_PLL>;
+ clocks = <&pll>;
clk-div = <RA_SYS_CLOCK_DIV_2>;
status = "okay";
};
diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.dts b/boards/renesas/ek_ra6m5/ek_ra6m5.dts
index ad84e26..902e281 100644
--- a/boards/renesas/ek_ra6m5/ek_ra6m5.dts
+++ b/boards/renesas/ek_ra6m5/ek_ra6m5.dts
@@ -68,7 +68,7 @@
};
&pll {
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
mul = <25 0>;
status = "okay";
diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts
index 698e90e..e17bf02 100644
--- a/boards/renesas/ek_ra8d1/ek_ra8d1.dts
+++ b/boards/renesas/ek_ra8d1/ek_ra8d1.dts
@@ -56,7 +56,7 @@
};
&pll {
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
@@ -69,7 +69,7 @@
};
&sciclk {
- clk-src = <RA_CLOCK_SOURCE_PLL1P>;
+ clocks = <&pll>;
clk-div = <RA_SCI_CLOCK_DIV_4>;
status = "okay";
};
diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.dts b/boards/renesas/ek_ra8m1/ek_ra8m1.dts
index de64b9e..df94f20 100644
--- a/boards/renesas/ek_ra8m1/ek_ra8m1.dts
+++ b/boards/renesas/ek_ra8m1/ek_ra8m1.dts
@@ -79,7 +79,7 @@
};
&pll {
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
@@ -92,7 +92,7 @@
};
&sciclk {
- clk-src = <RA_CLOCK_SOURCE_PLL1P>;
+ clocks = <&pll>;
clk-div = <RA_SCI_CLOCK_DIV_4>;
status = "okay";
};
diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts
index 6f73498..b0aa5b4 100644
--- a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts
+++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts
@@ -57,7 +57,7 @@
};
&pll {
- source = <RA_PLL_SOURCE_HOCO>;
+ clocks = <&hoco>;
div = <RA_PLL_DIV_2>;
mul = <20 0>;
status = "okay";
diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts
index bc7baa6..847f552 100644
--- a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts
+++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts
@@ -76,7 +76,7 @@
};
&pll {
- source = <RA_PLL_SOURCE_HOCO>;
+ clocks = <&hoco>;
div = <RA_PLL_DIV_1>;
mul = <10 0>;
status = "okay";
diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts
index f7046d4..ea06022 100644
--- a/boards/renesas/mck_ra8t1/mck_ra8t1.dts
+++ b/boards/renesas/mck_ra8t1/mck_ra8t1.dts
@@ -60,7 +60,7 @@
};
&pll {
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
mul = <80 0>;
divp = <RA_PLL_DIV_2>;
@@ -73,7 +73,7 @@
};
&sciclk {
- clk-src = <RA_CLOCK_SOURCE_PLL1P>;
+ clocks = <&pll>;
clk-div = <RA_SCI_CLOCK_DIV_4>;
status = "okay";
};
diff --git a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi
index 9139417..bb23016 100644
--- a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi
+++ b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi
@@ -64,7 +64,7 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD";
#clock-cells = <0>;
- sysclock-src = <RA_CLOCK_SOURCE_HOCO>;
+ clocks = <&hoco>;
status = "okay";
iclk: iclk {
diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi
index df7ee81..6feb69d 100644
--- a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi
+++ b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi
@@ -83,7 +83,7 @@
#clock-cells = <0>;
/* PLL */
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
mul = <10 0>;
status = "disabled";
@@ -96,7 +96,7 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD", "MSTPE";
#clock-cells = <0>;
- sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ clocks = <&pll>;
status = "okay";
iclk: iclk {
diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi
index 333d70d..7ed9fda 100644
--- a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi
+++ b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi
@@ -132,7 +132,7 @@
#clock-cells = <0>;
/* PLL */
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
mul = <25 0>;
status = "disabled";
@@ -143,7 +143,6 @@
#clock-cells = <0>;
/* PLL */
- source = <RA_PLL_SOURCE_DISABLE>;
div = <RA_PLL_DIV_2>;
mul = <20 0>;
status = "disabled";
@@ -156,7 +155,7 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD", "MSTPE";
#clock-cells = <0>;
- sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ clocks = <&pll>;
status = "okay";
iclk: iclk {
diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi
index 5bb6a46..1277844 100644
--- a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi
+++ b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi
@@ -142,7 +142,7 @@
#clock-cells = <0>;
/* PLL */
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
mul = <25 0>;
status = "disabled";
@@ -151,7 +151,6 @@
pll2: pll2 {
compatible = "renesas,ra-cgc-pll";
#clock-cells = <0>;
- source = <RA_PLL_SOURCE_DISABLE>;
div = <RA_PLL_DIV_2>;
mul = <20 0>;
status = "disabled";
@@ -164,7 +163,7 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD", "MSTPE";
#clock-cells = <0>;
- sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ clocks = <&pll>;
status = "okay";
iclk: iclk {
diff --git a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi
index a6cd0df..93ea675 100644
--- a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi
+++ b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi
@@ -77,7 +77,7 @@
#clock-cells = <0>;
/* PLL */
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
mul = <12 0>;
status = "disabled";
@@ -90,7 +90,7 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD";
#clock-cells = <0>;
- sysclock-src = <RA_CLOCK_SOURCE_HOCO>;
+ clocks = <&hoco>;
status = "okay";
iclk: iclk {
diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi
index 9e3dfe7..b070022 100644
--- a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi
+++ b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi
@@ -132,7 +132,7 @@
#clock-cells = <0>;
/* PLL */
- source = <RA_PLL_SOURCE_HOCO>;
+ clocks = <&hoco>;
div = <RA_PLL_DIV_2>;
mul = <20 0>;
status = "disabled";
@@ -143,7 +143,6 @@
#clock-cells = <0>;
/* PLL2 */
- source = <RA_PLL_SOURCE_DISABLE>;
div = <RA_PLL_DIV_2>;
mul = <20 0>;
status = "disabled";
@@ -156,7 +155,7 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD", "MSTPE";
#clock-cells = <0>;
- sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ clocks = <&pll>;
status = "okay";
iclk: iclk {
diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi
index 963ba9a..7576bb0 100644
--- a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi
+++ b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi
@@ -73,7 +73,7 @@
#clock-cells = <0>;
/* PLL */
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
mul = <10 0>;
status = "disabled";
@@ -86,7 +86,7 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD", "MSTPE";
#clock-cells = <0>;
- sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ clocks = <&pll>;
status = "okay";
iclk: iclk {
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi
index cb849f0..af17716 100644
--- a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi
+++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi
@@ -67,7 +67,7 @@
#clock-cells = <0>;
/* PLL */
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
mul = <20 0>;
status = "disabled";
@@ -80,7 +80,7 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD";
#clock-cells = <0>;
- sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ clocks = <&pll>;
status = "okay";
iclk: iclk {
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi
index ab689fd..a06241a 100644
--- a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi
+++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi
@@ -98,7 +98,7 @@
#clock-cells = <0>;
/* PLL */
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_1>;
mul = <20 0>;
status = "disabled";
@@ -111,7 +111,7 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD";
#clock-cells = <0>;
- sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ clocks = <&pll>;
status = "okay";
iclk: iclk {
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi
index 0870f6d..197be43 100644
--- a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi
+++ b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi
@@ -138,7 +138,7 @@
#clock-cells = <0>;
/* PLL */
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
mul = <20 0>;
status = "disabled";
@@ -151,7 +151,7 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD";
#clock-cells = <0>;
- sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ clocks = <&pll>;
status = "okay";
iclk: iclk {
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi
index 8f39ca6..0310f61 100644
--- a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi
+++ b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi
@@ -168,7 +168,7 @@
#clock-cells = <0>;
/* PLL */
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
mul = <25 0>;
status = "disabled";
@@ -179,7 +179,6 @@
#clock-cells = <0>;
/* PLL2 */
- source = <RA_PLL_SOURCE_DISABLE>;
div = <RA_PLL_DIV_2>;
mul = <20 0>;
status = "disabled";
@@ -192,7 +191,7 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD", "MSTPE";
#clock-cells = <0>;
- sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ clocks = <&pll>;
status = "okay";
iclk: iclk {
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi
index 12a95ce..91d95e2 100644
--- a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi
+++ b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi
@@ -228,7 +228,7 @@
#clock-cells = <0>;
/* PLL */
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_3>;
mul = <25 0>;
status = "disabled";
@@ -239,7 +239,6 @@
#clock-cells = <0>;
/* PLL2 */
- source = <RA_PLL_SOURCE_DISABLE>;
div = <RA_PLL_DIV_2>;
mul = <20 0>;
status = "disabled";
@@ -252,7 +251,7 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD", "MSTPE";
#clock-cells = <0>;
- sysclock-src = <RA_CLOCK_SOURCE_PLL>;
+ clocks = <&pll>;
status = "okay";
iclk: iclk {
diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi
index 2bd14bd..5b00642 100644
--- a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi
+++ b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi
@@ -49,7 +49,7 @@
#clock-cells = <0>;
/* PLL */
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
@@ -66,7 +66,6 @@
#clock-cells = <0>;
/* PLL2 */
- source = <RA_PLL_SOURCE_DISABLE>;
div = <RA_PLL_DIV_2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
@@ -85,7 +84,7 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD", "MSTPE";
#clock-cells = <0>;
- sysclock-src = <RA_CLOCK_SOURCE_PLL1P>;
+ clocks = <&pll>;
status = "okay";
cpuclk: cpuclk {
diff --git a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi
index 164928c..c184c14 100644
--- a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi
+++ b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi
@@ -49,7 +49,7 @@
#clock-cells = <0>;
/* PLL */
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
@@ -66,7 +66,6 @@
#clock-cells = <0>;
/* PLL2 */
- source = <RA_PLL_SOURCE_DISABLE>;
div = <RA_PLL_DIV_2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
@@ -85,7 +84,7 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD", "MSTPE";
#clock-cells = <0>;
- sysclock-src = <RA_CLOCK_SOURCE_PLL1P>;
+ clocks = <&pll>;
status = "okay";
cpuclk: cpuclk {
diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi
index 621239f..3f4fb71 100644
--- a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi
+++ b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi
@@ -49,7 +49,7 @@
#clock-cells = <0>;
/* PLL */
- source = <RA_PLL_SOURCE_MAIN_OSC>;
+ clocks = <&xtal>;
div = <RA_PLL_DIV_2>;
mul = <80 0>;
divp = <RA_PLL_DIV_2>;
@@ -66,7 +66,6 @@
#clock-cells = <0>;
/* PLL2 */
- source = <RA_PLL_SOURCE_DISABLE>;
div = <RA_PLL_DIV_2>;
mul = <96 0>;
divp = <RA_PLL_DIV_2>;
@@ -85,7 +84,7 @@
reg-names = "MSTPA", "MSTPB","MSTPC",
"MSTPD", "MSTPE";
#clock-cells = <0>;
- sysclock-src = <RA_CLOCK_SOURCE_PLL1P>;
+ clocks = <&pll>;
status = "okay";
cpuclk: cpuclk {
diff --git a/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml
index 6380b71..d455a1e 100644
--- a/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml
+++ b/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml
@@ -8,6 +8,5 @@
include: [clock-controller.yaml, base.yaml]
properties:
- sysclock-src:
+ clocks:
required: true
- type: int
diff --git a/dts/bindings/clock/renesas,ra-cgc-pclk.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml
index 5ea4d70..1aac515 100644
--- a/dts/bindings/clock/renesas,ra-cgc-pclk.yaml
+++ b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml
@@ -8,9 +8,6 @@
include: [clock-controller.yaml, base.yaml]
properties:
- clk-src:
- type: int
-
clk-div:
type: int
required: true
diff --git a/dts/bindings/clock/renesas,ra-cgc-pll.yaml b/dts/bindings/clock/renesas,ra-cgc-pll.yaml
index a974f54c..7c959b6 100644
--- a/dts/bindings/clock/renesas,ra-cgc-pll.yaml
+++ b/dts/bindings/clock/renesas,ra-cgc-pll.yaml
@@ -8,9 +8,8 @@
include: [clock-controller.yaml, base.yaml]
properties:
- source:
+ clocks:
required: true
- type: int
div:
required: true
type: int
