drivers: flash: nrf_qspi_nor: Add support for pinctrl
Add support for the new pinctrl API to the nRF QSPI NOR flash driver.
Update code of the driver and the related devicetree binding.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
diff --git a/drivers/flash/nrf_qspi_nor.c b/drivers/flash/nrf_qspi_nor.c
index 691360a..47fdbf3 100644
--- a/drivers/flash/nrf_qspi_nor.c
+++ b/drivers/flash/nrf_qspi_nor.c
@@ -10,6 +10,8 @@
#include <drivers/flash.h>
#include <init.h>
#include <pm/device.h>
+#include <drivers/pinctrl.h>
+#include <soc.h>
#include <string.h>
#include <logging/log.h>
LOG_MODULE_REGISTER(qspi_nor, CONFIG_FLASH_LOG_LEVEL);
@@ -51,6 +53,10 @@
/* JEDEC id from devicetree */
uint8_t id[SPI_NOR_MAX_ID_LEN];
+
+#ifdef CONFIG_PINCTRL
+ const struct pinctrl_dev_config *pcfg;
+#endif
};
/* Status register bits */
@@ -383,8 +389,10 @@
}
}
+#ifndef CONFIG_PINCTRL
nrf_gpio_cfg_output(QSPI_PROP_AT(csn_pins, 0));
nrf_gpio_pin_set(QSPI_PROP_AT(csn_pins, 0));
+#endif
nrfx_qspi_uninit();
qspi_initialized = false;
@@ -1070,6 +1078,15 @@
nrf_clock_hfclk192m_div_set(NRF_CLOCK, NRF_CLOCK_HFCLK_DIV_4);
#endif
+#ifdef CONFIG_PINCTRL
+ const struct qspi_nor_config *dev_config = dev->config;
+ int ret = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);
+
+ if (ret < 0) {
+ return ret;
+ }
+#endif
+
IRQ_CONNECT(DT_IRQN(QSPI_NODE), DT_IRQ(QSPI_NODE, priority),
nrfx_isr, nrfx_qspi_irq_handler, 0);
return qspi_nor_configure(dev);
@@ -1204,9 +1221,23 @@
}
nrfx_qspi_uninit();
+#ifdef CONFIG_PINCTRL
+ ret = pinctrl_apply_state(dev_config->pcfg,
+ PINCTRL_STATE_SLEEP);
+ if (ret < 0) {
+ return ret;
+ }
+#endif
break;
case PM_DEVICE_ACTION_RESUME:
+#ifdef CONFIG_PINCTRL
+ ret = pinctrl_apply_state(dev_config->pcfg,
+ PINCTRL_STATE_DEFAULT);
+ if (ret < 0) {
+ return ret;
+ }
+#endif
err = nrfx_qspi_init(&dev_config->nrfx_cfg,
qspi_handler,
dev_data);
@@ -1275,7 +1306,16 @@
#endif /* CONFIG_MULTITHREADING */
};
+NRF_DT_ENSURE_PINS_ASSIGNED(QSPI_NODE, sck_pin);
+
+IF_ENABLED(CONFIG_PINCTRL, (PINCTRL_DT_DEFINE(QSPI_NODE)));
+
static const struct qspi_nor_config qspi_nor_dev_config = {
+#ifdef CONFIG_PINCTRL
+ .nrfx_cfg.skip_gpio_cfg = true,
+ .nrfx_cfg.skip_psel_cfg = true,
+ .pcfg = PINCTRL_DT_DEV_CONFIG_GET(QSPI_NODE),
+#else
.nrfx_cfg.pins = {
.sck_pin = DT_PROP(QSPI_NODE, sck_pin),
.csn_pin = QSPI_PROP_AT(csn_pins, 0),
@@ -1289,6 +1329,7 @@
.io3_pin = NRF_QSPI_PIN_NOT_CONNECTED,
#endif
},
+#endif /* CONFIG_PINCTRL */
.nrfx_cfg.prot_if = {
.readoc = COND_CODE_1(DT_INST_NODE_HAS_PROP(0, readoc),
(_CONCAT(NRF_QSPI_READOC_,
diff --git a/dts/bindings/flash_controller/nordic,nrf-qspi.yaml b/dts/bindings/flash_controller/nordic,nrf-qspi.yaml
index 63b410c..aed890e 100644
--- a/dts/bindings/flash_controller/nordic,nrf-qspi.yaml
+++ b/dts/bindings/flash_controller/nordic,nrf-qspi.yaml
@@ -21,7 +21,7 @@
compatible: "nordic,nrf-qspi"
-include: flash-controller.yaml
+include: [flash-controller.yaml, pinctrl-device.yaml]
bus: qspi
@@ -39,8 +39,11 @@
sck-pin:
type: int
- required: true
+ required: false
description: |
+ IMPORTANT: This option will only be used if the new pin control driver
+ is not enabled. It will be deprecated in the future.
+
The SCK pin to use.
For pins P0.0 through P0.31, use the pin number. For example,
@@ -54,8 +57,11 @@
sck-pin = <34>; /* 32 + 2 */
io-pins:
type: array
- required: true
+ required: false
description: |
+ IMPORTANT: This option will only be used if the new pin control driver
+ is not enabled. It will be deprecated in the future.
+
Pin numbers associated with IO0 through IO3 signals.
Examples:
@@ -69,8 +75,11 @@
sck-pin property's.
csn-pins:
type: array
- required: true
+ required: false
description: |
+ IMPORTANT: This option will only be used if the new pin control driver
+ is not enabled. It will be deprecated in the future.
+
Chip select signal pin number. Exactly one pin should be
given. The pin numbering scheme is the same as the
sck-pin property's.
