soc: telink: tlsr951x: use RISC-V custom CSR common code
TLSR951x also supports Andes extended CSR. Reworks the following CSR
handling to use the RISC-V custom CSR common code:
1. Use common macros for HWDSP CSR context save/restore.
2. Use common macros for PFT CSR context save/restore.
3. Use common low-level CSR initialization via __reset hook.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
diff --git a/boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig b/boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig
index 881ec1f..b7d0f97 100644
--- a/boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig
+++ b/boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig
@@ -8,6 +8,3 @@
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
-
-# HW DSP options
-CONFIG_TELINK_B91_HWDSP=n
diff --git a/dts/riscv/telink/telink_b91.dtsi b/dts/riscv/telink/telink_b91.dtsi
index aa6f166..d572eac 100644
--- a/dts/riscv/telink/telink_b91.dtsi
+++ b/dts/riscv/telink/telink_b91.dtsi
@@ -23,7 +23,7 @@
cpu0: cpu@0 {
reg = <0>;
clock-frequency = <24000000>;
- compatible = "telink,b91", "riscv";
+ compatible = "telink,b91", "andestech,andescore-v5", "riscv";
riscv,isa = "rv32imac_zicsr_zifencei";
hlic: interrupt-controller {
diff --git a/soc/telink/tlsr/tlsr951x/CMakeLists.txt b/soc/telink/tlsr/tlsr951x/CMakeLists.txt
index 9e1dff4..7bca7f3 100644
--- a/soc/telink/tlsr/tlsr951x/CMakeLists.txt
+++ b/soc/telink/tlsr/tlsr951x/CMakeLists.txt
@@ -13,7 +13,7 @@
zephyr_ld_options(-fuse-ld=bfd)
# Set compile options
-zephyr_compile_options_ifdef(CONFIG_TELINK_B91_HWDSP -mext-dsp)
+zephyr_compile_options_ifdef(CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP -mext-dsp)
zephyr_compile_options_ifndef(CONFIG_RISCV_GP -mno-relax)
zephyr_linker_sources(ROM_START SORT_KEY 0x0 init.ld)
diff --git a/soc/telink/tlsr/tlsr951x/Kconfig b/soc/telink/tlsr/tlsr951x/Kconfig
index c538ed7..d7e5bc1 100644
--- a/soc/telink/tlsr/tlsr951x/Kconfig
+++ b/soc/telink/tlsr/tlsr951x/Kconfig
@@ -15,19 +15,23 @@
select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
select HAS_TELINK_DRIVERS
select CPU_HAS_FPU
- select INCLUDE_RESET_VECTOR
+ select CPU_HAS_DCACHE
+ select CPU_HAS_ICACHE
+ select CPU_HAS_ANDES_HWDSP
+ select CPU_HAS_ANDES_PFT
+ select RISCV_SOC_CONTEXT_SAVE if RISCV_CUSTOM_CSR_ANDES_HWDSP
+ select RISCV_SOC_CONTEXT_SAVE if RISCV_CUSTOM_CSR_ANDES_PFT
imply XIP
select SOC_EARLY_INIT_HOOK
if SOC_SERIES_TLSR951X
config TELINK_B91_HWDSP
- bool "Support Hardware DSP"
- select RISCV_SOC_CONTEXT_SAVE
+ bool
+ select DEPRECATED
config TELINK_B91_PFT_ARCH
- bool "Support performance throttling"
- default y
- select RISCV_SOC_CONTEXT_SAVE
+ bool
+ select DEPRECATED
endif # SOC_SERIES_TLSR951X
diff --git a/soc/telink/tlsr/tlsr951x/Kconfig.defconfig b/soc/telink/tlsr/tlsr951x/Kconfig.defconfig
index 777a0ac..1cbe882 100644
--- a/soc/telink/tlsr/tlsr951x/Kconfig.defconfig
+++ b/soc/telink/tlsr/tlsr951x/Kconfig.defconfig
@@ -30,4 +30,8 @@
config HAS_FLASH_LOAD_OFFSET
default y if BOOTLOADER_MCUBOOT
+choice CACHE_TYPE
+ default EXTERNAL_CACHE
+endchoice
+
endif # SOC_SERIES_TLSR951X
diff --git a/soc/telink/tlsr/tlsr951x/soc_context.h b/soc/telink/tlsr/tlsr951x/soc_context.h
index 0f06686..8f2b9dd 100644
--- a/soc/telink/tlsr/tlsr951x/soc_context.h
+++ b/soc/telink/tlsr/tlsr951x/soc_context.h
@@ -7,43 +7,16 @@
#ifndef SOC_RISCV_TELINK_B91_SOC_CONTEXT_H
#define SOC_RISCV_TELINK_B91_SOC_CONTEXT_H
+#include <csr_context.h>
+
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/* Telink B91 specific registers. */
-#if defined(CONFIG_TELINK_B91_PFT_ARCH) && defined(__riscv_dsp)
- #define SOC_ESF_MEMBERS \
- uint32_t mxstatus; \
- uint32_t ucode \
+#define SOC_ESF_MEMBERS \
+ CUSTOM_CSR_ESF_MEMBERS
- #define SOC_ESF_INIT \
- 0xdeadbaad, \
- 0xdeadbaad
-
- #define SOC_ESF_THREAD_INIT(soc_context) \
- (soc_context)->mxstatus = 0; \
- (soc_context)->ucode = 0
-
-#elif defined(CONFIG_TELINK_B91_PFT_ARCH)
- #define SOC_ESF_MEMBERS \
- uint32_t mxstatus
-
- #define SOC_ESF_INIT \
- 0xdeadbaad
-
- #define SOC_ESF_THREAD_INIT(soc_context) \
- (soc_context)->mxstatus = 0
-
-#elif defined(__riscv_dsp)
-
- #define SOC_ESF_MEMBERS \
- uint32_t ucode
-
- #define SOC_ESF_INIT \
- 0xdeadbaad
-
- #define SOC_ESF_THREAD_INIT(soc_context) \
- (soc_context)->ucode = 0
-#endif
+#define SOC_ESF_INIT \
+ CUSTOM_CSR_ESF_INIT
#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
diff --git a/soc/telink/tlsr/tlsr951x/soc_irq.S b/soc/telink/tlsr/tlsr951x/soc_irq.S
index 76b3ac5..4ddc1ea 100644
--- a/soc/telink/tlsr/tlsr951x/soc_irq.S
+++ b/soc/telink/tlsr/tlsr951x/soc_irq.S
@@ -6,51 +6,24 @@
#include <zephyr/offsets.h>
#include <zephyr/toolchain.h>
+#include <csr_irq.inc>
-#include <soc.h>
-
-#define NDS_MXSTATUS 0x7C4
+#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/* Exports */
-#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
GTEXT(__soc_save_context)
GTEXT(__soc_restore_context)
-#endif
-
-#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
SECTION_FUNC(exception.other, __soc_save_context)
-#ifdef CONFIG_TELINK_B91_PFT_ARCH
- csrr t0, NDS_MXSTATUS
-#endif
-#ifdef __riscv_dsp
- csrr t1, ucode
-#endif
+ __custom_csr_save_context a0, t0
-#ifdef CONFIG_TELINK_B91_PFT_ARCH
- sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
-#endif
-#ifdef __riscv_dsp
- sw t1, __soc_esf_t_ucode_OFFSET(a0)
-#endif
ret
SECTION_FUNC(exception.other, __soc_restore_context)
-#ifdef CONFIG_TELINK_B91_PFT_ARCH
- lw t0, __soc_esf_t_mxstatus_OFFSET(a0)
-#endif
-#ifdef __riscv_dsp
- lw t1, __soc_esf_t_ucode_OFFSET(a0)
-#endif
+ __custom_csr_restore_context a0, t0
-#ifdef CONFIG_TELINK_B91_PFT_ARCH
- csrw NDS_MXSTATUS, t0
-#endif
-#ifdef __riscv_dsp
- csrw ucode, t1
-#endif
ret
#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
diff --git a/soc/telink/tlsr/tlsr951x/soc_offsets.h b/soc/telink/tlsr/tlsr951x/soc_offsets.h
index 8b48bce..ff6b2e3 100644
--- a/soc/telink/tlsr/tlsr951x/soc_offsets.h
+++ b/soc/telink/tlsr/tlsr951x/soc_offsets.h
@@ -7,23 +7,13 @@
#ifndef SOC_RISCV_TELINK_B91_SOC_OFFSETS_H
#define SOC_RISCV_TELINK_B91_SOC_OFFSETS_H
+#include <csr_offsets.h>
+
#ifdef CONFIG_RISCV_SOC_OFFSETS
/* Telink B91 specific registers. */
-#if defined(CONFIG_TELINK_B91_PFT_ARCH) && defined(__riscv_dsp)
- #define GEN_SOC_OFFSET_SYMS() \
- GEN_OFFSET_SYM(soc_esf_t, mxstatus); \
- GEN_OFFSET_SYM(soc_esf_t, ucode)
-
-#elif defined(CONFIG_TELINK_B91_PFT_ARCH)
- #define GEN_SOC_OFFSET_SYMS() \
- GEN_OFFSET_SYM(soc_esf_t, mxstatus)
-
-#elif defined(__riscv_dsp)
- #define GEN_SOC_OFFSET_SYMS() \
- GEN_OFFSET_SYM(soc_esf_t, ucode)
-
-#endif
+#define GEN_SOC_OFFSET_SYMS() \
+ GEN_CUSTOM_CSR_OFFSET_SYMS()
#endif /* CONFIG_RISCV_SOC_OFFSETS */
diff --git a/soc/telink/tlsr/tlsr951x/start.S b/soc/telink/tlsr/tlsr951x/start.S
index 6e09dab..7074860 100644
--- a/soc/telink/tlsr/tlsr951x/start.S
+++ b/soc/telink/tlsr/tlsr951x/start.S
@@ -4,9 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
-#define NDS_MCACHE_CTL 0x7CA
-#define NDS_MMISC_CTL 0x7D0
-
#include <zephyr/toolchain.h>
.option push
@@ -31,17 +28,6 @@
start:
- /* Enable I/D-Cache */
- csrr t0, NDS_MCACHE_CTL
- ori t0, t0, 1 #/I-Cache
- ori t0, t0, 2 #/D-Cache
- csrw NDS_MCACHE_CTL, t0
- fence.i
-
- /* Enable misaligned access and non-blocking load */
- li t0, (1 << 8) | (1 << 6)
- csrs NDS_MMISC_CTL, t0
-
_ZERO_AES:
lui t0, 0
la t2, _AES_DATA_VMA_START
