| commit | c01625210802ad319aeee70830dadff9193fe7f3 | [log] [tgz] |
|---|---|---|
| author | Benjamin Walsh <benjamin.walsh@windriver.com> | Tue Dec 13 12:00:09 2016 -0500 |
| committer | Maureen Helm <maureen.helm@nxp.com> | Thu Dec 15 15:57:09 2016 +0000 |
| tree | ded74bb4d692c82fe88918d2f2dc00541a231fe4 | |
| parent | f5d0cbe8ad581927f50e6b85eef23e126807d501 [diff] |
arm: add CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS kconfig flag Cortex-M0/M0+ do not have other faults than the hard fault at priority -1, so they do not need to reserve a priority to allow exceptions to trigger during handling of ISRs. Change-Id: I479e439f7bcac70b4b2b787bcd744a4c65437e80 Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>