806c95163a404d3e3fbae299f8ce7ea8edf94870 - third_party/github/zephyrproject-rtos/zephyr

commit	806c95163a404d3e3fbae299f8ce7ea8edf94870	[log] [tgz]
author	Filip Kokosinski <fkokosinski@antmicro.com>	Tue Sep 05 15:15:25 2023 +0200
committer	Carles Cufí <carles.cufi@nordicsemi.no>	Thu Sep 14 14:34:34 2023 +0200
tree	3a6bea6a2adf60c77738b310d73aff500394b801
parent	9ed51516ed4a4e514db98b7077f7f2ab22a441f7 [diff]

dts/riscv: add missing `riscv,isa` fields and modify existing ones

This commit adds/modifies `riscv,isa` strings using the following rules:
* the ISA string is lowercase
* multi-letter extensions are preceded with the underscore mark
* if an extension is implied by another one, it is not specified - e.g. the
  D extension implies the F extension, so writing `rv32ifd` is redundant

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>

dts/bindings/cpu/espressif,riscv.yaml[diff]
dts/bindings/cpu/intel,niosv.yaml[diff]
dts/bindings/cpu/ite,riscv-ite.yaml[diff]
dts/bindings/cpu/neorv32-cpu.yaml[diff]
dts/bindings/cpu/nuclei,bumblebee.yaml[diff]
dts/bindings/cpu/telink,b91.yaml[diff]
dts/riscv/andes/andes_v5_ae350.dtsi[diff]
dts/riscv/efinix/sapphire_soc.dtsi[diff]
dts/riscv/espressif/esp32c3/esp32c3_common.dtsi[diff]
dts/riscv/gigadevice/gd32vf103.dtsi[diff]
dts/riscv/ite/it8xxx2.dtsi[diff]
dts/riscv/lowrisc/opentitan_earlgrey.dtsi[diff]
dts/riscv/microchip/microchip-miv.dtsi[diff]
dts/riscv/microchip/mpfs-icicle.dtsi[diff]
dts/riscv/neorv32.dtsi[diff]
dts/riscv/niosv/niosv-g.dtsi[diff]
dts/riscv/niosv/niosv-m.dtsi[diff]
dts/riscv/openisa/rv32m1.dtsi[diff]
dts/riscv/riscv32-litex-vexriscv.dtsi[diff]
dts/riscv/sifive/riscv32-fe310.dtsi[diff]
dts/riscv/sifive/riscv64-fu540.dtsi[diff]
dts/riscv/sifive/riscv64-fu740.dtsi[diff]
dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi[diff]
dts/riscv/telink/telink_b91.dtsi[diff]

24 files changed