driver: pinctrl: adapt for mcxe31x series
- add binding files: nxp,mcxe31x-siul2-pinctrl.yaml
- Enable PINCTRL_NXP_SIUL2 when nxp,mcxe31x-siul2-pinctrl is ok
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
diff --git a/drivers/pinctrl/Kconfig.nxp_siul2 b/drivers/pinctrl/Kconfig.nxp_siul2
index e60391f..1650f9d 100644
--- a/drivers/pinctrl/Kconfig.nxp_siul2
+++ b/drivers/pinctrl/Kconfig.nxp_siul2
@@ -4,6 +4,7 @@
config PINCTRL_NXP_SIUL2
bool "Pin controller driver for NXP SIUL2"
default y
- depends on DT_HAS_NXP_S32ZE_SIUL2_PINCTRL_ENABLED || DT_HAS_NXP_S32K3_SIUL2_PINCTRL_ENABLED
+ depends on DT_HAS_NXP_S32ZE_SIUL2_PINCTRL_ENABLED || DT_HAS_NXP_S32K3_SIUL2_PINCTRL_ENABLED || \
+ DT_HAS_NXP_MCXE31X_SIUL2_PINCTRL_ENABLED
help
Enable pin controller driver for NXP SIUL2.
diff --git a/dts/bindings/pinctrl/nxp,mcxe31x-siul2-pinctrl.yaml b/dts/bindings/pinctrl/nxp,mcxe31x-siul2-pinctrl.yaml
new file mode 100644
index 0000000..43b24d7
--- /dev/null
+++ b/dts/bindings/pinctrl/nxp,mcxe31x-siul2-pinctrl.yaml
@@ -0,0 +1,115 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+ NXP SIUL2 Pin Controller for MCXE31X SoCs
+
+ The NXP SIUL2 pin controller is a singleton node responsible for controlling
+ the pin function selection and pin properties. This node, labeled 'pinctrl' in
+ the SoC's devicetree, will define pin configurations in pin groups. Each group
+ within the pin configuration defines the pin configuration for a peripheral,
+ and each numbered subgroup in the pin group defines all the pins for that
+ peripheral with the same configuration properties. The 'pinmux' property in
+ a group selects the pins to be configured, and the remaining properties set
+ configuration values for those pins.
+
+ For example, to configure the pinmux for UART0, modify the 'pinctrl' from your
+ board or application devicetree overlay as follows:
+
+ /* Include the SoC package header containing the predefined pins definitions */
+ #include <nxp/mcx/MCXE31BMPB-pinctrl.h>
+
+ &pinctrl {
+ uart0_default: uart0_default {
+ group1 {
+ pinmux = <PTA3_LPUART0_TX_O>;
+ output-enable;
+ };
+ group2 {
+ pinmux = <PTA28_LPUART0_RX>;
+ input-enable;
+ };
+ };
+ };
+
+ The 'uart0_default' node contains the pin configurations for a particular state
+ of a device. The 'default' state is the active state. Other states for the same
+ device can be specified in separate child nodes of 'pinctrl'.
+
+ In addition to 'pinmux' property, each group can contain other properties such as
+ 'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
+ 'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
+ output buffer use 'output-enable'.
+
+ To link the pin configurations with UART0 device, use pinctrl-N property in the
+ device node, where 'N' is the zero-based state index (0 is the default state).
+ Following previous example:
+
+ &uart0 {
+ pinctrl-0 = <&uart0_default>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ If only the required properties are supplied, the pin configuration register
+ will be assigned the following values:
+ - input and output buffers disabled
+ - internal pull not enabled
+ - slew rate "fastest"
+ - invert disabled
+ - drive strength disabled.
+
+ Additionally, following settings are currently not supported and default to
+ the values indicated below:
+ - Safe Mode Control (disabled)
+ - Pad Keeping (disabled)
+ - Input Filter (disabled).
+
+compatible: "nxp,mcxe31x-siul2-pinctrl"
+
+include: base.yaml
+
+child-binding:
+ description: NXP SIUL2 pin controller pin group.
+ child-binding:
+ description: NXP SIUL2 pin controller pin configuration node.
+
+ include:
+ - name: pincfg-node.yaml
+ property-allowlist:
+ - bias-disable
+ - bias-pull-down
+ - bias-pull-up
+ - input-enable
+ - output-enable
+
+ properties:
+ pinmux:
+ required: true
+ type: array
+ description: |
+ An array of pins sharing the same group properties. The pins must be
+ defined using the macros from the SoC package header. These macros
+ encode all the pin muxing information in a 32-bit value.
+
+ slew-rate:
+ type: string
+ enum:
+ - "fastest"
+ - "slowest"
+ default: "fastest"
+ description: |
+ Slew rate control. Can be either slowest or fastest setting.
+ See the SoC reference manual for applicability of this setting.
+
+ nxp,invert:
+ type: boolean
+ description: |
+ Invert the signal selected by Source Signal Selection (SSS) before
+ transmitting it to the associated destination (chip pin or module port).
+
+ nxp,drive-strength:
+ type: boolean
+ description: |
+ Drive strength enable.
+ See the SoC reference manual for applicability of this setting.
