| commit | 837dd99a0e2b13bc4448b263918dd523aada93df | [log] [tgz] |
|---|---|---|
| author | Andy Ross <andrew.j.ross@intel.com> | Thu Dec 07 15:04:51 2017 -0800 |
| committer | Anas Nashif <nashif@linux.intel.com> | Fri Feb 16 10:44:29 2018 -0500 |
| tree | c525e1fb730e5b8bc33456d1f8d33de61bb45488 | |
| parent | a34f884f23dc67c67012557566b86700f10ea008 [diff] |
samples/xtensa-asm2: Unit test for new Xtensa assembly primitives This sample (which should eventually become a proper test) suite builds from simple applications of the new primitives to a full context switch test and interrupt handling suite (based on the CPU-internal CCOMPARE2 timer). It's been extraordinarily useful finding regressing as the asm2 code gets modified and should probably stick around as long as possible. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>