arch: riscv: add Kconfig option for imprecise FPU state tracking
According to the RISC-V Instruction Set Manual: Volume II, Version 20240411
(Section 3.1.6.6), some implementations may choose to track the dirtiness
of the floating-point register state imprecisely by reporting the state to
be dirty even when it has not been modified. This option reflects that.
Also add a filter in `tests/arch/riscv/fpu_sharing/` based on imprecise
FPU state tracking
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index a783247..8f426d0 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -1,4 +1,5 @@
# Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
menu "RISCV Options"
@@ -375,6 +376,15 @@
endif # NULL_POINTER_EXCEPTION_DETECTION_PMP
+config RISCV_IMPRECISE_FPU_STATE_TRACKING
+ bool "Imprecise implementation of FPU state tracking"
+ depends on FPU
+ help
+ According to the RISC-V Instruction Set Manual: Volume II, Version 20240411
+ (Section 3.1.6.6), some implementations may choose to track the dirtiness of
+ the floating-point register state imprecisely by reporting the state to be
+ dirty even when it has not been modified. This option reflects that.
+
endmenu
config MAIN_STACK_SIZE
diff --git a/tests/arch/riscv/fpu_sharing/testcase.yaml b/tests/arch/riscv/fpu_sharing/testcase.yaml
index 2ec10f2..797f750 100644
--- a/tests/arch/riscv/fpu_sharing/testcase.yaml
+++ b/tests/arch/riscv/fpu_sharing/testcase.yaml
@@ -1,4 +1,4 @@
tests:
arch.riscv.fpu_sharing:
arch_allow: riscv
- filter: CONFIG_CPU_HAS_FPU
+ filter: CONFIG_CPU_HAS_FPU and not CONFIG_RISCV_IMPRECISE_FPU_STATE_TRACKING
