boards, dts: fix filenames and dts refs for adsp clock
Changes filenames and DTS references from CAVS clock to
ADSP clock.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt
index c855a0f..2665e18 100644
--- a/drivers/clock_control/CMakeLists.txt
+++ b/drivers/clock_control/CMakeLists.txt
@@ -3,7 +3,7 @@
zephyr_library()
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE beetle_clock_control.c)
-zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ADSP clock_control_cavs.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ADSP clock_control_adsp.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32 clock_control_esp32.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_GD32 clock_control_gd32.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LITEX clock_control_litex.c)
diff --git a/drivers/clock_control/clock_control_cavs.c b/drivers/clock_control/clock_control_adsp.c
similarity index 92%
rename from drivers/clock_control/clock_control_cavs.c
rename to drivers/clock_control/clock_control_adsp.c
index 3295b78..c5e7af9 100644
--- a/drivers/clock_control/clock_control_cavs.c
+++ b/drivers/clock_control/clock_control_adsp.c
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
-#include <zephyr/drivers/clock_control/clock_control_cavs.h>
+#include <zephyr/drivers/clock_control/clock_control_adsp.h>
#include <zephyr/drivers/clock_control.h>
static int cavs_clock_ctrl_set_rate(const struct device *clk,
diff --git a/dts/bindings/clock/intel,adsp-shim-clkctl.yaml b/dts/bindings/clock/intel,adsp-shim-clkctl.yaml
index 95d5d38..9c60133 100644
--- a/dts/bindings/clock/intel,adsp-shim-clkctl.yaml
+++ b/dts/bindings/clock/intel,adsp-shim-clkctl.yaml
@@ -1,42 +1,42 @@
# Copyright (c) 2022 Intel Corporation. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
-description: Intel cAVS clock controlling related constants.
+description: Intel ADSP clock controlling related constants.
compatible: "intel,adsp-shim-clkctl"
properties:
- cavs-clkctl-clk-wovcro:
+ adsp-clkctl-clk-wovcro:
type: int
required: false
description: Index of WOVCRO clock encoding in the encoding array (if wovcro-supported is true).
- cavs-clkctl-clk-lpro:
+ adsp-clkctl-clk-lpro:
type: int
required: false
description: Index of LPRO clock encoding in the encoding array.
- cavs-clkctl-clk-hpro:
+ adsp-clkctl-clk-hpro:
type: int
required: false
description: Index of HPRO clock encoding in the encoding array.
- cavs-clkctl-freq-enc:
+ adsp-clkctl-freq-enc:
type: array
required: true
description: Array that encodes what is needed to enable each clock.
- cavs-clkctl-freq-mask:
+ adsp-clkctl-freq-mask:
type: array
required: false
description: Array that encodes needed masks to enable each clock.
- cavs-clkctl-freq-default:
+ adsp-clkctl-freq-default:
type: int
required: true
description: Index for the default clock.
- cavs-clkctl-freq-lowest:
+ adsp-clkctl-freq-lowest:
type: int
required: true
description: Index for the lowest frequency clock.
diff --git a/dts/xtensa/intel/intel_adsp_cavs15.dtsi b/dts/xtensa/intel/intel_adsp_cavs15.dtsi
index 4bd77e9..2499287 100644
--- a/dts/xtensa/intel/intel_adsp_cavs15.dtsi
+++ b/dts/xtensa/intel/intel_adsp_cavs15.dtsi
@@ -55,11 +55,11 @@
clkctl: clkctl {
compatible = "intel,adsp-shim-clkctl";
- cavs-clkctl-clk-lpro = <0>;
- cavs-clkctl-clk-hpro = <2>;
- cavs-clkctl-freq-enc = <0x3 0x1 0x0>;
- cavs-clkctl-freq-default = <1>;
- cavs-clkctl-freq-lowest = <0>;
+ adsp-clkctl-clk-lpro = <0>;
+ adsp-clkctl-clk-hpro = <2>;
+ adsp-clkctl-freq-enc = <0x3 0x1 0x0>;
+ adsp-clkctl-freq-default = <1>;
+ adsp-clkctl-freq-lowest = <0>;
};
soc {
diff --git a/dts/xtensa/intel/intel_adsp_cavs18.dtsi b/dts/xtensa/intel/intel_adsp_cavs18.dtsi
index 74255c7..44104f9 100644
--- a/dts/xtensa/intel/intel_adsp_cavs18.dtsi
+++ b/dts/xtensa/intel/intel_adsp_cavs18.dtsi
@@ -51,12 +51,12 @@
clkctl: clkctl {
compatible = "intel,adsp-shim-clkctl";
- cavs-clkctl-clk-lpro = <0>;
- cavs-clkctl-clk-hpro = <1>;
- cavs-clkctl-freq-enc = <0x20000002 0x80000006>;
- cavs-clkctl-freq-mask = <0x20000000 0x80000000>;
- cavs-clkctl-freq-default = <1>;
- cavs-clkctl-freq-lowest = <0>;
+ adsp-clkctl-clk-lpro = <0>;
+ adsp-clkctl-clk-hpro = <1>;
+ adsp-clkctl-freq-enc = <0x20000002 0x80000006>;
+ adsp-clkctl-freq-mask = <0x20000000 0x80000000>;
+ adsp-clkctl-freq-default = <1>;
+ adsp-clkctl-freq-lowest = <0>;
};
soc {
diff --git a/dts/xtensa/intel/intel_adsp_cavs20.dtsi b/dts/xtensa/intel/intel_adsp_cavs20.dtsi
index 51eb641..58c155c 100644
--- a/dts/xtensa/intel/intel_adsp_cavs20.dtsi
+++ b/dts/xtensa/intel/intel_adsp_cavs20.dtsi
@@ -51,12 +51,12 @@
clkctl: clkctl {
compatible = "intel,adsp-shim-clkctl";
- cavs-clkctl-clk-lpro = <0>;
- cavs-clkctl-clk-hpro = <1>;
- cavs-clkctl-freq-enc = <0x20000002 0x80000006>;
- cavs-clkctl-freq-mask = <0x20000000 0x80000000>;
- cavs-clkctl-freq-default = <1>;
- cavs-clkctl-freq-lowest = <0>;
+ adsp-clkctl-clk-lpro = <0>;
+ adsp-clkctl-clk-hpro = <1>;
+ adsp-clkctl-freq-enc = <0x20000002 0x80000006>;
+ adsp-clkctl-freq-mask = <0x20000000 0x80000000>;
+ adsp-clkctl-freq-default = <1>;
+ adsp-clkctl-freq-lowest = <0>;
};
soc {
diff --git a/dts/xtensa/intel/intel_adsp_cavs25.dtsi b/dts/xtensa/intel/intel_adsp_cavs25.dtsi
index 2d191d2..6c9778d 100644
--- a/dts/xtensa/intel/intel_adsp_cavs25.dtsi
+++ b/dts/xtensa/intel/intel_adsp_cavs25.dtsi
@@ -69,13 +69,13 @@
clkctl: clkctl {
compatible = "intel,adsp-shim-clkctl";
- cavs-clkctl-clk-wovcro = <0>;
- cavs-clkctl-clk-lpro = <1>;
- cavs-clkctl-clk-hpro = <2>;
- cavs-clkctl-freq-enc = <0x1a 0x20000002 0x80000002>;
- cavs-clkctl-freq-mask = <0x10 0x20000000 0x80000000>;
- cavs-clkctl-freq-default = <2>;
- cavs-clkctl-freq-lowest = <0>;
+ adsp-clkctl-clk-wovcro = <0>;
+ adsp-clkctl-clk-lpro = <1>;
+ adsp-clkctl-clk-hpro = <2>;
+ adsp-clkctl-freq-enc = <0x1a 0x20000002 0x80000002>;
+ adsp-clkctl-freq-mask = <0x10 0x20000000 0x80000000>;
+ adsp-clkctl-freq-default = <2>;
+ adsp-clkctl-freq-lowest = <0>;
wovcro-supported;
};
diff --git a/include/zephyr/drivers/clock_control/clock_control_cavs.h b/include/zephyr/drivers/clock_control/clock_control_adsp.h
similarity index 89%
rename from include/zephyr/drivers/clock_control/clock_control_cavs.h
rename to include/zephyr/drivers/clock_control/clock_control_adsp.h
index beadada..2d29eb6 100644
--- a/include/zephyr/drivers/clock_control/clock_control_cavs.h
+++ b/include/zephyr/drivers/clock_control/clock_control_adsp.h
@@ -6,6 +6,6 @@
#ifndef CLOCK_CONTROL_ADSP_H_
#define CLOCK_CONTROL_ADSP_H_
-#include <cavs-clk.h>
+#include <adsp-clk.h>
#endif /* CLOCK_CONTROL_ADSP_H_ */
diff --git a/soc/xtensa/intel_adsp/cavs/power.c b/soc/xtensa/intel_adsp/cavs/power.c
index fe24fd0..5a4578f 100644
--- a/soc/xtensa/intel_adsp/cavs/power.c
+++ b/soc/xtensa/intel_adsp/cavs/power.c
@@ -11,7 +11,7 @@
#include <zephyr/init.h>
#include <adsp_shim.h>
-#include <cavs-clk.h>
+#include <adsp-clk.h>
#include <cavs-idc.h>
#include "soc.h"
diff --git a/soc/xtensa/intel_adsp/common/clk.c b/soc/xtensa/intel_adsp/common/clk.c
index 52084be..503618e 100644
--- a/soc/xtensa/intel_adsp/common/clk.c
+++ b/soc/xtensa/intel_adsp/common/clk.c
@@ -5,7 +5,7 @@
*/
#include <zephyr/device.h>
-#include <cavs-clk.h>
+#include <adsp-clk.h>
#include <adsp_shim.h>
static struct cavs_clock_info platform_clocks[CONFIG_MP_NUM_CPUS];
diff --git a/soc/xtensa/intel_adsp/common/include/cavs-clk.h b/soc/xtensa/intel_adsp/common/include/adsp-clk.h
similarity index 74%
rename from soc/xtensa/intel_adsp/common/include/cavs-clk.h
rename to soc/xtensa/intel_adsp/common/include/adsp-clk.h
index 170685c..aef065d 100644
--- a/soc/xtensa/intel_adsp/common/include/cavs-clk.h
+++ b/soc/xtensa/intel_adsp/common/include/adsp-clk.h
@@ -38,14 +38,14 @@
#define CAVS_SHIM_BASE DT_REG_ADDR(DT_NODELABEL(shim))
#define CAVS_SHIM_CLKCTL (*((volatile uint32_t *)(CAVS_SHIM_BASE + 0x78)))
-#define CAVS_CLOCK_FREQ_ENC DT_PROP(DT_NODELABEL(clkctl), cavs_clkctl_freq_enc)
-#define CAVS_CLOCK_FREQ_MASK DT_PROP(DT_NODELABEL(clkctl), cavs_clkctl_freq_mask)
-#define CAVS_CLOCK_FREQ_LEN DT_PROP_LEN(DT_NODELABEL(clkctl), cavs_clkctl_freq_enc)
+#define CAVS_CLOCK_FREQ_ENC DT_PROP(DT_NODELABEL(clkctl), adsp_clkctl_freq_enc)
+#define CAVS_CLOCK_FREQ_MASK DT_PROP(DT_NODELABEL(clkctl), adsp_clkctl_freq_mask)
+#define CAVS_CLOCK_FREQ_LEN DT_PROP_LEN(DT_NODELABEL(clkctl), adsp_clkctl_freq_enc)
-#define CAVS_CLOCK_FREQ_DEFAULT DT_PROP(DT_NODELABEL(clkctl), cavs_clkctl_freq_default)
-#define CAVS_CLOCK_FREQ_LOWEST DT_PROP(DT_NODELABEL(clkctl), cavs_clkctl_freq_lowest)
+#define CAVS_CLOCK_FREQ_DEFAULT DT_PROP(DT_NODELABEL(clkctl), adsp_clkctl_freq_default)
+#define CAVS_CLOCK_FREQ_LOWEST DT_PROP(DT_NODELABEL(clkctl), adsp_clkctl_freq_lowest)
-#define CAVS_CLOCK_FREQ(name) DT_PROP(DT_NODELABEL(clkctl), cavs_clkctl_clk_##name)
+#define CAVS_CLOCK_FREQ(name) DT_PROP(DT_NODELABEL(clkctl), adsp_clkctl_clk_##name)
#if DT_PROP(DT_NODELABEL(clkctl), wovcro_supported)
#define CAVS_CLOCK_HAS_WOVCRO
diff --git a/tests/drivers/clock_control/cavs_clock/src/main.c b/tests/drivers/clock_control/cavs_clock/src/main.c
index ff4e30f..9dda8a9 100644
--- a/tests/drivers/clock_control/cavs_clock/src/main.c
+++ b/tests/drivers/clock_control/cavs_clock/src/main.c
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/ztest.h>
-#include <zephyr/drivers/clock_control/clock_control_cavs.h>
+#include <zephyr/drivers/clock_control/clock_control_adsp.h>
#include <zephyr/drivers/clock_control.h>
static void check_clocks(struct cavs_clock_info *clocks, uint32_t freq_idx)
