arm/fsl_frdm_k64f: serial/uart_k20: rework UART clock gating
The code to poke the system integration module to disable clock gating
for UARTs only works for UART0-3 since all the bits are in the same
register. However, clocks for UART4 and UART5 are controlled by
another register. This means that we have been writing to the wrong
bit for enabling UART4.
This patch fixes this issue, and moves the clock gating clock into
board initialization. The incorrect code has also been removed to
prevent accidental mis-use. The dev_data struct is no longer needed
for uart_k20, so that is removed as well.
Change-Id: I67845a417e43647bf0ffcbdbda34ce68fa887713
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
4 files changed
