commit 8b42be5333805b2834fae264da9ad8f44e85cc39
author Denis Brockus <dbrockus@google.com> Fri Jun 11 09:47:13 2021 -0600
committer Anas Nashif <anas.nashif@intel.com> Fri Jun 18 16:51:23 2021 -0400
tree b26e0bbc55b2475a85dd0d981aea20ba41fce348
parent 421ff4758f5cf3b371acc81bc87373afbda784f5

gpio: Add GPIO voltage overrides

Add GPIO_flag values for GPIO DTS creation that
allows for pins that do not use the default
voltage.  IT8xxx2 supports setting voltage
levels for each pin. The default for this SoC
is 3P3 but they can be set individually to
1P8.

This will be used, for example:

    i2c_c_scl {
            gpios = <&gpioc 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>;
            enum-name = "GPIO_I2C_C_SCL";
            label = "I2C_C_SCL";
    };

Signed-off-by: Denis Brockus <dbrockus@google.com>

include/dt-bindings/gpio/gpio.h

diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h
index e0ea0e71..10cb866 100644
--- a/include/dt-bindings/gpio/gpio.h
+++ b/include/dt-bindings/gpio/gpio.h
@@ -77,6 +77,32 @@
 /** @} */
 
 /**
+ * @name GPIO pin voltage flags
+ *
+ * The voltage flags are a Zephyr specific extension of the standard GPIO
+ * flags specified by the Linux GPIO binding. Only applicable if SoC allows
+ * to configure pin voltage per individual pin.
+ *
+ * @{
+ */
+
+/** @cond INTERNAL_HIDDEN */
+#define GPIO_VOLTAGE_POS	6
+#define GPIO_VOLTAGE_MASK	(3U << GPIO_VOLTAGE_POS)
+/** @endcond */
+
+/** Set pin at the default voltage level */
+#define GPIO_VOLTAGE_DEFAULT	(0U << GPIO_VOLTAGE_POS)
+/** Set pin voltage level at 1.8 V */
+#define GPIO_VOLTAGE_1P8	(1U << GPIO_VOLTAGE_POS)
+/** Set pin voltage level at 3.3 V */
+#define GPIO_VOLTAGE_3P3	(2U << GPIO_VOLTAGE_POS)
+/** Set pin voltage level at 5.0 V */
+#define GPIO_VOLTAGE_5P0	(3U << GPIO_VOLTAGE_POS)
+
+/** @} */
+
+/**
  * @}
  */