| commit | 8db36838207e7562ea2ce4e3653d59933ea4053b | [log] [tgz] |
|---|---|---|
| author | Jim Shu <cwshu@andestech.com> | Sun Mar 14 02:08:49 2021 +0800 |
| committer | Anas Nashif <anas.nashif@intel.com> | Mon Mar 22 15:47:09 2021 -0400 |
| tree | 26405f13aa42e0838eeb77e83d09c7032447c843 | |
| parent | 11aedbc4605676f83500c96cca4eee75769c3e5f [diff] |
arch: riscv: improve exception messages Add exception descriptions of mcause id 6~15. Also print mtval CSR for memory access fault & illegal instruction exceptions. Signed-off-by: Jim Shu <cwshu@andestech.com>