arch: riscv: improve exception messages
Add exception descriptions of mcause id 6~15. Also print mtval CSR for
memory access fault & illegal instruction exceptions.
Signed-off-by: Jim Shu <cwshu@andestech.com>
diff --git a/arch/riscv/core/fatal.c b/arch/riscv/core/fatal.c
index c853ef5..e65d5d2 100644
--- a/arch/riscv/core/fatal.c
+++ b/arch/riscv/core/fatal.c
@@ -65,6 +65,22 @@
return "Load address misaligned";
case 5:
return "Load access fault";
+ case 6:
+ return "Store/AMO address misaligned";
+ case 7:
+ return "Store/AMO access fault";
+ case 8:
+ return "Environment call from U-mode";
+ case 9:
+ return "Environment call from S-mode";
+ case 11:
+ return "Environment call from M-mode";
+ case 12:
+ return "Instruction page fault";
+ case 13:
+ return "Load page fault";
+ case 15:
+ return "Store/AMO page fault";
default:
return "unknown";
}
@@ -87,13 +103,15 @@
}
}
#endif /* CONFIG_USERSPACE */
- ulong_t mcause;
+ ulong_t mcause, mtval;
__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
+ __asm__ volatile("csrr %0, mtval" : "=r" (mtval));
mcause &= SOC_MCAUSE_EXP_MASK;
LOG_ERR("");
LOG_ERR(" mcause: %ld, %s", mcause, cause_str(mcause));
+ LOG_ERR(" mtval: %lx", mtval);
z_riscv_fatal_error(K_ERR_CPU_EXCEPTION, esf);
}
