ITE: drivers/i2c: create pinmux phandle to the I2C driver node
Create the pinmux phandle to the I2C driver node in the
devicetree. When the pinmux_pin_set function in
i2c_it8xxx2_init can refer to the setting of this phandle.
It is more flexible to use.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
diff --git a/drivers/i2c/i2c_ite_it8xxx2.c b/drivers/i2c/i2c_ite_it8xxx2.c
index dbf564e..3827a26 100644
--- a/drivers/i2c/i2c_ite_it8xxx2.c
+++ b/drivers/i2c/i2c_ite_it8xxx2.c
@@ -7,6 +7,7 @@
#define DT_DRV_COMPAT ite_it8xxx2_i2c
#include <drivers/i2c.h>
+#include <drivers/pinmux.h>
#include <errno.h>
#include <logging/log.h>
LOG_MODULE_REGISTER(i2c_ite_it8xxx2);
@@ -19,6 +20,19 @@
#define DEV_DATA(dev) \
((struct i2c_it8xxx2_data * const)(dev)->data)
+#define DEV_CLK_PINMUX(idx) DEVICE_DT_GET(DT_PHANDLE \
+ (DT_NODELABEL(pinctrl_i2c_clk##idx), pinctrls))
+#define DEV_DATA_PINMUX(idx) DEVICE_DT_GET(DT_PHANDLE \
+ (DT_NODELABEL(pinctrl_i2c_data##idx), pinctrls))
+#define DEV_CLK_PIN(idx) DT_PHA(DT_PHANDLE_BY_IDX \
+ (DT_DRV_INST(idx), pinctrl_0, 0), pinctrls, pin)
+#define DEV_DATA_PIN(idx) DT_PHA(DT_PHANDLE_BY_IDX \
+ (DT_DRV_INST(idx), pinctrl_1, 0), pinctrls, pin)
+#define DEV_CLK_ALT_FUNC(idx) DT_PHA(DT_PHANDLE_BY_IDX \
+ (DT_DRV_INST(idx), pinctrl_0, 0), pinctrls, alt_func)
+#define DEV_DATA_ALT_FUNC(idx) DT_PHA(DT_PHANDLE_BY_IDX \
+ (DT_DRV_INST(idx), pinctrl_1, 0), pinctrls, alt_func)
+
#define I2C_STANDARD_PORT_COUNT 3
/* Default PLL frequency. */
#define PLL_CLOCK 48000000
@@ -29,6 +43,15 @@
uint8_t *base;
uint8_t i2c_irq_base;
uint8_t port;
+ /* Pinmux control group */
+ const struct device *clk_pinctrls;
+ const struct device *data_pinctrls;
+ /* GPIO pin */
+ uint8_t clk_pin;
+ uint8_t data_pin;
+ /* Alternate function */
+ uint8_t clk_alt_fun;
+ uint8_t data_alt_fun;
};
enum i2c_ch_status {
@@ -905,6 +928,11 @@
return error;
}
+ /* The pin is set to I2C alternate function of clock */
+ pinmux_pin_set(config->clk_pinctrls, config->clk_pin, config->clk_alt_fun);
+ /* The pin is set to I2C alternate function of data */
+ pinmux_pin_set(config->data_pinctrls, config->data_pin, config->data_alt_fun);
+
return 0;
}
@@ -922,6 +950,12 @@
.bitrate = DT_INST_PROP(idx, clock_frequency), \
.i2c_irq_base = DT_INST_IRQN(idx), \
.port = DT_INST_PROP(idx, port_num), \
+ .clk_pinctrls = DEV_CLK_PINMUX(idx), \
+ .data_pinctrls = DEV_DATA_PINMUX(idx), \
+ .clk_pin = DEV_CLK_PIN(idx), \
+ .data_pin = DEV_DATA_PIN(idx), \
+ .clk_alt_fun = DEV_CLK_ALT_FUNC(idx), \
+ .data_alt_fun = DEV_DATA_ALT_FUNC(idx) \
}; \
\
static struct i2c_it8xxx2_data i2c_it8xxx2_data_##idx; \
diff --git a/dts/bindings/i2c/ite,it8xxx2-i2c.yaml b/dts/bindings/i2c/ite,it8xxx2-i2c.yaml
index 17dc166..c8feec9 100644
--- a/dts/bindings/i2c/ite,it8xxx2-i2c.yaml
+++ b/dts/bindings/i2c/ite,it8xxx2-i2c.yaml
@@ -21,3 +21,13 @@
type: int
required: true
description: Ordinal identifying the port
+
+ pinctrl-0:
+ type: phandle
+ required: true
+ description: Configuration of I2C clock pinmux controller
+
+ pinctrl-1:
+ type: phandle
+ required: true
+ description: Configuration of I2C data pinmux controller
diff --git a/dts/riscv/it8xxx2-alts-map.dtsi b/dts/riscv/it8xxx2-alts-map.dtsi
index bffcf1e..33ec95d 100644
--- a/dts/riscv/it8xxx2-alts-map.dtsi
+++ b/dts/riscv/it8xxx2-alts-map.dtsi
@@ -61,5 +61,43 @@
pinctrl_pwm7: pwm7 {
pinctrls = <&pinmuxa 7 IT8XXX2_PINMUX_FUNC_1>;
};
+
+ /* I2C alternate function */
+ pinctrl_i2c_clk0: i2c_clk0 {
+ pinctrls = <&pinmuxb 3 IT8XXX2_PINMUX_FUNC_1>;
+ };
+ pinctrl_i2c_data0: i2c_data0 {
+ pinctrls = <&pinmuxb 4 IT8XXX2_PINMUX_FUNC_1>;
+ };
+ pinctrl_i2c_clk1: i2c_clk1 {
+ pinctrls = <&pinmuxc 1 IT8XXX2_PINMUX_FUNC_1>;
+ };
+ pinctrl_i2c_data1: i2c_data1 {
+ pinctrls = <&pinmuxc 2 IT8XXX2_PINMUX_FUNC_1>;
+ };
+ pinctrl_i2c_clk2: i2c_clk2 {
+ pinctrls = <&pinmuxf 6 IT8XXX2_PINMUX_FUNC_1>;
+ };
+ pinctrl_i2c_data2: i2c_data2 {
+ pinctrls = <&pinmuxf 7 IT8XXX2_PINMUX_FUNC_1>;
+ };
+ pinctrl_i2c_clk3: i2c_clk3 {
+ pinctrls = <&pinmuxh 1 IT8XXX2_PINMUX_FUNC_3>;
+ };
+ pinctrl_i2c_data3: i2c_data3 {
+ pinctrls = <&pinmuxh 2 IT8XXX2_PINMUX_FUNC_3>;
+ };
+ pinctrl_i2c_clk4: i2c_clk4 {
+ pinctrls = <&pinmuxe 0 IT8XXX2_PINMUX_FUNC_3>;
+ };
+ pinctrl_i2c_data4: i2c_data4 {
+ pinctrls = <&pinmuxe 7 IT8XXX2_PINMUX_FUNC_3>;
+ };
+ pinctrl_i2c_clk5: i2c_clk5 {
+ pinctrls = <&pinmuxa 4 IT8XXX2_PINMUX_FUNC_3>;
+ };
+ pinctrl_i2c_data5: i2c_data5 {
+ pinctrls = <&pinmuxa 5 IT8XXX2_PINMUX_FUNC_3>;
+ };
};
};
diff --git a/dts/riscv/it8xxx2.dtsi b/dts/riscv/it8xxx2.dtsi
index 9fc4abd..d39e803 100644
--- a/dts/riscv/it8xxx2.dtsi
+++ b/dts/riscv/it8xxx2.dtsi
@@ -603,6 +603,8 @@
status = "disabled";
label = "I2C_0";
port-num = <0>;
+ pinctrl-0 = <&pinctrl_i2c_clk0>; /* GPB3 */
+ pinctrl-1 = <&pinctrl_i2c_data0>; /* GPB4 */
};
i2c1: i2c@f01c80 {
compatible = "ite,it8xxx2-i2c";
@@ -614,6 +616,8 @@
status = "disabled";
label = "I2C_1";
port-num = <1>;
+ pinctrl-0 = <&pinctrl_i2c_clk1>; /* GPC1 */
+ pinctrl-1 = <&pinctrl_i2c_data1>; /* GPC2 */
};
i2c2: i2c@f01cc0 {
compatible = "ite,it8xxx2-i2c";
@@ -625,6 +629,8 @@
status = "disabled";
label = "I2C_2";
port-num = <2>;
+ pinctrl-0 = <&pinctrl_i2c_clk2>; /* GPF6 */
+ pinctrl-1 = <&pinctrl_i2c_data2>; /* GPF7 */
};
i2c3: i2c@f03680 {
compatible = "ite,it8xxx2-i2c";
@@ -636,6 +642,8 @@
status = "disabled";
label = "I2C_3";
port-num = <3>;
+ pinctrl-0 = <&pinctrl_i2c_clk3>; /* GPH1 */
+ pinctrl-1 = <&pinctrl_i2c_data3>; /* GPH2 */
};
i2c4: i2c@f03500 {
compatible = "ite,it8xxx2-i2c";
@@ -647,6 +655,8 @@
status = "disabled";
label = "I2C_4";
port-num = <4>;
+ pinctrl-0 = <&pinctrl_i2c_clk4>; /* GPE0 */
+ pinctrl-1 = <&pinctrl_i2c_data4>; /* GPE7 */
};
i2c5: i2c@f03580 {
compatible = "ite,it8xxx2-i2c";
@@ -658,6 +668,8 @@
status = "disabled";
label = "I2C_5";
port-num = <5>;
+ pinctrl-0 = <&pinctrl_i2c_clk5>; /* GPA4 */
+ pinctrl-1 = <&pinctrl_i2c_data5>; /* GPA5 */
};
ecpm: clock-controller@f01e00 {
