dts: arm: silabs: Remove use of CONFIG_SOC_* from Silabs SoC dts files
To move forward and remove use of Kconfig in dts files lets just create
SoC specific dtsi files that the boards can include. This lets us
remove:
CONFIG_SOC_PART_NUMBER_EFM32WG990F256
CONFIG_SOC_PART_NUMBER_EFR32FG1P133F256GM48
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
diff --git a/boards/arm/efm32wg_stk3800/efm32wg_stk3800.dts b/boards/arm/efm32wg_stk3800/efm32wg_stk3800.dts
index 9db3661..81c93b8 100644
--- a/boards/arm/efm32wg_stk3800/efm32wg_stk3800.dts
+++ b/boards/arm/efm32wg_stk3800/efm32wg_stk3800.dts
@@ -5,7 +5,7 @@
*/
/dts-v1/;
-#include <silabs/efm32wg.dtsi>
+#include <silabs/efm32wg990f256.dtsi>
/ {
model = "Silicon Labs EFM32WG STK3800 board";
diff --git a/boards/arm/efr32_slwstk6061a/efr32_slwstk6061a.dts b/boards/arm/efr32_slwstk6061a/efr32_slwstk6061a.dts
index 128c6dc..aa4fbb2 100644
--- a/boards/arm/efr32_slwstk6061a/efr32_slwstk6061a.dts
+++ b/boards/arm/efr32_slwstk6061a/efr32_slwstk6061a.dts
@@ -5,7 +5,7 @@
*/
/dts-v1/;
-#include <silabs/efr32fg1p.dtsi>
+#include <silabs/efr32fg1p133f256gm48.dtsi>
/ {
model = "Silicon Labs EFR32 SLWSTK6061A board";
diff --git a/dts/arm/silabs/efm32wg.dtsi b/dts/arm/silabs/efm32wg.dtsi
index 348f89f..68a4a0f 100644
--- a/dts/arm/silabs/efm32wg.dtsi
+++ b/dts/arm/silabs/efm32wg.dtsi
@@ -1,5 +1,4 @@
#include <arm/armv7-m.dtsi>
-#include <silabs/mem.h>
/ {
cpus {
@@ -11,11 +10,6 @@
flash0: flash {
compatible = "soc-nv-flash";
label = "FLASH_0";
- reg = <0 DT_FLASH_SIZE>;
- };
-
- sram0: memory {
- reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
diff --git a/dts/arm/silabs/efm32wg990f256.dtsi b/dts/arm/silabs/efm32wg990f256.dtsi
new file mode 100644
index 0000000..e7d3c9e
--- /dev/null
+++ b/dts/arm/silabs/efm32wg990f256.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <silabs/efm32wg.dtsi>
+
+/ {
+ flash {
+ reg = <0 DT_SIZE_K(256)>;
+ };
+
+ sram0: memory {
+ reg = <0x20000000 DT_SIZE_K(32)>;
+ };
+};
diff --git a/dts/arm/silabs/efr32fg1p.dtsi b/dts/arm/silabs/efr32fg1p.dtsi
index d00ead7..c171275 100644
--- a/dts/arm/silabs/efr32fg1p.dtsi
+++ b/dts/arm/silabs/efr32fg1p.dtsi
@@ -1,5 +1,4 @@
#include <arm/armv7-m.dtsi>
-#include <silabs/mem.h>
/ {
cpus {
@@ -11,11 +10,6 @@
flash0: flash {
compatible = "soc-nv-flash";
label = "FLASH_0";
- reg = <0 DT_FLASH_SIZE>;
- };
-
- sram0: memory {
- reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
diff --git a/dts/arm/silabs/efr32fg1p133f256gm48.dtsi b/dts/arm/silabs/efr32fg1p133f256gm48.dtsi
new file mode 100644
index 0000000..c9f599e
--- /dev/null
+++ b/dts/arm/silabs/efr32fg1p133f256gm48.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <silabs/efr32fg1p.dtsi>
+
+/ {
+ flash {
+ reg = <0 DT_SIZE_K(256)>;
+ };
+
+ sram0: memory {
+ reg = <0x20000000 DT_SIZE_K(32)>;
+ };
+};
diff --git a/dts/arm/silabs/mem.h b/dts/arm/silabs/mem.h
deleted file mode 100644
index 562f218..0000000
--- a/dts/arm/silabs/mem.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __DT_BINDING_ST_MEM_H
-#define __DT_BINDING_ST_MEM_H
-
-#define __SIZE_K(x) ((x) * 1024)
-
-#if defined(CONFIG_SOC_PART_NUMBER_EFM32WG990F256)
-#define DT_FLASH_SIZE __SIZE_K(256)
-#define DT_SRAM_SIZE __SIZE_K(32)
-#elif defined(CONFIG_SOC_PART_NUMBER_EFR32FG1P133F256GM48)
-#define DT_FLASH_SIZE __SIZE_K(256)
-#define DT_SRAM_SIZE __SIZE_K(32)
-#else
-#error "Flash and RAM sizes not defined for this chip"
-#endif
-
-#endif /* __DT_BINDING_ST_MEM_H */
