| commit | 91516a2be32199cb2360afb0102ba2f536761503 | [log] [tgz] |
|---|---|---|
| author | Kai Vehmanen <kai.vehmanen@linux.intel.com> | Tue Mar 22 18:32:45 2022 +0200 |
| committer | Anas Nashif <anas.nashif@intel.com> | Wed Apr 06 22:00:14 2022 -0400 |
| tree | c39850f017be5adc3bb59db91917b85c507a90d6 | |
| parent | a52aa7f2ab98cdd5da248adc405dca515c32c9c2 [diff] |
drivers: intc: intc_cavs: use correct per-core register set for all ops Current code uses per-core register to check interrupt status and dispatch handlers. However to disable/enable the interrupt, core zero register is always used. While the handlers in _sw_isr_table are common for all cores, the status bits should still be handled separate for each core. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>