dts: arm: st: stm32l4: remove U suffix from "resets" in DTSI
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
diff --git a/dts/arm/st/l4/stm32l4.dtsi b/dts/arm/st/l4/stm32l4.dtsi
index 95c3d7e..c19e889 100644
--- a/dts/arm/st/l4/stm32l4.dtsi
+++ b/dts/arm/st/l4/stm32l4.dtsi
@@ -227,7 +227,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
- resets = <&rctl STM32_RESET(APB2, 14U)>;
+ resets = <&rctl STM32_RESET(APB2, 14)>;
interrupts = <37 0>;
status = "disabled";
};
@@ -236,7 +236,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
- resets = <&rctl STM32_RESET(APB1L, 17U)>;
+ resets = <&rctl STM32_RESET(APB1L, 17)>;
interrupts = <38 0>;
status = "disabled";
};
@@ -245,7 +245,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40008000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 0)>;
- resets = <&rctl STM32_RESET(APB1H, 0U)>;
+ resets = <&rctl STM32_RESET(APB1H, 0)>;
interrupts = <70 0>;
status = "disabled";
};
@@ -299,7 +299,7 @@
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 11)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 11U)>;
+ resets = <&rctl STM32_RESET(APB2, 11)>;
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
@@ -323,7 +323,7 @@
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 0)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 0U)>;
+ resets = <&rctl STM32_RESET(APB1L, 0)>;
interrupts = <28 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -352,7 +352,7 @@
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 4)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 4U)>;
+ resets = <&rctl STM32_RESET(APB1L, 4)>;
interrupts = <54 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -369,7 +369,7 @@
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 16)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 16U)>;
+ resets = <&rctl STM32_RESET(APB2, 16)>;
interrupts = <24 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -392,7 +392,7 @@
reg = <0x40014400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 17)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 17U)>;
+ resets = <&rctl STM32_RESET(APB2, 17)>;
interrupts = <25 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/l4/stm32l412.dtsi b/dts/arm/st/l4/stm32l412.dtsi
index 91ac6df..b9b9054 100644
--- a/dts/arm/st/l4/stm32l412.dtsi
+++ b/dts/arm/st/l4/stm32l412.dtsi
@@ -64,7 +64,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1L, 18U)>;
+ resets = <&rctl STM32_RESET(APB1L, 18)>;
interrupts = <39 0>;
status = "disabled";
};
diff --git a/dts/arm/st/l4/stm32l422.dtsi b/dts/arm/st/l4/stm32l422.dtsi
index 2101b20..e99f020 100644
--- a/dts/arm/st/l4/stm32l422.dtsi
+++ b/dts/arm/st/l4/stm32l422.dtsi
@@ -14,7 +14,7 @@
compatible = "st,stm32l4-aes", "st,stm32-aes";
reg = <0x50060000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 16)>;
- resets = <&rctl STM32_RESET(AHB2, 16U)>;
+ resets = <&rctl STM32_RESET(AHB2, 16)>;
interrupts = <79 0>;
interrupt-names = "aes";
status = "disabled";
diff --git a/dts/arm/st/l4/stm32l431.dtsi b/dts/arm/st/l4/stm32l431.dtsi
index cd24446..111d982 100644
--- a/dts/arm/st/l4/stm32l431.dtsi
+++ b/dts/arm/st/l4/stm32l431.dtsi
@@ -78,7 +78,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1L, 18U)>;
+ resets = <&rctl STM32_RESET(APB1L, 18)>;
interrupts = <39 0>;
status = "disabled";
};
@@ -88,7 +88,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 5U)>;
+ resets = <&rctl STM32_RESET(APB1L, 5)>;
interrupts = <55 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -114,7 +114,7 @@
reg = <0x40012800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 10)>,
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
- resets = <&rctl STM32_RESET(APB2, 10U)>;
+ resets = <&rctl STM32_RESET(APB2, 10)>;
interrupts = <49 0>;
status = "disabled";
};
diff --git a/dts/arm/st/l4/stm32l432.dtsi b/dts/arm/st/l4/stm32l432.dtsi
index f076557..48fc01b 100644
--- a/dts/arm/st/l4/stm32l432.dtsi
+++ b/dts/arm/st/l4/stm32l432.dtsi
@@ -39,7 +39,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 5U)>;
+ resets = <&rctl STM32_RESET(APB1L, 5)>;
interrupts = <55 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/l4/stm32l433.dtsi b/dts/arm/st/l4/stm32l433.dtsi
index f234d63..7b4764c 100644
--- a/dts/arm/st/l4/stm32l433.dtsi
+++ b/dts/arm/st/l4/stm32l433.dtsi
@@ -54,7 +54,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1L, 18U)>;
+ resets = <&rctl STM32_RESET(APB1L, 18)>;
interrupts = <39 0>;
status = "disabled";
};
diff --git a/dts/arm/st/l4/stm32l451.dtsi b/dts/arm/st/l4/stm32l451.dtsi
index b5e9f7e..1ba5f59 100644
--- a/dts/arm/st/l4/stm32l451.dtsi
+++ b/dts/arm/st/l4/stm32l451.dtsi
@@ -91,7 +91,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1L, 18U)>;
+ resets = <&rctl STM32_RESET(APB1L, 18)>;
interrupts = <39 0>;
status = "disabled";
};
@@ -100,7 +100,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
- resets = <&rctl STM32_RESET(APB1L, 19U)>;
+ resets = <&rctl STM32_RESET(APB1L, 19)>;
interrupts = <52 0>;
status = "disabled";
};
@@ -110,7 +110,7 @@
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 1)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 1U)>;
+ resets = <&rctl STM32_RESET(APB1L, 1)>;
interrupts = <29 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -156,7 +156,7 @@
reg = <0x40012800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 10)>,
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
- resets = <&rctl STM32_RESET(APB2, 10U)>;
+ resets = <&rctl STM32_RESET(APB2, 10)>;
interrupts = <49 0>;
status = "disabled";
};
diff --git a/dts/arm/st/l4/stm32l462.dtsi b/dts/arm/st/l4/stm32l462.dtsi
index daa2da6..78269a6 100644
--- a/dts/arm/st/l4/stm32l462.dtsi
+++ b/dts/arm/st/l4/stm32l462.dtsi
@@ -14,7 +14,7 @@
compatible = "st,stm32l4-aes", "st,stm32-aes";
reg = <0x50060000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 16)>;
- resets = <&rctl STM32_RESET(AHB2, 16U)>;
+ resets = <&rctl STM32_RESET(AHB2, 16)>;
interrupts = <79 0>;
interrupt-names = "aes";
status = "disabled";
diff --git a/dts/arm/st/l4/stm32l471.dtsi b/dts/arm/st/l4/stm32l471.dtsi
index e1da8ce..e8b66bf 100644
--- a/dts/arm/st/l4/stm32l471.dtsi
+++ b/dts/arm/st/l4/stm32l471.dtsi
@@ -62,7 +62,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1L, 18U)>;
+ resets = <&rctl STM32_RESET(APB1L, 18)>;
interrupts = <39 0>;
status = "disabled";
};
@@ -71,7 +71,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
- resets = <&rctl STM32_RESET(APB1L, 19U)>;
+ resets = <&rctl STM32_RESET(APB1L, 19)>;
interrupts = <52 0>;
status = "disabled";
};
@@ -80,7 +80,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
- resets = <&rctl STM32_RESET(APB1L, 20U)>;
+ resets = <&rctl STM32_RESET(APB1L, 20)>;
interrupts = <53 0>;
status = "disabled";
};
@@ -122,7 +122,7 @@
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 1)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 1U)>;
+ resets = <&rctl STM32_RESET(APB1L, 1)>;
interrupts = <29 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -151,7 +151,7 @@
reg = <0x40000800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 2)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 2U)>;
+ resets = <&rctl STM32_RESET(APB1L, 2)>;
interrupts = <30 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -180,7 +180,7 @@
reg = <0x40000c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 3)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 3U)>;
+ resets = <&rctl STM32_RESET(APB1L, 3)>;
interrupts = <50 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -209,7 +209,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 5U)>;
+ resets = <&rctl STM32_RESET(APB1L, 5)>;
interrupts = <55 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -226,7 +226,7 @@
reg = <0x40013400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 13)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 13U)>;
+ resets = <&rctl STM32_RESET(APB2, 13)>;
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
@@ -250,7 +250,7 @@
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 18)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 18U)>;
+ resets = <&rctl STM32_RESET(APB2, 18)>;
interrupts = <26 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -282,7 +282,7 @@
reg = <0x40012800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 10)>,
<&rcc STM32_SRC_MSI CLK48_SEL(3)>;
- resets = <&rctl STM32_RESET(APB2, 10U)>;
+ resets = <&rctl STM32_RESET(APB2, 10)>;
interrupts = <49 0>;
status = "disabled";
};
diff --git a/dts/arm/st/l4/stm32l486.dtsi b/dts/arm/st/l4/stm32l486.dtsi
index 46749e8..cb19688 100644
--- a/dts/arm/st/l4/stm32l486.dtsi
+++ b/dts/arm/st/l4/stm32l486.dtsi
@@ -14,7 +14,7 @@
compatible = "st,stm32l4-aes", "st,stm32-aes";
reg = <0x50060000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 16)>;
- resets = <&rctl STM32_RESET(AHB2, 16U)>;
+ resets = <&rctl STM32_RESET(AHB2, 16)>;
interrupts = <79 0>;
interrupt-names = "aes";
status = "disabled";
diff --git a/dts/arm/st/l4/stm32l4a6.dtsi b/dts/arm/st/l4/stm32l4a6.dtsi
index 0822296..80de9cb 100644
--- a/dts/arm/st/l4/stm32l4a6.dtsi
+++ b/dts/arm/st/l4/stm32l4a6.dtsi
@@ -14,7 +14,7 @@
compatible = "st,stm32l4-aes", "st,stm32-aes";
reg = <0x50060000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 16)>;
- resets = <&rctl STM32_RESET(AHB2, 16U)>;
+ resets = <&rctl STM32_RESET(AHB2, 16)>;
interrupts = <79 0>;
interrupt-names = "aes";
status = "disabled";
diff --git a/dts/arm/st/l4/stm32l4p5.dtsi b/dts/arm/st/l4/stm32l4p5.dtsi
index a77778b..7801a1b 100644
--- a/dts/arm/st/l4/stm32l4p5.dtsi
+++ b/dts/arm/st/l4/stm32l4p5.dtsi
@@ -111,7 +111,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1L, 18U)>;
+ resets = <&rctl STM32_RESET(APB1L, 18)>;
interrupts = <39 0>;
status = "disabled";
};
@@ -120,7 +120,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
- resets = <&rctl STM32_RESET(APB1L, 19U)>;
+ resets = <&rctl STM32_RESET(APB1L, 19)>;
interrupts = <52 0>;
status = "disabled";
};
@@ -129,7 +129,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
- resets = <&rctl STM32_RESET(APB1L, 20U)>;
+ resets = <&rctl STM32_RESET(APB1L, 20)>;
interrupts = <53 0>;
status = "disabled";
};
@@ -183,7 +183,7 @@
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 1)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 1U)>;
+ resets = <&rctl STM32_RESET(APB1L, 1)>;
interrupts = <29 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -212,7 +212,7 @@
reg = <0x40000800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 2)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 2U)>;
+ resets = <&rctl STM32_RESET(APB1L, 2)>;
interrupts = <30 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -241,7 +241,7 @@
reg = <0x40000c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 3)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 3U)>;
+ resets = <&rctl STM32_RESET(APB1L, 3)>;
interrupts = <50 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -270,7 +270,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 5U)>;
+ resets = <&rctl STM32_RESET(APB1L, 5)>;
interrupts = <55 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -293,7 +293,7 @@
reg = <0x40013400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 13)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 13U)>;
+ resets = <&rctl STM32_RESET(APB2, 13)>;
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
@@ -317,7 +317,7 @@
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 18)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 18U)>;
+ resets = <&rctl STM32_RESET(APB2, 18)>;
interrupts = <26 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -395,7 +395,7 @@
reg = <0x50062400 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 22)>,
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
- resets = <&rctl STM32_RESET(AHB2, 22U)>;
+ resets = <&rctl STM32_RESET(AHB2, 22)>;
interrupts = <49 0>;
idma;
status = "disabled";
@@ -406,7 +406,7 @@
reg = <0x50062800 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 23)>,
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
- resets = <&rctl STM32_RESET(AHB2, 23U)>;
+ resets = <&rctl STM32_RESET(AHB2, 23)>;
interrupts = <47 0>;
idma;
status = "disabled";
diff --git a/dts/arm/st/l4/stm32l4q5.dtsi b/dts/arm/st/l4/stm32l4q5.dtsi
index 4816739..549d105 100644
--- a/dts/arm/st/l4/stm32l4q5.dtsi
+++ b/dts/arm/st/l4/stm32l4q5.dtsi
@@ -14,7 +14,7 @@
compatible = "st,stm32l4-aes", "st,stm32-aes";
reg = <0x50060000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 16)>;
- resets = <&rctl STM32_RESET(AHB2, 16U)>;
+ resets = <&rctl STM32_RESET(AHB2, 16)>;
interrupts = <79 0>;
interrupt-names = "aes";
status = "disabled";
diff --git a/dts/arm/st/l4/stm32l4r9.dtsi b/dts/arm/st/l4/stm32l4r9.dtsi
index 5a67d82..1f89d00 100644
--- a/dts/arm/st/l4/stm32l4r9.dtsi
+++ b/dts/arm/st/l4/stm32l4r9.dtsi
@@ -18,7 +18,7 @@
interrupts = <91 0>, <92 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK(APB2, 26)>;
- resets = <&rctl STM32_RESET(APB2, 26U)>;
+ resets = <&rctl STM32_RESET(APB2, 26)>;
status = "disabled";
};
};
diff --git a/dts/arm/st/l4/stm32l4s5.dtsi b/dts/arm/st/l4/stm32l4s5.dtsi
index c558b66..f7bb987 100644
--- a/dts/arm/st/l4/stm32l4s5.dtsi
+++ b/dts/arm/st/l4/stm32l4s5.dtsi
@@ -14,7 +14,7 @@
compatible = "st,stm32l4-aes", "st,stm32-aes";
reg = <0x50060000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 16)>;
- resets = <&rctl STM32_RESET(AHB2, 16U)>;
+ resets = <&rctl STM32_RESET(AHB2, 16)>;
interrupts = <79 0>;
interrupt-names = "aes";
status = "disabled";
