interrupt-controller: intc_esp32c3: make logs optional
Allowing cleaner debug experience and preventing unwanted
outputs during debug.
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
diff --git a/drivers/interrupt_controller/Kconfig.esp32c3 b/drivers/interrupt_controller/Kconfig.esp32c3
index 1022dec..365b16f 100644
--- a/drivers/interrupt_controller/Kconfig.esp32c3
+++ b/drivers/interrupt_controller/Kconfig.esp32c3
@@ -8,3 +8,13 @@
help
Enables the esp32c3 interrupt controller driver to handle ISR
management at SoC level.
+
+config INTC_ESP32C3_DECISIONS_LOG
+ bool "Enables Espressif's interrupt allocator logging"
+ depends on INTC_ESP32C3
+ select LOG
+ help
+ Enable this option to visualize information on decisions made by the
+ interrupt allocator. This has no impact on the interrupt allocator usage
+ but may be valuable for debugging purposes. When enabled, messages are
+ print to the serial console.
diff --git a/drivers/interrupt_controller/intc_esp32c3.c b/drivers/interrupt_controller/intc_esp32c3.c
index 4883841..78e53e3 100644
--- a/drivers/interrupt_controller/intc_esp32c3.c
+++ b/drivers/interrupt_controller/intc_esp32c3.c
@@ -21,6 +21,17 @@
#include <logging/log.h>
LOG_MODULE_REGISTER(intc_esp32c3, CONFIG_LOG_DEFAULT_LEVEL);
+/*
+ * Define this to debug the choices made when allocating the interrupt. This leads to much debugging
+ * output within a critical region, which can lead to weird effects like e.g. the interrupt watchdog
+ * being triggered, that is why it is separate from the normal LOG* scheme.
+ */
+#ifdef CONFIG_INTC_ESP32C3_DECISIONS_LOG
+# define INTC_LOG(...) LOG_INF(__VA_ARGS__)
+#else
+# define INTC_LOG(...) do {} while (0)
+#endif
+
#define ESP32C3_INTC_DEFAULT_PRIORITY 15
#define ESP32C3_INTC_DEFAULT_THRESHOLD 1
#define ESP32C3_INTC_DISABLED_SLOT 31
@@ -37,7 +48,7 @@
__asm__ volatile("csrr %0, mcause" : "=r" (mcause));
mcause &= SOC_MCAUSE_EXP_MASK;
- LOG_DBG("Spurious interrupt, mcause: %ld, source %d", mcause, soc_intr_get_next_source());
+ INTC_LOG("Spurious interrupt, mcause: %ld, source %d", mcause, soc_intr_get_next_source());
}
static uint32_t esp_intr_find_irq_for_source(uint32_t source)
@@ -48,13 +59,13 @@
uint32_t irq = (source / ESP32C3_INTC_SRCS_PER_IRQ);
if (irq > ESP32C3_INTC_AVAILABLE_IRQS) {
- LOG_DBG("Clamping the source: %d no more IRQs available", source);
+ INTC_LOG("Clamping the source: %d no more IRQs available", source);
irq = ESP32C3_INTC_AVAILABLE_IRQS;
} else if (irq == 0) {
irq = 1;
}
- LOG_DBG("Found IRQ: %d for source: %d", irq, source);
+ INTC_LOG("Found IRQ: %d for source: %d", irq, source);
return irq;
}
@@ -118,7 +129,7 @@
esp_intr_enabled_mask[1] |= (1 << (source - 32));
}
- LOG_DBG("Enabled isrs -- 0: 0x%X -- 1: 0x%X",
+ INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X",
esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]);
irq_unlock(key);
@@ -145,7 +156,7 @@
esp_intr_enabled_mask[1] &= ~(1 << (source - 32));
}
- LOG_DBG("Enabled isrs -- 0: 0x%X -- 1: 0x%X",
+ INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X",
esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]);
irq_unlock(key);
@@ -171,7 +182,7 @@
esp_intr_enabled_mask[1] |= (1 << (source - 32));
}
- LOG_DBG("Enabled isrs -- 0: 0x%X -- 1: 0x%X",
+ INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X",
esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]);
irq_enable(irq);
@@ -182,7 +193,7 @@
uint32_t esp_intr_get_enabled_intmask(int status_mask_number)
{
- LOG_DBG("Enabled isrs -- 0: 0x%X -- 1: 0x%X",
+ INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X",
esp_intr_enabled_mask[0], esp_intr_enabled_mask[1]);
if (status_mask_number == 0) {
diff --git a/include/drivers/interrupt_controller/intc_esp32c3.h b/include/drivers/interrupt_controller/intc_esp32c3.h
index 761f1df..d548444 100644
--- a/include/drivers/interrupt_controller/intc_esp32c3.h
+++ b/include/drivers/interrupt_controller/intc_esp32c3.h
@@ -13,7 +13,6 @@
/*
* Interrupt allocation flags - These flags can be used to specify
* which interrupt qualities the code calling esp_intr_alloc* needs.
- *
*/
/* Keep the LEVELx values as they are here; they match up with (1<<level) */
diff --git a/include/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h b/include/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h
index 64e524c..f5e2cd6 100644
--- a/include/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h
+++ b/include/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h
@@ -7,67 +7,67 @@
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C3_INTMUX_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C3_INTMUX_H_
-#define WIFI_MAC_INTR_SOURCE 0 /**< interrupt of WiFi MAC, level*/
-#define WIFI_MAC_NMI_SOURCE 1 /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
-#define WIFI_PWR_INTR_SOURCE 2 /**< */
-#define WIFI_BB_INTR_SOURCE 3 /**< interrupt of WiFi BB, level, we can do some calibartion*/
-#define BT_MAC_INTR_SOURCE 4 /**< will be cancelled*/
-#define BT_BB_INTR_SOURCE 5 /**< interrupt of BT BB, level*/
-#define BT_BB_NMI_SOURCE 6 /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
-#define RWBT_INTR_SOURCE 7 /**< interrupt of RWBT, level*/
-#define RWBLE_INTR_SOURCE 8 /**< interrupt of RWBLE, level*/
-#define RWBT_NMI_SOURCE 9 /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
-#define RWBLE_NMI_SOURCE 10 /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
-#define I2C_MASTER_SOURCE 11 /**< interrupt of I2C Master, level*/
-#define SLC0_INTR_SOURCE 12 /**< interrupt of SLC0, level*/
-#define SLC1_INTR_SOURCE 13 /**< interrupt of SLC1, level*/
-#define APB_CTRL_INTR_SOURCE 14 /**< interrupt of APB ctrl, ?*/
-#define UHCI0_INTR_SOURCE 15 /**< interrupt of UHCI0, level*/
-#define GPIO_INTR_SOURCE 16 /**< interrupt of GPIO, level*/
-#define GPIO_NMI_SOURCE 17 /**< interrupt of GPIO, NMI*/
-#define SPI1_INTR_SOURCE 18 /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
-#define SPI2_INTR_SOURCE 19 /**< interrupt of SPI2, level*/
-#define I2S1_INTR_SOURCE 20 /**< interrupt of I2S1, level*/
-#define UART0_INTR_SOURCE 21 /**< interrupt of UART0, level*/
-#define UART1_INTR_SOURCE 22 /**< interrupt of UART1, level*/
-#define LEDC_INTR_SOURCE 23 /**< interrupt of LED PWM, level*/
-#define EFUSE_INTR_SOURCE 24 /**< interrupt of efuse, level, not likely to use*/
-#define TWAI_INTR_SOURCE 25 /**< interrupt of can, level*/
-#define USB_INTR_SOURCE 26 /**< interrupt of USB, level*/
-#define RTC_CORE_INTR_SOURCE 27 /**< interrupt of rtc core, level, include rtc watchdog*/
-#define RMT_INTR_SOURCE 28 /**< interrupt of remote controller, level*/
-#define I2C_EXT0_INTR_SOURCE 29 /**< interrupt of I2C controller1, level*/
-#define TIMER1_INTR_SOURCE 30
-#define TIMER2_INTR_SOURCE 31
-#define TG0_T0_LEVEL_INTR_SOURCE 32 /**< interrupt of TIMER_GROUP0, TIMER0, level*/
-#define TG0_WDT_LEVEL_INTR_SOURCE 33 /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
-#define TG1_T0_LEVEL_INTR_SOURCE 34 /**< interrupt of TIMER_GROUP1, TIMER0, level*/
-#define TG1_WDT_LEVEL_INTR_SOURCE 35 /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
-#define CACHE_IA_INTR_SOURCE 36 /**< interrupt of Cache Invalied Access, LEVEL*/
-#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 37 /**< interrupt of system timer 0, EDGE*/
-#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 38 /**< interrupt of system timer 1, EDGE*/
-#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 39 /**< interrupt of system timer 2, EDGE*/
-#define SPI_MEM_REJECT_CACHE_INTR_SOURCE 40 /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
-#define ICACHE_PRELOAD0_INTR_SOURCE 41 /**< interrupt of ICache perload operation, LEVEL*/
-#define ICACHE_SYNC0_INTR_SOURCE 42 /**< interrupt of instruction cache sync done, LEVEL*/
-#define APB_ADC_INTR_SOURCE 43 /**< interrupt of APB ADC, LEVEL*/
-#define DMA_CH0_INTR_SOURCE 44 /**< interrupt of general DMA channel 0, LEVEL*/
-#define DMA_CH1_INTR_SOURCE 45 /**< interrupt of general DMA channel 1, LEVEL*/
-#define DMA_CH2_INTR_SOURCE 46 /**< interrupt of general DMA channel 2, LEVEL*/
-#define RSA_INTR_SOURCE 47 /**< interrupt of RSA accelerator, level*/
-#define AES_INTR_SOURCE 48 /**< interrupt of AES accelerator, level*/
-#define SHA_INTR_SOURCE 49 /**< interrupt of SHA accelerator, level*/
-#define FROM_CPU_INTR0_SOURCE 50 /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
-#define FROM_CPU_INTR1_SOURCE 51 /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
-#define FROM_CPU_INTR2_SOURCE 52 /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
-#define FROM_CPU_INTR3_SOURCE 53 /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
-#define ASSIST_DEBUG_INTR_SOURCE 54 /**< interrupt of Assist debug module, LEVEL*/
-#define DMA_APBPERI_PMS_INTR_SOURCE 55
-#define CORE0_IRAM0_PMS_INTR_SOURCE 56
-#define CORE0_DRAM0_PMS_INTR_SOURCE 57
-#define CORE0_PIF_PMS_INTR_SOURCE 58
-#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 59
-#define BAK_PMS_VIOLATE_INTR_SOURCE 60
-#define CACHE_CORE0_ACS_INTR_SOURCE 61
+#define WIFI_MAC_INTR_SOURCE 0
+#define WIFI_MAC_NMI_SOURCE 1
+#define WIFI_PWR_INTR_SOURCE 2
+#define WIFI_BB_INTR_SOURCE 3
+#define BT_MAC_INTR_SOURCE 4
+#define BT_BB_INTR_SOURCE 5
+#define BT_BB_NMI_SOURCE 6
+#define RWBT_INTR_SOURCE 7
+#define RWBLE_INTR_SOURCE 8
+#define RWBT_NMI_SOURCE 9
+#define RWBLE_NMI_SOURCE 10
+#define I2C_MASTER_SOURCE 11
+#define SLC0_INTR_SOURCE 12
+#define SLC1_INTR_SOURCE 13
+#define APB_CTRL_INTR_SOURCE 14
+#define UHCI0_INTR_SOURCE 15
+#define GPIO_INTR_SOURCE 16
+#define GPIO_NMI_SOURCE 17
+#define SPI1_INTR_SOURCE 18
+#define SPI2_INTR_SOURCE 19
+#define I2S1_INTR_SOURCE 20
+#define UART0_INTR_SOURCE 21
+#define UART1_INTR_SOURCE 22
+#define LEDC_INTR_SOURCE 23
+#define EFUSE_INTR_SOURCE 24
+#define TWAI_INTR_SOURCE 25
+#define USB_INTR_SOURCE 26
+#define RTC_CORE_INTR_SOURCE 27
+#define RMT_INTR_SOURCE 28
+#define I2C_EXT0_INTR_SOURCE 29
+#define TIMER1_INTR_SOURCE 30
+#define TIMER2_INTR_SOURCE 31
+#define TG0_T0_LEVEL_INTR_SOURCE 32
+#define TG0_WDT_LEVEL_INTR_SOURCE 33
+#define TG1_T0_LEVEL_INTR_SOURCE 34
+#define TG1_WDT_LEVEL_INTR_SOURCE 35
+#define CACHE_IA_INTR_SOURCE 36
+#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 37
+#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 38
+#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 39
+#define SPI_MEM_REJECT_CACHE_INTR_SOURCE 40
+#define ICACHE_PRELOAD0_INTR_SOURCE 41
+#define ICACHE_SYNC0_INTR_SOURCE 42
+#define APB_ADC_INTR_SOURCE 43
+#define DMA_CH0_INTR_SOURCE 44
+#define DMA_CH1_INTR_SOURCE 45
+#define DMA_CH2_INTR_SOURCE 46
+#define RSA_INTR_SOURCE 47
+#define AES_INTR_SOURCE 48
+#define SHA_INTR_SOURCE 49
+#define FROM_CPU_INTR0_SOURCE 50
+#define FROM_CPU_INTR1_SOURCE 51
+#define FROM_CPU_INTR2_SOURCE 52
+#define FROM_CPU_INTR3_SOURCE 53
+#define ASSIST_DEBUG_INTR_SOURCE 54
+#define DMA_APBPERI_PMS_INTR_SOURCE 55
+#define CORE0_IRAM0_PMS_INTR_SOURCE 56
+#define CORE0_DRAM0_PMS_INTR_SOURCE 57
+#define CORE0_PIF_PMS_INTR_SOURCE 58
+#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 59
+#define BAK_PMS_VIOLATE_INTR_SOURCE 60
+#define CACHE_CORE0_ACS_INTR_SOURCE 61
#endif
