drivers: pinctrl: Support pinctrl with GD32VF103
Change the settings to support pinctrl on the GD32VF103.
- Split soc/arm/gigadevice/common/pinctrl_soc.h
and put it into include/dt-bindings.
- Leave some definitions that can't handle with device tree compiler
in pinctrl_soc.h.
- Remove dependency to SOC_FAMILY_GD32 because always enabled it
if GD32_HAS_AF(IO)_PINMAX was selected.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
diff --git a/drivers/pinctrl/Kconfig.gd32 b/drivers/pinctrl/Kconfig.gd32
index 7822033..d9bcc49 100644
--- a/drivers/pinctrl/Kconfig.gd32
+++ b/drivers/pinctrl/Kconfig.gd32
@@ -6,7 +6,7 @@
config PINCTRL_GD32_AF
bool "GD32 AF pin controller driver"
- depends on SOC_FAMILY_GD32 && GD32_HAS_AF_PINMUX
+ depends on GD32_HAS_AF_PINMUX
default $(dt_compat_enabled,$(DT_COMPAT_GIGADEVICE_GD32_PINCTRL_AF))
help
GD32 AF pin controller driver. This driver is used by series using the
@@ -14,7 +14,7 @@
config PINCTRL_GD32_AFIO
bool "GD32 AFIO pin controller driver"
- depends on SOC_FAMILY_GD32 && GD32_HAS_AFIO_PINMUX
+ depends on GD32_HAS_AFIO_PINMUX
default $(dt_compat_enabled,$(DT_COMPAT_GIGADEVICE_GD32_PINCTRL_AFIO))
help
GD32 AFIO pin controller driver. This driver is used by series using the
diff --git a/dts/riscv/gigadevice/gd32vf103.dtsi b/dts/riscv/gigadevice/gd32vf103.dtsi
index 75212e6..d6051de 100644
--- a/dts/riscv/gigadevice/gd32vf103.dtsi
+++ b/dts/riscv/gigadevice/gd32vf103.dtsi
@@ -53,5 +53,72 @@
write-block-size = <2>;
};
};
+
+ afio: afio@40010000 {
+ compatible = "gd,gd32-afio";
+ reg = <0x40010000 0x400>;
+ rcu-periph-clock = <0x600>;
+ status = "okay";
+ label = "AFIO";
+ };
+
+ pinctrl: pin-controller@40010800 {
+ compatible = "gd,gd32-pinctrl-afio";
+ reg = <0x40010800 0x1c00>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "okay";
+ label = "PINCTRL";
+
+ gpioa: gpio@40010800 {
+ compatible = "gd,gd32-gpio";
+ reg = <0x40010800 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ rcu-periph-clock = <0x602>;
+ status = "disabled";
+ label = "GPIOA";
+ };
+
+ gpiob: gpio@40010c00 {
+ compatible = "gd,gd32-gpio";
+ reg = <0x40010c00 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ rcu-periph-clock = <0x603>;
+ status = "disabled";
+ label = "GPIOB";
+ };
+
+ gpioc: gpio@40011000 {
+ compatible = "gd,gd32-gpio";
+ reg = <0x40011000 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ rcu-periph-clock = <0x604>;
+ status = "disabled";
+ label = "GPIOC";
+ };
+
+ gpiod: gpio@40011400 {
+ compatible = "gd,gd32-gpio";
+ reg = <0x40011400 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ rcu-periph-clock = <0x605>;
+ status = "disabled";
+ label = "GPIOD";
+ };
+
+ gpioe: gpio@40011800 {
+ compatible = "gd,gd32-gpio";
+ reg = <0x40011800 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ rcu-periph-clock = <0x606>;
+ status = "disabled";
+ label = "GPIOE";
+ };
+ };
};
};
diff --git a/include/drivers/pinctrl/pinctrl_soc_gd32_common.h b/include/drivers/pinctrl/pinctrl_soc_gd32_common.h
new file mode 100644
index 0000000..9ec61d2
--- /dev/null
+++ b/include/drivers/pinctrl/pinctrl_soc_gd32_common.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2021 Teslabs Engineering S.L.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * Gigadevice SoC specific helpers for pinctrl driver
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_
+#define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_
+
+#include <devicetree.h>
+#include <zephyr/types.h>
+
+#ifdef CONFIG_PINCTRL_GD32_AF
+#include <dt-bindings/pinctrl/gd32-af.h>
+#else
+#include <dt-bindings/pinctrl/gd32-afio.h>
+#endif /* CONFIG_PINCTRL_GD32_AF */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @cond INTERNAL_HIDDEN */
+
+/** @brief Type for GD32 pin.
+ *
+ * Bits (AF model):
+ * - 0-12: GD32_PINMUX_AF bit field.
+ * - 13-25: Reserved.
+ * - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
+ *
+ * Bits (AFIO model):
+ * - 0-19: GD32_PINMUX_AFIO bit field.
+ * - 20-25: Reserved.
+ * - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
+ */
+typedef uint32_t pinctrl_soc_pin_t;
+
+/**
+ * @brief Utility macro to initialize each pin.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name.
+ * @param idx Property entry index.
+ */
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
+ (DT_PROP_BY_IDX(node_id, prop, idx) | \
+ ((GD32_PUPD_PULLUP * DT_PROP(node_id, bias_pull_up)) \
+ << GD32_PUPD_POS) | \
+ ((GD32_PUPD_PULLDOWN * DT_PROP(node_id, bias_pull_down)) \
+ << GD32_PUPD_POS) | \
+ ((GD32_OTYPE_OD * DT_PROP(node_id, drive_open_drain)) \
+ << GD32_OTYPE_POS) | \
+ (DT_ENUM_IDX(node_id, slew_rate) << GD32_OSPEED_POS)),
+
+/**
+ * @brief Utility macro to initialize state pins contained in a given property.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name describing state pins.
+ */
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
+ {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
+ DT_FOREACH_PROP_ELEM, pinmux, \
+ Z_PINCTRL_STATE_PIN_INIT)}
+
+/** @endcond */
+
+/**
+ * @name GD32 PUPD (values match the ones in the HAL for AF model).
+ * @{
+ */
+
+/** No pull-up/down */
+#define GD32_PUPD_NONE 0U
+/** Pull-up */
+#define GD32_PUPD_PULLUP 1U
+/** Pull-down */
+#define GD32_PUPD_PULLDOWN 2U
+
+/** @} */
+
+/**
+ * @name GD32 OTYPE (values match the ones in the HAL for AF model).
+ * @{
+ */
+
+/** Push-pull */
+#define GD32_OTYPE_PP 0U
+/** Open-drain */
+#define GD32_OTYPE_OD 1U
+
+/** @} */
+
+/**
+ * @name GD32 OSPEED (values match the ones in the HAL for AF model, mode minus
+ * one for AFIO model).
+ * @{
+ */
+
+#ifdef CONFIG_PINCTRL_GD32_AF
+/** Maximum 2MHz */
+#define GD32_OSPEED_2MHZ 0U
+#ifdef CONFIG_SOC_SERIES_GD32F3X0
+/** Maximum 10MHz */
+#define GD32_OSPEED_10MHZ 1U
+/** Maximum 50MHz */
+#define GD32_OSPEED_50MHZ 3U
+#else
+/** Maximum 25MHz */
+#define GD32_OSPEED_25MHZ 1U
+/** Maximum 50MHz */
+#define GD32_OSPEED_50MHZ 2U
+/** Maximum 200MHz */
+#define GD32_OSPEED_200MHZ 3U
+#endif /* CONFIG_SOC_SERIES_GD32F3X0 */
+#else
+/** Maximum 10MHz */
+#define GD32_OSPEED_10MHZ 0U
+/** Maximum 2MHz */
+#define GD32_OSPEED_2MHZ 1U
+/** Maximum 50MHz */
+#define GD32_OSPEED_50MHZ 2U
+/** Maximum speed */
+#define GD32_OSPEED_MAX 3U
+#endif /* CONFIG_PINCTRL_GD32_AF */
+
+/** @} */
+
+/**
+ * @name GD32 pin configuration bit field mask and positions.
+ * @anchor GD32_PINCFG
+ *
+ * Fields:
+ *
+ * - 31..29: Pull-up/down
+ * - 28: Output type
+ * - 27..26: Output speed
+ *
+ * @{
+ */
+
+/** PUPD field mask. */
+#define GD32_PUPD_MSK 0x3U
+/** PUPD field position. */
+#define GD32_PUPD_POS 29U
+/** OTYPE field mask. */
+#define GD32_OTYPE_MSK 0x1U
+/** OTYPE field position. */
+#define GD32_OTYPE_POS 28U
+/** OSPEED field mask. */
+#define GD32_OSPEED_MSK 0x3U
+/** OSPEED field position. */
+#define GD32_OSPEED_POS 26U
+
+/** @} */
+
+/**
+ * Obtain PUPD field from pinctrl_soc_pin_t configuration.
+ *
+ * @param pincfg pinctrl_soc_pin_t bit field value.
+ */
+#define GD32_PUPD_GET(pincfg) \
+ (((pincfg) >> GD32_PUPD_POS) & GD32_PUPD_MSK)
+
+/**
+ * Obtain OTYPE field from pinctrl_soc_pin_t configuration.
+ *
+ * @param pincfg pinctrl_soc_pin_t bit field value.
+ */
+#define GD32_OTYPE_GET(pincfg) \
+ (((pincfg) >> GD32_OTYPE_POS) & GD32_OTYPE_MSK)
+
+/**
+ * Obtain OSPEED field from pinctrl_soc_pin_t configuration.
+ *
+ * @param pincfg pinctrl_soc_pin_t bit field value.
+ */
+#define GD32_OSPEED_GET(pincfg) \
+ (((pincfg) >> GD32_OSPEED_POS) & GD32_OSPEED_MSK)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_GD32_COMMON_H_ */
diff --git a/soc/arm/gigadevice/common/pinctrl_soc.h b/soc/arm/gigadevice/common/pinctrl_soc.h
index 331986b..e552ae4 100644
--- a/soc/arm/gigadevice/common/pinctrl_soc.h
+++ b/soc/arm/gigadevice/common/pinctrl_soc.h
@@ -12,180 +12,6 @@
#ifndef ZEPHYR_SOC_ARM_GIGADEVICE_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_GIGADEVICE_COMMON_PINCTRL_SOC_H_
-#include <devicetree.h>
-#include <zephyr/types.h>
-
-#ifdef CONFIG_PINCTRL_GD32_AF
-#include <dt-bindings/pinctrl/gd32-af.h>
-#else
-#include <dt-bindings/pinctrl/gd32-afio.h>
-#endif /* CONFIG_PINCTRL_GD32_AF */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @cond INTERNAL_HIDDEN */
-
-/** @brief Type for GD32 pin.
- *
- * Bits (AF model):
- * - 0-12: GD32_PINMUX_AF bit field.
- * - 13-25: Reserved.
- * - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
- *
- * Bits (AFIO model):
- * - 0-19: GD32_PINMUX_AFIO bit field.
- * - 20-25: Reserved.
- * - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
- */
-typedef uint32_t pinctrl_soc_pin_t;
-
-/**
- * @brief Utility macro to initialize each pin.
- *
- * @param node_id Node identifier.
- * @param prop Property name.
- * @param idx Property entry index.
- */
-#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
- (DT_PROP_BY_IDX(node_id, prop, idx) | \
- ((GD32_PUPD_PULLUP * DT_PROP(node_id, bias_pull_up)) \
- << GD32_PUPD_POS) | \
- ((GD32_PUPD_PULLDOWN * DT_PROP(node_id, bias_pull_down)) \
- << GD32_PUPD_POS) | \
- ((GD32_OTYPE_OD * DT_PROP(node_id, drive_open_drain)) \
- << GD32_OTYPE_POS) | \
- (DT_ENUM_IDX(node_id, slew_rate) << GD32_OSPEED_POS)),
-
-/**
- * @brief Utility macro to initialize state pins contained in a given property.
- *
- * @param node_id Node identifier.
- * @param prop Property name describing state pins.
- */
-#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
- {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
- DT_FOREACH_PROP_ELEM, pinmux, \
- Z_PINCTRL_STATE_PIN_INIT)}
-
-/** @endcond */
-
-/**
- * @name GD32 PUPD (values match the ones in the HAL for AF model).
- * @{
- */
-
-/** No pull-up/down */
-#define GD32_PUPD_NONE 0U
-/** Pull-up */
-#define GD32_PUPD_PULLUP 1U
-/** Pull-down */
-#define GD32_PUPD_PULLDOWN 2U
-
-/** @} */
-
-/**
- * @name GD32 OTYPE (values match the ones in the HAL for AF model).
- * @{
- */
-
-/** Push-pull */
-#define GD32_OTYPE_PP 0U
-/** Open-drain */
-#define GD32_OTYPE_OD 1U
-
-/** @} */
-
-/**
- * @name GD32 OSPEED (values match the ones in the HAL for AF model, mode minus
- * one for AFIO model).
- * @{
- */
-
-#ifdef CONFIG_PINCTRL_GD32_AF
-/** Maximum 2MHz */
-#define GD32_OSPEED_2MHZ 0U
-#ifdef CONFIG_SOC_SERIES_GD32F3X0
-/** Maximum 10MHz */
-#define GD32_OSPEED_10MHZ 1U
-/** Maximum 50MHz */
-#define GD32_OSPEED_50MHZ 3U
-#else
-/** Maximum 25MHz */
-#define GD32_OSPEED_25MHZ 1U
-/** Maximum 50MHz */
-#define GD32_OSPEED_50MHZ 2U
-/** Maximum 200MHz */
-#define GD32_OSPEED_200MHZ 3U
-#endif /* CONFIG_SOC_SERIES_GD32F3X0 */
-#else
-/** Maximum 10MHz */
-#define GD32_OSPEED_10MHZ 0U
-/** Maximum 2MHz */
-#define GD32_OSPEED_2MHZ 1U
-/** Maximum 50MHz */
-#define GD32_OSPEED_50MHZ 2U
-/** Maximum speed */
-#define GD32_OSPEED_MAX 3U
-#endif /* CONFIG_PINCTRL_GD32_AF */
-
-/** @} */
-
-/**
- * @name GD32 pin configuration bit field mask and positions.
- * @anchor GD32_PINCFG
- *
- * Fields:
- *
- * - 31..29: Pull-up/down
- * - 28: Output type
- * - 27..26: Output speed
- *
- * @{
- */
-
-/** PUPD field mask. */
-#define GD32_PUPD_MSK 0x3U
-/** PUPD field position. */
-#define GD32_PUPD_POS 29U
-/** OTYPE field mask. */
-#define GD32_OTYPE_MSK 0x1U
-/** OTYPE field position. */
-#define GD32_OTYPE_POS 28U
-/** OSPEED field mask. */
-#define GD32_OSPEED_MSK 0x3U
-/** OSPEED field position. */
-#define GD32_OSPEED_POS 26U
-
-/** @} */
-
-/**
- * Obtain PUPD field from pinctrl_soc_pin_t configuration.
- *
- * @param pincfg pinctrl_soc_pin_t bit field value.
- */
-#define GD32_PUPD_GET(pincfg) \
- (((pincfg) >> GD32_PUPD_POS) & GD32_PUPD_MSK)
-
-/**
- * Obtain OTYPE field from pinctrl_soc_pin_t configuration.
- *
- * @param pincfg pinctrl_soc_pin_t bit field value.
- */
-#define GD32_OTYPE_GET(pincfg) \
- (((pincfg) >> GD32_OTYPE_POS) & GD32_OTYPE_MSK)
-
-/**
- * Obtain OSPEED field from pinctrl_soc_pin_t configuration.
- *
- * @param pincfg pinctrl_soc_pin_t bit field value.
- */
-#define GD32_OSPEED_GET(pincfg) \
- (((pincfg) >> GD32_OSPEED_POS) & GD32_OSPEED_MSK)
-
-#ifdef __cplusplus
-}
-#endif
+#include <drivers/pinctrl/pinctrl_soc_gd32_common.h>
#endif /* ZEPHYR_SOC_ARM_GIGADEVICE_COMMON_PINCTRL_SOC_H_ */
diff --git a/soc/riscv/riscv-privilege/gd32vf103/Kconfig.defconfig.gd32vf103 b/soc/riscv/riscv-privilege/gd32vf103/Kconfig.defconfig.gd32vf103
index d749de7..3983705 100644
--- a/soc/riscv/riscv-privilege/gd32vf103/Kconfig.defconfig.gd32vf103
+++ b/soc/riscv/riscv-privilege/gd32vf103/Kconfig.defconfig.gd32vf103
@@ -36,4 +36,7 @@
config FLASH_BASE_ADDRESS
default $(dt_node_reg_addr_hex,flash0@8000000)
+config PINCTRL
+ default y
+
endif # GD32VF103
diff --git a/soc/riscv/riscv-privilege/gd32vf103/pinctrl_soc.h b/soc/riscv/riscv-privilege/gd32vf103/pinctrl_soc.h
new file mode 100644
index 0000000..5feaded
--- /dev/null
+++ b/soc/riscv/riscv-privilege/gd32vf103/pinctrl_soc.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * Gigadevice SoC specific helpers for pinctrl driver
+ */
+
+#ifndef ZEPHYR_SOC_RISCV_RISCV_PRIVILEGE_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_RISCV_RISCV_PRIVILEGE_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_
+
+#include <drivers/pinctrl/pinctrl_soc_gd32_common.h>
+
+#endif /* ZEPHYR_SOC_RISCV_RISCV_PRIVILEGE_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_ */
