dts: bindings: nxp,kinetis-pinmux: Update binding for pin data
Update the binding for how we represent pin data to support child
nodes with a nxp,kinetis-pins property that has the pin data.
For example:
UART0_CTS_PTA0: uart0_cts_pta0 {
nxp,kinetis-port-pins = < 0 2 >;
};
Also pull in pincfg-node.yaml to get various common pin flags like
"bias-pull-up", "drive-open-drain", etc.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
diff --git a/dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml b/dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml
index bc7d125..fc236da 100644
--- a/dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml
+++ b/dts/bindings/pinctrl/nxp,kinetis-pinmux.yaml
@@ -2,7 +2,9 @@
compatible: "nxp,kinetis-pinmux"
-include: base.yaml
+include:
+ - name: base.yaml
+ - name: pincfg-node.yaml
properties:
reg:
@@ -11,6 +13,27 @@
clocks:
required: true
-pinmux-cells:
- - pin
- - function
+child-binding:
+ description: |
+ NXP Kinetis Pin data. A series of child nodes that describe each pin
+ configuration supported by the SoC. Each node is expected to named as
+ follows - <periph>_<signal>_pt<port><pin>
+
+ The node will have a matching node label that board dtsi files can
+ utilized to reference in pinctrl-<N> properties.
+
+ The following is an example for UART0 CTS signal on pin 0, with mux
+ value of 2.
+
+ uart0_cts_pta0: uart0_cts_pta0 {
+ nxp,kinetis-port-pins = < 0 2 >;
+ };
+
+ properties:
+ "nxp,kinetis-port-pins":
+ description: |
+ The array is expected to have two elements. The first element is the
+ pin number and the second element is the mux value (i.e. PCR[MUX]).
+
+ type: array
+ required: true
