soc/arm: st_stm32: Add stm32u5 SoC series Add minimal support for STM32U5 series. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
diff --git a/soc/arm/st_stm32/stm32u5/CMakeLists.txt b/soc/arm/st_stm32/stm32u5/CMakeLists.txt new file mode 100644 index 0000000..ac3ba70 --- /dev/null +++ b/soc/arm/st_stm32/stm32u5/CMakeLists.txt
@@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + )
diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.series new file mode 100644 index 0000000..b2be2f0 --- /dev/null +++ b/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.series
@@ -0,0 +1,13 @@ +# ST Microelectronics STM32U5 MCU line + +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32U5X + +source "soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5*" + +config SOC_SERIES + default "stm32u5" + +endif # SOC_SERIES_STM32U5X
diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u575xx b/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u575xx new file mode 100644 index 0000000..47c6111 --- /dev/null +++ b/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u575xx
@@ -0,0 +1,14 @@ +# ST Microelectronics STM32U575XX MCU + +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32U575XX + +config SOC + default "stm32u575xx" + +config NUM_IRQS + default 125 + +endif # SOC_STM32U575XX
diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.series b/soc/arm/st_stm32/stm32u5/Kconfig.series new file mode 100644 index 0000000..69082b7 --- /dev/null +++ b/soc/arm/st_stm32/stm32u5/Kconfig.series
@@ -0,0 +1,19 @@ +# ST Microelectronics STM32U5 MCU series + +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32U5X + bool "STM32U5x Series MCU" + select ARM + select CPU_CORTEX_M33 + select SOC_FAMILY_STM32 + select ARM_TRUSTZONE_M + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + help + Enable support for STM32U5 MCU series
diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.soc b/soc/arm/st_stm32/stm32u5/Kconfig.soc new file mode 100644 index 0000000..c1a5a8f --- /dev/null +++ b/soc/arm/st_stm32/stm32u5/Kconfig.soc
@@ -0,0 +1,13 @@ +# ST Microelectronics STM32U5 MCU line + +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +choice +prompt "STM32U5x MCU Selection" +depends on SOC_SERIES_STM32U5X + +config SOC_STM32U575XX + bool "STM32U575XX" + +endchoice
diff --git a/soc/arm/st_stm32/stm32u5/linker.ld b/soc/arm/st_stm32/stm32u5/linker.ld new file mode 100644 index 0000000..f2d9eb7 --- /dev/null +++ b/soc/arm/st_stm32/stm32u5/linker.ld
@@ -0,0 +1,9 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2021 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>
diff --git a/soc/arm/st_stm32/stm32u5/soc.c b/soc/arm/st_stm32/stm32u5/soc.c new file mode 100644 index 0000000..dcce2b4 --- /dev/null +++ b/soc/arm/st_stm32/stm32u5/soc.c
@@ -0,0 +1,67 @@ +/* + * Copyright (c) 2021 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for STM32U5 processor + */ + +#include <device.h> +#include <init.h> +#include <stm32_ll_bus.h> +#include <stm32_ll_pwr.h> +#include <stm32_ll_icache.h> +#include <arch/cpu.h> +#include <arch/arm/aarch32/cortex_m/cmsis.h> + +#include <logging/log.h> + +#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL +LOG_MODULE_REGISTER(soc); + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int stm32u5_init(const struct device *arg) +{ + uint32_t key; + + ARG_UNUSED(arg); + + key = irq_lock(); + + /* Install default handler that simply resets the CPU + * if configured in the kernel, NOP otherwise + */ + NMI_INIT(); + + irq_unlock(key); + + /* Enable instruction cache in 1-way (direct mapped cache) */ + LL_ICACHE_SetMode(LL_ICACHE_1WAY); + LL_ICACHE_Enable(); + + /* Update CMSIS SystemCoreClock variable (HCLK) */ + /* At reset, system core clock is set to 4 MHz from MSIS */ + SystemCoreClock = 4000000; + + /* Enable PWR */ + LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR); + + /* Disable USB Type-C dead battery pull-down behavior */ + LL_PWR_DisableUCPDDeadBattery(); + + LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1); + + return 0; +} + +SYS_INIT(stm32u5_init, PRE_KERNEL_1, 0);
diff --git a/soc/arm/st_stm32/stm32u5/soc.h b/soc/arm/st_stm32/stm32u5/soc.h new file mode 100644 index 0000000..0a4c908 --- /dev/null +++ b/soc/arm/st_stm32/stm32u5/soc.h
@@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the STM32U5 family processors. + * + */ + + +#ifndef _STM32U5_SOC_H_ +#define _STM32U5_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include <stm32u5xx.h> + +/* Add generated devicetree information and STM32 helper macros */ +#include <st_stm32_dt.h> + +#endif /* !_ASMLANGUAGE */ + +#endif /* _STM32U5_SOC_H_ */