| commit | 9abc29e3aef47a8739df588019a1e28c1074d46a | [log] [tgz] |
|---|---|---|
| author | Simon Desfarges <simon.desfarges@intel.com> | Thu Mar 17 11:44:54 2016 +0100 |
| committer | Gerrit Code Review <gerrit@zephyrproject.org> | Thu Mar 24 12:05:37 2016 +0000 |
| tree | a57267b7cefbff6647a25988c65db9ded026f909 | |
| parent | 5cecd07ba25f8abc2282538df91a7f2ca2335182 [diff] |
arc_timer: assert that counter always lower than limit ASSERT are put each time the timer0 limit register or the timer0 count register is modified. Change-Id: I38684d57803de285f4e26c68b449c71396e4c750 Signed-off-by: Simon Desfarges <simon.desfarges@intel.com>