commit a413244f4af3834e29b3e17040fe29475dce3015
author Kumar Gala <kumar.gala@intel.com> Thu Mar 16 17:05:01 2023 +0000
committer Fabio Baltieri <fabio.baltieri@gmail.com> Wed May 10 14:10:27 2023 +0000
tree 1298bd6d5f1e9a9a2e7db8b41c370aa294bad6a4
parent 5b7742225e64b0019347a5bec419f6e3974ad9a5

linker: Add missing ram iterable sections

Add missing users of ITERABLE_SECTION_RAM* macros that should exist
in common-ram.cmake so that linker script generation for arm clang
works for those users.

Signed-off-by: Kumar Gala <kumar.gala@intel.com>
(cherry picked from commit aefe5ea1cd139bc85c7d87686587eefeffb45e65)

cmake/linker_script/common/common-ram.cmake

diff --git a/cmake/linker_script/common/common-ram.cmake b/cmake/linker_script/common/common-ram.cmake
index b1b77d0..8f6c9ff 100644
--- a/cmake/linker_script/common/common-ram.cmake
+++ b/cmake/linker_script/common/common-ram.cmake
@@ -55,6 +55,7 @@
 zephyr_iterable_section(NAME k_sem GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN 4)
 zephyr_iterable_section(NAME k_queue GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN 4)
 zephyr_iterable_section(NAME k_condvar GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN 4)
+zephyr_iterable_section(NAME k_event GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN 4)
 
 zephyr_linker_section(NAME _net_buf_pool_area GROUP DATA_REGION NOINPUT ${XIP_ALIGN_WITH_INPUT} SUBALIGN 4)
 zephyr_linker_section_configure(SECTION _net_buf_pool_area
@@ -110,3 +111,22 @@
   zephyr_iterable_section(NAME ztest_test_rule GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN 4)
   zephyr_iterable_section(NAME ztest_expected_result_entry GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN 4)
 endif()
+
+if(CONFIG_BT_MESH_ADV_EXT)
+  zephyr_iterable_section(NAME bt_mesh_ext_adv GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN 4)
+endif()
+
+if(CONFIG_LOG)
+  zephyr_iterable_section(NAME log_mpsc_pbuf GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN 4)
+  zephyr_iterable_section(NAME log_msg_ptr GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN 4)
+endif()
+
+if(CONFIG_PCIE)
+  zephyr_iterable_section(NAME pcie_dev GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN 4)
+endif()
+
+if(CONFIG_USB_DEVICE_STACK)
+  zephyr_iterable_section(NAME usb_cfg_data GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN 4)
+  zephyr_iterable_section(NAME usbd_contex GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN 4)
+  zephyr_iterable_section(NAME usbd_class_node GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN 4)
+endif()