drivers/clock_control: stm32: Remove CLOCK_STM32_ Kconfig symbols
Remove deprecated Kconfig based STM32 clock configuration system.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
diff --git a/drivers/clock_control/Kconfig.stm32 b/drivers/clock_control/Kconfig.stm32
index 8ba4f20..83b7083 100644
--- a/drivers/clock_control/Kconfig.stm32
+++ b/drivers/clock_control/Kconfig.stm32
@@ -33,190 +33,6 @@
Note: Device tree configuration is overridden when current symbol is set:
CONFIG_CLOCK_STM32_HSE_CLOCK=32000000
-config CLOCK_CONTROL_STM32_HAS_DTS
- bool
- default y if "$(dt_node_has_prop,rcc,clocks)" || "$(dt_node_has_prop,rcc,d1cpre)"
- help
- This symbol is added to prevent default use of CLOCK_CONTROL_STM32_* symbols
- when board make use of device tree to configure clocks.
-
-if !CLOCK_CONTROL_STM32_HAS_DTS && !SOC_SERIES_STM32MP1X
-
-choice CLOCK_STM32_SYSCLK_SRC
- prompt "STM32 System Clock Source"
-
-config CLOCK_STM32_SYSCLK_SRC_HSE
- bool "HSE"
- help
- Use HSE as source of SYSCLK
-
-config CLOCK_STM32_SYSCLK_SRC_HSI
- bool "HSI"
- help
- Use HSI as source of SYSCLK
-
-config CLOCK_STM32_SYSCLK_SRC_MSI
- bool "MSI"
- depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
- help
- Use MSI as source of SYSCLK
-
-config CLOCK_STM32_SYSCLK_SRC_PLL
- bool "PLL"
- help
- Use PLL as source of SYSCLK
-
-config CLOCK_STM32_SYSCLK_SRC_CSI
- bool "CSI"
- depends on SOC_SERIES_STM32H7X
- help
- Use CSI as source of SYSCLK
-
-endchoice #CLOCK_STM32_SYSCLK_SRC
-
-config CLOCK_STM32_HSE_BYPASS
- bool "HSE bypass"
- depends on CLOCK_STM32_SYSCLK_SRC_HSE || CLOCK_STM32_PLL_SRC_HSE
- help
- Enable this option to bypass external high-speed clock (HSE).
-
-config CLOCK_STM32_MSI_RANGE
- int "MSI frequency range"
- depends on CLOCK_STM32_SYSCLK_SRC_MSI || CLOCK_STM32_PLL_SRC_MSI
- default 8
- help
- Frequency range of MSI when MSI range is provided in RCC_CR register
- Range 0: 100kHz
- Range 1: 200kHz
- Range 2 around 400 kHz
- Range 3 around 800 kHz
- Range 4: 1 MHz
- Range 5: 2 MHz
- Range 6: 4 MHz (reset value)
- Range 7: 8 MHz
- Range 8: 16 MHz
- Range 9: 24 MHz
- Range 10: 32 MHz
- Range 11: 48 MHz
-
-choice
- prompt "STM32 PLL Clock Source"
- default CLOCK_STM32_PLL_SRC_HSI
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
-
-config CLOCK_STM32_PLL_SRC_MSI
- bool "MSI"
- depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
- help
- Use MSI as source of PLL
-
-config CLOCK_STM32_PLL_SRC_HSI
- bool "HSI"
- help
- Use HSI as source of PLL
-
-config CLOCK_STM32_PLL_SRC_HSE
- bool "HSE"
- help
- Use HSE as source of PLL
-
-config CLOCK_STM32_PLL_SRC_PLL2
- bool "PLL2"
- depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
- help
- Use PLL2 as source of main PLL. This is equivalent of defining
- PLL2 as source PREDIV1SCR. If not selected, default source is HSE.
-
-config CLOCK_STM32_PLL_SRC_CSI
- bool "CSI"
- depends on SOC_SERIES_STM32H7X
- help
- Use CSI 4MHz as source of the main PLL.
-
-endchoice
-
-
-# Source series specific files for PLL settings
-
-source "drivers/clock_control/Kconfig.stm32f0_f3"
-source "drivers/clock_control/Kconfig.stm32f1"
-source "drivers/clock_control/Kconfig.stm32f2_f4_f7"
-source "drivers/clock_control/Kconfig.stm32h7"
-source "drivers/clock_control/Kconfig.stm32l0_l1"
-source "drivers/clock_control/Kconfig.stm32l4_l5_wb_wl"
-source "drivers/clock_control/Kconfig.stm32g0"
-source "drivers/clock_control/Kconfig.stm32g4"
-
-# Bus clocks configuration options
-
-if !SOC_SERIES_STM32H7X
-
-config CLOCK_STM32_AHB_PRESCALER
- int "AHB prescaler"
- default 1
- range 1 512
- depends on !SOC_SERIES_STM32WBX && !SOC_SERIES_STM32WLX
- help
- AHB prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128,
- 256, 512.
-
-config CLOCK_STM32_APB1_PRESCALER
- int "APB1 prescaler"
- default 1
- range 1 16
- help
- APB1 Low speed clock (PCLK1) prescaler, allowed values:
- 1, 2, 4, 8, 16
-
-config CLOCK_STM32_APB2_PRESCALER
- int "APB2 prescaler"
- default 1
- range 1 16
- depends on !SOC_SERIES_STM32F0X && !SOC_SERIES_STM32G0X
- help
- APB2 High speed clock (PCLK2) prescaler, allowed values:
- 1, 2, 4, 8, 16
-
-config CLOCK_STM32_CPU1_PRESCALER
- int "CPU1 HCLK prescaler"
- default 1
- range 1 512
- depends on SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
- help
- CPU1 HCLK prescaler, allowed values: 1, 2, 3, 4, 5, 6, 8, 10, 16, 32,
- 64, 128, 256, 512.
-
-config CLOCK_STM32_CPU2_PRESCALER
- int "CPU2 HCLK prescaler"
- default 1
- range 1 512
- depends on SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
- help
- CPU2 HCLK prescaler, allowed values: 1, 2, 3, 4, 5, 6, 8, 10, 16, 32,
- 64, 128, 256, 512.
-
-config CLOCK_STM32_AHB3_PRESCALER
- int "AHB3 HCLK prescaler"
- default 1
- range 1 512
- depends on SOC_SERIES_STM32WLX
- help
- HCLK4 prescaler, allowed values: 1, 2, 3, 4, 5, 6, 8, 10, 16, 32,
- 64, 128, 256, 512.
-
-config CLOCK_STM32_AHB4_PRESCALER
- int "AHB4 HCLK prescaler"
- default 1
- range 1 512
- depends on SOC_SERIES_STM32WBX
- help
- HCLK4 prescaler, allowed values: 1, 2, 3, 4, 5, 6, 8, 10, 16, 32,
- 64, 128, 256, 512.
-
-endif # !SOC_SERIES_STM32H7X && !SOC_SERIES_STM32MP1X
-
-endif # CLOCK_CONTROL_STM32_HAS_DTS
-
# Micro-controller Clock output configuration options
choice
diff --git a/drivers/clock_control/Kconfig.stm32f0_f3 b/drivers/clock_control/Kconfig.stm32f0_f3
deleted file mode 100644
index 06bd2ff..0000000
--- a/drivers/clock_control/Kconfig.stm32f0_f3
+++ /dev/null
@@ -1,41 +0,0 @@
-# STM32F0 and STM32F3 PLL configuration options
-
-# Copyright (c) 2019 Linaro
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X
-
-config CLOCK_STM32_PLL_PREDIV
- int "PREDIV Prescaler"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 1
- range 1 16
- help
- PREDIV is a PLL clock signal prescaler for the HSE output.
- It is supported by those parts that do not support PREDIV1.
- If configured on a non-supported part, this config will be ignored.
- Allowed values: 1 - 16.
-
-config CLOCK_STM32_PLL_PREDIV1
- int "PREDIV1 Prescaler"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 1
- range 1 16
- help
- PREDIV1 is a PLL clock signal prescaler for any PLL input.
- It is supported by STM32F04xx, STM32F07xx, STM32F09xx, STM32F030xC,
- STM32F302xE, STM32F303xE and STM32F39xx parts.
- If configured on a non-supported part, this config will be ignored.
- Allowed values: 1 - 16.
-
-config CLOCK_STM32_PLL_MULTIPLIER
- int "PLL multiplier"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 6
- range 2 16
- help
- PLL multiplier, allowed values: 2-16.
- PLL output must not exceed 48MHz for STM32F0 series
- or 72MHz for STM32F3 series.
-
-endif # SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X
diff --git a/drivers/clock_control/Kconfig.stm32f1 b/drivers/clock_control/Kconfig.stm32f1
deleted file mode 100644
index 5e8a977..0000000
--- a/drivers/clock_control/Kconfig.stm32f1
+++ /dev/null
@@ -1,33 +0,0 @@
-# STM32F1 PLL configuration options
-
-# Copyright (c) 2019 Linaro
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_STM32F1X
-
-config CLOCK_STM32_PLL_XTPRE
- bool "HSE to PLL /2 prescaler"
- depends on SOC_STM32F10X_DENSITY_DEVICE && CLOCK_STM32_PLL_SRC_HSE
- help
- Enable this option to enable /2 prescaler on HSE to PLL clock signal
-
-config CLOCK_STM32_PLL_MULTIPLIER
- int "PLL multiplier"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 9
- range 2 16 if !SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
- range 4 9 if SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
- help
- PLL multiplier, PLL output must not exceed 72MHz. Allowed values:
- Density devices: 2-16
- Connectivity devices: 4 - 9 and 13 ( used for multiplication factor 6.5).
-
-config CLOCK_STM32_PLL_PREDIV1
- int "PREDIV1 Prescaler"
- depends on !SOC_STM32F10X_DENSITY_DEVICE && CLOCK_STM32_SYSCLK_SRC_PLL
- default 1
- range 1 16
- help
- PREDIV1 is PLL clock signal prescaler, allowed values: 1 - 16.
-
-endif # SOC_SERIES_STM32F1X
diff --git a/drivers/clock_control/Kconfig.stm32f2_f4_f7 b/drivers/clock_control/Kconfig.stm32f2_f4_f7
deleted file mode 100644
index 70e2030..0000000
--- a/drivers/clock_control/Kconfig.stm32f2_f4_f7
+++ /dev/null
@@ -1,50 +0,0 @@
-# STM32F2, STM32F4 and STM32F7 PLL configuration options
-
-# Copyright (c) 2019 Linaro
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_STM32F2X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X
-
-config CLOCK_STM32_PLL_M_DIVISOR
- int "Division factor for PLL VCO input clock"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 8
- range 2 63
- help
- PLLM division factor needs to be set correctly to ensure that the VCO
- input frequency ranges from 1 to 2 MHz. It is recommended to select a
- frequency of 2 MHz to limit PLL jitter.
- Allowed values: 2-63
-
-config CLOCK_STM32_PLL_N_MULTIPLIER
- int "Multiplier factor for PLL VCO output clock"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 336
- range 192 432 if SOC_STM32F401XE || SOC_SERIES_STM32F2X
- range 50 432
- help
- PLLN multiplier factor needs to be set correctly to ensure that the
- VCO output frequency is between 100 and 432 MHz, except on STM32F401
- where the frequency must be between 192 and 432 MHz.
- Allowed values: 50-432 (STM32F401: 192-432)
-
-config CLOCK_STM32_PLL_P_DIVISOR
- int "PLL division factor for main system clock"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 4
- range 2 8
- help
- PLLP division factor needs to be set correctly to not exceed 84MHz.
- Allowed values: 2, 4, 6, 8
-
-config CLOCK_STM32_PLL_Q_DIVISOR
- int "Division factor for OTG FS, SDIO and RNG clocks"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 7
- range 2 15
- help
- The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG
- need a frequency lower than or equal to 48 MHz to work correctly.
- Allowed values: 2-15
-
-endif # SOC_SERIES_STM32F2X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X
diff --git a/drivers/clock_control/Kconfig.stm32g0 b/drivers/clock_control/Kconfig.stm32g0
deleted file mode 100644
index 3495ea9..0000000
--- a/drivers/clock_control/Kconfig.stm32g0
+++ /dev/null
@@ -1,51 +0,0 @@
-# STM32G0 PLL configuration options
-
-# Copyright (c) 2019 Linaro
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_STM32G0X
-
-config CLOCK_STM32_PLL_N_MULTIPLIER
- int "PLL multiplier"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 8
- range 8 86
- help
- PLL multiplier, allowed values: 8-86
- PLL output must not exceed 56MHz(1.8V)/26MHz(1.2V).
-
-config CLOCK_STM32_PLL_M_DIVISOR
- int "PLL divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 1
- range 1 8
- help
- PLL divisor, allowed values: 1-8.
-
-config CLOCK_STM32_PLL_P_DIVISOR
- int "PLL P Divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 2
- range 2 32
- help
- PLL P VCO divisor, allowed values: 2-32.
-
-config CLOCK_STM32_PLL_Q_DIVISOR
- int "PLL Q Divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL && \
- (SOC_STM32G031XX || SOC_STM32G051XX || SOC_STM32G071XX || SOC_STM32G0B1XX || SOC_STM32G0B0XX)
- default 2
- range 2 8
- help
- PLL Q VCO divisor, allowed values: 2-8.
- Limited to STM32G0B0 and STM32G0X1 variants.
-
-config CLOCK_STM32_PLL_R_DIVISOR
- int "PLL R Divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 2
- range 2 8
- help
- PLL R VCO divisor, allowed values: 2-8.
-
-endif # SOC_SERIES_STM32G0X
diff --git a/drivers/clock_control/Kconfig.stm32g4 b/drivers/clock_control/Kconfig.stm32g4
deleted file mode 100644
index 2b9bc2e..0000000
--- a/drivers/clock_control/Kconfig.stm32g4
+++ /dev/null
@@ -1,54 +0,0 @@
-# STM32G4 PLL configuration options
-
-# Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_STM32G4X
-
-config CLOCK_STM32_PLL_M_DIVISOR
- int "PLL divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 4
- range 1 16
- help
- PLL divisor, allowed values: 1-16.
-
-config CLOCK_STM32_PLL_N_MULTIPLIER
- int "PLL multiplier"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 75
- range 8 127
- help
- PLL multiplier, allowed values: 8-127.
-
-config CLOCK_STM32_PLL_P_DIVISOR
- int "PLL P Divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 7
- range 7 17
- help
- PLL P Output divisor, allowed values: 7, 17.
-
-config CLOCK_STM32_PLL_Q_DIVISOR
- int "PLL Q Divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 2
- range 2 8
- help
- PLL Q Output divisor, allowed values: 2, 4, 6, 8.
-
-config CLOCK_STM32_PLL_R_DIVISOR
- int "PLL R Divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 2
- range 2 8
- help
- PLL R Output divisor, allowed values: 2, 4, 6, 8.
-
-config CLOCK_STM32_LSE
- bool "Low-speed external clock"
- help
- Enable the low-speed external (LSE) clock supplied with a 32.768 kHz
- crystal resonator oscillator.
-
-endif # SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX
diff --git a/drivers/clock_control/Kconfig.stm32h7 b/drivers/clock_control/Kconfig.stm32h7
deleted file mode 100644
index d1a23f0..0000000
--- a/drivers/clock_control/Kconfig.stm32h7
+++ /dev/null
@@ -1,171 +0,0 @@
-# STM32H7 PLL configuration options
-
-# Copyright (c) 2019 Linaro
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_STM32H7X
-
-# Oscillator clocks configuration options
-
-config CLOCK_STM32_HSI_DIVISOR
- int "HSI Divisor"
- depends on CLOCK_STM32_PLL_SRC_HSI || CLOCK_STM32_SYSCLK_SRC_HSI
- default 1
- range 1 8
- help
- HSI Divisor to divide HSI base frequency value
- allowed values: 1, 2, 4, 8
-
-# Bus clocks configuration options
-
-config CLOCK_STM32_D1CPRE
- int "D1 Domain, CPU1 clock prescaler"
- default 1
- range 1 512
- help
- D1 Domain, CPU1 clock (sys_d1cpre_ck prescaler),
- allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.
-
-config CLOCK_STM32_HPRE
- int "hclk prescaler, D2 domain (CPU2) Clock prescaler"
- default 1
- range 1 512
- help
- hclk prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128, 256, 512.
-
-config CLOCK_STM32_D2PPRE1
- int "APB1 prescaler"
- default 1
- range 1 16
- help
- APB1 clock (rcc_pclk1) prescaler, allowed values: 1, 2, 4, 8, 16
-
-config CLOCK_STM32_D2PPRE2
- int "D2 DOMAIN, APB2 prescaler"
- default 1
- range 1 16
- help
- APB2 clock (rcc_pclk2) prescaler, allowed values: 1, 2, 4, 8, 16
-
-config CLOCK_STM32_D1PPRE
- int "D1 DOMAIN, APB3 prescaler"
- default 1
- range 1 16
- help
- APB3 clock (rcc_pclk3) prescaler, allowed values: 1, 2, 4, 8, 16
-
-config CLOCK_STM32_D3PPRE
- int "APB4 prescaler"
- default 1
- range 1 16
- help
- APB4 clock (rcc_pclk4) prescaler, allowed values: 1, 2, 4, 8, 16
-
-
-# PLL settings
-
-config CLOCK_STM32_PLL_M_DIVISOR
- int "PLL divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 32
- range 0 63
- help
- PLL divisor, allowed values: 0-63.
-
-config CLOCK_STM32_PLL_N_MULTIPLIER
- int "PLL1 VCO multiplier"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 129
- range 4 512
- help
- PLL multiplier, allowed values: 4-512.
-
-config CLOCK_STM32_PLL_P_DIVISOR
- int "PLL P Divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 2
- range 1 128
- help
- PLL P Output divisor, allowed values: 1-128.
-
-config CLOCK_STM32_PLL_Q_DIVISOR
- int "PLL Q Divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 2
- range 1 128
- help
- PLL Q Output divisor, allowed values: 1-128.
-
-config CLOCK_STM32_PLL_R_DIVISOR
- int "PLL R Divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 2
- range 1 128
- help
- PLL R Output divisor, allowed values: 1-128.
-
-# PLL3 settings
-
-config CLOCK_STM32_PLL3_ENABLE
- bool "Enable PLL3"
- help
- Enable PLL3. It is used to generate the kernel clock for some peripherals.
-
-if CLOCK_STM32_PLL3_ENABLE
-
-config CLOCK_STM32_PLL3_M_DIVISOR
- int "PLL3 divisor"
- default 32
- range 1 63
- help
- PLL divisor, allowed values: 1-63.
-
-config CLOCK_STM32_PLL3_N_MULTIPLIER
- int "PLL3 VCO multiplier"
- default 129
- range 4 512
- help
- PLL3 multiplier, allowed values: 4-512.
-
-config CLOCK_STM32_PLL3_P_ENABLE
- bool "Enable PLL3 P output"
- help
- Enable PLL3 P output.
-
-config CLOCK_STM32_PLL3_P_DIVISOR
- int "PLL3 P Divisor"
- depends on CLOCK_STM32_PLL3_P_ENABLE
- default 2
- range 1 128
- help
- PLL3 P Output divisor, allowed values: 1-128.
-
-config CLOCK_STM32_PLL3_Q_ENABLE
- bool "Enable PLL3 Q output"
- help
- Enable PLL3 Q output.
-
-config CLOCK_STM32_PLL3_Q_DIVISOR
- int "PLL3 Q Divisor"
- depends on CLOCK_STM32_PLL3_Q_ENABLE
- default 2
- range 1 128
- help
- PLL3 Q Output divisor, allowed values: 1-128.
-
-config CLOCK_STM32_PLL3_R_ENABLE
- bool "Enable PLL3 R output"
- help
- Enable PLL3 R output.
-
-config CLOCK_STM32_PLL3_R_DIVISOR
- int "PLL3 R Divisor"
- depends on CLOCK_STM32_PLL3_R_ENABLE
- default 2
- range 1 128
- help
- PLL3 R Output divisor, allowed values: 1-128.
-
-endif # CLOCK_STM32_PLL3_ENABLE
-
-endif # SOC_SERIES_STM32H7X
diff --git a/drivers/clock_control/Kconfig.stm32l0_l1 b/drivers/clock_control/Kconfig.stm32l0_l1
deleted file mode 100644
index b063678..0000000
--- a/drivers/clock_control/Kconfig.stm32l0_l1
+++ /dev/null
@@ -1,25 +0,0 @@
-# STM32L0 and STM32L1 PLL configuration options
-
-# Copyright (c) 2019 Linaro
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_STM32L0X || SOC_SERIES_STM32L1X
-
-config CLOCK_STM32_PLL_MULTIPLIER
- int "PLL multiplier"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 4
- range 3 48
- help
- PLL multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48.
- PLL output must not exceed 96MHz(1.8V)/48MHz(1.5V)/24MHz(1.2V).
-
-config CLOCK_STM32_PLL_DIVISOR
- int "PLL divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 2
- range 2 4
- help
- PLL divisor, allowed values: 2-4.
-
-endif # SOC_SERIES_STM32L0X || SOC_SERIES_STM32L1X
diff --git a/drivers/clock_control/Kconfig.stm32l4_l5_wb_wl b/drivers/clock_control/Kconfig.stm32l4_l5_wb_wl
deleted file mode 100644
index 6e27383..0000000
--- a/drivers/clock_control/Kconfig.stm32l4_l5_wb_wl
+++ /dev/null
@@ -1,83 +0,0 @@
-# STM32L4, STM32L5, STM32WB and STM32WL PLL configuration options
-
-# Copyright (c) 2019 Linaro
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
-
-config CLOCK_STM32_PLL_M_DIVISOR
- int "PLL divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 1
- range 1 8 if SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
- range 1 16 if SOC_SERIES_STM32L5X
- help
- PLL divisor,
- L4: allowed values: 1-8. PLL VCO input ranges from 4 to 16MHz
- L5: allowed values: 1-16. PLL VCO input ranges from 4 to 16MHz
- WB: allowed values: 1-8. PLL VCO input ranges from 2.66 to 16MHz
- WL: allowed values: 1-8. PLL VCO input ranges from 2.66 to 16MHz
-
-config CLOCK_STM32_PLL_N_MULTIPLIER
- int "PLL multiplier"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 20
- range 8 86 if SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X
- range 6 127 if SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
- help
- PLL multiplier,
- L4: allowed values: 8-86. PLL VCO output ranges from 64 to 334MHz
- L5: allowed values: 8-86. PLL VCO output ranges from 64 to 334MHz
- WB: allowed values: 6-127. PLL VCO output ranges from 96 to 334MHz
- WL: allowed values: 6-127. PLL VCO output ranges from 96 to 334MHz
-
-config CLOCK_STM32_PLL_P_DIVISOR
- int "PLL P Divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 7
- range 0 17 if SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X
- range 0 32 if SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
- help
- PLL P Output divisor
- L4: allowed values: 0, 7, 17. PLLP do not exceed 80MHz
- L5: allowed values: 0, 7, 17. PLLP do not exceed 80MHz
- WB: allowed values: 0, 2-32. PLLP do not exceed 64MHz
- WL: allowed values: 0, 2-32. PLLP do not exceed 48MHz
-
-config CLOCK_STM32_PLL_Q_DIVISOR
- int "PLL Q Divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 2
- range 0 8
- help
- PLL Q Output divisor
- L4: allowed values: 0, 2, 4, 6, 8. PLLQ do not exceed 80MHz
- L5: allowed values: 0, 2, 4, 6, 8. PLLQ do not exceed 80MHz
- WB: allowed values: 0, 2-8. PLLQ do not exceed 64MHz
- WL: allowed values: 0, 2-8. PLLQ do not exceed 48MHz
-
-config CLOCK_STM32_PLL_R_DIVISOR
- int "PLL R Divisor"
- depends on CLOCK_STM32_SYSCLK_SRC_PLL
- default 4
- range 0 8
- help
- PLL R Output divisor
- L4: allowed values: 0, 2, 4, 6, 8. PLLR do not exceed 80MHz
- L5: allowed values: 0, 2, 4, 6, 8. PLLR do not exceed 110MHz
- WB: allowed values: 0, 2-8. PLLR do not exceed 64MHz
- WL: allowed values: 0, 2-8. PLLR do not exceed 48MHz
-
-config CLOCK_STM32_LSE
- bool "Low-speed external clock"
- help
- Enable the low-speed external (LSE) clock supplied with a 32.768 kHz
- crystal resonator oscillator.
-
-config CLOCK_STM32_MSI_PLL_MODE
- bool "MSI PLL MODE"
- depends on CLOCK_STM32_LSE
- help
- Enable hardware auto-calibration with LSE.
-
-endif # SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
diff --git a/include/drivers/clock_control/stm32_clock_control.h b/include/drivers/clock_control/stm32_clock_control.h
index 3c956ab..b4b3fe9 100644
--- a/include/drivers/clock_control/stm32_clock_control.h
+++ b/include/drivers/clock_control/stm32_clock_control.h
@@ -15,84 +15,10 @@
/* common clock control device node for all STM32 chips */
#define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc)
-/*
- * Kconfig to device tree transition for clocks on STM32 targets:
- *
- * Following definitions are provided to allow a smooth transition
- * between Kconfig based to dts based clocks configuration.
- * These symbols allow to have both configuration schemes used simultaneoulsy
- * while giving precedence to dts based configuration once available on a
- * target.
- * Finally, once all in-tree users are converted to dts based configuration,
- * we'll be able to generate deprecation warnings for out of tree users of
- * Kconfig related symbols.
- */
-
-#if defined(STM32_AHB_PRESCALER) || \
- defined(CONFIG_CLOCK_STM32_APB1_PRESCALER) || \
- defined(CONFIG_CLOCK_STM32_APB2_PRESCALER) || \
- defined(CONFIG_CLOCK_STM32_AHB3_PRESCALER) || \
- defined(CONFIG_CLOCK_STM32_AHB4_PRESCALER) || \
- defined(CONFIG_CLOCK_STM32_CPU1_PRESCALER) || \
- defined(CONFIG_CLOCK_STM32_CPU2_PRESCALER) || \
- defined(CONFIG_CLOCK_STM32_PLL_M_DIVISOR) || \
- defined(CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER) || \
- defined(CONFIG_CLOCK_STM32_PLL_P_DIVISOR) || \
- defined(CONFIG_CLOCK_STM32_PLL_Q_DIVISOR) || \
- defined(CONFIG_CLOCK_STM32_PLL_R_DIVISOR) || \
- defined(CONFIG_CLOCK_STM32_PLL_XTPRE) || \
- defined(CONFIG_CLOCK_STM32_PLL_MULTIPLIER) || \
- defined(CONFIG_CLOCK_STM32_PLL_PREDIV1) || \
- defined(CONFIG_CLOCK_STM32_PLL_PREDIV) || \
- defined(CONFIG_CLOCK_STM32_PLL_DIVISOR) || \
- defined(CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL) || \
- defined(CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI) || \
- defined(CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE) || \
- defined(CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI) || \
- defined(CONFIG_CLOCK_STM32_PLL_SRC_MSI) || \
- defined(CONFIG_CLOCK_STM32_PLL_SRC_HSI) || \
- defined(CONFIG_CLOCK_STM32_PLL_SRC_HSE) || \
- defined(CONFIG_CLOCK_STM32_PLL_SRC_PLL2) || \
- defined(CONFIG_CLOCK_STM32_LSE) || \
- defined(CONFIG_CLOCK_STM32_MSI_RANGE) || \
- defined(CONFIG_CLOCK_STM32_MSI_PLL_MODE) || \
- defined(CONFIG_CLOCK_STM32_HSE_BYPASS) || \
- defined(CONFIG_CLOCK_STM32_D1CPRE) || \
- defined(CONFIG_CLOCK_STM32_HPRE) || \
- defined(CONFIG_CLOCK_STM32_D2PPRE1) || \
- defined(CONFIG_CLOCK_STM32_D2PPRE2) || \
- defined(CONFIG_CLOCK_STM32_D1PPRE) || \
- defined(CONFIG_CLOCK_STM32_D3PPRE) || \
- defined(CONFIG_CLOCK_STM32_PLL3_ENABLE) || \
- defined(CONFIG_CLOCK_STM32_PLL3_M_DIVISOR) || \
- defined(CONFIG_CLOCK_STM32_PLL3_N_MULTIPLIER) || \
- defined(CONFIG_CLOCK_STM32_PLL3_P_ENABLE) || \
- defined(CONFIG_CLOCK_STM32_PLL3_P_DIVISOR) || \
- defined(CONFIG_CLOCK_STM32_PLL3_Q_ENABLE) || \
- defined(CONFIG_CLOCK_STM32_PLL3_Q_DIVISOR) || \
- defined(CONFIG_CLOCK_STM32_PLL3_R_ENABLE) || \
- defined(CONFIG_CLOCK_STM32_PLL3_R_DIVISOR) || \
- defined(CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI) || \
- defined(CONFIG_CLOCK_STM32_HSI_DIVISOR)
-#warning "Deprecated: Please use device tree for STM32 clock_control configuration"
-/*
- * Use of Kconfig for STM32 clock_control configuration is deprecated.
- * It is replaced by use of device tree.
- * For more information, see:
- * https://github.com/zephyrproject-rtos/zephyr/pull/34120
- * https://github.com/zephyrproject-rtos/zephyr/pull/34609
- * https://github.com/zephyrproject-rtos/zephyr/pull/34701
- * and
- * https://github.com/zephyrproject-rtos/zephyr/issues/34633
- */
-#endif
-
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), ahb_prescaler) || \
DT_NODE_HAS_PROP(DT_INST(0, st_stm32f0_rcc), ahb_prescaler) || \
DT_NODE_HAS_PROP(DT_INST(0, st_stm32u5_rcc), ahb_prescaler)
#define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler)
-#else
-#define STM32_AHB_PRESCALER CONFIG_CLOCK_STM32_AHB_PRESCALER
#endif
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), apb1_prescaler) || \
@@ -101,8 +27,6 @@
DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), apb1_prescaler) || \
DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), apb1_prescaler)
#define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
-#else
-#define STM32_APB1_PRESCALER CONFIG_CLOCK_STM32_APB1_PRESCALER
#endif
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_rcc), apb2_prescaler) || \
@@ -110,9 +34,6 @@
DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), apb2_prescaler) || \
DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), apb2_prescaler)
#define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
-#elif !DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32f0_rcc, okay)
- /* This should not be defined in F0 binding case */
-#define STM32_APB2_PRESCALER CONFIG_CLOCK_STM32_APB2_PRESCALER
#endif
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32u5_rcc), apb3_prescaler)
@@ -121,28 +42,20 @@
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), ahb3_prescaler)
#define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
-#else
-#define STM32_AHB3_PRESCALER CONFIG_CLOCK_STM32_AHB3_PRESCALER
#endif
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), ahb4_prescaler)
#define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
-#else
-#define STM32_AHB4_PRESCALER CONFIG_CLOCK_STM32_AHB4_PRESCALER
#endif
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), cpu1_prescaler) || \
DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), cpu1_prescaler)
#define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler)
-#else
-#define STM32_CPU1_PRESCALER CONFIG_CLOCK_STM32_CPU1_PRESCALER
#endif
#if DT_NODE_HAS_PROP(DT_INST(0, st_stm32wb_rcc), cpu2_prescaler) || \
DT_NODE_HAS_PROP(DT_INST(0, st_stm32wl_rcc), cpu2_prescaler)
#define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler)
-#else
-#define STM32_CPU2_PRESCALER CONFIG_CLOCK_STM32_CPU2_PRESCALER
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32h7_rcc, okay) && \
@@ -153,13 +66,6 @@
#define STM32_D2PPRE2 DT_PROP(DT_NODELABEL(rcc), d2ppre2)
#define STM32_D1PPRE DT_PROP(DT_NODELABEL(rcc), d1ppre)
#define STM32_D3PPRE DT_PROP(DT_NODELABEL(rcc), d3ppre)
-#else
-#define STM32_D1CPRE CONFIG_CLOCK_STM32_D1CPRE
-#define STM32_HPRE CONFIG_CLOCK_STM32_HPRE
-#define STM32_D2PPRE1 CONFIG_CLOCK_STM32_D2PPRE1
-#define STM32_D2PPRE2 CONFIG_CLOCK_STM32_D2PPRE2
-#define STM32_D1PPRE CONFIG_CLOCK_STM32_D1PPRE
-#define STM32_D3PPRE CONFIG_CLOCK_STM32_D3PPRE
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \
@@ -176,12 +82,6 @@
#define STM32_PLL_P_DIVISOR DT_PROP(DT_NODELABEL(pll), div_p)
#define STM32_PLL_Q_DIVISOR DT_PROP(DT_NODELABEL(pll), div_q)
#define STM32_PLL_R_DIVISOR DT_PROP(DT_NODELABEL(pll), div_r)
-#else
-#define STM32_PLL_M_DIVISOR CONFIG_CLOCK_STM32_PLL_M_DIVISOR
-#define STM32_PLL_N_MULTIPLIER CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER
-#define STM32_PLL_P_DIVISOR CONFIG_CLOCK_STM32_PLL_P_DIVISOR
-#define STM32_PLL_Q_DIVISOR CONFIG_CLOCK_STM32_PLL_Q_DIVISOR
-#define STM32_PLL_R_DIVISOR CONFIG_CLOCK_STM32_PLL_R_DIVISOR
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay)
@@ -194,16 +94,6 @@
#define STM32_PLL3_Q_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_q)
#define STM32_PLL3_R_ENABLE DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r)
#define STM32_PLL3_R_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_r)
-#else
-#define STM32_PLL3_ENABLE CONFIG_CLOCK_STM32_PLL3_ENABLE
-#define STM32_PLL3_M_DIVISOR CONFIG_CLOCK_STM32_PLL3_M_DIVISOR
-#define STM32_PLL3_N_MULTIPLIER CONFIG_CLOCK_STM32_PLL3_N_MULTIPLIER
-#define STM32_PLL3_P_ENABLE CONFIG_CLOCK_STM32_PLL3_P_ENABLE
-#define STM32_PLL3_P_DIVISOR CONFIG_CLOCK_STM32_PLL3_P_DIVISOR
-#define STM32_PLL3_Q_ENABLE CONFIG_CLOCK_STM32_PLL3_Q_ENABLE
-#define STM32_PLL3_Q_DIVISOR CONFIG_CLOCK_STM32_PLL3_Q_DIVISOR
-#define STM32_PLL3_R_ENABLE CONFIG_CLOCK_STM32_PLL3_R_ENABLE
-#define STM32_PLL3_R_DIVISOR CONFIG_CLOCK_STM32_PLL3_R_DIVISOR
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
@@ -220,12 +110,6 @@
#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay)
#define STM32_PLL_DIVISOR DT_PROP(DT_NODELABEL(pll), div)
#define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul)
-#else
-#define STM32_PLL_XTPRE CONFIG_CLOCK_STM32_PLL_XTPRE
-#define STM32_PLL_MULTIPLIER CONFIG_CLOCK_STM32_PLL_MULTIPLIER
-#define STM32_PLL_PREDIV1 CONFIG_CLOCK_STM32_PLL_PREDIV1
-#define STM32_PLL_PREDIV CONFIG_CLOCK_STM32_PLL_PREDIV
-#define STM32_PLL_DIVISOR CONFIG_CLOCK_STM32_PLL_DIVISOR
#endif
#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32_rcc, okay) || \
@@ -241,12 +125,6 @@
#define STM32_SYSCLK_SRC_HSE DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
#define STM32_SYSCLK_SRC_MSI DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
#define STM32_SYSCLK_SRC_CSI DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
-#else
-#define STM32_SYSCLK_SRC_PLL CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
-#define STM32_SYSCLK_SRC_HSI CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI
-#define STM32_SYSCLK_SRC_HSE CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE
-#define STM32_SYSCLK_SRC_MSI CONFIG_CLOCK_STM32_SYSCLK_SRC_MSI
-#define STM32_SYSCLK_SRC_CSI CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI
#endif
#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \
@@ -270,30 +148,19 @@
#define STM32_PLL_SRC_HSI DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
#define STM32_PLL_SRC_HSE DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
#define STM32_PLL_SRC_PLL2 DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2))
-#else
-#define STM32_PLL_SRC_MSI CONFIG_CLOCK_STM32_PLL_SRC_MSI
-#define STM32_PLL_SRC_HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI
-#define STM32_PLL_SRC_HSE CONFIG_CLOCK_STM32_PLL_SRC_HSE
-#define STM32_PLL_SRC_PLL2 CONFIG_CLOCK_STM32_PLL_SRC_PLL2
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
#define STM32_LSE_CLOCK DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
-#else
-#define STM32_LSE_CLOCK CONFIG_CLOCK_STM32_LSE
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay)
#define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range)
-#elif !DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
-#define STM32_MSI_RANGE CONFIG_CLOCK_STM32_MSI_RANGE
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay)
#define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode)
-#elif !DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
-#define STM32_MSI_PLL_MODE CONFIG_CLOCK_STM32_MSI_PLL_MODE
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay)
@@ -303,14 +170,10 @@
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay)
#define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
-#else
-#define STM32_HSI_DIVISOR CONFIG_CLOCK_STM32_HSI_DIVISOR
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay)
#define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
-#elif !DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
-#define STM32_HSE_BYPASS CONFIG_CLOCK_STM32_HSE_BYPASS
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay)
