| commit | ae4f7a1a067d5706f577ae69ab9db86fc46dace2 | [log] [tgz] |
|---|---|---|
| author | Andy Ross <andrew.j.ross@intel.com> | Mon Mar 01 11:51:28 2021 -0800 |
| committer | Anas Nashif <anas.nashif@intel.com> | Mon Mar 08 11:14:27 2021 -0500 |
| tree | ebe2d97080633f605df0335a815892f108c7bf9f | |
| parent | fed9f5aa048497fc064964045fd6be12bf32df12 [diff] |
arch/xtensa: Remember to spill windows in arch_cohere_stacks() When we reach this code in interrupt context, our upper GPRs contain a cross-stack call that may still include some registers from the interrupted thread. Those need to go out to memory before we can do our cache coherence dance here. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>