commit aeaf32aada93513bf10fbd921fce7e9c92de79e5
author James Roy <rruuaanng@outlook.com> Mon Nov 18 22:20:11 2024 +0800
committer Anas Nashif <anas.nashif@intel.com> Wed Nov 20 15:57:52 2024 -0500
tree 564573dca728e522c349b077c5fb159ebf3f21a6
parent 538753d51b906f0f1b744c1190a9375f2b1fbded

stm32: Fix wrong binding target for RTC_SEL in stm32u0

Change the stm32u0 clock from CSR_REG to BDCR_REG.

Signed-off-by: James Roy <rruuaanng@outlook.com>

include/zephyr/dt-bindings/clock/stm32u0_clock.h

diff --git a/include/zephyr/dt-bindings/clock/stm32u0_clock.h b/include/zephyr/dt-bindings/clock/stm32u0_clock.h
index 5ee5059..476c423 100644
--- a/include/zephyr/dt-bindings/clock/stm32u0_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32u0_clock.h
@@ -87,6 +87,6 @@
 #define CLK48_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)
 #define ADC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG)
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, CSR_REG)
+#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U0_CLOCK_H_ */