dts: arm: st: stm32l5: remove U suffix from "resets" in DTSI
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
diff --git a/dts/arm/st/l5/stm32l5.dtsi b/dts/arm/st/l5/stm32l5.dtsi
index 18cdd5b..2997e8a 100644
--- a/dts/arm/st/l5/stm32l5.dtsi
+++ b/dts/arm/st/l5/stm32l5.dtsi
@@ -276,7 +276,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
- resets = <&rctl STM32_RESET(APB2, 14U)>;
+ resets = <&rctl STM32_RESET(APB2, 14)>;
interrupts = <61 0>;
status = "disabled";
};
@@ -285,7 +285,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
- resets = <&rctl STM32_RESET(APB1L, 17U)>;
+ resets = <&rctl STM32_RESET(APB1L, 17)>;
interrupts = <62 0>;
status = "disabled";
};
@@ -294,7 +294,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1L, 18U)>;
+ resets = <&rctl STM32_RESET(APB1L, 18)>;
interrupts = <63 0>;
status = "disabled";
};
@@ -303,7 +303,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
- resets = <&rctl STM32_RESET(APB1L, 19U)>;
+ resets = <&rctl STM32_RESET(APB1L, 19)>;
interrupts = <64 0>;
status = "disabled";
};
@@ -312,7 +312,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
- resets = <&rctl STM32_RESET(APB1L, 20U)>;
+ resets = <&rctl STM32_RESET(APB1L, 20)>;
interrupts = <65 0>;
status = "disabled";
};
@@ -321,7 +321,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40008000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1_2, 0)>;
- resets = <&rctl STM32_RESET(APB1H, 0U)>;
+ resets = <&rctl STM32_RESET(APB1H, 0)>;
interrupts = <66 0>;
status = "disabled";
};
@@ -410,7 +410,7 @@
reg = <0x420c8000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 22)>,
<&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>;
- resets = <&rctl STM32_RESET(AHB2, 22U)>;
+ resets = <&rctl STM32_RESET(AHB2, 22)>;
interrupts = <78 0>;
status = "disabled";
};
@@ -482,7 +482,7 @@
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 11)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 11U)>;
+ resets = <&rctl STM32_RESET(APB2, 11)>;
interrupts = <41 0>, <42 0>, <43 0>, <44 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
@@ -506,7 +506,7 @@
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 0)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 0U)>;
+ resets = <&rctl STM32_RESET(APB1L, 0)>;
interrupts = <45 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -535,7 +535,7 @@
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 1)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 1U)>;
+ resets = <&rctl STM32_RESET(APB1L, 1)>;
interrupts = <46 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -564,7 +564,7 @@
reg = <0x40000800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 2)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 2U)>;
+ resets = <&rctl STM32_RESET(APB1L, 2)>;
interrupts = <47 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -593,7 +593,7 @@
reg = <0x40000c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 3)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1L, 3U)>;
+ resets = <&rctl STM32_RESET(APB1L, 3)>;
interrupts = <48 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -622,7 +622,7 @@
reg = <0x40013400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 13)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 13U)>;
+ resets = <&rctl STM32_RESET(APB2, 13)>;
interrupts = <51 0>, <52 0>, <53 0>, <54 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
@@ -646,7 +646,7 @@
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 16)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 16U)>;
+ resets = <&rctl STM32_RESET(APB2, 16)>;
interrupts = <69 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -669,7 +669,7 @@
reg = <0x40014400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 17)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 17U)>;
+ resets = <&rctl STM32_RESET(APB2, 17)>;
interrupts = <70 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -692,7 +692,7 @@
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 18)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 18U)>;
+ resets = <&rctl STM32_RESET(APB2, 18)>;
interrupts = <71 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/l5/stm32l562.dtsi b/dts/arm/st/l5/stm32l562.dtsi
index bd3b7f2..845c6e0 100644
--- a/dts/arm/st/l5/stm32l562.dtsi
+++ b/dts/arm/st/l5/stm32l562.dtsi
@@ -14,7 +14,7 @@
compatible = "st,stm32-aes";
reg = <0x420c0000 0x400>;
clocks = <&rcc STM32_CLOCK(AHB2, 16)>;
- resets = <&rctl STM32_RESET(AHB2, 16U)>;
+ resets = <&rctl STM32_RESET(AHB2, 16)>;
interrupts = <93 0>;
status = "disabled";
};
