ext: stm32cube: update stm32f1xx cube version
Update Cube version for STM32F1XX family
from version: V1.14.0
to version: V1.15.0
Add support for Low Level API on stm32f1 family
Change-Id: I8cb5fe2fd94be3a320e863c7b5ed59e4c2312e87
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
diff --git a/ext/hal/st/stm32cube/stm32f1xx/README b/ext/hal/st/stm32cube/stm32f1xx/README
index 2120a81..9018562 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/README
+++ b/ext/hal/st/stm32cube/stm32f1xx/README
@@ -1,2 +1,6 @@
-The current version supported in Zephyr for STM32F1 Cube is V1.4.0
+The current version supported in Zephyr for STM32F1 Cube is V1.5.0
+This version contains following patch vs the official version:
+drivers/include/stm32f1_hal_conf.h: l355
+- #include "stm32f4xx_hal_mmc.h"
++ #include "stm32f1xx_hal_mmc.h"
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/Legacy/stm32_hal_legacy.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/Legacy/stm32_hal_legacy.h
index e20f700..cab3734 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/Legacy/stm32_hal_legacy.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/Legacy/stm32_hal_legacy.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -138,6 +138,7 @@
#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
+#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
@@ -150,6 +151,9 @@
#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
@@ -160,8 +164,16 @@
#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
+/* to the second dedicated IO (only for COMP2). */
+#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
+#else
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
+#endif
#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
@@ -229,9 +241,9 @@
#define DAC1_CHANNEL_1 DAC_CHANNEL_1
#define DAC1_CHANNEL_2 DAC_CHANNEL_2
#define DAC2_CHANNEL_1 DAC_CHANNEL_1
-#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
-#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
+#define DAC_WAVE_NONE 0x00000000U
+#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
@@ -344,6 +356,7 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
+
/**
* @}
*/
@@ -369,7 +382,7 @@
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{
*/
-#if defined(STM32L4) || defined(STM32F7)
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@@ -444,6 +457,25 @@
* @}
*/
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32H7)
+ #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
+ #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
+ #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
+ #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
+ #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+ #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+
+/**
+ * @}
+ */
+
+
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
* @{
*/
@@ -841,6 +873,8 @@
#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
+#define __DIV_LPUART UART_DIV_LPUART
+
#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
@@ -881,9 +915,9 @@
#define CAN_IT_RQCP2 CAN_IT_TME
#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
-#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
-#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
+#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
+#define CAN_TXSTATUS_OK ((uint8_t)0x01)
+#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
/**
* @}
@@ -902,48 +936,45 @@
#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
-#define ETH_MMCCR ((uint32_t)0x00000100U)
-#define ETH_MMCRIR ((uint32_t)0x00000104U)
-#define ETH_MMCTIR ((uint32_t)0x00000108U)
-#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
-#define ETH_MMCTIMR ((uint32_t)0x00000110U)
-#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
-#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
-#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
-#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
-#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
-#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
+#define ETH_MMCCR 0x00000100U
+#define ETH_MMCRIR 0x00000104U
+#define ETH_MMCTIR 0x00000108U
+#define ETH_MMCRIMR 0x0000010CU
+#define ETH_MMCTIMR 0x00000110U
+#define ETH_MMCTGFSCCR 0x0000014CU
+#define ETH_MMCTGFMSCCR 0x00000150U
+#define ETH_MMCTGFCR 0x00000168U
+#define ETH_MMCRFCECR 0x00000194U
+#define ETH_MMCRFAECR 0x00000198U
+#define ETH_MMCRGUFCR 0x000001C4U
-#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
-#if defined(STM32F1)
-#else
-#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
+#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
+#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
/**
* @}
@@ -965,7 +996,7 @@
* @}
*/
-#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
@@ -990,7 +1021,7 @@
/**
* @}
*/
-#endif /* STM32L4xx || STM32F7*/
+#endif /* STM32L4 || STM32F7*/
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
@@ -1175,6 +1206,9 @@
* @{
*/
#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
/**
* @}
*/
@@ -1216,6 +1250,7 @@
#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
@@ -1610,7 +1645,11 @@
#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
+#else
#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
+#endif /* STM32F1 */
#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
@@ -2216,26 +2255,26 @@
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
-#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
-#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
-#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
-#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
-#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
-#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
-#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
-#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
+#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
@@ -2619,6 +2658,30 @@
#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
#endif
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
#if defined(STM32F7)
#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
@@ -2637,10 +2700,22 @@
#define RCC_IT_HSI14 RCC_IT_HSI14RDY
-#if defined(STM32L0)
-#define RCC_IT_LSECSS RCC_IT_CSSLSE
-#define RCC_IT_CSS RCC_IT_CSSHSE
-#endif
+#define RCC_IT_CSSLSE RCC_IT_LSECSS
+#define RCC_IT_CSSHSE RCC_IT_CSS
+
+#define RCC_PLLMUL_3 RCC_PLL_MUL3
+#define RCC_PLLMUL_4 RCC_PLL_MUL4
+#define RCC_PLLMUL_6 RCC_PLL_MUL6
+#define RCC_PLLMUL_8 RCC_PLL_MUL8
+#define RCC_PLLMUL_12 RCC_PLL_MUL12
+#define RCC_PLLMUL_16 RCC_PLL_MUL16
+#define RCC_PLLMUL_24 RCC_PLL_MUL24
+#define RCC_PLLMUL_32 RCC_PLL_MUL32
+#define RCC_PLLMUL_48 RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2 RCC_PLL_DIV2
+#define RCC_PLLDIV_3 RCC_PLL_DIV3
+#define RCC_PLLDIV_4 RCC_PLL_DIV4
#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
@@ -2757,10 +2832,22 @@
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
#define DfsdmClockSelection Dfsdm1ClockSelection
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
+#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
/**
* @}
@@ -2840,7 +2927,7 @@
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-#if defined(STM32F4)
+#if defined(STM32F4) || defined(STM32F2)
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
@@ -2891,6 +2978,14 @@
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
+#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
+#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
+#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
+#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
+#endif
+
/**
* @}
*/
@@ -3079,6 +3174,7 @@
* @{
*/
#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32_assert_template.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32_assert_template.h
new file mode 100644
index 0000000..c0fc8e7
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32_assert_template.h
@@ -0,0 +1,75 @@
+/**
+ ******************************************************************************
+ * @file stm32_assert.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief STM32 assert template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32_assert.h.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal.h
index 7095642..712ce88 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f1xx_hal.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -59,7 +59,6 @@
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
-
/** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{
*/
@@ -262,22 +261,18 @@
*/
/* Exported functions --------------------------------------------------------*/
-
/** @addtogroup HAL_Exported_Functions
* @{
*/
-
/** @addtogroup HAL_Exported_Functions_Group1
* @{
*/
-
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
-void HAL_MspInit(void);
-void HAL_MspDeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
-
/**
* @}
*/
@@ -285,23 +280,22 @@
/** @addtogroup HAL_Exported_Functions_Group2
* @{
*/
-
/* Peripheral Control functions ************************************************/
-void HAL_IncTick(void);
-void HAL_Delay(__IO uint32_t Delay);
-uint32_t HAL_GetTick(void);
-void HAL_SuspendTick(void);
-void HAL_ResumeTick(void);
-uint32_t HAL_GetHalVersion(void);
-uint32_t HAL_GetREVID(void);
-uint32_t HAL_GetDEVID(void);
-void HAL_DBGMCU_EnableDBGSleepMode(void);
-void HAL_DBGMCU_DisableDBGSleepMode(void);
-void HAL_DBGMCU_EnableDBGStopMode(void);
-void HAL_DBGMCU_DisableDBGStopMode(void);
-void HAL_DBGMCU_EnableDBGStandbyMode(void);
-void HAL_DBGMCU_DisableDBGStandbyMode(void);
-
+void HAL_IncTick(void);
+void HAL_Delay(__IO uint32_t Delay);
+uint32_t HAL_GetTick(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+void HAL_GetUID(uint32_t *UID);
/**
* @}
*/
@@ -309,11 +303,26 @@
/**
* @}
*/
-
-
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Variables HAL Private Variables
+ * @{
+ */
/**
* @}
- */
+ */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Constants HAL Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/**
+ * @}
+ */
/**
* @}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_adc.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_adc.h
index 03025ac..fe425b9 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_adc.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_adc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_adc.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention
@@ -154,36 +154,36 @@
* @brief HAL ADC state machine: ADC states definition (bitfields)
*/
/* States of ADC global scope */
-#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
+#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */
/* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
+#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */
/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
- external trigger, low power auto power-on, multimode ADC master control) */
-#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Not available on STM32F1 device: Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32F1 device: End Of Sampling flag raised */
+#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+ external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */
/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
- external trigger, low power auto power-on, multimode ADC master control) */
-#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */
-#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
+#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+ external trigger, low power auto power-on, multimode ADC master control) */
+#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
-#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */
-#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */
+#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */
/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< ADC in multimode slave state, controlled by another ADC master ( */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */
/**
@@ -218,11 +218,11 @@
/** @defgroup ADC_Error_Code ADC Error Code
* @{
*/
-#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
- enable/disable, erroneous state */
-#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
-#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
+#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */
+#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
+ enable/disable, erroneous state */
+#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
+#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
/**
* @}
@@ -232,7 +232,7 @@
/** @defgroup ADC_Data_align ADC data alignment
* @{
*/
-#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
+#define ADC_DATAALIGN_RIGHT 0x00000000U
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
/**
* @}
@@ -244,7 +244,7 @@
/* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */
/* compatibility with other STM32 devices having a sequencer with */
/* additional options. */
-#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
+#define ADC_SCAN_DISABLE 0x00000000U
#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
/**
* @}
@@ -253,7 +253,7 @@
/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
* @{
*/
-#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
/**
* @}
@@ -264,7 +264,7 @@
*/
/* Note: Depending on devices, some channels may not be available on package */
/* pins. Refer to device datasheet for channels availability. */
-#define ADC_CHANNEL_0 ((uint32_t)0x00000000)
+#define ADC_CHANNEL_0 0x00000000U
#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0))
#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 ))
#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
@@ -292,7 +292,7 @@
/** @defgroup ADC_sampling_times ADC sampling times
* @{
*/
-#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */
#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */
#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */
#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
@@ -307,22 +307,22 @@
/** @defgroup ADC_regular_rank ADC rank into regular group
* @{
*/
-#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
-#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
-#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
-#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
-#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
-#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
-#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
-#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
-#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
-#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
-#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
-#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
-#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
-#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
-#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
-#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
+#define ADC_REGULAR_RANK_1 0x00000001U
+#define ADC_REGULAR_RANK_2 0x00000002U
+#define ADC_REGULAR_RANK_3 0x00000003U
+#define ADC_REGULAR_RANK_4 0x00000004U
+#define ADC_REGULAR_RANK_5 0x00000005U
+#define ADC_REGULAR_RANK_6 0x00000006U
+#define ADC_REGULAR_RANK_7 0x00000007U
+#define ADC_REGULAR_RANK_8 0x00000008U
+#define ADC_REGULAR_RANK_9 0x00000009U
+#define ADC_REGULAR_RANK_10 0x0000000AU
+#define ADC_REGULAR_RANK_11 0x0000000BU
+#define ADC_REGULAR_RANK_12 0x0000000CU
+#define ADC_REGULAR_RANK_13 0x0000000DU
+#define ADC_REGULAR_RANK_14 0x0000000EU
+#define ADC_REGULAR_RANK_15 0x0000000FU
+#define ADC_REGULAR_RANK_16 0x00000010U
/**
* @}
*/
@@ -330,12 +330,12 @@
/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
* @{
*/
-#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
+#define ADC_ANALOGWATCHDOG_NONE 0x00000000U
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
+#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
/**
* @}
@@ -400,14 +400,14 @@
/* ADC conversion cycles (unit: ADC clock cycles) */
/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
/* resolution 12 bits) */
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ((uint32_t) 14)
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ((uint32_t) 20)
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ((uint32_t) 26)
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ((uint32_t) 41)
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ((uint32_t) 54)
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ((uint32_t) 68)
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ((uint32_t) 84)
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 ((uint32_t)252)
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U
+#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U
/**
* @}
*/
@@ -439,7 +439,7 @@
(ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
-#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS ((uint32_t)0x00000000)
+#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U
#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
@@ -448,7 +448,7 @@
#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
-#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS ((uint32_t)0x00000000)
+#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U
#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
@@ -629,7 +629,7 @@
* @retval None
*/
#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
- (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L))
+ (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
/**
* @brief Set the ADC's sample time for channel numbers between 10 and 18.
@@ -638,7 +638,7 @@
* @retval None
*/
#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
- ((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR1_SMP11) * ((_CHANNELNB_) - 10)))
+ ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))
/**
* @brief Set the ADC's sample time for channel numbers between 0 and 9.
@@ -647,7 +647,7 @@
* @retval None
*/
#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
- ((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR2_SMP1) * (_CHANNELNB_)))
+ ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
/**
* @brief Set the selected regular channel rank for rank between 1 and 6.
@@ -656,7 +656,7 @@
* @retval None
*/
#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
- ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR3_SQ2) * ((_RANKNB_) - 1)))
+ ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))
/**
* @brief Set the selected regular channel rank for rank between 7 and 12.
@@ -665,7 +665,7 @@
* @retval None
*/
#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
- ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR2_SQ8) * ((_RANKNB_) - 7)))
+ ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))
/**
* @brief Set the selected regular channel rank for rank between 13 and 16.
@@ -674,7 +674,7 @@
* @retval None
*/
#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
- ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR1_SQ14) * ((_RANKNB_) - 13)))
+ ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))
/**
* @brief Set the injected sequence length.
@@ -682,7 +682,7 @@
* @retval None
*/
#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
- (((_JSQR_JL_) -1) << POSITION_VAL(ADC_JSQR_JL))
+ (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)
/**
* @brief Set the selected injected channel rank
@@ -695,7 +695,7 @@
* @retval None
*/
#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
- ((_CHANNELNB_) << (POSITION_VAL(ADC_JSQR_JSQ2) * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
+ ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
/**
* @brief Enable ADC continuous conversion mode.
@@ -703,7 +703,7 @@
* @retval None
*/
#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
- ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT))
+ ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
/**
* @brief Configures the number of discontinuous conversions for the regular group channels.
@@ -711,7 +711,7 @@
* @retval None
*/
#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
- (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
+ (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)
/**
* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
@@ -825,7 +825,7 @@
* For a unique ADC resolution: 12 bits
* @{
*/
-#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF))
+#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU)
/**
* @}
*/
@@ -833,7 +833,7 @@
/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
* @{
*/
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
/**
* @}
*/
@@ -841,7 +841,7 @@
/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
* @{
*/
-#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_adc_ex.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_adc_ex.h
index d375f07..e820577 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_adc_ex.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_adc_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_adc_ex.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of ADC HAL extension module.
******************************************************************************
* @attention
@@ -125,7 +125,7 @@
configure a channel on injected group can impact the configuration of other channels previously set. */
}ADC_InjectionConfTypeDef;
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
/**
* @brief Structure definition of ADC multimode
* @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
@@ -145,7 +145,7 @@
}ADC_MultiModeTypeDef;
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
* @}
@@ -161,10 +161,10 @@
/** @defgroup ADCEx_injected_rank ADCEx rank into injected group
* @{
*/
-#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
-#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
-#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
-#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
+#define ADC_INJECTED_RANK_1 0x00000001U
+#define ADC_INJECTED_RANK_2 0x00000002U
+#define ADC_INJECTED_RANK_3 0x00000003U
+#define ADC_INJECTED_RANK_4 0x00000004U
/**
* @}
*/
@@ -172,7 +172,7 @@
/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
* @{
*/
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
/**
* @}
@@ -204,7 +204,7 @@
/*!< External triggers of regular group for all ADC instances */
#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
/*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
/* XL-density devices. */
/* To use it on ADC or ADC2, a remap of trigger must be done from */
@@ -216,7 +216,7 @@
/* its definition is set to value for ADC1&ADC2 by default and changed to */
/* value for ADC3 by HAL ADC driver if ADC3 is selected. */
#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
-#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#define ADC_SOFTWARE_START ADC1_2_3_SWSTART
/**
@@ -248,7 +248,7 @@
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
/*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
/* XL-density devices. */
/* To use it on ADC1 or ADC2, a remap of trigger must be done from */
@@ -260,18 +260,18 @@
/* its definition is set to value for ADC1&ADC2 by default and changed to */
/* value for ADC3 by HAL ADC driver if ADC3 is selected. */
#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
-#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART
/**
* @}
*/
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
* @{
*/
-#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /*!< ADC dual mode disabled (ADC independent mode) */
+#define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */
#define ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
@@ -284,7 +284,7 @@
/**
* @}
*/
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
* @}
@@ -305,13 +305,13 @@
/* (used internally by HAL driver. To not use into HAL structure parameters) */
/* External triggers of regular group for ADC1&ADC2 (if ADCx available) */
-#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t) 0x00000000)
+#define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U
#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0))
#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 ))
#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 ))
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
+#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG)
/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
/* XL-density devices. */
#define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11
@@ -347,7 +347,7 @@
#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 ))
#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 ))
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
+#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG)
/* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
/* XL-density devices. */
#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
@@ -363,7 +363,7 @@
#endif /* STM32F103xE || defined STM32F103xG */
/* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */
-#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t) 0x00000000)
+#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U
#define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0))
#define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
/**
@@ -448,7 +448,7 @@
* @param __HANDLE__: ADC handle
* @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled
*/
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
)? \
@@ -459,14 +459,14 @@
#else
#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \
(RESET)
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
* @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
* @param __HANDLE__: ADC handle
* @retval None
*/
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
(( (((__HANDLE__)->Instance) == ADC2) \
)? \
@@ -477,14 +477,14 @@
#else
#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
(!RESET)
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
* @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
* @param __HANDLE__: ADC handle
* @retval None
*/
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
(( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
)? \
@@ -495,9 +495,9 @@
#else
#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
(RESET)
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
/**
* @brief Set handle of the other ADC sharing the common multimode settings
* @param __HANDLE__: ADC handle
@@ -518,21 +518,20 @@
#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
((__HANDLE_SLAVE__)->Instance = ADC2)
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
((CHANNEL) == ADC_INJECTED_RANK_2) || \
((CHANNEL) == ADC_INJECTED_RANK_3) || \
- ((CHANNEL) == ADC_INJECTED_RANK_4) )
+ ((CHANNEL) == ADC_INJECTED_RANK_4))
#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) )
+ ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))
/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
* @{
*/
-#define IS_ADC_INJECTED_NB_CONV(LENGTH) \
- (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
+#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
/**
* @}
*/
@@ -544,10 +543,9 @@
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
- \
- ((REGTRIG) == ADC_SOFTWARE_START) )
+ ((REGTRIG) == ADC_SOFTWARE_START))
#endif
-#if defined (STM32F101xE) || defined (STM32F101xG)
+#if defined (STM32F101xE)
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
@@ -555,8 +553,16 @@
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
- \
- ((REGTRIG) == ADC_SOFTWARE_START) )
+ ((REGTRIG) == ADC_SOFTWARE_START))
+#endif
+#if defined (STM32F101xG)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
+ ((REGTRIG) == ADC_SOFTWARE_START))
#endif
#if defined (STM32F103xE) || defined (STM32F103xG)
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
@@ -565,16 +571,14 @@
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
- \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
- \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
- ((REGTRIG) == ADC_SOFTWARE_START) )
+ ((REGTRIG) == ADC_SOFTWARE_START))
#endif
#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
@@ -583,24 +587,30 @@
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- \
- ((REGTRIG) == ADC_INJECTED_SOFTWARE_START) )
+ ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif
-#if defined (STM32F101xE) || defined (STM32F101xG)
+#if defined (STM32F101xE)
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
- \
- ((REGTRIG) == ADC_INJECTED_SOFTWARE_START) )
+ ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
+#endif
+#if defined (STM32F101xG)
+#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
+ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
+ ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif
#if defined (STM32F103xE) || defined (STM32F103xG)
#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
@@ -609,20 +619,17 @@
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
- \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
- \
- ((REGTRIG) == ADC_INJECTED_SOFTWARE_START) )
+ ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
#endif
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
@@ -632,8 +639,8 @@
((MODE) == ADC_DUALMODE_REGSIMULT) || \
((MODE) == ADC_DUALMODE_INTERLFAST) || \
((MODE) == ADC_DUALMODE_INTERLSLOW) || \
- ((MODE) == ADC_DUALMODE_ALTERTRIG) )
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+ ((MODE) == ADC_DUALMODE_ALTERTRIG) )
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
* @}
@@ -666,17 +673,17 @@
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
/* ADC multimode */
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
@@ -690,9 +697,9 @@
* @{
*/
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_can.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_can.h
index a59747f..befd3af 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_can.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_can.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f1xx_hal_can.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -36,13 +36,13 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __stm32f1xx_CAN_H
-#define __stm32f1xx_CAN_H
+#ifndef __STM32F1xx_HAL_CAN_H
+#define __STM32F1xx_HAL_CAN_H
#ifdef __cplusplus
extern "C" {
#endif
-
+
#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
@@ -60,37 +60,41 @@
/* Exported types ------------------------------------------------------------*/
/** @defgroup CAN_Exported_Types CAN Exported Types
* @{
- */
-/**
- * @brief HAL State structures definition
- */
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
typedef enum
{
- HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */
- HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
- HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */
- HAL_CAN_STATE_TIMEOUT = 0x03, /*!< CAN in Timeout state */
- HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
+ HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
+ HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
+ HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
+ HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
}HAL_CAN_StateTypeDef;
-
-/**
+/**
* @brief CAN init structure definition
*/
typedef struct
{
- uint32_t Prescaler; /*!< Specifies the length of a time quantum.
- This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
-
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+
uint32_t Mode; /*!< Specifies the CAN operating mode.
This parameter can be a value of @ref CAN_operating_mode */
- uint32_t SJW; /*!< Specifies the maximum number of time quanta
- the CAN hardware is allowed to lengthen or
+ uint32_t SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
shorten a bit to perform resynchronization.
This parameter can be a value of @ref CAN_synchronisation_jump_width */
@@ -99,24 +103,24 @@
uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
+
uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
- This parameter can be set to ENABLE or DISABLE. */
+ uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set to ENABLE or DISABLE */
uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
- This parameter can be set to ENABLE or DISABLE. */
+ This parameter can be set to ENABLE or DISABLE */
- uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
- This parameter can be set to ENABLE or DISABLE. */
+ uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
+ This parameter can be set to ENABLE or DISABLE */
uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
- This parameter can be set to ENABLE or DISABLE. */
+ This parameter can be set to ENABLE or DISABLE */
}CAN_InitTypeDef;
/**
@@ -125,81 +129,84 @@
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
-
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
-
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
- This parameter can be a value of @ref CAN_identifier_type */
+ This parameter can be a value of @ref CAN_Identifier_Type */
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
- uint8_t Data[8]; /*!< Contains the data to be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
-
+ uint8_t Data[8]; /*!< Contains the data to be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
}CanTxMsgTypeDef;
-/**
- * @brief CAN Rx message structure definition
+/**
+ * @brief CAN Rx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
- This parameter can be a value of @ref CAN_identifier_type */
+ This parameter can be a value of @ref CAN_Identifier_Type */
uint32_t RTR; /*!< Specifies the type of frame for the received message.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be received.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
- uint8_t Data[8]; /*!< Contains the data to be received.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+ uint8_t Data[8]; /*!< Contains the data to be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
- uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
- This parameter can be a value of @ref CAN_receive_FIFO_number_constants */
+ uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
+ This parameter can be CAN_FIFO0 or CAN_FIFO1 */
}CanRxMsgTypeDef;
-/**
- * @brief CAN handle Structure definition
- */
+/**
+ * @brief CAN handle Structure definition
+ */
typedef struct
{
CAN_TypeDef *Instance; /*!< Register base address */
-
+
CAN_InitTypeDef Init; /*!< CAN required parameters */
-
+
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
- CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
-
- HAL_LockTypeDef Lock; /*!< CAN locking object */
-
+ CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
+
+ CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
+
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
-
+
+ HAL_LockTypeDef Lock; /*!< CAN locking object */
+
__IO uint32_t ErrorCode; /*!< CAN Error code */
-
+
}CAN_HandleTypeDef;
+
/**
* @}
*/
-/* Exported constants --------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
/** @defgroup CAN_Exported_Constants CAN Exported Constants
* @{
*/
@@ -207,30 +214,28 @@
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
-
-
-#define HAL_CAN_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_CAN_ERROR_EWG ((uint32_t)0x01) /*!< EWG error */
-#define HAL_CAN_ERROR_EPV ((uint32_t)0x02) /*!< EPV error */
-#define HAL_CAN_ERROR_BOF ((uint32_t)0x04) /*!< BOF error */
-#define HAL_CAN_ERROR_STF ((uint32_t)0x08) /*!< Stuff error */
-#define HAL_CAN_ERROR_FOR ((uint32_t)0x10) /*!< Form error */
-#define HAL_CAN_ERROR_ACK ((uint32_t)0x20) /*!< Acknowledgment error */
-#define HAL_CAN_ERROR_BR ((uint32_t)0x40) /*!< Bit recessive */
-#define HAL_CAN_ERROR_BD ((uint32_t)0x80) /*!< LEC dominant */
-#define HAL_CAN_ERROR_CRC ((uint32_t)0x100) /*!< LEC transfer error */
-
-
+#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
+#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
+#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
+#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
+#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
+#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
+#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
+#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
+#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
+#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
/**
* @}
*/
-
/** @defgroup CAN_InitStatus CAN initialization Status
* @{
*/
-#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */
-#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */
+#define CAN_INITSTATUS_FAILED 0x00000000U /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS 0x00000001U /*!< CAN initialization OK */
/**
* @}
*/
@@ -238,24 +243,21 @@
/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
-#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
+#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
-
/**
* @}
*/
-
/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
* @{
*/
-#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
-
/**
* @}
*/
@@ -263,7 +265,7 @@
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
* @{
*/
-#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
@@ -279,15 +281,14 @@
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
-
/**
* @}
*/
-/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
* @{
*/
-#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
+#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
@@ -295,17 +296,15 @@
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
-
/**
* @}
*/
-/** @defgroup CAN_filter_mode CAN Filter Mode
+/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
-
/**
* @}
*/
@@ -315,7 +314,6 @@
*/
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
-
/**
* @}
*/
@@ -325,18 +323,15 @@
*/
#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
-
-
/**
* @}
*/
-/** @defgroup CAN_identifier_type CAN Identifier Type
+/** @defgroup CAN_Identifier_Type CAN Identifier Type
* @{
*/
-#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
-#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
-
+#define CAN_ID_STD 0x00000000U /*!< Standard Id */
+#define CAN_ID_EXT 0x00000004U /*!< Extended Id */
/**
* @}
*/
@@ -344,9 +339,8 @@
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
-#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
-#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
-
+#define CAN_RTR_DATA 0x00000000U /*!< Data frame */
+#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
/**
* @}
*/
@@ -355,7 +349,6 @@
* @{
*/
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
-
/**
* @}
*/
@@ -365,7 +358,6 @@
*/
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
-
/**
* @}
*/
@@ -375,7 +367,7 @@
*/
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
CAN_GetFlagStatus() function. */
/* Transmit Flags */
@@ -400,6 +392,7 @@
#define CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION)) /*!< Wake up flag */
#define CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION)) /*!< Sleep acknowledge flag */
#define CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION)) /*!< Sleep acknowledge flag */
+
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
@@ -412,10 +405,9 @@
* @}
*/
-
-/** @defgroup CAN_interrupts CAN Interrupts
+/** @defgroup CAN_Interrupts CAN Interrupts
* @{
- */
+ */
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
/* Receive Interrupts */
@@ -436,14 +428,10 @@
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
-
-
/**
* @}
*/
-
-
/**
* @}
*/
@@ -453,57 +441,54 @@
*/
/* CAN intermediate shift values used for CAN flags */
-#define TSR_REGISTER_INDEX ((uint32_t)0x5)
-#define RF0R_REGISTER_INDEX ((uint32_t)0x2)
-#define RF1R_REGISTER_INDEX ((uint32_t)0x4)
-#define MSR_REGISTER_INDEX ((uint32_t)0x1)
-#define ESR_REGISTER_INDEX ((uint32_t)0x3)
+#define TSR_REGISTER_INDEX 0x5U
+#define RF0R_REGISTER_INDEX 0x2U
+#define RF1R_REGISTER_INDEX 0x4U
+#define MSR_REGISTER_INDEX 0x1U
+#define ESR_REGISTER_INDEX 0x3U
/* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR regsiters) */
/* Transmit Flags */
-#define CAN_TSR_RQCP0_BIT_POSITION ((uint32_t)0x00000000)
-#define CAN_TSR_RQCP1_BIT_POSITION ((uint32_t)0x00000008)
-#define CAN_TSR_RQCP2_BIT_POSITION ((uint32_t)0x00000010)
-#define CAN_TSR_TXOK0_BIT_POSITION ((uint32_t)0x00000001)
-#define CAN_TSR_TXOK1_BIT_POSITION ((uint32_t)0x00000009)
-#define CAN_TSR_TXOK2_BIT_POSITION ((uint32_t)0x00000011)
-#define CAN_TSR_TME0_BIT_POSITION ((uint32_t)0x0000001A)
-#define CAN_TSR_TME1_BIT_POSITION ((uint32_t)0x0000001B)
-#define CAN_TSR_TME2_BIT_POSITION ((uint32_t)0x0000001C)
+#define CAN_TSR_RQCP0_BIT_POSITION 0x00000000U
+#define CAN_TSR_RQCP1_BIT_POSITION 0x00000008U
+#define CAN_TSR_RQCP2_BIT_POSITION 0x00000010U
+#define CAN_TSR_TXOK0_BIT_POSITION 0x00000001U
+#define CAN_TSR_TXOK1_BIT_POSITION 0x00000009U
+#define CAN_TSR_TXOK2_BIT_POSITION 0x00000011U
+#define CAN_TSR_TME0_BIT_POSITION 0x0000001AU
+#define CAN_TSR_TME1_BIT_POSITION 0x0000001BU
+#define CAN_TSR_TME2_BIT_POSITION 0x0000001CU
/* Receive Flags */
-#define CAN_RF0R_FF0_BIT_POSITION ((uint32_t)0x00000003)
-#define CAN_RF0R_FOV0_BIT_POSITION ((uint32_t)0x00000004)
+#define CAN_RF0R_FF0_BIT_POSITION 0x00000003U
+#define CAN_RF0R_FOV0_BIT_POSITION 0x00000004U
-#define CAN_RF1R_FF1_BIT_POSITION ((uint32_t)0x00000003)
-#define CAN_RF1R_FOV1_BIT_POSITION ((uint32_t)0x00000004)
+#define CAN_RF1R_FF1_BIT_POSITION 0x00000003U
+#define CAN_RF1R_FOV1_BIT_POSITION 0x00000004U
/* Operating Mode Flags */
-#define CAN_MSR_WKU_BIT_POSITION ((uint32_t)0x00000003)
-#define CAN_MSR_SLAK_BIT_POSITION ((uint32_t)0x00000001)
-#define CAN_MSR_SLAKI_BIT_POSITION ((uint32_t)0x00000004)
+#define CAN_MSR_WKU_BIT_POSITION 0x00000003U
+#define CAN_MSR_SLAK_BIT_POSITION 0x00000001U
+#define CAN_MSR_SLAKI_BIT_POSITION 0x00000004U
/* Error Flags */
-#define CAN_ESR_EWG_BIT_POSITION ((uint32_t)0x00000000)
-#define CAN_ESR_EPV_BIT_POSITION ((uint32_t)0x00000001)
-#define CAN_ESR_BOF_BIT_POSITION ((uint32_t)0x00000002)
+#define CAN_ESR_EWG_BIT_POSITION 0x00000000U
+#define CAN_ESR_EPV_BIT_POSITION 0x00000001U
+#define CAN_ESR_BOF_BIT_POSITION 0x00000002U
/* Mask used by macro to get/clear CAN flags*/
-#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
+#define CAN_FLAG_MASK 0x000000FFU
/* Mailboxes definition */
#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
-
-
/**
* @}
*/
-
/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CAN_Exported_Macro CAN Exported Macros
+/** @defgroup CAN_Exported_Macros CAN Exported Macros
* @{
*/
@@ -566,7 +551,7 @@
* @retval The number of pending message.
*/
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
+((uint8_t)((__HANDLE__)->Instance->RF0R & 0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
/** @brief Check whether the specified CAN flag is set or not.
* @param __HANDLE__: specifies the CAN Handle.
@@ -596,10 +581,10 @@
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
/** @brief Clear the specified CAN pending flag.
@@ -629,8 +614,7 @@
((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
-
+ (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
* @param __HANDLE__: specifies the CAN Handle.
@@ -661,9 +645,9 @@
* @retval The new status of transmission (TRUE or FALSE).
*/
#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
- ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
/**
* @brief Release the specified receive FIFO.
@@ -672,7 +656,7 @@
* @retval None.
*/
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
+((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
/**
* @brief Cancel a transmit request.
@@ -681,68 +665,21 @@
* @retval None.
*/
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
- ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
+ ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
/**
* @brief Enable or disables the DBG Freeze for CAN.
* @param __HANDLE__: specifies the CAN Handle.
- * @param __NEWSTATE__: new state of the CAN peripheral.
+ * @param __NEWSTATE__: new state of the CAN peripheral.
* This parameter can be: ENABLE (CAN reception/transmission is frozen
- * during debug. Reception FIFOs can still be accessed/controlled normally)
+ * during debug. Reception FIFOs can still be accessed/controlled normally)
* or DISABLE (CAN is working during debug).
* @retval None
*/
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup CAN_Private_Macros CAN Private Macros
- * @{
- */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
- ((MODE) == CAN_MODE_LOOPBACK)|| \
- ((MODE) == CAN_MODE_SILENT) || \
- ((MODE) == CAN_MODE_SILENT_LOOPBACK))
-
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
- ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
-
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
-
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
-
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
- ((MODE) == CAN_FILTERMODE_IDLIST))
-
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
- ((SCALE) == CAN_FILTERSCALE_32BIT))
-
-
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
- ((FIFO) == CAN_FILTER_FIFO1))
-
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
- ((IDTYPE) == CAN_ID_EXT))
-
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
-
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
-
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
/**
* @}
@@ -751,30 +688,30 @@
/* Include CAN HAL Extension module */
#include "stm32f1xx_hal_can_ex.h"
-/* Exported functions --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @addtogroup CAN_Exported_Functions
* @{
*/
-
+
/** @addtogroup CAN_Exported_Functions_Group1
- * @brief Initialization and Configuration functions
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
/**
- * @}
- */
-
+ * @}
+ */
+
/** @addtogroup CAN_Exported_Functions_Group2
- * @brief I/O operation functions
- * @{
- */
-/* IO operation functions *****************************************************/
+ * @brief I/O operation functions
+ * @{
+ */
+/* I/O operation functions *****************************************************/
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
@@ -786,24 +723,61 @@
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
/**
- * @}
- */
-
+ * @}
+ */
+
/** @addtogroup CAN_Exported_Functions_Group3
- * @brief CAN Peripheral State functions
- * @{
- */
+ * @brief CAN Peripheral State functions
+ * @{
+ */
/* Peripheral State and Error functions ***************************************/
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
/**
- * @}
- */
-
+ * @}
+ */
+
/**
- * @}
- */
-
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
+ * @{
+ */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+ ((MODE) == CAN_MODE_LOOPBACK)|| \
+ ((MODE) == CAN_MODE_SILENT) || \
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+ ((MODE) == CAN_FILTERMODE_IDLIST))
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+ ((SCALE) == CAN_FILTERSCALE_32BIT))
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+ ((FIFO) == CAN_FILTER_FIFO1))
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= 0x00007FFU)
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
+ ((IDTYPE) == CAN_ID_EXT))
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -812,14 +786,13 @@
* @}
*/
-#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || */
- /* STM32F103xG) || STM32F105xC || STM32F107xC */
+#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
#ifdef __cplusplus
}
#endif
-#endif /* __stm32f1xx_CAN_H */
+#endif /* __STM32F1xx_HAL_CAN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_can_ex.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_can_ex.h
index 16b6851..fd49a5f 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_can_ex.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_can_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_can_ex.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of CAN HAL Extension module.
******************************************************************************
* @attention
@@ -58,7 +58,7 @@
*/
/* Exported types ------------------------------------------------------------*/
-
+
/**
* @brief CAN filter configuration structure definition
*/
@@ -117,9 +117,9 @@
* @{
*/
#if defined(STM32F105xC) || defined(STM32F107xC)
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
#else
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13U)
#endif /* STM32F105xC || STM32F107xC */
/**
@@ -135,8 +135,7 @@
* @}
*/
-#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || */
- /* STM32F103xG) || STM32F105xC || STM32F107xC */
+#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
#ifdef __cplusplus
}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_cec.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_cec.h
index d0d37c8..66f5937 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_cec.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_cec.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f1xx_hal_cec.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -53,90 +53,83 @@
/** @addtogroup CEC
* @{
- */
-
-/** @addtogroup CEC_Private_Constants
- * @{
*/
-#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \
- ((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE))
-#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \
- ((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE))
-
-/** @brief Check CEC device Own Address Register (OAR) setting.
- * @param __ADDRESS__: CEC own address.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
-
-/** @brief Check CEC initiator or destination logical address setting.
- * Initiator and destination addresses are coded over 4 bits.
- * @param __ADDRESS__: CEC initiator or logical address.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
-
-/** @brief Check CEC message size.
- * The message size is the payload size: without counting the header,
- * it varies from 0 byte (ping operation, one header only, no payload) to
- * 15 bytes (1 opcode and up to 14 operands following the header).
- * @param __SIZE__: CEC message size.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
-
-/**
- * @}
- */
/* Exported types ------------------------------------------------------------*/
/** @defgroup CEC_Exported_Types CEC Exported Types
* @{
- */
+ */
/**
* @brief CEC Init Structure definition
*/
typedef struct
-{
+{
uint32_t TimingErrorFree; /*!< Configures the CEC Bit Timing Error Mode.
This parameter can be a value of @ref CEC_BitTimingErrorMode */
uint32_t PeriodErrorFree; /*!< Configures the CEC Bit Period Error Mode.
This parameter can be a value of @ref CEC_BitPeriodErrorMode */
- uint8_t InitiatorAddress; /*!< Initiator address (source logical address, sent in each header)
- This parameter can be a value <= 0xF */
+ uint16_t OwnAddress; /*!< Own addresses configuration
+ This parameter can be a value of @ref CEC_OWN_ADDRESS */
+ uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
}CEC_InitTypeDef;
/**
- * @brief HAL CEC State structures definition
+ * @brief HAL CEC State structures definition
+ * @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
+ * - gState contains CEC state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7 (not used)
+ * x : Should be set to 0
+ * b6 Error information
+ * 0 : No Error
+ * 1 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP initialized. HAL CEC Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
*/
typedef enum
{
- HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */
- HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_CEC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
- HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
- HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
- HAL_CEC_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
- HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */
- HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */
+ HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
+ Value is allowed for gState and RxState */
+ HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+ HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
+ Value is allowed for gState only */
+ HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+ HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+ HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
+ Value is allowed for gState only */
+ HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
}HAL_CEC_StateTypeDef;
/**
- * @brief HAL Error structures definition
- */
-typedef enum
-{
- HAL_CEC_ERROR_NONE = (uint32_t) 0x0, /*!< no error */
- HAL_CEC_ERROR_BTE = CEC_ESR_BTE, /*!< Bit Timing Error */
- HAL_CEC_ERROR_BPE = CEC_ESR_BPE, /*!< Bit Period Error */
- HAL_CEC_ERROR_RBTFE = CEC_ESR_RBTFE, /*!< Rx Block Transfer Finished Error */
- HAL_CEC_ERROR_SBE = CEC_ESR_SBE, /*!< Start Bit Error */
- HAL_CEC_ERROR_ACKE = CEC_ESR_ACKE, /*!< Block Acknowledge Error */
- HAL_CEC_ERROR_LINE = CEC_ESR_LINE, /*!< Line Error */
- HAL_CEC_ERROR_TBTFE = CEC_ESR_TBTFE, /*!< Tx Block Transfer Finished Error */
-}HAL_CEC_ErrorTypeDef;
-
-/**
* @brief CEC handle Structure definition
*/
typedef struct
@@ -149,31 +142,48 @@
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
- uint8_t *pRxBuffPtr; /*!< Pointer to CEC Rx transfer Buffer */
-
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
- uint32_t ErrorCode; /*!< For errors handling purposes, copy of ESR register in case error is reported */
-
HAL_LockTypeDef Lock; /*!< Locking object */
-
- HAL_CEC_StateTypeDef State; /*!< CEC communication state */
-
-}CEC_HandleTypeDef;
+ HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_CEC_StateTypeDef */
+
+ HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
+ This parameter can be a value of @ref HAL_CEC_StateTypeDef */
+
+ uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
+ in case error is reported */
+}CEC_HandleTypeDef;
/**
- * @}
- */
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
/** @defgroup CEC_Exported_Constants CEC Exported Constants
* @{
*/
-
+
+/** @defgroup CEC_Error_Code CEC Error Code
+ * @{
+ */
+#define HAL_CEC_ERROR_NONE 0x00000000U /*!< no error */
+#define HAL_CEC_ERROR_BTE CEC_ESR_BTE /*!< Bit Timing Error */
+#define HAL_CEC_ERROR_BPE CEC_ESR_BPE /*!< Bit Period Error */
+#define HAL_CEC_ERROR_RBTFE CEC_ESR_RBTFE /*!< Rx Block Transfer Finished Error */
+#define HAL_CEC_ERROR_SBE CEC_ESR_SBE /*!< Start Bit Error */
+#define HAL_CEC_ERROR_ACKE CEC_ESR_ACKE /*!< Block Acknowledge Error */
+#define HAL_CEC_ERROR_LINE CEC_ESR_LINE /*!< Line Error */
+#define HAL_CEC_ERROR_TBTFE CEC_ESR_TBTFE /*!< Tx Block Transfer Finished Error */
+/**
+ * @}
+ */
+
/** @defgroup CEC_BitTimingErrorMode Bit Timing Error Mode
* @{
*/
-#define CEC_BIT_TIMING_ERROR_MODE_STANDARD ((uint32_t)0x00) /*!< Bit timing error Standard Mode */
+#define CEC_BIT_TIMING_ERROR_MODE_STANDARD 0x00000000U /*!< Bit timing error Standard Mode */
#define CEC_BIT_TIMING_ERROR_MODE_ERRORFREE CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
/**
* @}
@@ -182,19 +192,44 @@
/** @defgroup CEC_BitPeriodErrorMode Bit Period Error Mode
* @{
*/
-#define CEC_BIT_PERIOD_ERROR_MODE_STANDARD ((uint32_t)0x00) /*!< Bit period error Standard Mode */
+#define CEC_BIT_PERIOD_ERROR_MODE_STANDARD 0x00000000U /*!< Bit period error Standard Mode */
#define CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
/**
* @}
*/
-/** @defgroup CEC_Initiator_Position Initiator logical address position in message header
+/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
* @{
*/
-#define CEC_INITIATOR_LSB_POS ((uint32_t) 4)
+#define CEC_INITIATOR_LSB_POS 4U
/**
* @}
*/
+
+/** @defgroup CEC_OWN_ADDRESS CEC Own Address
+ * @{
+ */
+#define CEC_OWN_ADDRESS_NONE CEC_OWN_ADDRESS_0 /* Reset value */
+#define CEC_OWN_ADDRESS_0 ((uint16_t)0x0000U) /* Logical Address 0 */
+#define CEC_OWN_ADDRESS_1 ((uint16_t)0x0001U) /* Logical Address 1 */
+#define CEC_OWN_ADDRESS_2 ((uint16_t)0x0002U) /* Logical Address 2 */
+#define CEC_OWN_ADDRESS_3 ((uint16_t)0x0003U) /* Logical Address 3 */
+#define CEC_OWN_ADDRESS_4 ((uint16_t)0x0004U) /* Logical Address 4 */
+#define CEC_OWN_ADDRESS_5 ((uint16_t)0x0005U) /* Logical Address 5 */
+#define CEC_OWN_ADDRESS_6 ((uint16_t)0x0006U) /* Logical Address 6 */
+#define CEC_OWN_ADDRESS_7 ((uint16_t)0x0007U) /* Logical Address 7 */
+#define CEC_OWN_ADDRESS_8 ((uint16_t)0x0008U) /* Logical Address 8 */
+#define CEC_OWN_ADDRESS_9 ((uint16_t)0x0009U) /* Logical Address 9 */
+#define CEC_OWN_ADDRESS_10 ((uint16_t)0x000AU) /* Logical Address 10 */
+#define CEC_OWN_ADDRESS_11 ((uint16_t)0x000BU) /* Logical Address 11 */
+#define CEC_OWN_ADDRESS_12 ((uint16_t)0x000CU) /* Logical Address 12 */
+#define CEC_OWN_ADDRESS_13 ((uint16_t)0x000DU) /* Logical Address 13 */
+#define CEC_OWN_ADDRESS_14 ((uint16_t)0x000EU) /* Logical Address 14 */
+#define CEC_OWN_ADDRESS_15 ((uint16_t)0x000FU) /* Logical Address 15 */
+/**
+ * @}
+ */
+
/** @defgroup CEC_Interrupts_Definitions Interrupts definition
* @{
*/
@@ -227,63 +262,66 @@
* @{
*/
-/** @brief Reset CEC handle state
+/** @brief Reset CEC handle gstate & RxState
* @param __HANDLE__: CEC handle.
* @retval None
*/
-#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
+ } while(0U)
/** @brief Checks whether or not the specified CEC interrupt flag is set.
* @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: specifies the interrupt to check.
+ * @param __FLAG__: specifies the flag to check.
* @arg CEC_FLAG_TERR: Tx Error
- * @arg CEC_FLAG_TBTF: Tx Block Transfer Finished
+ * @arg CEC_FLAG_TBTRF:Tx Block Transfer Finished
* @arg CEC_FLAG_RERR: Rx Error
* @arg CEC_FLAG_RBTF: Rx Block Transfer Finished
* @retval ITStatus
*/
-#define __HAL_CEC_GET_FLAG(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CSR,(__INTERRUPT__))
+#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) READ_BIT((__HANDLE__)->Instance->CSR,(__FLAG__))
/** @brief Clears the CEC's pending flags.
* @param __HANDLE__: specifies the CEC Handle.
- * @param __FLAG__: specifies the flag to clear.
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg CEC_CSR_TERR: Tx Error
- * @arg CEC_CSR_TBTF: Tx Block Transfer Finished
+ * @arg CEC_FLAG_TBTRF: Tx Block Transfer Finished
* @arg CEC_CSR_RERR: Rx Error
* @arg CEC_CSR_RBTF: Rx Block Transfer Finished
* @retval none
*/
-#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
- do { \
- uint32_t tmp = 0x0; \
- tmp = (__HANDLE__)->Instance->CSR & 0x2; \
- (__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFC) | tmp);\
- } while(0)
-
+#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+ do { \
+ uint32_t tmp = 0x0U; \
+ tmp = (__HANDLE__)->Instance->CSR & 0x00000002U; \
+ (__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFCU) | tmp);\
+ } while(0U)
+
/** @brief Enables the specified CEC interrupt.
* @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: The CEC interrupt to enable.
+ * @param __INTERRUPT__: specifies the CEC interrupt to enable.
* This parameter can be:
- * @arg CEC_IT_IE : Interrupt Enable
+ * @arg CEC_IT_IE : Interrupt Enable.
* @retval none
*/
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
/** @brief Disables the specified CEC interrupt.
* @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: The CEC interrupt to enable.
+ * @param __INTERRUPT__: specifies the CEC interrupt to disable.
* This parameter can be:
- * @arg CEC_IT_IE : Interrupt Enable
+ * @arg CEC_IT_IE : Interrupt Enable
* @retval none
*/
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
/** @brief Checks whether or not the specified CEC interrupt is enabled.
* @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: The CEC interrupt to enable.
+ * @param __INTERRUPT__: specifies the CEC interrupt to check.
* This parameter can be:
- * @arg CEC_IT_IE : Interrupt Enable
+ * @arg CEC_IT_IE : Interrupt Enable
* @retval FlagStatus
*/
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
@@ -308,7 +346,7 @@
/** @brief Set Transmission End flag
* @param __HANDLE__: specifies the CEC Handle.
- * @retval none
+ * @retval none
*/
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
@@ -345,7 +383,7 @@
/** @addtogroup CEC_Exported_Functions CEC Exported Functions
* @{
*/
-
+
/** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
* @{
@@ -353,6 +391,7 @@
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
+HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
/**
@@ -363,15 +402,13 @@
* @brief CEC Transmit/Receive functions
* @{
*/
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
-HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
-uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
+uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
-void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
+void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
/**
* @}
@@ -392,6 +429,78 @@
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CEC_Private_Types CEC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Variables CEC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Constants CEC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CEC_Private_Macros CEC Private Macros
+ * @{
+ */
+#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \
+ ((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE))
+
+#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \
+ ((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE))
+
+/** @brief Check CEC message size.
+ * The message size is the payload size: without counting the header,
+ * it varies from 0 byte (ping operation, one header only, no payload) to
+ * 15 bytes (1 opcode and up to 14 operands following the header).
+ * @param __SIZE__: CEC message size.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
+/** @brief Check CEC device Own Address Register (OAR) setting.
+ * @param __ADDRESS__: CEC own address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
+
+/** @brief Check CEC initiator or destination logical address setting.
+ * Initiator and destination addresses are coded over 4 bits.
+ * @param __ADDRESS__: CEC initiator or logical address.
+ * @retval Test result (TRUE or FALSE).
+ */
+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
+
+
+
+/**
+ * @}
+ */
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CEC_Private_Functions CEC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -399,9 +508,7 @@
/**
* @}
*/
-
#endif /* defined(STM32F100xB) || defined(STM32F100xE) */
-
#ifdef __cplusplus
}
#endif
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_conf.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_conf.h
index 9e84d74..0bd8d8a 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_conf.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_conf.h
@@ -2,15 +2,15 @@
******************************************************************************
* @file stm32f1xx_hal_conf.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32f1xx_hal_conf.h.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -35,7 +35,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_CONF_H
@@ -50,7 +50,7 @@
/* ########################## Module Selection ############################## */
/**
- * @brief This is the list of modules to be used in the HAL driver
+ * @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
@@ -83,103 +83,109 @@
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
+#define HAL_MMC_MODULE_ENABLED
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
+ * (when HSE is used as system clock source, directly or through the PLL).
*/
-#if !defined (HSE_VALUE)
+#if !defined (HSE_VALUE)
#if defined(USE_STM3210C_EVAL)
- #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+ #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
#else
- #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+ #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
+ #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
+ * (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
+ #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz */
#endif /* HSI_VALUE */
/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
- #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+ #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
-
#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
+ #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
-
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
- */
-#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
-#define TICK_INT_PRIORITY ((uint32_t)0x000F) /*!< tick interrupt priority */
-#define USE_RTOS 0
-#define PREFETCH_ENABLE 1
+ */
+#define VDD_VALUE 3300U /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 1U
/* ########################## Assert Selection ############################## */
/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
-/*#define USE_FULL_ASSERT 1*/
-
+/* #define USE_FULL_ASSERT 1U */
/* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0 2
-#define MAC_ADDR1 0
-#define MAC_ADDR2 0
-#define MAC_ADDR3 0
-#define MAC_ADDR4 0
-#define MAC_ADDR5 0
+#define MAC_ADDR0 2U
+#define MAC_ADDR1 0U
+#define MAC_ADDR2 0U
+#define MAC_ADDR3 0U
+#define MAC_ADDR4 0U
+#define MAC_ADDR5 0U
-/* Definition of the Ethernet driver buffers size and count */
+/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
-#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
-#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+#define ETH_RXBUFNB 8U /* 8 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */
-/* DP83848 PHY Address*/
-#define DP83848_PHY_ADDRESS 0x01
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01U
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY 0x000000FFU
/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+#define PHY_CONFIG_DELAY 0x00000FFFU
-#define PHY_READ_TO ((uint32_t)0x0000FFFF)
-#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+#define PHY_READ_TO 0x0000FFFFU
+#define PHY_WRITE_TO 0x0000FFFFU
/* Section 3: Common PHY Registers */
-#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
-#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
-
+#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
+
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
@@ -194,13 +200,13 @@
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
-
+
/* Section 4: Extended PHY Registers */
-#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
-#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
-#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
-
+#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
+
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
@@ -211,11 +217,18 @@
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
+/* ################## SPI peripheral configuration ########################## */
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC 1U
/* Includes ------------------------------------------------------------------*/
/**
- * @brief Include module's header file
+ * @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
@@ -225,15 +238,15 @@
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f1xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
-
+
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f1xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
-
+
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32f1xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
+#endif /* HAL_ETH_MODULE_ENABLED */
+
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f1xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
@@ -292,15 +305,15 @@
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f1xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
+#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32f1xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
+#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f1xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
+#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f1xx_hal_spi.h"
@@ -334,11 +347,13 @@
#include "stm32f1xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
-
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32f1xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f1xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
@@ -346,17 +361,18 @@
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
- * line number of the call that failed.
+ * line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
- #define assert_param(expr) ((void)0)
+ #define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
+
#ifdef __cplusplus
}
#endif
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_cortex.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_cortex.h
index 4d7e75a..ec0fe3b 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_cortex.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_cortex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f1xx_hal_cortex.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -58,7 +58,7 @@
* @{
*/
-#if (__MPU_PRESENT == 1)
+#if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
@@ -97,34 +97,33 @@
*/
/* Exported constants --------------------------------------------------------*/
+
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
-
-/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
-
-#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
- 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
- 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
- 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
- 1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
- 0 bits for subpriority */
+#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
/**
* @}
*/
-/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
* @{
*/
-#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
-#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
+#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
+#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
/**
* @}
@@ -134,10 +133,11 @@
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
* @{
*/
-#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
-#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
-#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
-#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
+#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
+#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
+#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
+#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
+
/**
* @}
*/
@@ -202,44 +202,44 @@
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
-#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
-#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
-#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
-#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
+#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
+#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
+#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
+#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
-#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
-#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
-#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
-#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
-#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
+#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
+#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
+#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
+#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
+#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
-#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
-#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
-#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
-#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
+#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
+#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
+#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
+#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
-#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
-#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
+#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
+#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
-/**
+/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
-#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
-#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
-#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
-#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
-#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
+#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
+#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
+#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
+#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
+#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/**
* @}
@@ -248,11 +248,11 @@
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
-#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
-#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
-#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
-#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
-#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
+#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
+#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
+#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
+#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
+#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
@@ -264,14 +264,61 @@
/**
* @}
*/
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+
+/* Exported Macros -----------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
* @{
- */
+ */
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization and de-initialization functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+ * @}
+ */
-/** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ * @{
+ */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1U)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{
*/
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
@@ -280,25 +327,16 @@
((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4))
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
-#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
-/**
- * @}
- */
+#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
-/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
- * @{
- */
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-/**
- * @}
- */
-#if (__MPU_PRESENT == 1)
+
+#if (__MPU_PRESENT == 1U)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
((STATE) == MPU_REGION_DISABLE))
@@ -366,97 +404,11 @@
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */
-/**
- * @}
+/**
+ * @}
*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CORTEX_Exported_Functions
- * @{
- */
-
-/** @addtogroup CORTEX_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-/**
- * @}
- */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-#if (__MPU_PRESENT == 1)
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void HAL_SYSTICK_IRQHandler(void);
-void HAL_SYSTICK_Callback(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
- * @brief CORTEX private functions
- * @{
- */
-
-#if (__MPU_PRESENT == 1)
-/**
- * @brief Disables the MPU
- * @retval None
- */
-__STATIC_INLINE void HAL_MPU_Disable(void)
-{
- /* Disable fault exceptions */
- SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-
- /* Disable the MPU */
- MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
-}
-
-/**
- * @brief Enables the MPU
- * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
- * NMI, FAULTMASK and privileged accessto the default memory
- * This parameter can be one of the following values:
- * @arg MPU_HFNMI_PRIVDEF_NONE
- * @arg MPU_HARDFAULT_NMI
- * @arg MPU_PRIVILEGED_DEFAULT
- * @arg MPU_HFNMI_PRIVDEF
- * @retval None
- */
-__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
-{
- /* Enable the MPU */
- MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-
- /* Enable fault exceptions */
- SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-}
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
+/* Private functions ---------------------------------------------------------*/
/**
* @}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_crc.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_crc.h
index 2e08b9d..6d6d15e 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_crc.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_crc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_crc.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
@@ -65,11 +65,11 @@
*/
typedef enum
{
- HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */
- HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */
- HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */
- HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */
- HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
+ HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
+ HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
+ HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
+ HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
+ HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
}HAL_CRC_StateTypeDef;
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dac.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dac.h
index c0d6292..2785c84 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dac.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dac.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_dac.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
@@ -67,11 +67,11 @@
*/
typedef enum
{
- HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
- HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
- HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
- HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
- HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
+ HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
+ HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
+ HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
+ HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
+ HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
}HAL_DAC_StateTypeDef;
@@ -121,10 +121,10 @@
/** @defgroup DAC_Error_Code DAC Error Code
* @{
*/
-#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */
-#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
+#define HAL_DAC_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x00000001U /*!< DAC channel1 DMA underrun error */
+#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x00000002U /*!< DAC channel2 DMA underrun error */
+#define HAL_DAC_ERROR_DMA 0x00000004U /*!< DMA error */
/**
* @}
*/
@@ -132,7 +132,7 @@
/** @defgroup DAC_output_buffer DAC output buffer
* @{
*/
-#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
+#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
/**
@@ -142,8 +142,8 @@
/** @defgroup DAC_Channel_selection DAC Channel selection
* @{
*/
-#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
-#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
+#define DAC_CHANNEL_1 0x00000000U
+#define DAC_CHANNEL_2 0x00000010U
/**
* @}
@@ -152,9 +152,9 @@
/** @defgroup DAC_data_alignement DAC data alignement
* @{
*/
-#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
-#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
-#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
+#define DAC_ALIGN_12B_R 0x00000000U
+#define DAC_ALIGN_12B_L 0x00000004U
+#define DAC_ALIGN_8B_R 0x00000008U
/**
* @}
@@ -212,13 +212,13 @@
((ALIGN) == DAC_ALIGN_12B_L) || \
((ALIGN) == DAC_ALIGN_8B_R))
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__))
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
/**
* @}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dac_ex.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dac_ex.h
index d694bce..d4f86b3 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dac_ex.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dac_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_dac_ex.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention
@@ -67,7 +67,7 @@
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
* @{
*/
-#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
@@ -79,7 +79,7 @@
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
@@ -96,20 +96,10 @@
* @}
*/
-/** @defgroup DACEx_wave_generation DACEx wave generation
- * @{
- */
-#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
-
-/**
- * @}
- */
-
/** @defgroup DACEx_trigger_selection DAC trigger selection
* @{
*/
-#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T7_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_def.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_def.h
index 79f4d2b..e7825e4 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_def.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_def.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f1xx_hal_def.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -46,7 +46,9 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
+#if defined(USE_HAL_LEGACY)
#include "Legacy/stm32_hal_legacy.h"
+#endif
#include <stdio.h>
/* Exported types ------------------------------------------------------------*/
@@ -56,10 +58,10 @@
*/
typedef enum
{
- HAL_OK = 0x00,
- HAL_ERROR = 0x01,
- HAL_BUSY = 0x02,
- HAL_TIMEOUT = 0x03
+ HAL_OK = 0x00U,
+ HAL_ERROR = 0x01U,
+ HAL_BUSY = 0x02U,
+ HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/**
@@ -67,22 +69,21 @@
*/
typedef enum
{
- HAL_UNLOCKED = 0x00,
- HAL_LOCKED = 0x01
+ HAL_UNLOCKED = 0x00U,
+ HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
-
-#define HAL_MAX_DELAY 0xFFFFFFFF
+#define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
- do{ \
- (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
- (__DMA_HANDLE_).Parent = (__HANDLE__); \
- } while(0)
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
+ do{ \
+ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+ (__DMA_HANDLE__).Parent = (__HANDLE__); \
+ } while(0U)
#define UNUSED(x) ((void)(x))
@@ -101,14 +102,15 @@
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
-#if (USE_RTOS == 1)
- #error " USE_RTOS should be 0 in the current HAL release "
+#if (USE_RTOS == 1U)
+ /* Reserved for future use */
+ #error "USE_RTOS should be 0 in the current HAL release"
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
- if((__HANDLE__)->Lock == HAL_LOCKED) \
+ if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \
return HAL_BUSY; \
} \
@@ -116,12 +118,12 @@
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
- }while (0)
+ }while (0U)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
- (__HANDLE__)->Lock = HAL_UNLOCKED; \
- }while (0)
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \
+ }while (0U)
#endif /* USE_RTOS */
#if defined ( __GNUC__ )
@@ -148,13 +150,14 @@
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
- #define __ALIGN_BEGIN __align(4)
+ #define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
+
/**
* @brief __RAM_FUNC definition
*/
@@ -194,7 +197,7 @@
/* ARM & GNUCompiler
----------------
*/
-#define __NOINLINE __attribute__ ( (noinline) )
+#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
@@ -204,7 +207,6 @@
#endif
-
#ifdef __cplusplus
}
#endif
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dma.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dma.h
index 460036f..3db12d7 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dma.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dma.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f1xx_hal_dma.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_DMA_H
@@ -52,15 +52,15 @@
/** @addtogroup DMA
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Types DMA Exported Types
* @{
*/
-
-/**
+
+/**
* @brief DMA Configuration Structure definition
*/
typedef struct
@@ -71,58 +71,59 @@
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-
+
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
This parameter can be a value of @ref DMA_Memory_incremented_mode */
-
+
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_Peripheral_data_size */
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_Memory_data_size */
-
+
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Channel */
+ data transfer is configured on the selected Channel */
- uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
- This parameter can be a value of @ref DMA_Priority_level */
+ uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_Priority_level */
} DMA_InitTypeDef;
-/**
- * @brief DMA Configuration enumeration values definition
- */
-typedef enum
-{
- DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
- DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
-
-} DMA_ControlTypeDef;
-
/**
- * @brief HAL DMA State structures definition
+ * @brief HAL DMA State structures definition
*/
typedef enum
{
- HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
- HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
- HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
- HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
- HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
- HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
+ HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
+ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
+ HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
+ HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
}HAL_DMA_StateTypeDef;
-/**
+/**
* @brief HAL DMA Error Code structure definition
*/
typedef enum
{
- HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
- HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
+ HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
+ HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef;
/**
+ * @brief HAL DMA Callback ID structure definition
+ */
+typedef enum
+{
+ HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
+ HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
+ HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
+ HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
+ HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
+
+}HAL_DMA_CallbackIDTypeDef;
+
+/**
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef
@@ -142,8 +143,15 @@
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
+
+ void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
+
+ DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
+
+ uint32_t ChannelIndex; /*!< DMA Channel Index */
+
} DMA_HandleTypeDef;
/**
* @}
@@ -158,18 +166,19 @@
/** @defgroup DMA_Error_Code DMA Error Code
* @{
*/
- #define HAL_DMA_ERROR_NONE ((uint32_t)0x00) /*!< No error */
- #define HAL_DMA_ERROR_TE ((uint32_t)0x01) /*!< Transfer error */
- #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */
-
+#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
+#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */
+#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
+#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
/**
* @}
*/
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @{
- */
-#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
+ */
+#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
@@ -179,46 +188,46 @@
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @{
- */
-#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
+ */
+#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
/**
* @}
- */
+ */
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @{
- */
-#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
-#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
+ */
+#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
+#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @{
- */
-#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
-#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
-#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */
+ */
+#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
+#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
+#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */
/**
* @}
- */
+ */
/** @defgroup DMA_Memory_data_size DMA Memory data size
- * @{
+ * @{
*/
-#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
-#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
-#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */
+#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
+#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */
/**
* @}
*/
/** @defgroup DMA_mode DMA mode
* @{
- */
-#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
+ */
+#define DMA_NORMAL 0x00000000U /*!< Normal mode */
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
/**
* @}
@@ -227,13 +236,13 @@
/** @defgroup DMA_Priority_level DMA Priority level
* @{
*/
-#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
-#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
-#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
-#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
+#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
+#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
+#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
+#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
/**
* @}
- */
+ */
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
@@ -248,35 +257,35 @@
/** @defgroup DMA_flag_definitions DMA flag definitions
* @{
- */
-#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
-#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
-#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
-#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
-#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
-#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
-#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
-#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
-#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
-#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
-#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
-#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
-#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
-#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
-#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
-#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
-#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
-#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
-#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
-#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
-#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
-#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
-#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
-#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
-#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
-#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
-#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
-#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
+ */
+#define DMA_FLAG_GL1 0x00000001U
+#define DMA_FLAG_TC1 0x00000002U
+#define DMA_FLAG_HT1 0x00000004U
+#define DMA_FLAG_TE1 0x00000008U
+#define DMA_FLAG_GL2 0x00000010U
+#define DMA_FLAG_TC2 0x00000020U
+#define DMA_FLAG_HT2 0x00000040U
+#define DMA_FLAG_TE2 0x00000080U
+#define DMA_FLAG_GL3 0x00000100U
+#define DMA_FLAG_TC3 0x00000200U
+#define DMA_FLAG_HT3 0x00000400U
+#define DMA_FLAG_TE3 0x00000800U
+#define DMA_FLAG_GL4 0x00001000U
+#define DMA_FLAG_TC4 0x00002000U
+#define DMA_FLAG_HT4 0x00004000U
+#define DMA_FLAG_TE4 0x00008000U
+#define DMA_FLAG_GL5 0x00010000U
+#define DMA_FLAG_TC5 0x00020000U
+#define DMA_FLAG_HT5 0x00040000U
+#define DMA_FLAG_TE5 0x00080000U
+#define DMA_FLAG_GL6 0x00100000U
+#define DMA_FLAG_TC6 0x00200000U
+#define DMA_FLAG_HT6 0x00400000U
+#define DMA_FLAG_TE6 0x00800000U
+#define DMA_FLAG_GL7 0x01000000U
+#define DMA_FLAG_TC7 0x02000000U
+#define DMA_FLAG_HT7 0x04000000U
+#define DMA_FLAG_TE7 0x08000000U
/**
* @}
*/
@@ -284,15 +293,15 @@
/**
* @}
*/
-
-/* Exported macro ------------------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros
* @{
*/
-/** @brief Reset DMA handle state
- * @param __HANDLE__: DMA handle.
+/** @brief Reset DMA handle state.
+ * @param __HANDLE__: DMA handle
* @retval None
*/
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
@@ -300,14 +309,14 @@
/**
* @brief Enable the specified DMA Channel.
* @param __HANDLE__: DMA handle
- * @retval None.
+ * @retval None
*/
#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
/**
* @brief Disable the specified DMA Channel.
* @param __HANDLE__: DMA handle
- * @retval None.
+ * @retval None
*/
#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
@@ -317,7 +326,7 @@
/**
* @brief Enables the specified DMA Channel interrupts.
* @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
@@ -327,9 +336,9 @@
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
/**
- * @brief Disables the specified DMA Channel interrupts.
+ * @brief Disable the specified DMA Channel interrupts.
* @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
@@ -339,7 +348,7 @@
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
/**
- * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
+ * @brief Check whether the specified DMA Channel interrupt is enabled or not.
* @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
@@ -351,9 +360,8 @@
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
- * @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
+ * @brief Return the number of remaining data units in the current DMA Channel transfer.
* @param __HANDLE__: DMA handle
- *
* @retval The number of remaining data units in the current DMA Channel transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
@@ -366,11 +374,11 @@
#include "stm32f1xx_hal_dma_ex.h"
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_Exported_Functions DMA Exported Functions
+/** @addtogroup DMA_Exported_Functions
* @{
*/
-/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup DMA_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
@@ -380,25 +388,29 @@
* @}
*/
-/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
+/** @addtogroup DMA_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
/**
* @}
*/
-/** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
+/** @addtogroup DMA_Exported_Functions_Group3
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
@@ -407,26 +419,16 @@
* @}
*/
-/* Private Constants -------------------------------------------------------------*/
-/** @defgroup DMA_Private_Constants DMA Private Constants
- * @brief DMA private defines and constants
- * @{
- */
-/**
- * @}
- */
-
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros
- * @brief DMA private macros
* @{
*/
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
- ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+ ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
((STATE) == DMA_PINC_DISABLE))
@@ -443,29 +445,22 @@
((SIZE) == DMA_MDATAALIGN_WORD ))
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
- ((MODE) == DMA_CIRCULAR))
+ ((MODE) == DMA_CIRCULAR))
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
((PRIORITY) == DMA_PRIORITY_HIGH) || \
- ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+ ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
- * @brief DMA private functions
- * @{
- */
-/**
- * @}
- */
/**
* @}
- */
+ */
/**
* @}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dma_ex.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dma_ex.h
index ecb351b..eba02a9 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dma_ex.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_dma_ex.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f1xx_hal_dma_ex.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -52,7 +52,7 @@
/** @defgroup DMAEx DMAEx
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
@@ -125,6 +125,25 @@
DMA_FLAG_TE5)
/**
+ * @brief Return the current DMA Channel Global interrupt flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
+ DMA_FLAG_GL5)
+
+/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
* @param __FLAG__: Get the specified flag.
@@ -178,10 +197,10 @@
DMA_FLAG_TC7)
/**
- * @brief Returns the current DMA Channel half transfer complete flag.
+ * @brief Return the current DMA Channel half transfer complete flag.
* @param __HANDLE__: DMA handle
* @retval The specified half transfer complete flag index.
- */
+ */
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
@@ -192,7 +211,7 @@
DMA_FLAG_HT7)
/**
- * @brief Returns the current DMA Channel transfer error flag.
+ * @brief Return the current DMA Channel transfer error flag.
* @param __HANDLE__: DMA handle
* @retval The specified transfer error flag index.
*/
@@ -206,6 +225,20 @@
DMA_FLAG_TE7)
/**
+ * @brief Return the current DMA Channel Global interrupt flag.
+ * @param __HANDLE__: DMA handle
+ * @retval The specified transfer error flag index.
+ */
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
+ DMA_FLAG_GL7)
+
+/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
* @param __FLAG__: Get the specified flag.
@@ -213,6 +246,7 @@
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
+ * @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be 1_7 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/
@@ -220,13 +254,14 @@
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
/**
- * @brief Clears the DMA Channel pending flags.
+ * @brief Clear the DMA Channel pending flags.
* @param __HANDLE__: DMA handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
+ * @arg DMA_FLAG_GLx: Global interrupt flag
* Where x can be 1_7 to select the DMA Channel flag.
* @retval None
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_eth.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_eth.h
index e07fa4f..230596b 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_eth.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_eth.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_eth.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
@@ -58,7 +58,7 @@
/** @addtogroup ETH_Private_Macros
* @{
*/
-#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
((CMD) == ETH_AUTONEGOTIATION_DISABLE))
#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
@@ -122,7 +122,7 @@
#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
-#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
@@ -137,7 +137,7 @@
((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
-#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
((ADDRESS) == ETH_MAC_ADDRESS1) || \
((ADDRESS) == ETH_MAC_ADDRESS2) || \
@@ -207,80 +207,157 @@
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
-#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
-
+#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
+ ((FLAG) == ETH_DMATXDESC_IC) || \
+ ((FLAG) == ETH_DMATXDESC_LS) || \
+ ((FLAG) == ETH_DMATXDESC_FS) || \
+ ((FLAG) == ETH_DMATXDESC_DC) || \
+ ((FLAG) == ETH_DMATXDESC_DP) || \
+ ((FLAG) == ETH_DMATXDESC_TTSE) || \
+ ((FLAG) == ETH_DMATXDESC_TER) || \
+ ((FLAG) == ETH_DMATXDESC_TCH) || \
+ ((FLAG) == ETH_DMATXDESC_TTSS) || \
+ ((FLAG) == ETH_DMATXDESC_IHE) || \
+ ((FLAG) == ETH_DMATXDESC_ES) || \
+ ((FLAG) == ETH_DMATXDESC_JT) || \
+ ((FLAG) == ETH_DMATXDESC_FF) || \
+ ((FLAG) == ETH_DMATXDESC_PCE) || \
+ ((FLAG) == ETH_DMATXDESC_LCA) || \
+ ((FLAG) == ETH_DMATXDESC_NC) || \
+ ((FLAG) == ETH_DMATXDESC_LCO) || \
+ ((FLAG) == ETH_DMATXDESC_EC) || \
+ ((FLAG) == ETH_DMATXDESC_VF) || \
+ ((FLAG) == ETH_DMATXDESC_CC) || \
+ ((FLAG) == ETH_DMATXDESC_ED) || \
+ ((FLAG) == ETH_DMATXDESC_UF) || \
+ ((FLAG) == ETH_DMATXDESC_DB))
#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
-#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
-
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
+#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
+ ((FLAG) == ETH_DMARXDESC_AFM) || \
+ ((FLAG) == ETH_DMARXDESC_ES) || \
+ ((FLAG) == ETH_DMARXDESC_DE) || \
+ ((FLAG) == ETH_DMARXDESC_SAF) || \
+ ((FLAG) == ETH_DMARXDESC_LE) || \
+ ((FLAG) == ETH_DMARXDESC_OE) || \
+ ((FLAG) == ETH_DMARXDESC_VLAN) || \
+ ((FLAG) == ETH_DMARXDESC_FS) || \
+ ((FLAG) == ETH_DMARXDESC_LS) || \
+ ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
+ ((FLAG) == ETH_DMARXDESC_LC) || \
+ ((FLAG) == ETH_DMARXDESC_FT) || \
+ ((FLAG) == ETH_DMARXDESC_RWT) || \
+ ((FLAG) == ETH_DMARXDESC_RE) || \
+ ((FLAG) == ETH_DMARXDESC_DBE) || \
+ ((FLAG) == ETH_DMARXDESC_CE) || \
+ ((FLAG) == ETH_DMARXDESC_MAMPCE))
#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
((BUFFER) == ETH_DMARXDESC_BUFFER2))
-
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
+ ((FLAG) == ETH_PMT_FLAG_MPR))
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
+ ((FLAG) == ETH_DMA_FLAG_T))
+#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
+ ((IT) == ETH_MAC_IT_PMT))
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
+ ((FLAG) == ETH_MAC_FLAG_PMT))
+#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
+#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
+ ((IT) != 0x00U))
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
+#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
+ ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
/**
* @}
*/
-/** @addtogroup ETH_Private_Constants
+/** @addtogroup ETH_Private_Defines
* @{
*/
/* Delay to wait when writing to some Ethernet registers */
-#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
+#define ETH_REG_WRITE_DELAY 0x00000001U
/* ETHERNET Errors */
-#define ETH_SUCCESS ((uint32_t)0)
-#define ETH_ERROR ((uint32_t)1)
+#define ETH_SUCCESS 0U
+#define ETH_ERROR 1U
/* ETHERNET DMA Tx descriptors Collision Count Shift */
-#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
-#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
/* ETHERNET DMA Rx descriptors Frame Length Shift */
-#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
-#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
/* ETHERNET DMA Rx descriptors Frame length Shift */
-#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
+#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
/* ETHERNET MAC address offsets */
-#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
-#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
+#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
/* ETHERNET MACMIIAR register Mask */
-#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
+#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
/* ETHERNET MACCR register Mask */
-#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
+#define ETH_MACCR_CLEAR_MASK 0xFF20810FU
/* ETHERNET MACFCR register Mask */
-#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
+#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
/* ETHERNET DMAOMR register Mask */
-#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
+#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
/* ETHERNET Remote Wake-up frame register length */
-#define ETH_WAKEUP_REGISTER_LENGTH 8
+#define ETH_WAKEUP_REGISTER_LENGTH 8U
/* ETHERNET Missed frames counter Shift */
-#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
/**
* @}
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup ETH_Exported_Types ETH Exported Types
@@ -292,16 +369,16 @@
*/
typedef enum
{
- HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
- HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
- HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
- HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
- HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+ HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
+ HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
+ HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */
+ HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
+ HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
}HAL_ETH_StateTypeDef;
/**
@@ -332,7 +409,7 @@
uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
This parameter can be a value of @ref ETH_Checksum_Mode */
- uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
+ uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
This parameter can be a value of @ref ETH_Media_Interface */
} ETH_InitTypeDef;
@@ -387,10 +464,10 @@
uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
This parameter can be a value of @ref ETH_Receive_All */
- uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
- This parameter can be a value of @ref ETH_Source_Addr_Filter */
+ uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
+ This parameter can be a value of @ref ETH_Source_Addr_Filter */
- uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
+ uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
This parameter can be a value of @ref ETH_Pass_Control_Frames */
uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
@@ -409,13 +486,13 @@
This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
@@ -423,7 +500,7 @@
uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
automatic retransmission of PAUSE Frame.
This parameter can be a value of @ref ETH_Pause_Low_Threshold */
-
+
uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
unicast address and unique multicast address).
This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
@@ -444,7 +521,6 @@
} ETH_MACInitTypeDef;
-
/**
* @brief ETH DMA Configuration Structure definition
*/
@@ -485,7 +561,7 @@
uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
This parameter can be a value of @ref ETH_Fixed_Burst */
-
+
uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
@@ -493,7 +569,7 @@
This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
- This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
This parameter can be a value of @ref ETH_DMA_Arbitration */
@@ -516,7 +592,6 @@
} ETH_DMADescTypeDef;
-
/**
* @brief Received Frame Informations structure definition
*/
@@ -534,7 +609,6 @@
} ETH_DMARxFrameInfos;
-
/**
* @brief ETH Handle Structure definition
*/
@@ -571,14 +645,14 @@
/** @defgroup ETH_Buffers_setting ETH Buffers setting
* @{
*/
-#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
-#define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
-#define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
-#define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
-#define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
-#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
-#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
-#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
+#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC 4U /*!< Ethernet CRC */
+#define ETH_EXTRA 2U /*!< Extra bytes in some cases */
+#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */
+#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
/* Ethernet driver receive buffers are organized in a chained linked-list, when
an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
@@ -603,7 +677,7 @@
/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
#ifndef ETH_RXBUFNB
- #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
+ #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
#endif
@@ -630,7 +704,7 @@
/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
#ifndef ETH_TXBUFNB
- #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
+ #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
#endif
/**
@@ -642,7 +716,7 @@
*/
/*
- DMA Tx Desciptor
+ DMA Tx Descriptor
-----------------------------------------------------------------------------------------------
TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
-----------------------------------------------------------------------------------------------
@@ -657,56 +731,56 @@
/**
* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
*/
-#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
-#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
-#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
-#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
-#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
-#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
-#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
-#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
-#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
-#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
-#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
-#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
-#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
-#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
-#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
-#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
-#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
-#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
-#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
-#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
-#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
-#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
-#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
-#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
-#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
-#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
+#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */
+#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */
+#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */
+#define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */
+#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */
+#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */
+#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */
+#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */
+#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */
+#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */
+#define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */
+#define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */
+#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */
+#define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */
+#define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */
+#define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */
+#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */
/**
* @brief Bit definition of TDES1 register
*/
-#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
-#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
+#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */
+#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */
/**
* @brief Bit definition of TDES2 register
*/
-#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
+#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
/**
* @brief Bit definition of TDES3 register
*/
-#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
+#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
/**
* @}
*/
-/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
+/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
* @{
*/
@@ -726,44 +800,44 @@
/**
* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
*/
-#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
-#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
-#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
-#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
-#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
-#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
-#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
-#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
-#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
-#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
-#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
-#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
-#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
-#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
-#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
-#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
-#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
-#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */
+#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */
+#define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */
+#define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */
+#define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */
+#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */
+#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */
+#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
+#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */
+#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */
+#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
+#define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */
+#define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */
+#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */
+#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
/**
* @brief Bit definition of RDES1 register
*/
-#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
-#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
-#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
-#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
-#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
+#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */
+#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */
+#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */
+#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */
+#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */
/**
* @brief Bit definition of RDES2 register
*/
-#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
+#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
/**
* @brief Bit definition of RDES3 register
*/
-#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
+#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
/**
* @}
@@ -771,8 +845,8 @@
/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
* @{
*/
-#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
-#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
+#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
+#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
/**
* @}
@@ -780,25 +854,25 @@
/** @defgroup ETH_Speed ETH Speed
* @{
*/
-#define ETH_SPEED_10M ((uint32_t)0x00000000)
-#define ETH_SPEED_100M ((uint32_t)0x00004000)
+#define ETH_SPEED_10M 0x00000000U
+#define ETH_SPEED_100M 0x00004000U
/**
* @}
*/
-/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
* @{
*/
-#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
-#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
+#define ETH_MODE_FULLDUPLEX 0x00000800U
+#define ETH_MODE_HALFDUPLEX 0x00000000U
/**
* @}
*/
-/** @defgroup ETH_Rx_Mode ETH Rx Mode
+/** @defgroup ETH_Rx_Mode ETH Rx Mode
* @{
*/
-#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
-#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
+#define ETH_RXPOLLING_MODE 0x00000000U
+#define ETH_RXINTERRUPT_MODE 0x00000001U
/**
* @}
*/
@@ -806,8 +880,8 @@
/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
* @{
*/
-#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
-#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
+#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
+#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
/**
* @}
*/
@@ -815,7 +889,7 @@
/** @defgroup ETH_Media_Interface ETH Media Interface
* @{
*/
-#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
+#define ETH_MEDIA_INTERFACE_MII 0x00000000U
#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL)
/**
@@ -825,19 +899,17 @@
/** @defgroup ETH_Watchdog ETH Watchdog
* @{
*/
-#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
-#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
-
+#define ETH_WATCHDOG_ENABLE 0x00000000U
+#define ETH_WATCHDOG_DISABLE 0x00800000U
/**
* @}
*/
-/** @defgroup ETH_Jabber ETH Jabber
+/** @defgroup ETH_Jabber ETH Jabber
* @{
*/
-#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
-#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
-
+#define ETH_JABBER_ENABLE 0x00000000U
+#define ETH_JABBER_DISABLE 0x00400000U
/**
* @}
*/
@@ -845,15 +917,14 @@
/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
* @{
*/
-#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
-#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
-#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
-#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
-#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
-#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
-#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
-#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
-
+#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */
+#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */
+#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */
+#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */
+#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */
+#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */
+#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */
+#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */
/**
* @}
*/
@@ -861,9 +932,8 @@
/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
* @{
*/
-#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
-#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
-
+#define ETH_CARRIERSENCE_ENABLE 0x00000000U
+#define ETH_CARRIERSENCE_DISABLE 0x00010000U
/**
* @}
*/
@@ -871,19 +941,17 @@
/** @defgroup ETH_Receive_Own ETH Receive Own
* @{
*/
-#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
-#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
-
+#define ETH_RECEIVEOWN_ENABLE 0x00000000U
+#define ETH_RECEIVEOWN_DISABLE 0x00002000U
/**
* @}
*/
-/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
+/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
* @{
*/
-#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
-#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_LOOPBACKMODE_ENABLE 0x00001000U
+#define ETH_LOOPBACKMODE_DISABLE 0x00000000U
/**
* @}
*/
@@ -891,9 +959,8 @@
/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
* @{
*/
-#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
-#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
+#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
/**
* @}
*/
@@ -901,9 +968,8 @@
/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
* @{
*/
-#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
-#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
-
+#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
+#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
/**
* @}
*/
@@ -911,9 +977,8 @@
/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
* @{
*/
-#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
-#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
+#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
/**
* @}
*/
@@ -921,11 +986,10 @@
/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
* @{
*/
-#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
-#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
-#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
-#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
-
+#define ETH_BACKOFFLIMIT_10 0x00000000U
+#define ETH_BACKOFFLIMIT_8 0x00000020U
+#define ETH_BACKOFFLIMIT_4 0x00000040U
+#define ETH_BACKOFFLIMIT_1 0x00000060U
/**
* @}
*/
@@ -933,9 +997,8 @@
/** @defgroup ETH_Deferral_Check ETH Deferral Check
* @{
*/
-#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
-#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
+#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
/**
* @}
*/
@@ -943,9 +1006,8 @@
/** @defgroup ETH_Receive_All ETH Receive All
* @{
*/
-#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
-#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_RECEIVEALL_ENABLE 0x80000000U
+#define ETH_RECEIVEAll_DISABLE 0x00000000U
/**
* @}
*/
@@ -953,10 +1015,9 @@
/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
* @{
*/
-#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
-#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
-#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
+#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
+#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
/**
* @}
*/
@@ -964,10 +1025,9 @@
/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
* @{
*/
-#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
-#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
-#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
-
+#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */
+#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */
/**
* @}
*/
@@ -975,9 +1035,8 @@
/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
* @{
*/
-#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
-#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
-
+#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
+#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
/**
* @}
*/
@@ -985,9 +1044,8 @@
/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
* @{
*/
-#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
-#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
-
+#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
+#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
/**
* @}
*/
@@ -995,9 +1053,8 @@
/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
* @{
*/
-#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
-#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
+#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
/**
* @}
*/
@@ -1005,11 +1062,10 @@
/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
* @{
*/
-#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
-#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
-#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
-#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
-
+#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
+#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
+#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
+#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
/**
* @}
*/
@@ -1017,20 +1073,18 @@
/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
* @{
*/
-#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
-#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
-#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
-
+#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
+#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
+#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
/**
* @}
*/
-/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
+/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
* @{
*/
-#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
-#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
-
+#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
+#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
/**
* @}
*/
@@ -1038,11 +1092,10 @@
/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
* @{
*/
-#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
-
+#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */
/**
* @}
*/
@@ -1050,9 +1103,8 @@
/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
* @{
*/
-#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
-#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
+#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
/**
* @}
*/
@@ -1060,9 +1112,8 @@
/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
* @{
*/
-#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
-#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
+#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
/**
* @}
*/
@@ -1070,9 +1121,8 @@
/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
* @{
*/
-#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
-#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
+#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
/**
* @}
*/
@@ -1080,9 +1130,8 @@
/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
* @{
*/
-#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
-#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
-
+#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
+#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
/**
* @}
*/
@@ -1090,69 +1139,32 @@
/** @defgroup ETH_MAC_addresses ETH MAC addresses
* @{
*/
-#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
-#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
-#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
-#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
-
+#define ETH_MAC_ADDRESS0 0x00000000U
+#define ETH_MAC_ADDRESS1 0x00000008U
+#define ETH_MAC_ADDRESS2 0x00000010U
+#define ETH_MAC_ADDRESS3 0x00000018U
/**
* @}
*/
-/** @defgroup ETH_MAC_Addresses_Filter_SA_DA ETH MAC Addresses Filter SA DA
+/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
* @{
*/
-#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
-#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
+#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
+#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
/**
* @}
*/
-/** @defgroup ETH_MAC_Addresses_Filter_Mask_Bytes ETH_MAC Addresses Filter Mask Bytes
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
* @{
*/
-#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
-#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
-#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
-#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
-
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_Debug_Flags ETH MAC Debug Flags
- * @{
- */
-#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
-#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
-
+#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */
/**
* @}
*/
@@ -1160,19 +1172,17 @@
/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
* @{
*/
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
-
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
/**
* @}
*/
-/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
+/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
* @{
*/
-#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
-#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
+#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
/**
* @}
*/
@@ -1180,9 +1190,8 @@
/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
* @{
*/
-#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
-#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
-
+#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
+#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
/**
* @}
*/
@@ -1190,9 +1199,8 @@
/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
* @{
*/
-#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
-#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
+#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
/**
* @}
*/
@@ -1200,15 +1208,14 @@
/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
* @{
*/
-#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
-
+#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
/**
* @}
*/
@@ -1216,9 +1223,8 @@
/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
* @{
*/
-#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
-#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
+#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
/**
* @}
*/
@@ -1226,9 +1232,8 @@
/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
* @{
*/
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
/**
* @}
*/
@@ -1236,11 +1241,10 @@
/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
* @{
*/
-#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
-
+#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
/**
* @}
*/
@@ -1248,19 +1252,17 @@
/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
* @{
*/
-#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
-#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
+#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
/**
* @}
*/
-/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
+/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
* @{
*/
-#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
-#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
+#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
/**
* @}
*/
@@ -1268,29 +1270,27 @@
/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
* @{
*/
-#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
-#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_FIXEDBURST_ENABLE 0x00010000U
+#define ETH_FIXEDBURST_DISABLE 0x00000000U
/**
* @}
*/
-/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA_Burst Length
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
* @{
*/
-#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
-#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
-#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
-
+#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
/**
* @}
*/
@@ -1298,18 +1298,18 @@
/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
* @{
*/
-#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
/**
* @}
@@ -1318,44 +1318,40 @@
/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
* @{
*/
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
-#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
-
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
+#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
/**
* @}
*/
-/** @defgroup ETH_DMA_Tx_Descriptor_Segment ETH DMA Tx Descriptor Segment
+/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
* @{
*/
-#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
-#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
-
+#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */
+#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */
/**
* @}
*/
-/** @defgroup ETH_DMA_Tx_Descriptor_Checksum_Insertion_Control ETH DMA Tx Descriptor Checksum Insertion Control
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
* @{
*/
-#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
-#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
-
+#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */
+#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
/**
* @}
*/
-/** @defgroup ETH_DMA_Rx_Descriptor_Buffers ETH DMA Rx Descriptor Buffers
+/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
* @{
*/
-#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
-#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
-
+#define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */
+#define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */
/**
* @}
*/
@@ -1363,10 +1359,9 @@
/** @defgroup ETH_PMT_Flags ETH PMT Flags
* @{
*/
-#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
-#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
-
+#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */
+#define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */
/**
* @}
*/
@@ -1374,10 +1369,9 @@
/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
* @{
*/
-#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
-#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
-#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
-
+#define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */
/**
* @}
*/
@@ -1385,10 +1379,9 @@
/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
* @{
*/
-#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
-#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
-
+#define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */
+#define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */
/**
* @}
*/
@@ -1396,12 +1389,11 @@
/** @defgroup ETH_MAC_Flags ETH MAC Flags
* @{
*/
-#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
-#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
-#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
-#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
-#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
-
+#define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */
+#define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */
+#define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */
+#define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */
+#define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */
/**
* @}
*/
@@ -1409,67 +1401,64 @@
/** @defgroup ETH_DMA_Flags ETH DMA Flags
* @{
*/
-#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
-#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
-#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
-#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
-#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
-#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
-#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
-#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
-#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
-#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
-#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
-#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
-#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
-#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
-#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
-#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
-#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
-#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
-#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
-
+#define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */
+#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */
+#define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */
+#define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */
+#define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */
+#define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */
+#define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */
+#define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */
+#define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */
+#define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */
+#define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */
+#define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */
+#define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */
+#define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */
+#define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */
+#define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */
/**
* @}
*/
-/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
* @{
*/
-#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
-#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
-#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
-#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
-#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
-
+#define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */
+#define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */
+#define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */
+#define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */
+#define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */
/**
* @}
*/
-/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
* @{
*/
-#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
-#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
-#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
-#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
-#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
-#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
-#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
-#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
-#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
-#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
-#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
-#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
-#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
-#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
-#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
-#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
-#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
-
+#define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */
+#define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */
+#define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */
+#define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */
+#define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */
+#define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */
+#define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */
+#define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */
+#define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */
+#define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */
+#define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */
+#define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */
+#define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */
+#define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */
+#define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */
/**
* @}
*/
@@ -1477,12 +1466,12 @@
/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
* @{
*/
-#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
-#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
-#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
-#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
-#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
-#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
+#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */
+#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */
+#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */
+#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */
+#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */
/**
* @}
@@ -1492,12 +1481,12 @@
/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
* @{
*/
-#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
-#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
-#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
-#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
-#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
-#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
+#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */
+#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */
+#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */
+#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */
+#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */
/**
* @}
@@ -1506,17 +1495,16 @@
/** @defgroup ETH_DMA_overflow ETH DMA overflow
* @{
*/
-#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
-#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
-
+#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */
+#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */
/**
* @}
*/
- /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
+/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
* @{
*/
-#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
+#define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */
/**
* @}
@@ -1541,7 +1529,7 @@
/**
* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
* @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag of TDES0 to check .
+ * @param __FLAG__: specifies the flag of TDES0 to check.
* @retval the ETH_DMATxDescFlag (SET or RESET).
*/
#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
@@ -1611,7 +1599,7 @@
* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
- * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
* @retval None
*/
#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
@@ -1854,7 +1842,7 @@
* @retval None
*/
#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
- (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
+ (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while(0U)
/**
* @brief Enables the MMC Counter Freeze.
@@ -1915,7 +1903,7 @@
* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
* @retval None
*/
-#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
+#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
/**
* @brief Disables the specified ETHERNET MMC Rx interrupts.
* @param __HANDLE__: ETH Handle.
@@ -1926,7 +1914,7 @@
* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
* @retval None
*/
-#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
+#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
/**
* @brief Enables the specified ETHERNET MMC Tx interrupts.
* @param __HANDLE__: ETH Handle.
@@ -1992,17 +1980,17 @@
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
-
+
/**
* @brief Disables the rising edge trigger to the ETH External interrupt line.
* @retval None
*/
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
/**
* @brief Enables falling edge trigger to the ETH External interrupt line.
* @retval None
- */
+ */
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
/**
@@ -2010,27 +1998,22 @@
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
-
/**
* @brief Enables rising/falling edge trigger to the ETH External interrupt line.
* @retval None
*/
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() \
- do{ \
- EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
- EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
- } while(0)
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
+ EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
+ }while(0U)
/**
* @brief Disables rising/falling edge trigger to the ETH External interrupt line.
* @retval None
*/
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() \
- do{ \
- EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
- EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
- } while(0)
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
+ EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
+ }while(0U)
/**
* @brief Generate a Software interrupt on selected EXTI line.
@@ -2041,7 +2024,6 @@
/**
* @}
*/
-
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ETH_Exported_Functions
@@ -2053,7 +2035,6 @@
/** @addtogroup ETH_Exported_Functions_Group1
* @{
*/
-
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
@@ -2064,7 +2045,6 @@
/**
* @}
*/
-
/* IO operation functions ****************************************************/
/** @addtogroup ETH_Exported_Functions_Group2
@@ -2075,14 +2055,13 @@
/* Communication with PHY functions*/
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
- /* Non-Blocking mode: Interrupt */
+/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
- /* Callback in non blocking modes (Interrupt) */
+/* Callback in non blocking modes (Interrupt) */
void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
-
/**
* @}
*/
@@ -2092,6 +2071,7 @@
/** @addtogroup ETH_Exported_Functions_Group3
* @{
*/
+
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
@@ -2099,22 +2079,21 @@
/**
* @}
*/
-
+
/* Peripheral State functions ************************************************/
/** @addtogroup ETH_Exported_Functions_Group4
* @{
*/
HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
+/**
+ * @}
+ */
/**
* @}
*/
-
-/**
- * @}
- */
-
+
/**
* @}
*/
@@ -2122,7 +2101,7 @@
#endif /* STM32F107xC */
/**
* @}
- */
+ */
#ifdef __cplusplus
}
@@ -2131,5 +2110,4 @@
#endif /* __STM32F1xx_HAL_ETH_H */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_flash.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_flash.h
index 48c0cd4..c7ba2e9 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_flash.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_flash.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_flash.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of Flash HAL module.
******************************************************************************
* @attention
@@ -57,7 +57,7 @@
/** @addtogroup FLASH_Private_Constants
* @{
*/
-#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
+#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
/**
* @}
*/
@@ -87,18 +87,17 @@
* @{
*/
-
/**
* @brief FLASH Procedure structure definition
*/
typedef enum
{
- FLASH_PROC_NONE = 0,
- FLASH_PROC_PAGEERASE = 1,
- FLASH_PROC_MASSERASE = 2,
- FLASH_PROC_PROGRAMHALFWORD = 3,
- FLASH_PROC_PROGRAMWORD = 4,
- FLASH_PROC_PROGRAMDOUBLEWORD = 5
+ FLASH_PROC_NONE = 0U,
+ FLASH_PROC_PAGEERASE = 1U,
+ FLASH_PROC_MASSERASE = 2U,
+ FLASH_PROC_PROGRAMHALFWORD = 3U,
+ FLASH_PROC_PROGRAMWORD = 4U,
+ FLASH_PROC_PROGRAMDOUBLEWORD = 5U
} FLASH_ProcedureTypeDef;
/**
@@ -133,10 +132,10 @@
* @{
*/
-#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_FLASH_ERROR_PROG ((uint32_t)0x01) /*!< Programming error */
-#define HAL_FLASH_ERROR_WRP ((uint32_t)0x02) /*!< Write protection error */
-#define HAL_FLASH_ERROR_OPTV ((uint32_t)0x04) /*!< Option validity error */
+#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
+#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
+#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
+#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */
/**
* @}
@@ -145,9 +144,9 @@
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
-#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!<Program a half-word (16-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!<Program a double word (64-bit) at a specified address*/
+#define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!<Program a half-word (16-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_WORD 0x02U /*!<Program a word (32-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U /*!<Program a double word (64-bit) at a specified address*/
/**
* @}
@@ -157,7 +156,7 @@
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
-#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
@@ -169,7 +168,7 @@
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
-#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
/**
* @}
@@ -296,7 +295,7 @@
HAL_StatusTypeDef HAL_FLASH_Lock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+void HAL_FLASH_OB_Launch(void);
/**
* @}
@@ -320,7 +319,6 @@
/** @addtogroup FLASH_Private_Functions
* @{
*/
-void FLASH_PageErase(uint32_t PageAddress);
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
#if defined(FLASH_BANK2_END)
HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_flash_ex.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_flash_ex.h
index f29680e..93bf21f 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_flash_ex.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_flash_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_flash_ex.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of Flash HAL Extended module.
******************************************************************************
* @attention
@@ -58,9 +58,9 @@
* @{
*/
-#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFFF7E0)
-#define OBR_REG_INDEX ((uint32_t)1)
-#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
+#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U
+#define OBR_REG_INDEX 1U
+#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
/**
* @}
@@ -74,7 +74,7 @@
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
-#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
+#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
@@ -92,39 +92,39 @@
/* Low Density */
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF))
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU))
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
/* Medium Density */
#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF))))
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU))))
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
/* High Density */
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFF) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFF) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF)))
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU)))
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
/* XL Density */
#if defined(FLASH_BANK2_END)
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFF) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFF))
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU))
#endif /* FLASH_BANK2_END */
/* Connectivity Line */
#if (defined(STM32F105xC) || defined(STM32F107xC))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF)))
+#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \
+ (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
+ ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU)))
#endif /* STM32F105xC || STM32F107xC */
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
#if defined(FLASH_BANK2_END)
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
@@ -136,40 +136,40 @@
/* Low Density */
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \
- ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFF)))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
+ ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU)))
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
/* Medium Density */
#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \
- ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? \
- ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \
- ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFF)))))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
+ ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
+ ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
+ ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU)))))
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
/* High Density */
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200) ? \
- ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180) ? \
- ((ADDRESS) <= 0x0805FFFF) : ((ADDRESS) <= 0x0803FFFF))))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \
+ ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \
+ ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU))))
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
/* XL Density */
#if defined(FLASH_BANK2_END)
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400) ? \
- ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFF)))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \
+ ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU)))
#endif /* FLASH_BANK2_END */
/* Connectivity Line */
#if (defined(STM32F105xC) || defined(STM32F107xC))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? \
- ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \
- ((ADDRESS) <= 0x0801FFFF) : ((ADDRESS) <= 0x0800FFFF))))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
+ ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
+ ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
#endif /* STM32F105xC || STM32F107xC */
@@ -258,12 +258,12 @@
* @{
*/
#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
-#define FLASH_PAGE_SIZE ((uint32_t)0x400)
+#define FLASH_PAGE_SIZE 0x400U
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
/* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC))
-#define FLASH_PAGE_SIZE ((uint32_t)0x800)
+#define FLASH_PAGE_SIZE 0x800U
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
/* STM32F101xG || STM32F103xG */
/* STM32F105xC || STM32F107xC */
@@ -275,8 +275,8 @@
/** @defgroup FLASHEx_Type_Erase Type Erase
* @{
*/
-#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Pages erase only*/
-#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x02) /*!<Flash mass erase activation*/
+#define FLASH_TYPEERASE_PAGES 0x00U /*!<Pages erase only*/
+#define FLASH_TYPEERASE_MASSERASE 0x02U /*!<Flash mass erase activation*/
/**
* @}
@@ -286,12 +286,12 @@
* @{
*/
#if defined(FLASH_BANK2_END)
-#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
-#define FLASH_BANK_2 ((uint32_t)2) /*!< Bank 2 */
+#define FLASH_BANK_1 1U /*!< Bank 1 */
+#define FLASH_BANK_2 2U /*!< Bank 2 */
#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
#else
-#define FLASH_BANK_1 ((uint32_t)1) /*!< Bank 1 */
+#define FLASH_BANK_1 1U /*!< Bank 1 */
#endif
/**
* @}
@@ -308,10 +308,10 @@
/** @defgroup FLASHEx_OB_Type Option Bytes Type
* @{
*/
-#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!<WRP option byte configuration*/
-#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!<RDP option byte configuration*/
-#define OPTIONBYTE_USER ((uint32_t)0x04) /*!<USER option byte configuration*/
-#define OPTIONBYTE_DATA ((uint32_t)0x08) /*!<DATA option byte configuration*/
+#define OPTIONBYTE_WRP 0x01U /*!<WRP option byte configuration*/
+#define OPTIONBYTE_RDP 0x02U /*!<RDP option byte configuration*/
+#define OPTIONBYTE_USER 0x04U /*!<USER option byte configuration*/
+#define OPTIONBYTE_DATA 0x08U /*!<DATA option byte configuration*/
/**
* @}
@@ -320,8 +320,8 @@
/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
* @{
*/
-#define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!<Disable the write protection of the desired pages*/
-#define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!<Enable the write protection of the desired pagess*/
+#define OB_WRPSTATE_DISABLE 0x00U /*!<Disable the write protection of the desired pages*/
+#define OB_WRPSTATE_ENABLE 0x01U /*!<Enable the write protection of the desired pagess*/
/**
* @}
@@ -334,43 +334,43 @@
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \
|| defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \
|| defined(STM32F103xB)
-#define OB_WRP_PAGES0TO3 ((uint32_t)0x00000001) /*!< Write protection of page 0 to 3 */
-#define OB_WRP_PAGES4TO7 ((uint32_t)0x00000002) /*!< Write protection of page 4 to 7 */
-#define OB_WRP_PAGES8TO11 ((uint32_t)0x00000004) /*!< Write protection of page 8 to 11 */
-#define OB_WRP_PAGES12TO15 ((uint32_t)0x00000008) /*!< Write protection of page 12 to 15 */
-#define OB_WRP_PAGES16TO19 ((uint32_t)0x00000010) /*!< Write protection of page 16 to 19 */
-#define OB_WRP_PAGES20TO23 ((uint32_t)0x00000020) /*!< Write protection of page 20 to 23 */
-#define OB_WRP_PAGES24TO27 ((uint32_t)0x00000040) /*!< Write protection of page 24 to 27 */
-#define OB_WRP_PAGES28TO31 ((uint32_t)0x00000080) /*!< Write protection of page 28 to 31 */
+#define OB_WRP_PAGES0TO3 0x00000001U /*!< Write protection of page 0 to 3 */
+#define OB_WRP_PAGES4TO7 0x00000002U /*!< Write protection of page 4 to 7 */
+#define OB_WRP_PAGES8TO11 0x00000004U /*!< Write protection of page 8 to 11 */
+#define OB_WRP_PAGES12TO15 0x00000008U /*!< Write protection of page 12 to 15 */
+#define OB_WRP_PAGES16TO19 0x00000010U /*!< Write protection of page 16 to 19 */
+#define OB_WRP_PAGES20TO23 0x00000020U /*!< Write protection of page 20 to 23 */
+#define OB_WRP_PAGES24TO27 0x00000040U /*!< Write protection of page 24 to 27 */
+#define OB_WRP_PAGES28TO31 0x00000080U /*!< Write protection of page 28 to 31 */
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
/* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
/* STM32 Medium-density devices */
#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
-#define OB_WRP_PAGES32TO35 ((uint32_t)0x00000100) /*!< Write protection of page 32 to 35 */
-#define OB_WRP_PAGES36TO39 ((uint32_t)0x00000200) /*!< Write protection of page 36 to 39 */
-#define OB_WRP_PAGES40TO43 ((uint32_t)0x00000400) /*!< Write protection of page 40 to 43 */
-#define OB_WRP_PAGES44TO47 ((uint32_t)0x00000800) /*!< Write protection of page 44 to 47 */
-#define OB_WRP_PAGES48TO51 ((uint32_t)0x00001000) /*!< Write protection of page 48 to 51 */
-#define OB_WRP_PAGES52TO55 ((uint32_t)0x00002000) /*!< Write protection of page 52 to 55 */
-#define OB_WRP_PAGES56TO59 ((uint32_t)0x00004000) /*!< Write protection of page 56 to 59 */
-#define OB_WRP_PAGES60TO63 ((uint32_t)0x00008000) /*!< Write protection of page 60 to 63 */
-#define OB_WRP_PAGES64TO67 ((uint32_t)0x00010000) /*!< Write protection of page 64 to 67 */
-#define OB_WRP_PAGES68TO71 ((uint32_t)0x00020000) /*!< Write protection of page 68 to 71 */
-#define OB_WRP_PAGES72TO75 ((uint32_t)0x00040000) /*!< Write protection of page 72 to 75 */
-#define OB_WRP_PAGES76TO79 ((uint32_t)0x00080000) /*!< Write protection of page 76 to 79 */
-#define OB_WRP_PAGES80TO83 ((uint32_t)0x00100000) /*!< Write protection of page 80 to 83 */
-#define OB_WRP_PAGES84TO87 ((uint32_t)0x00200000) /*!< Write protection of page 84 to 87 */
-#define OB_WRP_PAGES88TO91 ((uint32_t)0x00400000) /*!< Write protection of page 88 to 91 */
-#define OB_WRP_PAGES92TO95 ((uint32_t)0x00800000) /*!< Write protection of page 92 to 95 */
-#define OB_WRP_PAGES96TO99 ((uint32_t)0x01000000) /*!< Write protection of page 96 to 99 */
-#define OB_WRP_PAGES100TO103 ((uint32_t)0x02000000) /*!< Write protection of page 100 to 103 */
-#define OB_WRP_PAGES104TO107 ((uint32_t)0x04000000) /*!< Write protection of page 104 to 107 */
-#define OB_WRP_PAGES108TO111 ((uint32_t)0x08000000) /*!< Write protection of page 108 to 111 */
-#define OB_WRP_PAGES112TO115 ((uint32_t)0x10000000) /*!< Write protection of page 112 to 115 */
-#define OB_WRP_PAGES116TO119 ((uint32_t)0x20000000) /*!< Write protection of page 115 to 119 */
-#define OB_WRP_PAGES120TO123 ((uint32_t)0x40000000) /*!< Write protection of page 120 to 123 */
-#define OB_WRP_PAGES124TO127 ((uint32_t)0x80000000) /*!< Write protection of page 124 to 127 */
+#define OB_WRP_PAGES32TO35 0x00000100U /*!< Write protection of page 32 to 35 */
+#define OB_WRP_PAGES36TO39 0x00000200U /*!< Write protection of page 36 to 39 */
+#define OB_WRP_PAGES40TO43 0x00000400U /*!< Write protection of page 40 to 43 */
+#define OB_WRP_PAGES44TO47 0x00000800U /*!< Write protection of page 44 to 47 */
+#define OB_WRP_PAGES48TO51 0x00001000U /*!< Write protection of page 48 to 51 */
+#define OB_WRP_PAGES52TO55 0x00002000U /*!< Write protection of page 52 to 55 */
+#define OB_WRP_PAGES56TO59 0x00004000U /*!< Write protection of page 56 to 59 */
+#define OB_WRP_PAGES60TO63 0x00008000U /*!< Write protection of page 60 to 63 */
+#define OB_WRP_PAGES64TO67 0x00010000U /*!< Write protection of page 64 to 67 */
+#define OB_WRP_PAGES68TO71 0x00020000U /*!< Write protection of page 68 to 71 */
+#define OB_WRP_PAGES72TO75 0x00040000U /*!< Write protection of page 72 to 75 */
+#define OB_WRP_PAGES76TO79 0x00080000U /*!< Write protection of page 76 to 79 */
+#define OB_WRP_PAGES80TO83 0x00100000U /*!< Write protection of page 80 to 83 */
+#define OB_WRP_PAGES84TO87 0x00200000U /*!< Write protection of page 84 to 87 */
+#define OB_WRP_PAGES88TO91 0x00400000U /*!< Write protection of page 88 to 91 */
+#define OB_WRP_PAGES92TO95 0x00800000U /*!< Write protection of page 92 to 95 */
+#define OB_WRP_PAGES96TO99 0x01000000U /*!< Write protection of page 96 to 99 */
+#define OB_WRP_PAGES100TO103 0x02000000U /*!< Write protection of page 100 to 103 */
+#define OB_WRP_PAGES104TO107 0x04000000U /*!< Write protection of page 104 to 107 */
+#define OB_WRP_PAGES108TO111 0x08000000U /*!< Write protection of page 108 to 111 */
+#define OB_WRP_PAGES112TO115 0x10000000U /*!< Write protection of page 112 to 115 */
+#define OB_WRP_PAGES116TO119 0x20000000U /*!< Write protection of page 115 to 119 */
+#define OB_WRP_PAGES120TO123 0x40000000U /*!< Write protection of page 120 to 123 */
+#define OB_WRP_PAGES124TO127 0x80000000U /*!< Write protection of page 124 to 127 */
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
@@ -378,81 +378,81 @@
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \
|| defined(STM32F101xG) || defined(STM32F103xG) \
|| defined(STM32F105xC) || defined(STM32F107xC)
-#define OB_WRP_PAGES0TO1 ((uint32_t)0x00000001) /*!< Write protection of page 0 TO 1 */
-#define OB_WRP_PAGES2TO3 ((uint32_t)0x00000002) /*!< Write protection of page 2 TO 3 */
-#define OB_WRP_PAGES4TO5 ((uint32_t)0x00000004) /*!< Write protection of page 4 TO 5 */
-#define OB_WRP_PAGES6TO7 ((uint32_t)0x00000008) /*!< Write protection of page 6 TO 7 */
-#define OB_WRP_PAGES8TO9 ((uint32_t)0x00000010) /*!< Write protection of page 8 TO 9 */
-#define OB_WRP_PAGES10TO11 ((uint32_t)0x00000020) /*!< Write protection of page 10 TO 11 */
-#define OB_WRP_PAGES12TO13 ((uint32_t)0x00000040) /*!< Write protection of page 12 TO 13 */
-#define OB_WRP_PAGES14TO15 ((uint32_t)0x00000080) /*!< Write protection of page 14 TO 15 */
-#define OB_WRP_PAGES16TO17 ((uint32_t)0x00000100) /*!< Write protection of page 16 TO 17 */
-#define OB_WRP_PAGES18TO19 ((uint32_t)0x00000200) /*!< Write protection of page 18 TO 19 */
-#define OB_WRP_PAGES20TO21 ((uint32_t)0x00000400) /*!< Write protection of page 20 TO 21 */
-#define OB_WRP_PAGES22TO23 ((uint32_t)0x00000800) /*!< Write protection of page 22 TO 23 */
-#define OB_WRP_PAGES24TO25 ((uint32_t)0x00001000) /*!< Write protection of page 24 TO 25 */
-#define OB_WRP_PAGES26TO27 ((uint32_t)0x00002000) /*!< Write protection of page 26 TO 27 */
-#define OB_WRP_PAGES28TO29 ((uint32_t)0x00004000) /*!< Write protection of page 28 TO 29 */
-#define OB_WRP_PAGES30TO31 ((uint32_t)0x00008000) /*!< Write protection of page 30 TO 31 */
-#define OB_WRP_PAGES32TO33 ((uint32_t)0x00010000) /*!< Write protection of page 32 TO 33 */
-#define OB_WRP_PAGES34TO35 ((uint32_t)0x00020000) /*!< Write protection of page 34 TO 35 */
-#define OB_WRP_PAGES36TO37 ((uint32_t)0x00040000) /*!< Write protection of page 36 TO 37 */
-#define OB_WRP_PAGES38TO39 ((uint32_t)0x00080000) /*!< Write protection of page 38 TO 39 */
-#define OB_WRP_PAGES40TO41 ((uint32_t)0x00100000) /*!< Write protection of page 40 TO 41 */
-#define OB_WRP_PAGES42TO43 ((uint32_t)0x00200000) /*!< Write protection of page 42 TO 43 */
-#define OB_WRP_PAGES44TO45 ((uint32_t)0x00400000) /*!< Write protection of page 44 TO 45 */
-#define OB_WRP_PAGES46TO47 ((uint32_t)0x00800000) /*!< Write protection of page 46 TO 47 */
-#define OB_WRP_PAGES48TO49 ((uint32_t)0x01000000) /*!< Write protection of page 48 TO 49 */
-#define OB_WRP_PAGES50TO51 ((uint32_t)0x02000000) /*!< Write protection of page 50 TO 51 */
-#define OB_WRP_PAGES52TO53 ((uint32_t)0x04000000) /*!< Write protection of page 52 TO 53 */
-#define OB_WRP_PAGES54TO55 ((uint32_t)0x08000000) /*!< Write protection of page 54 TO 55 */
-#define OB_WRP_PAGES56TO57 ((uint32_t)0x10000000) /*!< Write protection of page 56 TO 57 */
-#define OB_WRP_PAGES58TO59 ((uint32_t)0x20000000) /*!< Write protection of page 58 TO 59 */
-#define OB_WRP_PAGES60TO61 ((uint32_t)0x40000000) /*!< Write protection of page 60 TO 61 */
-#define OB_WRP_PAGES62TO127 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 127 */
-#define OB_WRP_PAGES62TO255 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 255 */
-#define OB_WRP_PAGES62TO511 ((uint32_t)0x80000000) /*!< Write protection of page 62 TO 511 */
+#define OB_WRP_PAGES0TO1 0x00000001U /*!< Write protection of page 0 TO 1 */
+#define OB_WRP_PAGES2TO3 0x00000002U /*!< Write protection of page 2 TO 3 */
+#define OB_WRP_PAGES4TO5 0x00000004U /*!< Write protection of page 4 TO 5 */
+#define OB_WRP_PAGES6TO7 0x00000008U /*!< Write protection of page 6 TO 7 */
+#define OB_WRP_PAGES8TO9 0x00000010U /*!< Write protection of page 8 TO 9 */
+#define OB_WRP_PAGES10TO11 0x00000020U /*!< Write protection of page 10 TO 11 */
+#define OB_WRP_PAGES12TO13 0x00000040U /*!< Write protection of page 12 TO 13 */
+#define OB_WRP_PAGES14TO15 0x00000080U /*!< Write protection of page 14 TO 15 */
+#define OB_WRP_PAGES16TO17 0x00000100U /*!< Write protection of page 16 TO 17 */
+#define OB_WRP_PAGES18TO19 0x00000200U /*!< Write protection of page 18 TO 19 */
+#define OB_WRP_PAGES20TO21 0x00000400U /*!< Write protection of page 20 TO 21 */
+#define OB_WRP_PAGES22TO23 0x00000800U /*!< Write protection of page 22 TO 23 */
+#define OB_WRP_PAGES24TO25 0x00001000U /*!< Write protection of page 24 TO 25 */
+#define OB_WRP_PAGES26TO27 0x00002000U /*!< Write protection of page 26 TO 27 */
+#define OB_WRP_PAGES28TO29 0x00004000U /*!< Write protection of page 28 TO 29 */
+#define OB_WRP_PAGES30TO31 0x00008000U /*!< Write protection of page 30 TO 31 */
+#define OB_WRP_PAGES32TO33 0x00010000U /*!< Write protection of page 32 TO 33 */
+#define OB_WRP_PAGES34TO35 0x00020000U /*!< Write protection of page 34 TO 35 */
+#define OB_WRP_PAGES36TO37 0x00040000U /*!< Write protection of page 36 TO 37 */
+#define OB_WRP_PAGES38TO39 0x00080000U /*!< Write protection of page 38 TO 39 */
+#define OB_WRP_PAGES40TO41 0x00100000U /*!< Write protection of page 40 TO 41 */
+#define OB_WRP_PAGES42TO43 0x00200000U /*!< Write protection of page 42 TO 43 */
+#define OB_WRP_PAGES44TO45 0x00400000U /*!< Write protection of page 44 TO 45 */
+#define OB_WRP_PAGES46TO47 0x00800000U /*!< Write protection of page 46 TO 47 */
+#define OB_WRP_PAGES48TO49 0x01000000U /*!< Write protection of page 48 TO 49 */
+#define OB_WRP_PAGES50TO51 0x02000000U /*!< Write protection of page 50 TO 51 */
+#define OB_WRP_PAGES52TO53 0x04000000U /*!< Write protection of page 52 TO 53 */
+#define OB_WRP_PAGES54TO55 0x08000000U /*!< Write protection of page 54 TO 55 */
+#define OB_WRP_PAGES56TO57 0x10000000U /*!< Write protection of page 56 TO 57 */
+#define OB_WRP_PAGES58TO59 0x20000000U /*!< Write protection of page 58 TO 59 */
+#define OB_WRP_PAGES60TO61 0x40000000U /*!< Write protection of page 60 TO 61 */
+#define OB_WRP_PAGES62TO127 0x80000000U /*!< Write protection of page 62 TO 127 */
+#define OB_WRP_PAGES62TO255 0x80000000U /*!< Write protection of page 62 TO 255 */
+#define OB_WRP_PAGES62TO511 0x80000000U /*!< Write protection of page 62 TO 511 */
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
/* STM32F101xG || STM32F103xG */
/* STM32F105xC || STM32F107xC */
-#define OB_WRP_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
+#define OB_WRP_ALLPAGES 0xFFFFFFFFU /*!< Write protection of all Pages */
/* Low Density */
#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
-#define OB_WRP_PAGES0TO31MASK ((uint32_t)0x000000FF)
+#define OB_WRP_PAGES0TO31MASK 0x000000FFU
#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
/* Medium Density */
#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
-#define OB_WRP_PAGES0TO31MASK ((uint32_t)0x000000FF)
-#define OB_WRP_PAGES32TO63MASK ((uint32_t)0x0000FF00)
-#define OB_WRP_PAGES64TO95MASK ((uint32_t)0x00FF0000)
-#define OB_WRP_PAGES96TO127MASK ((uint32_t)0xFF000000)
+#define OB_WRP_PAGES0TO31MASK 0x000000FFU
+#define OB_WRP_PAGES32TO63MASK 0x0000FF00U
+#define OB_WRP_PAGES64TO95MASK 0x00FF0000U
+#define OB_WRP_PAGES96TO127MASK 0xFF000000U
#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
/* High Density */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)
-#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
-#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
-#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
-#define OB_WRP_PAGES48TO255MASK ((uint32_t)0xFF000000)
+#define OB_WRP_PAGES0TO15MASK 0x000000FFU
+#define OB_WRP_PAGES16TO31MASK 0x0000FF00U
+#define OB_WRP_PAGES32TO47MASK 0x00FF0000U
+#define OB_WRP_PAGES48TO255MASK 0xFF000000U
#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
/* XL Density */
#if defined(STM32F101xG) || defined(STM32F103xG)
-#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
-#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
-#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
-#define OB_WRP_PAGES48TO511MASK ((uint32_t)0xFF000000)
+#define OB_WRP_PAGES0TO15MASK 0x000000FFU
+#define OB_WRP_PAGES16TO31MASK 0x0000FF00U
+#define OB_WRP_PAGES32TO47MASK 0x00FF0000U
+#define OB_WRP_PAGES48TO511MASK 0xFF000000U
#endif /* STM32F101xG || STM32F103xG */
/* Connectivity line devices */
#if defined(STM32F105xC) || defined(STM32F107xC)
-#define OB_WRP_PAGES0TO15MASK ((uint32_t)0x000000FF)
-#define OB_WRP_PAGES16TO31MASK ((uint32_t)0x0000FF00)
-#define OB_WRP_PAGES32TO47MASK ((uint32_t)0x00FF0000)
-#define OB_WRP_PAGES48TO127MASK ((uint32_t)0xFF000000)
+#define OB_WRP_PAGES0TO15MASK 0x000000FFU
+#define OB_WRP_PAGES16TO31MASK 0x0000FF00U
+#define OB_WRP_PAGES32TO47MASK 0x00FF0000U
+#define OB_WRP_PAGES48TO127MASK 0xFF000000U
#endif /* STM32F105xC || STM32F107xC */
/**
@@ -509,8 +509,8 @@
/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
* @{
*/
-#define OB_DATA_ADDRESS_DATA0 ((uint32_t)0x1FFFF804)
-#define OB_DATA_ADDRESS_DATA1 ((uint32_t)0x1FFFF806)
+#define OB_DATA_ADDRESS_DATA0 0x1FFFF804U
+#define OB_DATA_ADDRESS_DATA1 0x1FFFF806U
/**
* @}
*/
@@ -538,10 +538,10 @@
#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag */
#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< FLASH Bank1 End of Operation flag */
- #define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16) /*!< FLASH Bank2 Busy flag */
- #define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16) /*!< FLASH Bank2 Programming error flag */
- #define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16) /*!< FLASH Bank2 Write protected error flag */
- #define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16) /*!< FLASH Bank2 End of Operation flag */
+ #define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16U) /*!< FLASH Bank2 Busy flag */
+ #define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16U) /*!< FLASH Bank2 Programming error flag */
+ #define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16U) /*!< FLASH Bank2 Write protected error flag */
+ #define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16U) /*!< FLASH Bank2 End of Operation flag */
#else
@@ -551,7 +551,7 @@
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
#endif
- #define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8 | FLASH_OBR_OPTERR)) /*!< Option Byte Error */
+ #define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR)) /*!< Option Byte Error */
/**
* @}
*/
@@ -567,8 +567,8 @@
#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source Bank1 */
#define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE /*!< Error Interrupt source Bank1 */
- #define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16) /*!< End of FLASH Operation Interrupt source Bank2 */
- #define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16) /*!< Error Interrupt source Bank2 */
+ #define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16U) /*!< End of FLASH Operation Interrupt source Bank2 */
+ #define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16U) /*!< Error Interrupt source Bank2 */
#else
@@ -612,10 +612,10 @@
*/
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \
/* Enable Bank1 IT */ \
- SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFF)); \
+ SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
/* Enable Bank2 IT */ \
- SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16)); \
- } while(0)
+ SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
+ } while(0U)
/**
* @brief Disable the specified FLASH interrupt.
@@ -629,10 +629,10 @@
*/
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \
/* Disable Bank1 IT */ \
- CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFF)); \
+ CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
/* Disable Bank2 IT */ \
- CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16)); \
- } while(0)
+ CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
+ } while(0U)
/**
* @brief Get the specified FLASH flag status.
@@ -653,7 +653,7 @@
(FLASH->OBR & FLASH_OBR_OPTERR) : \
((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
(FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
- (FLASH->SR2 & ((__FLAG__) >> 16))))
+ (FLASH->SR2 & ((__FLAG__) >> 16U))))
/**
* @brief Clear the specified FLASH flag.
@@ -683,12 +683,12 @@
FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \
} \
/* Clear Flag in Bank2 */ \
- if (((__FLAG__) >> 16) != RESET) \
+ if (((__FLAG__) >> 16U) != RESET) \
{ \
- FLASH->SR2 = ((__FLAG__) >> 16); \
+ FLASH->SR2 = ((__FLAG__) >> 16U); \
} \
} \
- } while(0)
+ } while(0U)
#else
/**
* @brief Enable the specified FLASH interrupt.
@@ -744,7 +744,7 @@
/* Clear Flag in Bank1 */ \
FLASH->SR = (__FLAG__); \
} \
- } while(0)
+ } while(0U)
#endif
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_gpio.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_gpio.h
index 27a55fc..fa14df7 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_gpio.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_gpio.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_gpio.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
@@ -57,10 +57,10 @@
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
- */
+ */
/**
- * @brief GPIO Init structure definition
+ * @brief GPIO Init structure definition
*/
typedef struct
{
@@ -69,28 +69,26 @@
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode_define */
-
+
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull_define */
-
+
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed_define */
}GPIO_InitTypeDef;
-
+
/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
-{
- GPIO_PIN_RESET = 0,
+{
+ GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
}GPIO_PinState;
-
/**
* @}
*/
-
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
@@ -99,7 +97,7 @@
/** @defgroup GPIO_pins_define GPIO pins define
* @{
- */
+ */
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
@@ -118,12 +116,11 @@
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
-#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
+#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */
/**
* @}
- */
+ */
-
/** @defgroup GPIO_mode_define GPIO mode define
* @brief GPIO Configuration Mode
* Elements values convention: 0xX0yz00YZ
@@ -134,32 +131,31 @@
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{
*/
-#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */
-#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */
-#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */
-#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */
-#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */
+#define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */
+#define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */
+#define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */
+#define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */
+#define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */
-#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */
+#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */
-#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */
+#define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */
+#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
-#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */
+#define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */
+#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
-
-
-/** @defgroup GPIO_speed_define GPIO speed define
+
+/** @defgroup GPIO_speed_define GPIO speed define
* @brief GPIO Output Maximum frequency
* @{
- */
+ */
#define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */
#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */
#define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */
@@ -168,15 +164,13 @@
* @}
*/
-
/** @defgroup GPIO_pull_define GPIO pull define
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
-#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
-#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
-#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
-
+#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */
+#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */
+#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */
/**
* @}
*/
@@ -185,40 +179,6 @@
* @}
*/
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Macros
- * @{
- */
-
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-
-#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
-
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
- ((PULL) == GPIO_PULLDOWN))
-
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
- ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
-
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
- ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
- ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
- ((MODE) == GPIO_MODE_AF_PP) ||\
- ((MODE) == GPIO_MODE_AF_OD) ||\
- ((MODE) == GPIO_MODE_IT_RISING) ||\
- ((MODE) == GPIO_MODE_IT_FALLING) ||\
- ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING) ||\
- ((MODE) == GPIO_MODE_EVT_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_ANALOG))
-
-/**
- * @}
- */
-
-
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{
@@ -230,8 +190,8 @@
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
/**
* @brief Clears the EXTI's line pending flags.
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
@@ -246,8 +206,8 @@
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
/**
* @brief Clears the EXTI's line pending bits.
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
@@ -263,18 +223,14 @@
* @retval None
*/
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
-
-/* Include GPIO HAL Extension module */
-#include "stm32f1xx_hal_gpio_ex.h"
-
/**
* @}
*/
+/* Include GPIO HAL Extension module */
+#include "stm32f1xx_hal_gpio_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/* Initialization and de-initialization functions *******************************/
+/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions
* @{
*/
@@ -282,22 +238,73 @@
/** @addtogroup GPIO_Exported_Functions_Group1
* @{
*/
+/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/**
* @}
*/
-/* IO operation functions *******************************************************/
/** @addtogroup GPIO_Exported_Functions_Group2
* @{
*/
+/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+ * @{
+ */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+#define IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
+ ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
+ ((MODE) == GPIO_MODE_AF_PP) ||\
+ ((MODE) == GPIO_MODE_AF_OD) ||\
+ ((MODE) == GPIO_MODE_IT_RISING) ||\
+ ((MODE) == GPIO_MODE_IT_FALLING) ||\
+ ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING) ||\
+ ((MODE) == GPIO_MODE_EVT_FALLING) ||\
+ ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+ ((MODE) == GPIO_MODE_ANALOG))
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
+ ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+ ((PULL) == GPIO_PULLDOWN))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Functions GPIO Private Functions
+ * @{
+ */
+
/**
* @}
*/
@@ -308,12 +315,7 @@
/**
* @}
- */
-
-/**
- * @}
- */
-
+ */
#ifdef __cplusplus
}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_gpio_ex.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_gpio_ex.h
index 214fe18..13fa3bd 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_gpio_ex.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_gpio_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_gpio_ex.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
@@ -197,70 +197,89 @@
* @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
* @retval None
*/
-#define __HAL_AFIO_REMAP_USART3_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
-
+#define __HAL_AFIO_REMAP_USART3_ENABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_FULLREMAP); \
+ }while(0U)
/**
* @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
* @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
* @retval None
*/
-#define __HAL_AFIO_REMAP_USART3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_PARTIALREMAP)
+#define __HAL_AFIO_REMAP_USART3_PARTIAL() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_PARTIALREMAP); \
+ }while(0U)
/**
* @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
* @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
* @retval None
*/
-#define __HAL_AFIO_REMAP_USART3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_NOREMAP)
+#define __HAL_AFIO_REMAP_USART3_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_NOREMAP); \
+ }while(0U)
/**
* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
* @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
* @retval None
*/
-#define __HAL_AFIO_REMAP_TIM1_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
+#define __HAL_AFIO_REMAP_TIM1_ENABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_FULLREMAP); \
+ }while(0U)
/**
* @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
* @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
* @retval None
*/
-#define __HAL_AFIO_REMAP_TIM1_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP)
+#define __HAL_AFIO_REMAP_TIM1_PARTIAL() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP); \
+ }while(0U)
/**
* @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
* @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
* @retval None
*/
-#define __HAL_AFIO_REMAP_TIM1_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_NOREMAP)
+#define __HAL_AFIO_REMAP_TIM1_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_NOREMAP); \
+ }while(0U)
/**
* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
* @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
* @retval None
*/
-#define __HAL_AFIO_REMAP_TIM2_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
+#define __HAL_AFIO_REMAP_TIM2_ENABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_FULLREMAP); \
+ }while(0U)
/**
* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
* @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
* @retval None
*/
-#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2)
+#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2); \
+ }while(0U)
/**
* @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
* @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
* @retval None
*/
-#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1)
+#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1); \
+ }while(0U)
/**
* @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
* @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
* @retval None
*/
-#define __HAL_AFIO_REMAP_TIM2_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_NOREMAP)
+#define __HAL_AFIO_REMAP_TIM2_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_NOREMAP); \
+ }while(0U)
/**
* @brief Enable the remapping of TIM3 alternate function channels 1 to 4
@@ -268,7 +287,9 @@
* @note TIM3_ETR on PE0 is not re-mapped.
* @retval None
*/
-#define __HAL_AFIO_REMAP_TIM3_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
+#define __HAL_AFIO_REMAP_TIM3_ENABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_FULLREMAP); \
+ }while(0U)
/**
* @brief Enable the remapping of TIM3 alternate function channels 1 to 4
@@ -276,7 +297,9 @@
* @note TIM3_ETR on PE0 is not re-mapped.
* @retval None
*/
-#define __HAL_AFIO_REMAP_TIM3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP)
+#define __HAL_AFIO_REMAP_TIM3_PARTIAL() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP); \
+ }while(0U)
/**
* @brief Disable the remapping of TIM3 alternate function channels 1 to 4
@@ -284,7 +307,9 @@
* @note TIM3_ETR on PE0 is not re-mapped.
* @retval None
*/
-#define __HAL_AFIO_REMAP_TIM3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_NOREMAP)
+#define __HAL_AFIO_REMAP_TIM3_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_NOREMAP); \
+ }while(0U)
/**
* @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
@@ -309,21 +334,27 @@
* @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
* @retval None
*/
-#define __HAL_AFIO_REMAP_CAN1_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP1)
+#define __HAL_AFIO_REMAP_CAN1_1() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP1); \
+ }while(0U)
/**
* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
* @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
* @retval None
*/
-#define __HAL_AFIO_REMAP_CAN1_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP2)
+#define __HAL_AFIO_REMAP_CAN1_2() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP2); \
+ }while(0U)
/**
* @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
* @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
* @retval None
*/
-#define __HAL_AFIO_REMAP_CAN1_3() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP3)
+#define __HAL_AFIO_REMAP_CAN1_3() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP3); \
+ }while(0U)
#endif
/**
@@ -486,28 +517,36 @@
* @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
* @retval None
*/
-#define __HAL_AFIO_REMAP_SWJ_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_RESET)
+#define __HAL_AFIO_REMAP_SWJ_ENABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET); \
+ }while(0U)
/**
* @brief Enable the Serial wire JTAG configuration
* @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
* @retval None
*/
-#define __HAL_AFIO_REMAP_SWJ_NONJTRST() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_NOJNTRST)
+#define __HAL_AFIO_REMAP_SWJ_NONJTRST() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST); \
+ }while(0U)
/**
* @brief Enable the Serial wire JTAG configuration
* @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
* @retval None
*/
-#define __HAL_AFIO_REMAP_SWJ_NOJTAG() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
+#define __HAL_AFIO_REMAP_SWJ_NOJTAG() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE); \
+ }while(0U)
/**
* @brief Disable the Serial wire JTAG configuration
* @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
* @retval None
*/
-#define __HAL_AFIO_REMAP_SWJ_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_DISABLE)
+#define __HAL_AFIO_REMAP_SWJ_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG); \
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE); \
+ }while(0U)
#if defined(AFIO_MAPR_SPI3_REMAP)
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_hcd.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_hcd.h
index 784f08b..e1ee3d4 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_hcd.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_hcd.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_hcd.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention
@@ -67,11 +67,11 @@
*/
typedef enum
{
- HAL_HCD_STATE_RESET = 0x00,
- HAL_HCD_STATE_READY = 0x01,
- HAL_HCD_STATE_ERROR = 0x02,
- HAL_HCD_STATE_BUSY = 0x03,
- HAL_HCD_STATE_TIMEOUT = 0x04
+ HAL_HCD_STATE_RESET = 0x00U,
+ HAL_HCD_STATE_READY = 0x01U,
+ HAL_HCD_STATE_ERROR = 0x02U,
+ HAL_HCD_STATE_BUSY = 0x03U,
+ HAL_HCD_STATE_TIMEOUT = 0x04U
} HCD_StateTypeDef;
typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
@@ -87,7 +87,7 @@
{
HCD_TypeDef *Instance; /*!< Register base address */
HCD_InitTypeDef Init; /*!< HCD required parameters */
- HCD_HCTypeDef hc[15]; /*!< Host channels parameters */
+ HCD_HCTypeDef hc[15U]; /*!< Host channels parameters */
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
__IO HCD_StateTypeDef State; /*!< HCD communication state */
void *pData; /*!< Pointer Stack Handler */
@@ -104,8 +104,8 @@
/** @defgroup HCD_Speed HCD Speed
* @{
*/
-#define HCD_SPEED_LOW 2
-#define HCD_SPEED_FULL 3
+#define HCD_SPEED_LOW 2U
+#define HCD_SPEED_FULL 3U
/**
* @}
@@ -126,7 +126,7 @@
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
-#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_i2c.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_i2c.h
index e4d055e..f5646a1 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_i2c.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_i2c.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
@@ -54,14 +54,13 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
-
-/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+
+/**
* @brief I2C Configuration Structure definition
- * @{
*/
typedef struct
{
@@ -91,112 +90,146 @@
}I2C_InitTypeDef;
-/**
- * @}
+/**
+ * @brief HAL State structure definition
+ * @note HAL I2C State value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : Abort (Abort user request on going)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
+ * b4 (not used)
+ * x : Should be set to 0
+ * b3
+ * 0 : Ready or Busy (No Listen mode ongoing)
+ * 1 : Listen (IP in Address Listen Mode)
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
*/
-
-/** @defgroup HAL_state_structure_definition HAL state structure definition
- * @brief HAL State structure definition
- * @{
- */
-
typedef enum
{
- HAL_I2C_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
- HAL_I2C_STATE_READY = 0x20, /*!< Peripheral Initialized and ready for use */
- HAL_I2C_STATE_BUSY = 0x24, /*!< An internal process is ongoing */
- HAL_I2C_STATE_BUSY_TX = 0x21, /*!< Data Transmission process is ongoing */
- HAL_I2C_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_I2C_STATE_TIMEOUT = 0xA0, /*!< Timeout state */
- HAL_I2C_STATE_ERROR = 0xE0 /*!< Error */
+ HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
+ HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
+ HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
+ HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
+ HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
+ HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
+ process is ongoing */
+ HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
+ process is ongoing */
+ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
+ HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
+ HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
}HAL_I2C_StateTypeDef;
-/**
- * @}
- */
-
-/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+/**
* @brief HAL Mode structure definition
- * @{
+ * @note HAL I2C Mode value coding follow below described bitmap :
+ * b7 (not used)
+ * x : Should be set to 0
+ * b6
+ * 0 : None
+ * 1 : Memory (HAL I2C communication is in Memory Mode)
+ * b5
+ * 0 : None
+ * 1 : Slave (HAL I2C communication is in Slave Mode)
+ * b4
+ * 0 : None
+ * 1 : Master (HAL I2C communication is in Master Mode)
+ * b3-b2-b1-b0 (not used)
+ * xxxx : Should be set to 0000
*/
typedef enum
{
- HAL_I2C_MODE_NONE = 0x00, /*!< No I2C communication on going */
- HAL_I2C_MODE_MASTER = 0x10, /*!< I2C communication is in Master Mode */
- HAL_I2C_MODE_SLAVE = 0x20, /*!< I2C communication is in Slave Mode */
- HAL_I2C_MODE_MEM = 0x40 /*!< I2C communication is in Memory Mode */
+ HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
+ HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
+ HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
+ HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
}HAL_I2C_ModeTypeDef;
-/**
- * @}
- */
-
-/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
- * @brief I2C handle Structure definition
- * @{
+/**
+ * @brief I2C handle Structure definition
*/
typedef struct
{
- I2C_TypeDef *Instance; /*!< I2C registers base address */
+ I2C_TypeDef *Instance; /*!< I2C registers base address */
+
+ I2C_InitTypeDef Init; /*!< I2C communication parameters */
+
+ uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
+
+ uint16_t XferSize; /*!< I2C transfer size */
+
+ __IO uint16_t XferCount; /*!< I2C transfer counter */
+
+ __IO uint32_t XferOptions; /*!< I2C transfer options */
+
+ __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
+ context for internal usage */
+
+ DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< I2C locking object */
+
+ __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
+
+ __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
+
+ __IO uint32_t ErrorCode; /*!< I2C Error code */
- I2C_InitTypeDef Init; /*!< I2C communication parameters */
+ __IO uint32_t Devaddress; /*!< I2C Target device address */
- uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
+ __IO uint32_t Memaddress; /*!< I2C Target memory address */
- uint16_t XferSize; /*!< I2C transfer size */
+ __IO uint32_t MemaddSize; /*!< I2C Target memory address size */
- __IO uint16_t XferCount; /*!< I2C transfer counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
-
- HAL_LockTypeDef Lock; /*!< I2C locking object */
-
- __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
-
- __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
-
- __IO uint32_t ErrorCode; /*!< I2C Error code */
-
+ __IO uint32_t EventCount; /*!< I2C Event counter */
+
}I2C_HandleTypeDef;
+
/**
* @}
*/
-/**
- * @}
- */
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/
-/** @defgroup I2C_Error_Codes I2C Error Codes
+/** @defgroup I2C_Error_Code I2C Error Code
+ * @brief I2C Error Code
* @{
*/
-
-#define HAL_I2C_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_I2C_ERROR_BERR ((uint32_t)0x01) /*!< BERR error */
-#define HAL_I2C_ERROR_ARLO ((uint32_t)0x02) /*!< ARLO error */
-#define HAL_I2C_ERROR_AF ((uint32_t)0x04) /*!< AF error */
-#define HAL_I2C_ERROR_OVR ((uint32_t)0x08) /*!< OVR error */
-#define HAL_I2C_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
-#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */
-
-/**
+#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */
+#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */
+#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */
+#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */
+#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
+/**
* @}
*/
-
-
-/** @defgroup I2C_duty_cycle_in_fast_mode I2C Duty Cycle
+/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
* @{
*/
-#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000)
+#define I2C_DUTYCYCLE_2 0x00000000U
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
/**
* @}
@@ -205,17 +238,17 @@
/** @defgroup I2C_addressing_mode I2C addressing mode
* @{
*/
-#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000)
-#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
+#define I2C_ADDRESSINGMODE_7BIT 0x00004000U
+#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)
/**
* @}
*/
-/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
+/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
* @{
*/
-#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
-#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
+#define I2C_DUALADDRESS_DISABLE 0x00000000U
+#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
/**
* @}
*/
@@ -223,8 +256,8 @@
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
* @{
*/
-#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
-#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
+#define I2C_GENERALCALL_DISABLE 0x00000000U
+#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
/**
* @}
*/
@@ -232,8 +265,8 @@
/** @defgroup I2C_nostretch_mode I2C nostretch mode
* @{
*/
-#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
-#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
+#define I2C_NOSTRETCH_DISABLE 0x00000000U
+#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
@@ -241,8 +274,28 @@
/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
* @{
*/
-#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
-#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010)
+#define I2C_MEMADD_SIZE_8BIT 0x00000001U
+#define I2C_MEMADD_SIZE_16BIT 0x00000010U
+/**
+ * @}
+ */
+
+/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
+ * @{
+ */
+#define I2C_DIRECTION_RECEIVE 0x00000000U
+#define I2C_DIRECTION_TRANSMIT 0x00000001U
+/**
+ * @}
+ */
+
+/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
+ * @{
+ */
+#define I2C_FIRST_FRAME 0x00000001U
+#define I2C_NEXT_FRAME 0x00000002U
+#define I2C_FIRST_AND_LAST_FRAME 0x00000004U
+#define I2C_LAST_FRAME 0x00000008U
/**
* @}
*/
@@ -258,199 +311,188 @@
*/
/** @defgroup I2C_Flag_definition I2C Flag definition
- * @brief I2C Interrupt definition
- * - 0001XXXX : Flag control mask for SR1 Register
- * - 0010XXXX : Flag control mask for SR2 Register
* @{
*/
-#define I2C_FLAG_SMBALERT ((uint32_t)0x00018000)
-#define I2C_FLAG_TIMEOUT ((uint32_t)0x00014000)
-#define I2C_FLAG_PECERR ((uint32_t)0x00011000)
-#define I2C_FLAG_OVR ((uint32_t)0x00010800)
-#define I2C_FLAG_AF ((uint32_t)0x00010400)
-#define I2C_FLAG_ARLO ((uint32_t)0x00010200)
-#define I2C_FLAG_BERR ((uint32_t)0x00010100)
-#define I2C_FLAG_TXE ((uint32_t)0x00010080)
-#define I2C_FLAG_RXNE ((uint32_t)0x00010040)
-#define I2C_FLAG_STOPF ((uint32_t)0x00010010)
-#define I2C_FLAG_ADD10 ((uint32_t)0x00010008)
-#define I2C_FLAG_BTF ((uint32_t)0x00010004)
-#define I2C_FLAG_ADDR ((uint32_t)0x00010002)
-#define I2C_FLAG_SB ((uint32_t)0x00010001)
-#define I2C_FLAG_DUALF ((uint32_t)0x00100080)
-#define I2C_FLAG_SMBHOST ((uint32_t)0x00100040)
-#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020)
-#define I2C_FLAG_GENCALL ((uint32_t)0x00100010)
-#define I2C_FLAG_TRA ((uint32_t)0x00100004)
-#define I2C_FLAG_BUSY ((uint32_t)0x00100002)
-#define I2C_FLAG_MSL ((uint32_t)0x00100001)
-#define I2C_FLAG_MASK ((uint32_t)0x0000FFFF)
+#define I2C_FLAG_SMBALERT 0x00018000U
+#define I2C_FLAG_TIMEOUT 0x00014000U
+#define I2C_FLAG_PECERR 0x00011000U
+#define I2C_FLAG_OVR 0x00010800U
+#define I2C_FLAG_AF 0x00010400U
+#define I2C_FLAG_ARLO 0x00010200U
+#define I2C_FLAG_BERR 0x00010100U
+#define I2C_FLAG_TXE 0x00010080U
+#define I2C_FLAG_RXNE 0x00010040U
+#define I2C_FLAG_STOPF 0x00010010U
+#define I2C_FLAG_ADD10 0x00010008U
+#define I2C_FLAG_BTF 0x00010004U
+#define I2C_FLAG_ADDR 0x00010002U
+#define I2C_FLAG_SB 0x00010001U
+#define I2C_FLAG_DUALF 0x00100080U
+#define I2C_FLAG_SMBHOST 0x00100040U
+#define I2C_FLAG_SMBDEFAULT 0x00100020U
+#define I2C_FLAG_GENCALL 0x00100010U
+#define I2C_FLAG_TRA 0x00100004U
+#define I2C_FLAG_BUSY 0x00100002U
+#define I2C_FLAG_MSL 0x00100001U
/**
* @}
*/
/**
* @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
+ */
+/* Exported macro ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Macros I2C Exported Macros
* @{
*/
-/** @brief Reset I2C handle state.
- * @param __HANDLE__ specifies the I2C Handle.
+/** @brief Reset I2C handle state
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @retval None
*/
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-/** @brief Enable the specified I2C interrupt.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __INTERRUPT__: specifies the interrupt source to enable.
+/** @brief Enable or disable the specified I2C interrupts.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
- * @arg @ref I2C_IT_BUF Buffer interrupt enable
- * @arg @ref I2C_IT_EVT Event interrupt enable
- * @arg @ref I2C_IT_ERR Error interrupt enable
+ * @arg I2C_IT_BUF: Buffer interrupt enable
+ * @arg I2C_IT_EVT: Event interrupt enable
+ * @arg I2C_IT_ERR: Error interrupt enable
* @retval None
*/
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)))
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
-/** @brief Disable the specified I2C interrupt.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __INTERRUPT__: specifies the interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg @ref I2C_IT_BUF Buffer interrupt enable
- * @arg @ref I2C_IT_EVT Event interrupt enable
- * @arg @ref I2C_IT_ERR Error interrupt enable
- * @retval None
- */
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)))
-
-/** @brief Check whether the specified I2C interrupt source is enabled or not.
- * @param __HANDLE__ specifies the I2C Handle.
+/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @param __INTERRUPT__: specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
- * @arg @ref I2C_IT_BUF Buffer interrupt enable
- * @arg @ref I2C_IT_EVT Event interrupt enable
- * @arg @ref I2C_IT_ERR Error interrupt enable
+ * @arg I2C_IT_BUF: Buffer interrupt enable
+ * @arg I2C_IT_EVT: Event interrupt enable
+ * @arg I2C_IT_ERR: Error interrupt enable
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-/** @brief Check whether the specified I2C flag is set or not.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __FLAG__ specifies the flag to check.
+/** @brief Checks whether the specified I2C flag is set or not.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
- * @arg @ref I2C_FLAG_SMBALERT SMBus Alert flag
- * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow error flag
- * @arg @ref I2C_FLAG_PECERR PEC error in reception flag
- * @arg @ref I2C_FLAG_OVR Overrun/Underrun flag
- * @arg @ref I2C_FLAG_AF Acknowledge failure flag
- * @arg @ref I2C_FLAG_ARLO Arbitration lost flag
- * @arg @ref I2C_FLAG_BERR Bus error flag
- * @arg @ref I2C_FLAG_TXE Data register empty flag
- * @arg @ref I2C_FLAG_RXNE Data register not empty flag
- * @arg @ref I2C_FLAG_STOPF Stop detection flag
- * @arg @ref I2C_FLAG_ADD10 10-bit header sent flag
- * @arg @ref I2C_FLAG_BTF Byte transfer finished flag
- * @arg @ref I2C_FLAG_ADDR Address sent flag
- * Address matched flag
- * @arg @ref I2C_FLAG_SB Start bit flag
- * @arg @ref I2C_FLAG_DUALF Dual flag
- * @arg @ref I2C_FLAG_SMBHOST SMBus host header
- * @arg @ref I2C_FLAG_SMBDEFAULT SMBus default header
- * @arg @ref I2C_FLAG_GENCALL General call header flag
- * @arg @ref I2C_FLAG_TRA Transmitter/Receiver flag
- * @arg @ref I2C_FLAG_BUSY Bus busy flag
- * @arg @ref I2C_FLAG_MSL Master/Slave flag
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag
+ * @arg I2C_FLAG_BERR: Bus error flag
+ * @arg I2C_FLAG_TXE: Data register empty flag
+ * @arg I2C_FLAG_RXNE: Data register not empty flag
+ * @arg I2C_FLAG_STOPF: Stop detection flag
+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag
+ * @arg I2C_FLAG_BTF: Byte transfer finished flag
+ * @arg I2C_FLAG_ADDR: Address sent flag
+ * Address matched flag
+ * @arg I2C_FLAG_SB: Start bit flag
+ * @arg I2C_FLAG_DUALF: Dual flag
+ * @arg I2C_FLAG_SMBHOST: SMBus host header
+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header
+ * @arg I2C_FLAG_GENCALL: General call header flag
+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+ * @arg I2C_FLAG_BUSY: Bus busy flag
+ * @arg I2C_FLAG_MSL: Master/Slave flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
-/** @brief Clear the I2C pending flags which are cleared by writing 0 in a specific bit.
- * @param __HANDLE__ specifies the I2C Handle.
- * @param __FLAG__ specifies the flag to clear.
+/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
+ * @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
- * @arg @ref I2C_FLAG_SMBALERT SMBus Alert flag
- * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow error flag
- * @arg @ref I2C_FLAG_PECERR PEC error in reception flag
- * @arg @ref I2C_FLAG_OVR Overrun/Underrun flag (Slave mode)
- * @arg @ref I2C_FLAG_AF Acknowledge failure flag
- * @arg @ref I2C_FLAG_ARLO Arbitration lost flag (Master mode)
- * @arg @ref I2C_FLAG_BERR Bus error flag
- *
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+ * @arg I2C_FLAG_AF: Acknowledge failure flag
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+ * @arg I2C_FLAG_BERR: Bus error flag
* @retval None
*/
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HANDLE__)->Instance->SR1 = (((__HANDLE__)->Instance->SR1) & (~((__FLAG__) & I2C_FLAG_MASK)))
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
/** @brief Clears the I2C ADDR pending flag.
* @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @retval None
*/
-#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->SR1; \
- tmpreg = (__HANDLE__)->Instance->SR2; \
- UNUSED(tmpreg); \
-}while(0)
+#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR1; \
+ tmpreg = (__HANDLE__)->Instance->SR2; \
+ UNUSED(tmpreg); \
+ } while(0U)
/** @brief Clears the I2C STOPF pending flag.
* @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @retval None
*/
-#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
-do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->SR1; \
- tmpreg = (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \
- UNUSED(tmpreg); \
-}while(0)
+#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR1; \
+ (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \
+ UNUSED(tmpreg); \
+ } while(0U)
+
+/** @brief Enable the I2C peripheral.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
+ * @retval None
+ */
+#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
-/** @brief Enable the specified I2C peripheral.
- * @param __HANDLE__ specifies the I2C Handle.
+/** @brief Disable the I2C peripheral.
+ * @param __HANDLE__: specifies the I2C Handle.
+ * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
* @retval None
*/
-#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief Disable the specified I2C peripheral.
- * @param __HANDLE__ specifies the I2C Handle.
- * @retval None
- */
-#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
/**
* @}
- */
+ */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_Exported_Functions
* @{
*/
-/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup I2C_Exported_Functions_Group1
* @{
*/
-
-/* Initialization/de-initialization functions ********************************/
+/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-
/**
* @}
- */
+ */
-/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+/** @addtogroup I2C_Exported_Functions_Group2
* @{
*/
-
-/* IO operation functions ****************************************************/
-
- /******* Blocking mode: Polling */
+/* I/O operation functions *****************************************************/
+/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -458,29 +500,31 @@
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
-
- /******* Non-Blocking mode: Interrupt */
+
+/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
- /******* Non-Blocking mode: DMA */
+
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+
+/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-/**
- * @}
- */
-/** @addtogroup I2C_Exported_Functions_Group4 IRQ Handler and Callbacks
- * @{
- */
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
@@ -488,22 +532,23 @@
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-
+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
- */
+ */
-
-/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
+/** @addtogroup I2C_Exported_Functions_Group3
* @{
*/
-
-/* Peripheral State and Errors functions *************************************/
+/* Peripheral State, Mode and Errors functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/**
* @}
@@ -511,85 +556,88 @@
/**
* @}
- */
-
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
-#define I2C_STANDARD_MODE_MAX_CLK ((uint32_t)100000) /* Standard Clock Up to 100kHz */
-#define I2C_FAST_MODE_MAX_CLK ((uint32_t)400000) /* Fast Clock up to 400kHz */
+#define I2C_FLAG_MASK 0x0000FFFFU
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macro I2C Private Macros
+/** @defgroup I2C_Private_Macros I2C Private Macros
* @{
*/
-#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
- ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
-
-#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
- ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
-
-#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
- ((CALL) == I2C_GENERALCALL_ENABLE))
-
-#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
- ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-
-#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
- ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
-
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
-
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= I2C_FAST_MODE_MAX_CLK))
-
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
- ((CYCLE) == I2C_DUTYCYCLE_16_9))
-
-#define I2C_FREQ_RANGE(__PCLK__) ((__PCLK__)/1000000)
-#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= I2C_STANDARD_MODE_MAX_CLK) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
-
-#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
-#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
-#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
- ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
+
+#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
+#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
+#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
+#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9))
+#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
+ ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
-#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-
-#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
-#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
+#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
+#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
-#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
-#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
+#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))
+#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
+
+/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
+ * @{
+ */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
+ ((CYCLE) == I2C_DUTYCYCLE_16_9))
+#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
+ ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
+#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+ ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
+ ((CALL) == I2C_GENERALCALL_ENABLE))
+#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+ ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+ ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U))
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
+ ((REQUEST) == I2C_NEXT_FRAME) || \
+ ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
+ ((REQUEST) == I2C_LAST_FRAME))
/**
* @}
- */
+ */
-/* Private Fonctions ---------------------------------------------------------*/
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
-/* Private functions are defined in stm32f1xx_hal_i2c.c file */
-/**
- * @}
- */
/**
* @}
- */
+ */
/**
* @}
- */
-
+ */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_i2s.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_i2s.h
index c3dfe6e..f38f617 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_i2s.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_i2s.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f1xx_hal_i2s.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_I2S_H
@@ -54,87 +54,91 @@
/** @addtogroup I2S
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2S_Exported_Types I2S Exported Types
* @{
*/
-/**
- * @brief I2S Init structure definition
+/**
+ * @brief I2S Init structure definition
*/
typedef struct
{
- uint32_t Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_Mode */
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_Mode */
- uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_Standard */
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_Standard */
- uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref I2S_Data_Format */
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_Data_Format */
- uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref I2S_MCLK_Output */
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_MCLK_Output */
- uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref I2S_Audio_Frequency */
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_Audio_Frequency */
- uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref I2S_Clock_Polarity */
-
+ uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_Clock_Polarity */
}I2S_InitTypeDef;
-/**
+/**
* @brief HAL State structures definition
- */
+ */
typedef enum
{
- HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
- HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
- HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
- HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S timeout state */
- HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */
+ HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
+ HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
+ HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
+ HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
+ HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
+ HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
+ HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
+
}HAL_I2S_StateTypeDef;
-/**
- * @brief I2S handle Structure definition
+/**
+ * @brief I2S handle Structure definition
*/
-typedef struct
+typedef struct __I2S_HandleTypeDef
{
- SPI_TypeDef *Instance; /* I2S registers base address */
+ SPI_TypeDef *Instance; /*!< I2S registers base address */
- I2S_InitTypeDef Init; /* I2S communication parameters */
-
- uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
-
- __IO uint16_t TxXferSize; /* I2S Tx transfer size */
-
- __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
-
- uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
-
- __IO uint16_t RxXferSize; /* I2S Rx transfer size */
-
- __IO uint16_t RxXferCount; /* I2S Rx transfer counter
- (This field is initialized at the
- same value as transfer size at the
- beginning of the transfer and
- decremented when a sample is received.
+ I2S_InitTypeDef Init; /*!< I2S communication parameters */
+
+ uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
+
+ __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
+
+ __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
+
+ uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
+
+ __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
+
+ __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
+ (This field is initialized at the
+ same value as transfer size at the
+ beginning of the transfer and
+ decremented when a sample is received
NbSamplesReceived = RxBufferSize-RxBufferCount) */
- DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
+ void (*IrqHandlerISR) (struct __I2S_HandleTypeDef *hi2s); /*!< I2S function pointer on IrqHandler */
- DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
-
- __IO HAL_LockTypeDef Lock; /* I2S locking object */
-
- __IO HAL_I2S_StateTypeDef State; /* I2S communication state */
+ DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
- __IO uint32_t ErrorCode; /* I2S Error code */
+ DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
+
+ __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
+
+ __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
+
+ __IO uint32_t ErrorCode; /*!< I2S Error code
+ This parameter can be a value of @ref I2S_ErrorCode */
}I2S_HandleTypeDef;
/**
@@ -145,66 +149,59 @@
/** @defgroup I2S_Exported_Constants I2S Exported Constants
* @{
*/
-
-/** @defgroup I2S_Error_Codes I2S Error Codes
+/**
+ * @defgroup I2S_ErrorCode I2S Error Code
* @{
*/
-#define HAL_I2S_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_I2S_ERROR_UDR ((uint32_t)0x01) /*!< I2S Underrun error */
-#define HAL_I2S_ERROR_OVR ((uint32_t)0x02) /*!< I2S Overrun error */
-#define HAL_I2S_ERROR_FRE ((uint32_t)0x04) /*!< I2S Frame format error */
-#define HAL_I2S_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */
-
+#define HAL_I2S_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_I2S_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
+#define HAL_I2S_ERROR_OVR 0x00000002U /*!< OVR error */
+#define HAL_I2S_ERROR_UDR 0x00000004U /*!< UDR error */
+#define HAL_I2S_ERROR_DMA 0x00000008U /*!< DMA transfer error */
+#define HAL_I2S_ERROR_PRESCALER 0x00000010U /*!< Prescaler Calculation error */
/**
* @}
*/
-
/** @defgroup I2S_Mode I2S Mode
* @{
*/
-#define I2S_MODE_SLAVE_TX ((uint32_t) 0x00000000)
-#define I2S_MODE_SLAVE_RX ((uint32_t) SPI_I2SCFGR_I2SCFG_0)
-#define I2S_MODE_MASTER_TX ((uint32_t) SPI_I2SCFGR_I2SCFG_1)
-#define I2S_MODE_MASTER_RX ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 |\
- SPI_I2SCFGR_I2SCFG_1))
-
+#define I2S_MODE_SLAVE_TX 0x00000000U
+#define I2S_MODE_SLAVE_RX ((uint32_t)SPI_I2SCFGR_I2SCFG_0)
+#define I2S_MODE_MASTER_TX ((uint32_t)SPI_I2SCFGR_I2SCFG_1)
+#define I2S_MODE_MASTER_RX ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
/**
* @}
*/
-
+
/** @defgroup I2S_Standard I2S Standard
* @{
*/
-#define I2S_STANDARD_PHILIPS ((uint32_t) 0x00000000)
-#define I2S_STANDARD_MSB ((uint32_t) SPI_I2SCFGR_I2SSTD_0)
-#define I2S_STANDARD_LSB ((uint32_t) SPI_I2SCFGR_I2SSTD_1)
-#define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
- SPI_I2SCFGR_I2SSTD_1))
-#define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
- SPI_I2SCFGR_I2SSTD_1 |\
- SPI_I2SCFGR_PCMSYNC))
-
+#define I2S_STANDARD_PHILIPS 0x00000000U
+#define I2S_STANDARD_MSB ((uint32_t)SPI_I2SCFGR_I2SSTD_0)
+#define I2S_STANDARD_LSB ((uint32_t)SPI_I2SCFGR_I2SSTD_1)
+#define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
+#define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
/**
* @}
*/
-
+
/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
-#define I2S_DATAFORMAT_16B ((uint32_t) 0x00000000)
-#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t) SPI_I2SCFGR_CHLEN)
+#define I2S_DATAFORMAT_16B 0x00000000U
+#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)SPI_I2SCFGR_CHLEN)
#define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
#define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
/**
* @}
*/
-/** @defgroup I2S_MCLK_Output I2S MCLK Output
+/** @defgroup I2S_MCLK_Output I2S Mclk Output
* @{
*/
#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
+#define I2S_MCLKOUTPUT_DISABLE 0x00000000U
/**
* @}
*/
@@ -212,30 +209,30 @@
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
-#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
-#define I2S_AUDIOFREQ_96K ((uint32_t)96000)
-#define I2S_AUDIOFREQ_48K ((uint32_t)48000)
-#define I2S_AUDIOFREQ_44K ((uint32_t)44100)
-#define I2S_AUDIOFREQ_32K ((uint32_t)32000)
-#define I2S_AUDIOFREQ_22K ((uint32_t)22050)
-#define I2S_AUDIOFREQ_16K ((uint32_t)16000)
-#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
-#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
-#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
+#define I2S_AUDIOFREQ_192K 192000U
+#define I2S_AUDIOFREQ_96K 96000U
+#define I2S_AUDIOFREQ_48K 48000U
+#define I2S_AUDIOFREQ_44K 44100U
+#define I2S_AUDIOFREQ_32K 32000U
+#define I2S_AUDIOFREQ_22K 22050U
+#define I2S_AUDIOFREQ_16K 16000U
+#define I2S_AUDIOFREQ_11K 11025U
+#define I2S_AUDIOFREQ_8K 8000U
+#define I2S_AUDIOFREQ_DEFAULT 2U
/**
* @}
*/
-/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
+/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
-#define I2S_CPOL_LOW ((uint32_t)0x00000000)
+#define I2S_CPOL_LOW 0x00000000U
#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
/**
* @}
*/
-/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
+/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
* @{
*/
#define I2S_IT_TXE SPI_CR2_TXEIE
@@ -245,7 +242,7 @@
* @}
*/
-/** @defgroup I2S_Flag_definition I2S Flag definition
+/** @defgroup I2S_Flags_Definition I2S Flags Definition
* @{
*/
#define I2S_FLAG_TXE SPI_SR_TXE
@@ -263,21 +260,21 @@
/**
* @}
- */
-
+ */
+
/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_macros I2S Exported Macros
+/** @defgroup I2S_Exported_Macros I2S Exported Macros
* @{
*/
-/** @brief Reset I2S handle state
+/** @brief Reset I2S handle state
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
/** @brief Enable the specified SPI peripheral (in I2S mode).
- * @param __HANDLE__: specifies the I2S Handle.
+ * @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
@@ -296,7 +293,7 @@
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
- */
+ */
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
/** @brief Disable the specified I2S interrupts.
@@ -330,6 +327,7 @@
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
* @arg I2S_FLAG_UDR: Underrun flag
* @arg I2S_FLAG_OVR: Overrun flag
+ * @arg I2S_FLAG_FRE: Frame error flag
* @arg I2S_FLAG_CHSIDE: Channel Side flag
* @arg I2S_FLAG_BSY: Busy flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
@@ -339,25 +337,34 @@
/** @brief Clears the I2S OVR pending flag.
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
- */
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\
- tmpreg = (__HANDLE__)->Instance->SR;\
- UNUSED(tmpreg); \
- }while(0)
+ */
+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0U)
+
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg); \
+ } while(0U)
/**
* @}
- */
-
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2S_Exported_Functions
* @{
*/
-
+
/** @addtogroup I2S_Exported_Functions_Group1
* @{
*/
@@ -374,7 +381,7 @@
* @{
*/
/* I/O operation functions ***************************************************/
- /* Blocking mode: Polling */
+/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
@@ -415,6 +422,17 @@
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_Private_Constants I2S Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_irda.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_irda.h
index b0ac712..d91ae9a 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_irda.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_irda.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f1xx_hal_irda.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -57,7 +57,7 @@
/* Exported types ------------------------------------------------------------*/
/** @defgroup IRDA_Exported_Types IRDA Exported Types
* @{
- */
+ */
/**
* @brief IRDA Init Structure definition
@@ -79,8 +79,8 @@
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
-
- uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref IRDA_Transfer_Mode */
uint8_t Prescaler; /*!< Specifies the Prescaler value prescaler value to be programmed
@@ -93,52 +93,100 @@
}IRDA_InitTypeDef;
/**
- * @brief HAL IRDA State structures definition
+ * @brief HAL IRDA State structures definition
+ * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
+ * - gState contains IRDA state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : (Not Used)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized. HAL IRDA Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
*/
typedef enum
{
- HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
- HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
- HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */
+ HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
+ Value is allowed for gState and RxState */
+ HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+ HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing
+ Value is allowed for gState only */
+ HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+ HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+ HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+ HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
+ Value is allowed for gState only */
+ HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
+ Value is allowed for gState only */
}HAL_IRDA_StateTypeDef;
-
/**
- * @brief IRDA handle Structure definition
+ * @brief IRDA handle Structure definition
*/
typedef struct
{
USART_TypeDef *Instance; /*!< USART registers base address */
-
+
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
-
+
uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
-
+
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
-
- uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
-
+
+ __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
+
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
-
+
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
-
- uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
-
+
+ __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
+
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
-
+
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
-
+
HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_IRDA_StateTypeDef State; /*!< IRDA communication state */
-
- __IO uint32_t ErrorCode; /*!< IRDA Error code */
-
+
+ __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+ __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
+ This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
+
+ __IO uint32_t ErrorCode; /*!< IRDA Error code */
}IRDA_HandleTypeDef;
/**
@@ -149,44 +197,39 @@
/** @defgroup IRDA_Exported_Constants IRDA Exported constants
* @{
*/
-
-/** @defgroup IRDA_Error_Codes IRDA Error Codes
+/** @defgroup IRDA_Error_Code IRDA Error Code
* @{
- */
-#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_IRDA_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
-#define HAL_IRDA_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
-#define HAL_IRDA_ERROR_FE ((uint32_t)0x04) /*!< frame error */
-#define HAL_IRDA_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
-#define HAL_IRDA_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
-
+ */
+#define HAL_IRDA_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_IRDA_ERROR_PE 0x00000001U /*!< Parity error */
+#define HAL_IRDA_ERROR_NE 0x00000002U /*!< Noise error */
+#define HAL_IRDA_ERROR_FE 0x00000004U /*!< Frame error */
+#define HAL_IRDA_ERROR_ORE 0x00000008U /*!< Overrun error */
+#define HAL_IRDA_ERROR_DMA 0x00000010U /*!< DMA transfer error */
/**
* @}
*/
-
/** @defgroup IRDA_Word_Length IRDA Word Length
* @{
*/
-#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define IRDA_WORDLENGTH_8B 0x00000000U
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
*/
-
-/** @defgroup IRDA_Parity IRDA Parity
+/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
-#define IRDA_PARITY_NONE ((uint32_t)0x00000000)
+#define IRDA_PARITY_NONE 0x00000000U
#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
* @}
*/
-
-/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
+/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
* @{
*/
#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
@@ -196,11 +239,11 @@
* @}
*/
-/** @defgroup IRDA_Low_Power IRDA Low Power
+/** @defgroup IRDA_Low_Power IRDA Low Power
* @{
*/
-#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
-#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000)
+#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
+#define IRDA_POWERMODE_NORMAL 0x00000000U
/**
* @}
*/
@@ -224,26 +267,23 @@
/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
* Elements values convention: 0xY000XXXX
- * - XXXX : Interrupt mask (16 bits) in the Y register
- * - Y : Interrupt source register (4 bits)
- * - 0001: CR1 register
- * - 0010: CR2 register
- * - 0011: CR3 register
- *
+ * - XXXX : Interrupt mask in the XX register
+ * - Y : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
* @{
*/
+#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
-#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
-#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
-#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
-#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
+#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
-#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
-
-#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
-#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_EIE))
-
+#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
+#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
/**
* @}
*/
@@ -252,19 +292,20 @@
* @}
*/
-
/* Exported macro ------------------------------------------------------------*/
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
* @{
*/
-/** @brief Reset IRDA handle state
+/** @brief Reset IRDA handle gstate & RxState
* @param __HANDLE__: specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
- * @retval None
*/
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
+ } while(0U)
/** @brief Flush the IRDA DR register
* @param __HANDLE__: specifies the USART Handle.
@@ -309,7 +350,6 @@
* USART_SR register followed by a write operation to USART_DR register.
* @note TXE flag is cleared only by a write to the USART_DR register.
*
- * @retval None
*/
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
@@ -317,21 +357,19 @@
* @param __HANDLE__: specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
- * @retval None
*/
-#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \
-do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- UNUSED(tmpreg); \
- }while(0) \
-
+#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \
+do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+ } while(0U)
+
/** @brief Clear the IRDA FE pending flag.
* @param __HANDLE__: specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
- * @retval None
*/
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
@@ -339,7 +377,6 @@
* @param __HANDLE__: specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
- * @retval None
*/
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
@@ -347,7 +384,6 @@
* @param __HANDLE__: specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
- * @retval None
*/
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
@@ -355,7 +391,6 @@
* @param __HANDLE__: specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
- * @retval None
*/
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
@@ -371,12 +406,10 @@
* @arg IRDA_IT_IDLE: Idle line detection interrupt
* @arg IRDA_IT_PE: Parity Error interrupt
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @retval None
*/
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
-
/** @brief Disable the specified IRDA interrupt.
* @param __HANDLE__: specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
@@ -389,10 +422,9 @@
* @arg IRDA_IT_IDLE: Idle line detection interrupt
* @arg IRDA_IT_PE: Parity Error interrupt
* @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @retval None
*/
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
/** @brief Check whether the specified IRDA interrupt has occurred or not.
@@ -409,22 +441,20 @@
* @arg IRDA_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:((((__IT__) >> 28) == IRDA_CR2_REG_INDEX)? \
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == IRDA_CR2_REG_INDEX)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
/** @brief Enable UART/USART associated to IRDA Handle
* @param __HANDLE__: specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
- * @retval None
- */
+ */
#define __HAL_IRDA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
/** @brief Disable UART/USART associated to IRDA Handle
* @param __HANDLE__: specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
- * @retval None
*/
#define __HAL_IRDA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
@@ -432,80 +462,27 @@
* @}
*/
-/* Private macros --------------------------------------------------------*/
-/** @defgroup IRDA_Private_Macros IRDA Private Macros
- * @{
- */
-
-#define IRDA_CR1_REG_INDEX 1
-#define IRDA_CR2_REG_INDEX 2
-#define IRDA_CR3_REG_INDEX 3
-
-#define IRDA_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__)))
-#define IRDA_DIVMANT(__PCLK__, __BAUD__) (IRDA_DIV((__PCLK__), (__BAUD__))/100)
-#define IRDA_DIVFRAQ(__PCLK__, __BAUD__) (((IRDA_DIV((__PCLK__), (__BAUD__)) - (IRDA_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100)
-/* UART BRR = mantissa + overflow + fraction
- = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */
-#define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4) + \
- (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0)) + \
- (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
-
-/** Ensure that IRDA Baud rate is less or equal to maximum value
- * __BAUDRATE__: specifies the IRDA Baudrate set by the user.
- * The maximum Baud Rate is 115200bps
- * Returns : True or False
- */
-#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
-
-#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
- ((LENGTH) == IRDA_WORDLENGTH_9B))
-
-#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
- ((PARITY) == IRDA_PARITY_EVEN) || \
- ((PARITY) == IRDA_PARITY_ODD))
-
-#define IS_IRDA_MODE(MODE) ((((MODE) & (~((uint32_t)IRDA_MODE_TX_RX))) == 0x00) && \
- ((MODE) != (uint32_t)0x00000000))
-
-#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
- ((MODE) == IRDA_POWERMODE_NORMAL))
-
-/** IRDA interruptions flag mask
- *
- */
-#define IRDA_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
- USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
-
-/**
- * @}
- */
-
-
/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
+/** @addtogroup IRDA_Exported_Functions
* @{
*/
-/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup IRDA_Exported_Functions_Group1
* @{
*/
-
-/* Initialization and de-initialization functions ****************************/
+/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
-
/**
* @}
*/
-/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
+/** @addtogroup IRDA_Exported_Functions_Group2
* @{
*/
-
-/* IO operation functions *****************************************************/
+/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
@@ -515,29 +492,92 @@
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
+
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
+void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
+
+/** @addtogroup IRDA_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
+uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+/**
+ * @}
+ */
/**
* @}
*/
-/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IRDA_Private_Constants IRDA Private Constants
* @{
*/
-/* Peripheral State and Error functions ***************************************/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+/** @brief IRDA interruptions flag mask
+ *
+ */
+#define IRDA_IT_MASK 0x0000FFFFU
+
+#define IRDA_CR1_REG_INDEX 1U
+#define IRDA_CR2_REG_INDEX 2U
+#define IRDA_CR3_REG_INDEX 3U
+/**
+ * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup IRDA_Private_Macros IRDA Private Macros
+ * @{
+ */
+#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
+ ((LENGTH) == IRDA_WORDLENGTH_9B))
+#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
+ ((PARITY) == IRDA_PARITY_EVEN) || \
+ ((PARITY) == IRDA_PARITY_ODD))
+#define IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
+#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
+ ((MODE) == IRDA_POWERMODE_NORMAL))
+#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
+
+#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
+#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
+#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+/* UART BRR = mantissa + overflow + fraction
+ = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
+#define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
+ (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
+ (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
/**
* @}
*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup IRDA_Private_Functions IRDA Private Functions
+ * @{
+ */
+
/**
* @}
*/
@@ -549,7 +589,7 @@
/**
* @}
*/
-
+
#ifdef __cplusplus
}
#endif
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_iwdg.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_iwdg.h
index 26816a9..a6b1958 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_iwdg.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_iwdg.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_iwdg.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_IWDG_H
@@ -52,53 +52,35 @@
/** @addtogroup IWDG
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
-
/** @defgroup IWDG_Exported_Types IWDG Exported Types
* @{
*/
/**
- * @brief IWDG HAL State Structure definition
- */
-typedef enum
-{
- HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
- HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
- HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
- HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
- HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
-
-}HAL_IWDG_StateTypeDef;
-
-/**
- * @brief IWDG Init structure definition
- */
+ * @brief IWDG Init structure definition
+ */
typedef struct
{
- uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
+ uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
This parameter can be a value of @ref IWDG_Prescaler */
-
- uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
+
+ uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-}IWDG_InitTypeDef;
+} IWDG_InitTypeDef;
-/**
- * @brief IWDG Handle Structure definition
- */
+/**
+ * @brief IWDG Handle Structure definition
+ */
typedef struct
{
- IWDG_TypeDef *Instance; /*!< Register base address */
-
+ IWDG_TypeDef *Instance; /*!< Register base address */
+
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
-
- HAL_LockTypeDef Lock; /*!< IWDG Locking object */
-
- __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
-
+
}IWDG_HandleTypeDef;
/**
@@ -106,190 +88,149 @@
*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
* @{
*/
-/** @defgroup IWDG_Registers_BitMask IWDG Registers BitMask
- * @brief IWDG registers bit mask
- * @{
- */
-/* --- KR Register ---*/
-/* KR register bit mask */
-#define IWDG_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */
-#define IWDG_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */
-#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */
-#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Flag_definition IWDG Flag definition
- * @{
- */
-#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update Flag */
-#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update Flag */
-
-/**
- * @}
- */
-
/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
- */
-#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
-#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
-#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
-#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
-#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
-#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
-
+ */
+#define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */
+#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
+#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
+#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
+#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
+#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
+#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
/**
* @}
- */
-
+ */
/**
* @}
*/
-/* Exported macros -----------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
* @{
*/
-/** @brief Reset IWDG handle state
- * @param __HANDLE__: IWDG handle.
+/**
+ * @brief Enable the IWDG peripheral.
+ * @param __HANDLE__ IWDG handle
* @retval None
*/
-#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
+#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
/**
- * @brief Enables the IWDG peripheral.
- * @param __HANDLE__: IWDG handle
+ * @brief Reload IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR & IWDG_RLR registers disabled).
+ * @param __HANDLE__ IWDG handle
* @retval None
*/
-#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
-
-/**
- * @brief Reloads IWDG counter with value defined in the reload register
- * (write access to IWDG_PR and IWDG_RLR registers disabled).
- * @param __HANDLE__: IWDG handle
- * @retval None
- */
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
-
-
-
-/**
- * @brief Gets the selected IWDG's flag status.
- * @param __HANDLE__: IWDG handle
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
- * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
/**
* @}
- */
+ */
-/* Private macro -------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
+ * @{
+ */
+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
+ * @{
+ */
+/* Initialization/Start functions ********************************************/
+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
+ * @{
+ */
+/* I/O operation functions ****************************************************/
+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_Private_Constants IWDG Private Constants
+ * @{
+ */
+
+/**
+ * @brief IWDG Key Register BitMask
+ */
+#define IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
+#define IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
+#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
+#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Macros IWDG Private Macros
* @{
*/
-
/**
- * @brief Enables write access to IWDG_PR and IWDG_RLR registers.
- * @param __HANDLE__: IWDG handle
+ * @brief Enable write access to IWDG_PR and IWDG_RLR registers.
+ * @param __HANDLE__ IWDG handle
* @retval None
*/
-#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
/**
- * @brief Disables write access to IWDG_PR and IWDG_RLR registers.
- * @param __HANDLE__: IWDG handle
+ * @brief Disable write access to IWDG_PR and IWDG_RLR registers.
+ * @param __HANDLE__ IWDG handle
* @retval None
*/
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
+/**
+ * @brief Check IWDG prescaler value.
+ * @param __PRESCALER__ IWDG prescaler value
+ * @retval None
+ */
+#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_8) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_16) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_32) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_64) || \
+ ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
+ ((__PRESCALER__) == IWDG_PRESCALER_256))
-#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
- ((__PRESCALER__) == IWDG_PRESCALER_8) || \
- ((__PRESCALER__) == IWDG_PRESCALER_16) || \
- ((__PRESCALER__) == IWDG_PRESCALER_32) || \
- ((__PRESCALER__) == IWDG_PRESCALER_64) || \
- ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
- ((__PRESCALER__) == IWDG_PRESCALER_256))
+/**
+ * @brief Check IWDG reload value.
+ * @param __RELOAD__ IWDG reload value
+ * @retval None
+ */
+#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
+/**
+ * @}
+ */
-#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
-
+/**
+ * @}
+ */
/**
* @}
*/
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup IWDG_Exported_Functions
- * @{
- */
-
-/** @addtogroup IWDG_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
-void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
-
-/**
- * @}
- */
-
-/** @addtogroup IWDG_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
-
-/**
- * @}
- */
-
-/** @addtogroup IWDG_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions ************************************************/
-HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
#ifdef __cplusplus
}
#endif
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_mmc.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_mmc.h
new file mode 100644
index 0000000..7fa628e
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_mmc.h
@@ -0,0 +1,718 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_mmc.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of MMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_HAL_MMC_H
+#define __STM32F1xx_HAL_MMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_sdmmc.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup MMC MMC
+ * @brief MMC HAL module driver
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup MMC_Exported_Types MMC Exported Types
+ * @{
+ */
+
+/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
+ * @{
+ */
+typedef enum
+{
+ HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */
+ HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */
+ HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */
+ HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */
+ HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */
+ HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */
+ HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfert State */
+ HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */
+}HAL_MMC_StateTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
+ * @{
+ */
+typedef enum
+{
+ HAL_MMC_CARD_READY = 0x00000001U, /*!< Card state is ready */
+ HAL_MMC_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
+ HAL_MMC_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
+ HAL_MMC_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
+ HAL_MMC_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
+ HAL_MMC_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
+ HAL_MMC_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
+ HAL_MMC_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
+ HAL_MMC_CARD_ERROR = 0x000000FFU /*!< Card response Error */
+}HAL_MMC_CardStateTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
+ * @{
+ */
+#define MMC_InitTypeDef SDIO_InitTypeDef
+#define MMC_TypeDef SDIO_TypeDef
+
+/**
+ * @brief MMC Card Information Structure definition
+ */
+typedef struct
+{
+ uint32_t CardType; /*!< Specifies the card Type */
+
+ uint32_t Class; /*!< Specifies the class of the card class */
+
+ uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
+
+ uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
+
+ uint32_t BlockSize; /*!< Specifies one block size in bytes */
+
+ uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
+
+ uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
+
+}HAL_MMC_CardInfoTypeDef;
+
+/**
+ * @brief MMC handle Structure definition
+ */
+typedef struct
+{
+ MMC_TypeDef *Instance; /*!< MMC registers base address */
+
+ MMC_InitTypeDef Init; /*!< MMC required parameters */
+
+ HAL_LockTypeDef Lock; /*!< MMC locking object */
+
+ uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
+
+ uint32_t TxXferSize; /*!< MMC Tx Transfer size */
+
+ uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
+
+ uint32_t RxXferSize; /*!< MMC Rx Transfer size */
+
+ __IO uint32_t Context; /*!< MMC transfer context */
+
+ __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
+
+ __IO uint32_t ErrorCode; /*!< MMC Card Error codes */
+
+ DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
+
+ HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
+
+ uint32_t CSD[4U]; /*!< MMC card specific data table */
+
+ uint32_t CID[4U]; /*!< MMC card identification number table */
+
+}MMC_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t CSDStruct; /*!< CSD structure */
+ __IO uint8_t SysSpecVersion; /*!< System specification version */
+ __IO uint8_t Reserved1; /*!< Reserved */
+ __IO uint8_t TAAC; /*!< Data read access time 1 */
+ __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
+ __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
+ __IO uint16_t CardComdClasses; /*!< Card command classes */
+ __IO uint8_t RdBlockLen; /*!< Max. read data block length */
+ __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
+ __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
+ __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
+ __IO uint8_t DSRImpl; /*!< DSR implemented */
+ __IO uint8_t Reserved2; /*!< Reserved */
+ __IO uint32_t DeviceSize; /*!< Device Size */
+ __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
+ __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
+ __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
+ __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
+ __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
+ __IO uint8_t EraseGrSize; /*!< Erase group size */
+ __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
+ __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
+ __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
+ __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
+ __IO uint8_t WrSpeedFact; /*!< Write speed factor */
+ __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
+ __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
+ __IO uint8_t Reserved3; /*!< Reserved */
+ __IO uint8_t ContentProtectAppli; /*!< Content protection application */
+ __IO uint8_t FileFormatGrouop; /*!< File format group */
+ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
+ __IO uint8_t PermWrProtect; /*!< Permanent write protection */
+ __IO uint8_t TempWrProtect; /*!< Temporary write protection */
+ __IO uint8_t FileFormat; /*!< File format */
+ __IO uint8_t ECC; /*!< ECC code */
+ __IO uint8_t CSD_CRC; /*!< CSD CRC */
+ __IO uint8_t Reserved4; /*!< Always 1 */
+
+}HAL_MMC_CardCSDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
+ __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
+ __IO uint32_t ProdName1; /*!< Product Name part1 */
+ __IO uint8_t ProdName2; /*!< Product Name part2 */
+ __IO uint8_t ProdRev; /*!< Product Revision */
+ __IO uint32_t ProdSN; /*!< Product Serial Number */
+ __IO uint8_t Reserved1; /*!< Reserved1 */
+ __IO uint16_t ManufactDate; /*!< Manufacturing Date */
+ __IO uint8_t CID_CRC; /*!< CID CRC */
+ __IO uint8_t Reserved2; /*!< Always 1 */
+
+}HAL_MMC_CardCIDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group6 MMC Card Status returned by ACMD13
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
+ __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
+ __IO uint16_t CardType; /*!< Carries information about card type */
+ __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
+ __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
+ __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
+ __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
+ __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
+ __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
+ __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
+
+}HAL_MMC_CardStatusTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup MMC_Exported_Constants Exported Constants
+ * @{
+ */
+
+#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
+
+#define CAPACITY 0x400000U /*!< Log Block Nuumber for 2 G bytes Cards */
+
+/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
+ * @{
+ */
+#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
+#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
+#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
+#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
+#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
+#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
+#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
+#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
+#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
+ number of transferred bytes does not match the block length */
+#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
+#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
+#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
+#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
+ command or if there was an attempt to access a locked card */
+#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
+#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
+#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
+#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
+#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
+#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
+#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
+#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
+#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
+#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
+#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
+ of erase sequence command was received */
+#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
+#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
+#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
+#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
+#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
+#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
+#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
+#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
+#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration structure
+ * @{
+ */
+#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
+#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
+#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
+#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
+#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
+#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
+#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
+ * @{
+ */
+/**
+ * @brief
+ */
+#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */
+#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */
+#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
+#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
+#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
+ * @{
+ */
+#define MMC_HIGH_VOLTAGE_CARD 0x00000000U
+#define MMC_DUAL_VOLTAGE_CARD 0x00000001U
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup MMC_Exported_macros MMC Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/**
+ * @brief Enable the MMC device.
+ * @retval None
+ */
+#define __HAL_MMC_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Disable the MMC device.
+ * @retval None
+ */
+#define __HAL_MMC_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Enable the SDMMC DMA transfer.
+ * @retval None
+ */
+#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Disable the SDMMC DMA transfer.
+ * @retval None
+ */
+#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Enable the MMC device interrupt.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval None
+ */
+#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Disable the MMC device interrupt.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval None
+ */
+#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified MMC flag is set or not.
+ * @param __HANDLE__: MMC Handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress
+ * @arg SDIO_FLAG_RXACT: Data receive in progress
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @retval The new state of MMC FLAG (SET or RESET).
+ */
+#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Clear the MMC's pending flags.
+ * @param __HANDLE__: MMC Handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
+ * @retval None
+ */
+#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Check whether the specified MMC interrupt has occurred or not.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval The new state of MMC IT (SET or RESET).
+ */
+#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Clear the MMC's interrupt pending bits.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval None
+ */
+#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MMC_Exported_Functions MMC Exported Functions
+ * @{
+ */
+
+/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
+void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+/* Non-Blocking mode: IT */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+
+void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
+
+/* Callback in non blocking modes (DMA) */
+void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
+ * @{
+ */
+HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
+ * @{
+ */
+HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
+uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup MMC_Private_Types MMC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup MMC_Private_Defines MMC Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Variables MMC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Constants MMC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup MMC_Private_Macros MMC Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Functions MMC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F103xE || STM32F103xG */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F1xx_HAL_MMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_nand.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_nand.h
index 0ba688e..fdabaae 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_nand.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_nand.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f1xx_hal_nand.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -55,69 +55,6 @@
* @{
*/
-/** @addtogroup NAND_Private_Constants
- * @{
- */
-
-#define NAND_DEVICE1 FSMC_BANK2
-#define NAND_DEVICE2 FSMC_BANK3
-#define NAND_WRITE_TIMEOUT ((uint32_t)1000)
-
-#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
-#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
-
-#define NAND_CMD_AREA_A ((uint8_t)0x00)
-#define NAND_CMD_AREA_B ((uint8_t)0x01)
-#define NAND_CMD_AREA_C ((uint8_t)0x50)
-#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
-
-#define NAND_CMD_WRITE0 ((uint8_t)0x80)
-#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
-#define NAND_CMD_ERASE0 ((uint8_t)0x60)
-#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
-#define NAND_CMD_READID ((uint8_t)0x90)
-#define NAND_CMD_STATUS ((uint8_t)0x70)
-#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
-#define NAND_CMD_RESET ((uint8_t)0xFF)
-
-/* NAND memory status */
-#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
-#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
-#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
-#define NAND_BUSY ((uint32_t)0x00000000)
-#define NAND_ERROR ((uint32_t)0x00000001)
-#define NAND_READY ((uint32_t)0x00000040)
-
-/**
- * @}
- */
-
-/** @addtogroup NAND_Private_Macros
- * @{
- */
-
-/**
- * @brief NAND memory address computation.
- * @param __ADDRESS__: NAND memory address.
- * @param __HANDLE__ : NAND handle.
- * @retval NAND Raw address value
- */
-#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
- (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
-
-/**
- * @brief NAND memory address cycling.
- * @param __ADDRESS__: NAND memory address.
- * @retval NAND address cycling value.
- */
-#define ADDR_1st_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
-#define ADDR_2nd_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
-#define ADDR_3rd_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
-#define ADDR_4th_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
-
-/**
- * @}
- */
/* Exported typedef ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
@@ -130,10 +67,10 @@
*/
typedef enum
{
- HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
- HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
- HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
- HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
+ HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
+ HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
+ HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
+ HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
}HAL_NAND_StateTypeDef;
/**
@@ -157,11 +94,11 @@
*/
typedef struct
{
- uint16_t Page; /*!< NAND memory Page address */
+ uint16_t Page; /*!< NAND memory Page address */
- uint16_t Zone; /*!< NAND memory Zone address */
+ uint16_t Plane; /*!< NAND memory Plane address */
- uint16_t Block; /*!< NAND memory Block address */
+ uint16_t Block; /*!< NAND memory Block address */
}NAND_AddressTypeDef;
@@ -170,31 +107,43 @@
*/
typedef struct
{
- uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
+ uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
+ for 8 bits adressing or words for 16 bits addressing */
- uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
+ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
+ for 8 bits adressing or words for 16 bits addressing */
+
+ uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
- uint32_t BlockSize; /*!< NAND memory block size number of pages */
+ uint32_t BlockNbr; /*!< NAND memory number of total blocks */
+
+ uint32_t PlaneNbr; /*!< NAND memory number of planes */
- uint32_t BlockNbr; /*!< NAND memory number of blocks */
+ uint32_t PlaneSize; /*!< NAND memory plane size measured in number of blocks */
- uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
-}NAND_InfoTypeDef;
+ FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
+ parameter is mandatory for some NAND parts after the read
+ command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
+ Example: Toshiba THTH58BYG3S0HBAI6.
+ This parameter could be ENABLE or DISABLE
+ Please check the Read Mode sequnece in the NAND device datasheet */
+}NAND_DeviceConfigTypeDef;
/**
* @brief NAND handle Structure definition
*/
typedef struct
{
- FSMC_NAND_TypeDef *Instance; /*!< Register base address */
+ FSMC_NAND_TypeDef *Instance; /*!< Register base address */
- FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
+ FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
- HAL_LockTypeDef Lock; /*!< NAND locking object */
+ HAL_LockTypeDef Lock; /*!< NAND locking object */
- __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
+ __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
- NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
+ NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
+
}NAND_HandleTypeDef;
/**
@@ -202,10 +151,10 @@
*/
/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup NAND_Exported_Macros NAND Exported Macros
- * @{
- */
+ * @{
+ */
/** @brief Reset NAND handle state
* @param __HANDLE__: specifies the NAND handle.
@@ -229,10 +178,15 @@
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
-void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+
+HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
+
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+
+void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
+void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
/**
* @}
@@ -243,15 +197,22 @@
*/
/* IO operation functions ****************************************************/
-HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
-HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
+
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
/**
* @}
@@ -262,9 +223,9 @@
*/
/* NAND Control functions ****************************************************/
-HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
/**
* @}
@@ -285,6 +246,88 @@
/**
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup NAND_Private_Constants
+ * @{
+ */
+
+#define NAND_DEVICE1 FSMC_BANK2
+#define NAND_DEVICE2 FSMC_BANK3
+#define NAND_WRITE_TIMEOUT 1000U
+
+#define CMD_AREA (1U<<16U) /* A16 = CLE high */
+#define ADDR_AREA (1U<<17U) /* A17 = ALE high */
+
+#define NAND_CMD_AREA_A ((uint8_t)0x00)
+#define NAND_CMD_AREA_B ((uint8_t)0x01)
+#define NAND_CMD_AREA_C ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
+
+#define NAND_CMD_WRITE0 ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
+#define NAND_CMD_ERASE0 ((uint8_t)0x60)
+#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
+#define NAND_CMD_READID ((uint8_t)0x90)
+#define NAND_CMD_STATUS ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
+#define NAND_CMD_RESET ((uint8_t)0xFF)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS 0x00000100U
+#define NAND_INVALID_ADDRESS 0x00000200U
+#define NAND_TIMEOUT_ERROR 0x00000400U
+#define NAND_BUSY 0x00000000U
+#define NAND_ERROR 0x00000001U
+#define NAND_READY 0x00000040U
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup NAND_Private_Macros
+ * @{
+ */
+
+/**
+ * @brief NAND memory address computation.
+ * @param __ADDRESS__: NAND memory address.
+ * @param __HANDLE__ : NAND handle.
+ * @retval NAND Raw address value
+ */
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
+ (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+
+/**
+ * @brief NAND memory Column address computation.
+ * @param __HANDLE__: NAND handle.
+ * @retval NAND Raw address value
+ */
+#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
+
+/**
+ * @brief NAND memory address cycling.
+ * @param __ADDRESS__: NAND memory address.
+ * @retval NAND address cycling value.
+ */
+#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
+#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8U) /* 2nd addressing cycle */
+#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16U) /* 3rd addressing cycle */
+#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24U) /* 4th addressing cycle */
+
+/**
+ * @brief NAND memory Columns cycling.
+ * @param __ADDRESS__: NAND memory address.
+ * @retval NAND Column address cycling value.
+ */
+#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
+#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8U) /* 2nd Column addressing cycle */
+
+/**
+ * @}
+ */
/**
* @}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_nor.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_nor.h
index 243015a..7a33c6f 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_nor.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_nor.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_nor.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
@@ -101,7 +101,7 @@
*/
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
- ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
+ ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
/**
@@ -126,11 +126,11 @@
*/
typedef enum
{
- HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
- HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
- HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
- HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
- HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
+ HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
+ HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
+ HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
+ HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
+ HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
}HAL_NOR_StateTypeDef;
/**
@@ -138,7 +138,7 @@
*/
typedef enum
{
- HAL_NOR_STATUS_SUCCESS = 0,
+ HAL_NOR_STATUS_SUCCESS = 0U,
HAL_NOR_STATUS_ONGOING,
HAL_NOR_STATUS_ERROR,
HAL_NOR_STATUS_TIMEOUT
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pccard.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pccard.h
index 2c6cac0..a31b172 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pccard.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pccard.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_pccard.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of PCCARD HAL module.
******************************************************************************
* @attention
@@ -60,10 +60,10 @@
*/
#define PCCARD_DEVICE_ADDRESS FSMC_BANK4
-#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(FSMC_BANK4 + 0x08000000)) /* Attribute space size to @0x9BFF FFFF */
+#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(FSMC_BANK4 + 0x08000000U)) /* Attribute space size to @0x9BFF FFFF */
#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
-#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(FSMC_BANK4 + 0x0C000000)) /* IO space size to @0x9FFF FFFF */
-#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(FSMC_BANK4 + 0x0C0001F0)) /* IO space size to @0x9FFF FFFF */
+#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(FSMC_BANK4 + 0x0C000000U)) /* IO space size to @0x9FFF FFFF */
+#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(FSMC_BANK4 + 0x0C0001F0U)) /* IO space size to @0x9FFF FFFF */
/* Compact Flash-ATA registers description */
#define ATA_DATA ((uint8_t)0x00) /* Data register */
@@ -89,7 +89,7 @@
#define PCCARD_PROGR ((uint8_t)0x01)
#define PCCARD_READY ((uint8_t)0x40)
-#define PCCARD_SECTOR_SIZE ((uint32_t)255) /* In half words */
+#define PCCARD_SECTOR_SIZE 255U /* In half words */
/* Compact Flash redefinition */
@@ -98,18 +98,17 @@
#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
#define HAL_CF_Reset HAL_PCCARD_Reset
-
+
#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
-
+
#define CF_SUCCESS HAL_PCCARD_STATUS_SUCCESS
#define CF_ONGOING HAL_PCCARD_STATUS_ONGOING
#define CF_ERROR HAL_PCCARD_STATUS_ERROR
#define CF_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
#define CF_StatusTypedef HAL_PCCARD_StatusTypeDef
-
-#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
+#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
@@ -136,15 +135,15 @@
*/
typedef enum
{
- HAL_PCCARD_STATE_RESET = 0x00, /*!< PCCARD peripheral not yet initialized or disabled */
- HAL_PCCARD_STATE_READY = 0x01, /*!< PCCARD peripheral ready */
- HAL_PCCARD_STATE_BUSY = 0x02, /*!< PCCARD peripheral busy */
- HAL_PCCARD_STATE_ERROR = 0x04 /*!< PCCARD peripheral error */
+ HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */
+ HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */
+ HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */
+ HAL_PCCARD_STATE_ERROR = 0x04U /*!< PCCARD peripheral error */
}HAL_PCCARD_StateTypeDef;
typedef enum
{
- HAL_PCCARD_STATUS_SUCCESS = 0,
+ HAL_PCCARD_STATUS_SUCCESS = 0U,
HAL_PCCARD_STATUS_ONGOING,
HAL_PCCARD_STATUS_ERROR,
HAL_PCCARD_STATUS_TIMEOUT
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pcd.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pcd.h
index 7d0dd4a..3993ce5 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pcd.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pcd.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_pcd.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
@@ -69,11 +69,11 @@
*/
typedef enum
{
- HAL_PCD_STATE_RESET = 0x00,
- HAL_PCD_STATE_READY = 0x01,
- HAL_PCD_STATE_ERROR = 0x02,
- HAL_PCD_STATE_BUSY = 0x03,
- HAL_PCD_STATE_TIMEOUT = 0x04
+ HAL_PCD_STATE_RESET = 0x00U,
+ HAL_PCD_STATE_READY = 0x01U,
+ HAL_PCD_STATE_ERROR = 0x02U,
+ HAL_PCD_STATE_BUSY = 0x03U,
+ HAL_PCD_STATE_TIMEOUT = 0x04U
} PCD_StateTypeDef;
#if defined (USB)
@@ -118,11 +118,11 @@
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address: not used by USB OTG FS */
- PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
+ PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
- uint32_t Setup[12]; /*!< Setup packet buffer */
+ uint32_t Setup[12U]; /*!< Setup packet buffer */
void *pData; /*!< Pointer to upper stack Handler */
} PCD_HandleTypeDef;
@@ -141,9 +141,9 @@
/** @defgroup PCD_Speed PCD Speed
* @{
*/
-#define PCD_SPEED_HIGH 0 /* Not Supported */
-#define PCD_SPEED_HIGH_IN_FULL 1 /* Not Supported */
-#define PCD_SPEED_FULL 2
+#define PCD_SPEED_HIGH 0U /* Not Supported */
+#define PCD_SPEED_HIGH_IN_FULL 1U /* Not Supported */
+#define PCD_SPEED_FULL 2U
/**
* @}
*/
@@ -151,7 +151,7 @@
/** @defgroup PCD_PHY_Module PCD PHY Module
* @{
*/
-#define PCD_PHY_EMBEDDED 2
+#define PCD_PHY_EMBEDDED 2U
/**
* @}
*/
@@ -160,7 +160,7 @@
* @{
*/
#ifndef USBD_FS_TRDT_VALUE
- #define USBD_FS_TRDT_VALUE 5
+ #define USBD_FS_TRDT_VALUE 5U
#endif /* USBD_FS_TRDT_VALUE */
/**
* @}
@@ -182,14 +182,14 @@
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
-#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
~(USB_OTG_PCGCCTL_STOPCLK)
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
@@ -200,13 +200,13 @@
do{ \
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
- } while(0)
+ } while(0U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() \
do{ \
EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE); \
EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
- } while(0)
+ } while(0U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() \
do{ \
@@ -214,7 +214,7 @@
EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
- } while(0)
+ } while(0U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
#endif /* USB_OTG_FS */
@@ -234,13 +234,13 @@
do{ \
EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \
- } while(0)
+ } while(0U)
#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() \
do{ \
EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE); \
EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \
- } while(0)
+ } while(0U)
#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() \
do{ \
@@ -248,7 +248,7 @@
EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \
EXTI->FTSR |= USB_WAKEUP_EXTI_LINE; \
- } while(0)
+ } while(0U)
#endif /* USB */
/**
@@ -338,15 +338,15 @@
* @{
*/
#if defined (USB_OTG_FS)
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
-#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB EXTI Line */
+#define USB_OTG_FS_WAKEUP_EXTI_LINE 0x00040000U /*!< External interrupt line 18 Connected to the USB EXTI Line */
#endif /* USB_OTG_FS */
#if defined (USB)
-#define USB_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB EXTI Line */
+#define USB_WAKEUP_EXTI_LINE 0x00040000U /*!< External interrupt line 18 Connected to the USB EXTI Line */
#endif /* USB */
/**
* @}
@@ -382,8 +382,8 @@
/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
* @{
*/
-#define PCD_SNG_BUF 0
-#define PCD_DBL_BUF 1
+#define PCD_SNG_BUF 0U
+#define PCD_DBL_BUF 1U
/**
* @}
*/
@@ -398,10 +398,10 @@
*/
#if defined (USB)
/* SetENDPOINT */
-#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue))
+#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2U)= (uint16_t)(wRegValue))
/* GetENDPOINT */
-#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2))
+#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2U))
/* ENDPOINT transfer */
#define USB_EP0StartXfer USB_EPStartXfer
@@ -414,7 +414,7 @@
* @retval None
*/
#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
- ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
+ ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
/**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
@@ -472,12 +472,12 @@
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
/* toggle first bit ? */ \
- if((USB_EPTX_DTOG1 & (wState))!= 0)\
+ if((USB_EPTX_DTOG1 & (wState))!= 0U)\
{ \
_wRegVal ^= USB_EPTX_DTOG1; \
} \
/* toggle second bit ? */ \
- if((USB_EPTX_DTOG2 & (wState))!= 0) \
+ if((USB_EPTX_DTOG2 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG2; \
} \
@@ -496,12 +496,12 @@
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
/* toggle first bit ? */ \
- if((USB_EPRX_DTOG1 & (wState))!= 0) \
+ if((USB_EPRX_DTOG1 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
- if((USB_EPRX_DTOG2 & (wState))!= 0) \
+ if((USB_EPRX_DTOG2 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG2; \
} \
@@ -521,22 +521,22 @@
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
/* toggle first bit ? */ \
- if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \
+ if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
- if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \
+ if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG2; \
} \
/* toggle first bit ? */ \
- if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \
+ if((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG1; \
} \
/* toggle second bit ? */ \
- if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \
+ if((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG2; \
} \
@@ -609,9 +609,9 @@
* @retval None
*/
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
- PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK))
+ PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
- PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK))
+ PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
/**
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
@@ -630,11 +630,11 @@
* @param bEpNum: Endpoint Number.
* @retval None
*/
-#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0U)\
{ \
PCD_RX_DTOG((USBx), (bEpNum)); \
}
-#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0U)\
{ \
PCD_TX_DTOG((USBx), (bEpNum)); \
}
@@ -651,10 +651,10 @@
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
-#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400)))
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400)))
-#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400)))
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400)))
+#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U)*2U+ ((uint32_t)(USBx) + 0x400U)))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+2U)*2U+ ((uint32_t)(USBx) + 0x400U)))
+#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+4U)*2U+ ((uint32_t)(USBx) + 0x400U)))
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+6U)*2U+ ((uint32_t)(USBx) + 0x400U)))
#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \
@@ -668,8 +668,8 @@
* @param wAddr: address to be set (must be word aligned).
* @retval None
*/
-#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
-#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
+#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
+#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
/**
* @brief Gets address of the tx/rx buffer.
@@ -688,26 +688,26 @@
* @retval None
*/
#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
- (wNBlocks) = (wCount) >> 5;\
- if(((wCount) & 0x1f) == 0)\
+ (wNBlocks) = (wCount) >> 5U;\
+ if(((wCount) & 0x1FU) == 0U)\
{ \
(wNBlocks)--;\
} \
- *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \
+ *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | 0x8000U); \
}/* PCD_CALC_BLK32 */
#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
- (wNBlocks) = (wCount) >> 1;\
- if(((wCount) & 0x1) != 0)\
+ (wNBlocks) = (wCount) >> 1U;\
+ if(((wCount) & 0x01U) != 0U)\
{ \
(wNBlocks)++;\
} \
- *pdwReg = (uint16_t)((wNBlocks) << 10);\
+ *pdwReg = (uint16_t)((wNBlocks) << 10U);\
}/* PCD_CALC_BLK2 */
#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
uint16_t wNBlocks;\
- if((wCount) > 62) \
+ if((wCount) > 62U) \
{ \
PCD_CALC_BLK32((dwReg),(wCount),wNBlocks); \
} \
@@ -738,8 +738,8 @@
* @param bEpNum: Endpoint Number.
* @retval Counter value
*/
-#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff)
-#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff)
+#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3FFU)
+#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3FFU)
/**
* @brief Sets buffer 0/1 address in a double buffer endpoint.
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pcd_ex.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pcd_ex.h
index 59d07c8..1ed14c1 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pcd_ex.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pcd_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_pcd_ex.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of Extended PCD HAL module.
******************************************************************************
* @attention
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pwr.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pwr.h
index 9ca5d78..70d65ae 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pwr.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_pwr.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_pwr.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
@@ -116,13 +116,13 @@
/** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{
*/
-#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
-#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
@@ -142,7 +142,7 @@
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
* @{
*/
-#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
+#define PWR_MAINREGULATOR_ON 0x00000000U
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
/**
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rcc.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rcc.h
index 0032363..e025675 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rcc.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rcc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
@@ -54,176 +54,6 @@
* @{
*/
-/** @addtogroup RCC_Private_Constants
- * @{
- */
-
-/** @defgroup RCC_Timeout RCC Timeout
- * @{
- */
-
-/* Disable Backup domain write protection state change timeout */
-#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-/* LSE state change timeout */
-#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
-#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
-#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
-#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
-#define LSI_VALUE ((uint32_t)40000) /* 40kHz */
-/**
- * @}
- */
-
-/** @defgroup RCC_Register_Offset Register offsets
- * @{
- */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-#define RCC_CR_OFFSET 0x00
-#define RCC_CFGR_OFFSET 0x04
-#define RCC_CIR_OFFSET 0x08
-#define RCC_BDCR_OFFSET 0x20
-#define RCC_CSR_OFFSET 0x24
-
-/**
- * @}
- */
-
-/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
- * @brief RCC registers bit address in the alias region
- * @{
- */
-#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
-#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
-#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
-#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
-#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
-
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
-#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4)))
-/* Alias word address of HSEON bit */
-#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
-#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4)))
-/* Alias word address of CSSON bit */
-#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
-#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4)))
-/* Alias word address of PLLON bit */
-#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
-#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4)))
-
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
-#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4)))
-
-/* Alias word address of RMVF bit */
-#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
-#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4)))
-
-/* --- BDCR Registers ---*/
-/* Alias word address of LSEON bit */
-#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON)
-#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4)))
-
-/* Alias word address of LSEON bit */
-#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP)
-#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4)))
-
-/* Alias word address of RTCEN bit */
-#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN)
-#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4)))
-
-/* Alias word address of BDRST bit */
-#define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST)
-#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_BDRST_BIT_NUMBER * 4)))
-
-/**
- * @}
- */
-
-/* CR register byte 2 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
-
-/* CIR register byte 1 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
-
-/* CIR register byte 2 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
-
-/* Defines used for Flags */
-#define CR_REG_INDEX ((uint8_t)1)
-#define BDCR_REG_INDEX ((uint8_t)2)
-#define CSR_REG_INDEX ((uint8_t)3)
-
-#define RCC_FLAG_MASK ((uint8_t)0x1F)
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_Private_Macros
- * @{
- */
-/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
- * @{
- */
-#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-/**
- * @}
- */
-
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
- ((__SOURCE__) == RCC_PLLSOURCE_HSE))
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
-#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
- ((__HSE__) == RCC_HSE_BYPASS))
-#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
- ((__LSE__) == RCC_LSE_BYPASS))
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
-#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
- ((__PLL__) == RCC_PLL_ON))
-
-#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
- (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
- (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
- (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
-#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
-#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
- ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
- ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
- ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
- ((__HCLK__) == RCC_SYSCLK_DIV512))
-#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
- ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
- ((__PCLK__) == RCC_HCLK_DIV16))
-#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
-#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
-
-/**
- * @}
- */
-
/* Exported types ------------------------------------------------------------*/
/** @defgroup RCC_Exported_Types RCC Exported Types
@@ -279,7 +109,7 @@
* @{
*/
-#define RCC_PLLSOURCE_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */
#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */
/**
@@ -289,11 +119,11 @@
/** @defgroup RCC_Oscillator_Type Oscillator Type
* @{
*/
-#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
-#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
-#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
-#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
-#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
+#define RCC_OSCILLATORTYPE_NONE 0x00000000U
+#define RCC_OSCILLATORTYPE_HSE 0x00000001U
+#define RCC_OSCILLATORTYPE_HSI 0x00000002U
+#define RCC_OSCILLATORTYPE_LSE 0x00000004U
+#define RCC_OSCILLATORTYPE_LSI 0x00000008U
/**
* @}
*/
@@ -301,7 +131,7 @@
/** @defgroup RCC_HSE_Config HSE Config
* @{
*/
-#define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */
+#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
/**
@@ -311,8 +141,8 @@
/** @defgroup RCC_LSE_Config LSE Config
* @{
*/
-#define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */
-#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
+#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
+#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
/**
@@ -322,10 +152,10 @@
/** @defgroup RCC_HSI_Config HSI Config
* @{
*/
-#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
+#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
-#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
+#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
/**
* @}
@@ -334,7 +164,7 @@
/** @defgroup RCC_LSI_Config LSI Config
* @{
*/
-#define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */
+#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
/**
@@ -344,9 +174,9 @@
/** @defgroup RCC_PLL_Config PLL Config
* @{
*/
-#define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */
-#define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */
-#define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */
+#define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */
+#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
+#define RCC_PLL_ON 0x00000002U /*!< PLL activation */
/**
* @}
@@ -355,10 +185,10 @@
/** @defgroup RCC_System_Clock_Type System Clock Type
* @{
*/
-#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */
-#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */
-#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */
-#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */
+#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
+#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
+#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
+#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
/**
* @}
@@ -419,7 +249,7 @@
/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
* @{
*/
-#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */
#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */
@@ -431,7 +261,7 @@
/** @defgroup RCC_MCO_Index MCO Index
* @{
*/
-#define RCC_MCO1 ((uint32_t)0x00000000)
+#define RCC_MCO1 0x00000000U
#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
/**
@@ -441,7 +271,7 @@
/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
* @{
*/
-#define RCC_MCODIV_1 ((uint32_t)0x00000000)
+#define RCC_MCODIV_1 0x00000000U
/**
* @}
@@ -470,21 +300,21 @@
* @{
*/
/* Flags in the CR register */
-#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
-#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
-#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
+#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */
+#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */
+#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */
/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
-#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
-#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
-#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
-#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
-#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
-#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
+#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */
+#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */
+#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */
+#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */
+#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
+#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
+#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
/* Flags in the BDCR register */
-#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */
+#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */
/**
* @}
@@ -513,7 +343,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -521,7 +351,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -529,7 +359,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -537,7 +367,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
@@ -582,7 +412,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -590,7 +420,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -598,7 +428,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_USART2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -606,7 +436,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -614,7 +444,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_BKP_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -622,7 +452,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -630,7 +460,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
@@ -659,14 +489,14 @@
#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
-#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
-#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
-#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
-#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
-#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
-#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
+#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
+#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
+#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
/**
* @}
@@ -685,7 +515,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -693,7 +523,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -701,7 +531,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -709,7 +539,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -717,7 +547,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -725,7 +555,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -733,7 +563,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -741,7 +571,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_USART1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -749,7 +579,7 @@
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
@@ -776,22 +606,22 @@
#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
-#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
-#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
/**
* @}
@@ -882,7 +712,7 @@
* This parameter must be a number between 0 and 0x1F.
*/
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
- (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM)))
+ (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
/**
* @}
@@ -957,7 +787,7 @@
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
} \
- }while(0)
+ }while(0U)
/**
* @}
@@ -1005,7 +835,7 @@
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
- }while(0)
+ }while(0U)
/**
* @}
@@ -1315,9 +1145,9 @@
* @arg @ref RCC_FLAG_LPWRRST Low Power reset.
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
- ((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : \
- RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
+ ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
+ RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
/**
* @}
@@ -1377,6 +1207,176 @@
* @}
*/
+/** @addtogroup RCC_Private_Constants
+ * @{
+ */
+
+/** @defgroup RCC_Timeout RCC Timeout
+ * @{
+ */
+
+/* Disable Backup domain write protection state change timeout */
+#define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */
+/* LSE state change timeout */
+#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
+#define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */
+#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
+#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
+#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_Register_Offset Register offsets
+ * @{
+ */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+#define RCC_CR_OFFSET 0x00U
+#define RCC_CFGR_OFFSET 0x04U
+#define RCC_CIR_OFFSET 0x08U
+#define RCC_BDCR_OFFSET 0x20U
+#define RCC_CSR_OFFSET 0x24U
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
+ * @brief RCC registers bit address in the alias region
+ * @{
+ */
+#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
+#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
+#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
+#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
+#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
+
+/* --- CR Register ---*/
+/* Alias word address of HSION bit */
+#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos
+#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
+/* Alias word address of HSEON bit */
+#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos
+#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
+/* Alias word address of CSSON bit */
+#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos
+#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
+/* Alias word address of PLLON bit */
+#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos
+#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
+
+/* --- CSR Register ---*/
+/* Alias word address of LSION bit */
+#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos
+#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
+
+/* Alias word address of RMVF bit */
+#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos
+#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
+
+/* --- BDCR Registers ---*/
+/* Alias word address of LSEON bit */
+#define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos
+#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
+
+/* Alias word address of LSEON bit */
+#define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos
+#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
+
+/* Alias word address of RTCEN bit */
+#define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos
+#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
+
+/* Alias word address of BDRST bit */
+#define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos
+#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
+
+/**
+ * @}
+ */
+
+/* CR register byte 2 (Bits[23:16]) base address */
+#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
+
+/* CIR register byte 1 (Bits[15:8]) base address */
+#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
+
+/* CIR register byte 2 (Bits[23:16]) base address */
+#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
+
+/* Defines used for Flags */
+#define CR_REG_INDEX ((uint8_t)1)
+#define BDCR_REG_INDEX ((uint8_t)2)
+#define CSR_REG_INDEX ((uint8_t)3)
+
+#define RCC_FLAG_MASK ((uint8_t)0x1F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_Private_Macros
+ * @{
+ */
+/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
+ * @{
+ */
+#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+/**
+ * @}
+ */
+
+#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
+ ((__SOURCE__) == RCC_PLLSOURCE_HSE))
+#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
+ (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
+#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
+ ((__HSE__) == RCC_HSE_BYPASS))
+#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
+ ((__LSE__) == RCC_LSE_BYPASS))
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
+#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
+#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
+#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
+ ((__PLL__) == RCC_PLL_ON))
+
+#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
+ (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
+ (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
+ (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
+#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
+#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
+ ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
+#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
+ ((__HCLK__) == RCC_SYSCLK_DIV512))
+#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
+ ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
+ ((__PCLK__) == RCC_HCLK_DIV16))
+#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
+#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
+ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
+
+/**
+ * @}
+ */
+
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rcc_ex.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rcc_ex.h
index b754cd5..20884a2 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rcc_ex.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rcc_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
@@ -61,14 +61,14 @@
#if defined(STM32F105xC) || defined(STM32F107xC)
/* Alias word address of PLLI2SON bit */
-#define PLLI2SON_BITNUMBER POSITION_VAL(RCC_CR_PLL3ON)
-#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLI2SON_BITNUMBER * 4)))
+#define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos
+#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U)))
/* Alias word address of PLL2ON bit */
-#define PLL2ON_BITNUMBER POSITION_VAL(RCC_CR_PLL2ON)
-#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLL2ON_BITNUMBER * 4)))
+#define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos
+#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U)))
-#define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
-#define PLL2_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
+#define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */
+#define PLL2_TIMEOUT_VALUE 100U /* 100 ms */
#endif /* STM32F105xC || STM32F107xC */
@@ -346,17 +346,17 @@
/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
* @{
*/
-#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001)
-#define RCC_PERIPHCLK_ADC ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_RTC 0x00000001U
+#define RCC_PERIPHCLK_ADC 0x00000002U
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
|| defined(STM32F107xC)
-#define RCC_PERIPHCLK_I2S2 ((uint32_t)0x00000004)
-#define RCC_PERIPHCLK_I2S3 ((uint32_t)0x00000008)
+#define RCC_PERIPHCLK_I2S2 0x00000004U
+#define RCC_PERIPHCLK_I2S3 0x00000008U
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
|| defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_PERIPHCLK_USB ((uint32_t)0x00000010)
+#define RCC_PERIPHCLK_USB 0x00000010U
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
/**
@@ -380,9 +380,9 @@
/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
* @{
*/
-#define RCC_I2S2CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
+#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U
#if defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
+#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
#endif /* STM32F105xC || STM32F107xC */
/**
@@ -392,9 +392,9 @@
/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
* @{
*/
-#define RCC_I2S3CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
+#define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U
#if defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
+#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
#endif /* STM32F105xC || STM32F107xC */
/**
@@ -410,7 +410,7 @@
* @{
*/
#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE
-#define RCC_USBCLKSOURCE_PLL_DIV1_5 ((uint32_t)0x00000000)
+#define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U
/**
* @}
@@ -424,7 +424,7 @@
* @{
*/
#define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE
-#define RCC_USBCLKSOURCE_PLL_DIV3 ((uint32_t)0x00000000)
+#define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U
/**
* @}
@@ -466,7 +466,7 @@
* @{
*/
-#define RCC_HSE_PREDIV_DIV1 ((uint32_t)0x00000000)
+#define RCC_HSE_PREDIV_DIV1 0x00000000U
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
|| defined(STM32F100xE)
@@ -522,9 +522,9 @@
/** @defgroup RCCEx_PLL2_Config PLL Config
* @{
*/
-#define RCC_PLL2_NONE ((uint32_t)0x00000000)
-#define RCC_PLL2_OFF ((uint32_t)0x00000001)
-#define RCC_PLL2_ON ((uint32_t)0x00000002)
+#define RCC_PLL2_NONE 0x00000000U
+#define RCC_PLL2_OFF 0x00000001U
+#define RCC_PLL2_ON 0x00000002U
/**
* @}
@@ -617,8 +617,8 @@
* @{
*/
/* Flags in the CR register */
-#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL2RDY)))
-#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL3RDY)))
+#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos))
+#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos))
/**
* @}
*/
@@ -650,7 +650,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
@@ -663,7 +663,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
@@ -675,7 +675,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
@@ -688,7 +688,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
@@ -701,7 +701,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -709,7 +709,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -717,7 +717,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
@@ -730,7 +730,7 @@
__HAL_RCC_ETHMAC_CLK_ENABLE(); \
__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
- } while(0)
+ } while(0U)
/**
* @brief Disable ETHERNET clock.
*/
@@ -738,7 +738,7 @@
__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
__HAL_RCC_ETHMAC_CLK_DISABLE(); \
- } while(0)
+ } while(0U)
#endif /* STM32F107xC*/
@@ -802,7 +802,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
@@ -817,7 +817,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -825,7 +825,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_USART3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -833,7 +833,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -841,7 +841,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
@@ -857,7 +857,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
@@ -870,7 +870,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -878,7 +878,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -886,7 +886,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -894,7 +894,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_UART4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -902,7 +902,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_UART5_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -910,7 +910,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_DAC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -918,7 +918,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
@@ -936,7 +936,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -944,7 +944,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_DAC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -952,7 +952,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_CEC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -960,7 +960,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
@@ -975,7 +975,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -983,7 +983,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -991,7 +991,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -999,7 +999,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -1007,7 +1007,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_UART4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -1015,7 +1015,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_UART5_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -1023,7 +1023,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
@@ -1041,7 +1041,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
#endif /* STM32F105xC || STM32F107xC */
@@ -1053,7 +1053,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -1061,7 +1061,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -1069,7 +1069,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
@@ -1188,7 +1188,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
@@ -1200,7 +1200,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -1208,7 +1208,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -1216,7 +1216,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
@@ -1233,7 +1233,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
@@ -1246,7 +1246,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -1254,7 +1254,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
@@ -1267,7 +1267,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -1275,7 +1275,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
@@ -1288,7 +1288,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -1296,7 +1296,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
@@ -1309,7 +1309,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -1317,7 +1317,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
@@ -1325,7 +1325,7 @@
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
UNUSED(tmpreg); \
- } while(0)
+ } while(0U)
#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rtc.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rtc.h
index 50623c0..6c9961b 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rtc.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rtc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_rtc.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
@@ -58,14 +58,14 @@
* @{
*/
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) (((PREDIV) <= (uint32_t)0xFFFFF) || ((PREDIV) == RTC_AUTO_1_SECOND))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
+#define IS_RTC_ASYNCH_PREDIV(PREDIV) (((PREDIV) <= 0xFFFFFU) || ((PREDIV) == RTC_AUTO_1_SECOND))
+#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
+#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
+#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
-#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
+#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
+#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A)
#define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUTSOURCE_NONE) || \
((__OUTPUT__) == RTC_OUTPUTSOURCE_CALIBCLOCK) || \
@@ -83,7 +83,7 @@
/** @defgroup RTC_Timeout_Value Default Timeout Value
* @{
*/
-#define RTC_TIMEOUT_VALUE 1000
+#define RTC_TIMEOUT_VALUE 1000U
/**
* @}
*/
@@ -137,11 +137,11 @@
*/
typedef enum
{
- HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */
- HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */
- HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */
- HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */
- HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */
+ HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
+ HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
+ HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
+ HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
+ HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
}HAL_RTCStateTypeDef;
@@ -207,7 +207,7 @@
/** @defgroup RTC_Automatic_Prediv_1_Second Automatic calculation of prediv for 1sec timebase
* @{
*/
-#define RTC_AUTO_1_SECOND ((uint32_t)0xFFFFFFFF)
+#define RTC_AUTO_1_SECOND 0xFFFFFFFFU
/**
* @}
@@ -216,8 +216,8 @@
/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format
* @{
*/
-#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
-#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
+#define RTC_FORMAT_BIN 0x000000000U
+#define RTC_FORMAT_BCD 0x000000001U
/**
* @}
@@ -263,7 +263,7 @@
/** @defgroup RTC_Alarms_Definitions Alarms Definitions
* @{
*/
-#define RTC_ALARM_A 0 /*!< Specify alarm ID (mainly for legacy purposes) */
+#define RTC_ALARM_A 0U /*!< Specify alarm ID (mainly for legacy purposes) */
/**
* @}
@@ -274,7 +274,7 @@
* @{
*/
-#define RTC_OUTPUTSOURCE_NONE ((uint32_t)0x00000000) /*!< No output on the TAMPER pin */
+#define RTC_OUTPUTSOURCE_NONE 0x00000000U /*!< No output on the TAMPER pin */
#define RTC_OUTPUTSOURCE_CALIBCLOCK BKP_RTCCR_CCO /*!< RTC clock with a frequency divided by 64 on the TAMPER pin */
#define RTC_OUTPUTSOURCE_ALARM BKP_RTCCR_ASOE /*!< Alarm pulse signal on the TAMPER pin */
#define RTC_OUTPUTSOURCE_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Second pulse signal on the TAMPER pin */
@@ -453,14 +453,22 @@
* @brief ALARM EXTI line configuration: set rising & falling edge trigger.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() \
+do{ \
+ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
/**
* @brief Disable the ALARM Extended Interrupt Rising & Falling Trigger.
* This parameter can be:
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()();
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() \
+do{ \
+ __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
/**
* @brief Check whether the specified ALARM EXTI interrupt flag is set or not.
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rtc_ex.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rtc_ex.h
index aeb69e8..2bdf662 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rtc_ex.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_rtc_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_rtc_ex.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of RTC HAL Extension module.
******************************************************************************
* @attention
@@ -73,14 +73,14 @@
#define IS_RTC_TAMPER(__TAMPER__) ((__TAMPER__) == RTC_TAMPER_1)
#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
- ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
+ ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
-#if RTC_BKP_NUMBER > 10
-#define IS_RTC_BKP(BKP) (((BKP) <= (uint32_t) RTC_BKP_DR10) || (((BKP) >= (uint32_t) RTC_BKP_DR11) && ((BKP) <= (uint32_t) RTC_BKP_DR42)))
+#if RTC_BKP_NUMBER > 10U
+#define IS_RTC_BKP(BKP) (((BKP) <= (uint32_t)RTC_BKP_DR10) || (((BKP) >= (uint32_t)RTC_BKP_DR11) && ((BKP) <= (uint32_t)RTC_BKP_DR42)))
#else
-#define IS_RTC_BKP(BKP) ((BKP) <= (uint32_t) RTC_BKP_NUMBER)
+#define IS_RTC_BKP(BKP) ((BKP) <= (uint32_t)RTC_BKP_NUMBER)
#endif
-#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007F)
+#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007FU)
/**
* @}
@@ -129,7 +129,7 @@
* @{
*/
#define RTC_TAMPERTRIGGER_LOWLEVEL BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
-#define RTC_TAMPERTRIGGER_HIGHLEVEL ((uint32_t)0x00000000) /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
+#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x00000000U /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
/**
* @}
@@ -138,52 +138,52 @@
/** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions
* @{
*/
-#if RTC_BKP_NUMBER > 0
-#define RTC_BKP_DR1 ((uint32_t)0x00000001)
-#define RTC_BKP_DR2 ((uint32_t)0x00000002)
-#define RTC_BKP_DR3 ((uint32_t)0x00000003)
-#define RTC_BKP_DR4 ((uint32_t)0x00000004)
-#define RTC_BKP_DR5 ((uint32_t)0x00000005)
-#define RTC_BKP_DR6 ((uint32_t)0x00000006)
-#define RTC_BKP_DR7 ((uint32_t)0x00000007)
-#define RTC_BKP_DR8 ((uint32_t)0x00000008)
-#define RTC_BKP_DR9 ((uint32_t)0x00000009)
-#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
+#if RTC_BKP_NUMBER > 0U
+#define RTC_BKP_DR1 0x00000001U
+#define RTC_BKP_DR2 0x00000002U
+#define RTC_BKP_DR3 0x00000003U
+#define RTC_BKP_DR4 0x00000004U
+#define RTC_BKP_DR5 0x00000005U
+#define RTC_BKP_DR6 0x00000006U
+#define RTC_BKP_DR7 0x00000007U
+#define RTC_BKP_DR8 0x00000008U
+#define RTC_BKP_DR9 0x00000009U
+#define RTC_BKP_DR10 0x0000000AU
#endif /* RTC_BKP_NUMBER > 0 */
-#if RTC_BKP_NUMBER > 10
-#define RTC_BKP_DR11 ((uint32_t)0x00000010)
-#define RTC_BKP_DR12 ((uint32_t)0x00000011)
-#define RTC_BKP_DR13 ((uint32_t)0x00000012)
-#define RTC_BKP_DR14 ((uint32_t)0x00000013)
-#define RTC_BKP_DR15 ((uint32_t)0x00000014)
-#define RTC_BKP_DR16 ((uint32_t)0x00000015)
-#define RTC_BKP_DR17 ((uint32_t)0x00000016)
-#define RTC_BKP_DR18 ((uint32_t)0x00000017)
-#define RTC_BKP_DR19 ((uint32_t)0x00000018)
-#define RTC_BKP_DR20 ((uint32_t)0x00000019)
-#define RTC_BKP_DR21 ((uint32_t)0x0000001A)
-#define RTC_BKP_DR22 ((uint32_t)0x0000001B)
-#define RTC_BKP_DR23 ((uint32_t)0x0000001C)
-#define RTC_BKP_DR24 ((uint32_t)0x0000001D)
-#define RTC_BKP_DR25 ((uint32_t)0x0000001E)
-#define RTC_BKP_DR26 ((uint32_t)0x0000001F)
-#define RTC_BKP_DR27 ((uint32_t)0x00000020)
-#define RTC_BKP_DR28 ((uint32_t)0x00000021)
-#define RTC_BKP_DR29 ((uint32_t)0x00000022)
-#define RTC_BKP_DR30 ((uint32_t)0x00000023)
-#define RTC_BKP_DR31 ((uint32_t)0x00000024)
-#define RTC_BKP_DR32 ((uint32_t)0x00000025)
-#define RTC_BKP_DR33 ((uint32_t)0x00000026)
-#define RTC_BKP_DR34 ((uint32_t)0x00000027)
-#define RTC_BKP_DR35 ((uint32_t)0x00000028)
-#define RTC_BKP_DR36 ((uint32_t)0x00000029)
-#define RTC_BKP_DR37 ((uint32_t)0x0000002A)
-#define RTC_BKP_DR38 ((uint32_t)0x0000002B)
-#define RTC_BKP_DR39 ((uint32_t)0x0000002C)
-#define RTC_BKP_DR40 ((uint32_t)0x0000002D)
-#define RTC_BKP_DR41 ((uint32_t)0x0000002E)
-#define RTC_BKP_DR42 ((uint32_t)0x0000002F)
+#if RTC_BKP_NUMBER > 10U
+#define RTC_BKP_DR11 0x00000010U
+#define RTC_BKP_DR12 0x00000011U
+#define RTC_BKP_DR13 0x00000012U
+#define RTC_BKP_DR14 0x00000013U
+#define RTC_BKP_DR15 0x00000014U
+#define RTC_BKP_DR16 0x00000015U
+#define RTC_BKP_DR17 0x00000016U
+#define RTC_BKP_DR18 0x00000017U
+#define RTC_BKP_DR19 0x00000018U
+#define RTC_BKP_DR20 0x00000019U
+#define RTC_BKP_DR21 0x0000001AU
+#define RTC_BKP_DR22 0x0000001BU
+#define RTC_BKP_DR23 0x0000001CU
+#define RTC_BKP_DR24 0x0000001DU
+#define RTC_BKP_DR25 0x0000001EU
+#define RTC_BKP_DR26 0x0000001FU
+#define RTC_BKP_DR27 0x00000020U
+#define RTC_BKP_DR28 0x00000021U
+#define RTC_BKP_DR29 0x00000022U
+#define RTC_BKP_DR30 0x00000023U
+#define RTC_BKP_DR31 0x00000024U
+#define RTC_BKP_DR32 0x00000025U
+#define RTC_BKP_DR33 0x00000026U
+#define RTC_BKP_DR34 0x00000027U
+#define RTC_BKP_DR35 0x00000028U
+#define RTC_BKP_DR36 0x00000029U
+#define RTC_BKP_DR37 0x0000002AU
+#define RTC_BKP_DR38 0x0000002BU
+#define RTC_BKP_DR39 0x0000002CU
+#define RTC_BKP_DR40 0x0000002DU
+#define RTC_BKP_DR41 0x0000002EU
+#define RTC_BKP_DR42 0x0000002FU
#endif /* RTC_BKP_NUMBER > 10 */
/**
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_sd.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_sd.h
index 0a8d771..7cf9f06 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_sd.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_sd.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f1xx_hal_sd.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of SD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -52,7 +52,8 @@
* @{
*/
-/** @addtogroup SD
+/** @defgroup SD SD
+ * @brief SD HAL module driver
* @{
*/
@@ -61,45 +62,116 @@
* @{
*/
+/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
+ * @{
+ */
+typedef enum
+{
+ HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */
+ HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */
+ HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */
+ HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */
+ HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */
+ HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receinving State */
+ HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfert State */
+ HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */
+}HAL_SD_StateTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
+ * @{
+ */
+typedef enum
+{
+ HAL_SD_CARD_READY = 0x00000001U, /*!< Card state is ready */
+ HAL_SD_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
+ HAL_SD_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
+ HAL_SD_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
+ HAL_SD_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
+ HAL_SD_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
+ HAL_SD_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
+ HAL_SD_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
+ HAL_SD_CARD_ERROR = 0x000000FFU /*!< Card response Error */
+}HAL_SD_CardStateTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
+ * @{
+ */
#define SD_InitTypeDef SDIO_InitTypeDef
#define SD_TypeDef SDIO_TypeDef
/**
- * @brief SDIO Handle Structure definition
+ * @brief SD Card Information Structure definition
*/
typedef struct
{
- SD_TypeDef *Instance; /*!< SDIO register base address */
+ uint32_t CardType; /*!< Specifies the card Type */
- SD_InitTypeDef Init; /*!< SD required parameters */
+ uint32_t CardVersion; /*!< Specifies the card version */
+
+ uint32_t Class; /*!< Specifies the class of the card class */
+
+ uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
- HAL_LockTypeDef Lock; /*!< SD locking object */
+ uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
+
+ uint32_t BlockSize; /*!< Specifies one block size in bytes */
- uint32_t CardType; /*!< SD card type */
+ uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
+
+ uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
+
+}HAL_SD_CardInfoTypeDef;
+
+/**
+ * @brief SD handle Structure definition
+ */
+typedef struct
+{
+ SD_TypeDef *Instance; /*!< SD registers base address */
- uint32_t RCA; /*!< SD relative card address */
+ SD_InitTypeDef Init; /*!< SD required parameters */
- uint32_t CSD[4]; /*!< SD card specific data table */
+ HAL_LockTypeDef Lock; /*!< SD locking object */
- uint32_t CID[4]; /*!< SD card identification number table */
+ uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
+
+ uint32_t TxXferSize; /*!< SD Tx Transfer size */
+
+ uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
+
+ uint32_t RxXferSize; /*!< SD Rx Transfer size */
- __IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */
+ __IO uint32_t Context; /*!< SD transfer context */
+
+ __IO HAL_SD_StateTypeDef State; /*!< SD card State */
- __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */
+ __IO uint32_t ErrorCode; /*!< SD Card Error codes */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
- __IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */
+ DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
- __IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */
+ HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
- DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
+ uint32_t CSD[4]; /*!< SD card specific data table */
- DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
+ uint32_t CID[4]; /*!< SD card identification number table */
}SD_HandleTypeDef;
/**
- * @brief Card Specific Data: CSD Register
- */
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
+ * @{
+ */
typedef struct
{
__IO uint8_t CSDStruct; /*!< CSD structure */
@@ -139,11 +211,14 @@
__IO uint8_t ECC; /*!< ECC code */
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
-
-}HAL_SD_CSDTypedef;
-
+
+}HAL_SD_CardCSDTypeDef;
/**
- * @brief Card Identification Data: CID Register
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
+ * @{
*/
typedef struct
{
@@ -158,287 +233,160 @@
__IO uint8_t CID_CRC; /*!< CID CRC */
__IO uint8_t Reserved2; /*!< Always 1 */
-}HAL_SD_CIDTypedef;
-
+}HAL_SD_CardCIDTypeDef;
/**
- * @brief SD Card Status returned by ACMD13
+ * @}
+ */
+
+/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
+ * @{
*/
typedef struct
{
- __IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */
- __IO uint8_t SECURED_MODE; /*!< Card is in secured mode of operation */
- __IO uint16_t SD_CARD_TYPE; /*!< Carries information about card type */
- __IO uint32_t SIZE_OF_PROTECTED_AREA; /*!< Carries information about the capacity of protected area */
- __IO uint8_t SPEED_CLASS; /*!< Carries information about the speed class of the card */
- __IO uint8_t PERFORMANCE_MOVE; /*!< Carries information about the card's performance move */
- __IO uint8_t AU_SIZE; /*!< Carries information about the card's allocation unit size */
- __IO uint16_t ERASE_SIZE; /*!< Determines the number of AUs to be erased in one operation */
- __IO uint8_t ERASE_TIMEOUT; /*!< Determines the timeout for any number of AU erase */
- __IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */
+ __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
+ __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
+ __IO uint16_t CardType; /*!< Carries information about card type */
+ __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
+ __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
+ __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
+ __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
+ __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
+ __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
+ __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
-}HAL_SD_CardStatusTypedef;
-
+}HAL_SD_CardStatusTypeDef;
/**
- * @brief SD Card information structure
+ * @}
*/
-typedef struct
-{
- HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */
- HAL_SD_CIDTypedef SD_cid; /*!< SD card identification number register */
- uint64_t CardCapacity; /*!< Card capacity */
- uint32_t CardBlockSize; /*!< Card block size */
- uint16_t RCA; /*!< SD relative card address */
- uint8_t CardType; /*!< SD card type */
-
-}HAL_SD_CardInfoTypedef;
/**
- * @brief SD Error status enumeration Structure definition
+ * @}
*/
-typedef enum
-{
-/**
- * @brief SD specific error defines
- */
- SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */
- SD_DATA_CRC_FAIL = (2), /*!< Data block sent/received (CRC check failed) */
- SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */
- SD_DATA_TIMEOUT = (4), /*!< Data timeout */
- SD_TX_UNDERRUN = (5), /*!< Transmit FIFO underrun */
- SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */
- SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in wide bus mode */
- SD_CMD_OUT_OF_RANGE = (8), /*!< Command's argument was out of range. */
- SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */
- SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
- SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs. */
- SD_BAD_ERASE_PARAM = (12), /*!< An invalid selection for erase groups */
- SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */
- SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
- SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */
- SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */
- SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */
- SD_CC_ERROR = (18), /*!< Internal card controller error */
- SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or unknown error */
- SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */
- SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */
- SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */
- SD_WP_ERASE_SKIP = (23), /*!< Only partial address space was erased */
- SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */
- SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
- SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */
- SD_INVALID_VOLTRANGE = (27),
- SD_ADDR_OUT_OF_RANGE = (28),
- SD_SWITCH_ERROR = (29),
- SD_SDIO_DISABLED = (30),
- SD_SDIO_FUNCTION_BUSY = (31),
- SD_SDIO_FUNCTION_FAILED = (32),
- SD_SDIO_UNKNOWN_FUNCTION = (33),
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SD_Exported_Constants Exported Constants
+ * @{
+ */
+
+#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
+
+/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
+ * @{
+ */
+#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
+#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
+#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
+#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
+#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
+#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
+#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
+#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
+#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
+ number of transferred bytes does not match the block length */
+#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
+#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
+#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
+#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
+ command or if there was an attempt to access a locked card */
+#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
+#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
+#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
+#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
+#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
+#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
+#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
+#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
+#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
+#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
+#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
+ of erase sequence command was received */
+#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
+#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
+#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
+#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
+#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
+#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
+#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
+#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
+#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+
/**
- * @brief Standard error defines
+ * @}
+ */
+
+/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
+ * @{
*/
- SD_INTERNAL_ERROR = (34),
- SD_NOT_CONFIGURED = (35),
- SD_REQUEST_PENDING = (36),
- SD_REQUEST_NOT_APPLICABLE = (37),
- SD_INVALID_PARAMETER = (38),
- SD_UNSUPPORTED_FEATURE = (39),
- SD_UNSUPPORTED_HW = (40),
- SD_ERROR = (41),
- SD_OK = (0)
-
-}HAL_SD_ErrorTypedef;
-
-/**
- * @brief SD Transfer state enumeration structure
- */
-typedef enum
-{
- SD_TRANSFER_OK = 0, /*!< Transfer success */
- SD_TRANSFER_BUSY = 1, /*!< Transfer is occurring */
- SD_TRANSFER_ERROR = 2 /*!< Transfer failed */
-
-}HAL_SD_TransferStateTypedef;
-
-/**
- * @brief SD Card State enumeration structure
- */
-typedef enum
-{
- SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */
- SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), /*!< Card is in identification state */
- SD_CARD_STANDBY = ((uint32_t)0x00000003), /*!< Card is in standby state */
- SD_CARD_TRANSFER = ((uint32_t)0x00000004), /*!< Card is in transfer state */
- SD_CARD_SENDING = ((uint32_t)0x00000005), /*!< Card is sending an operation */
- SD_CARD_RECEIVING = ((uint32_t)0x00000006), /*!< Card is receiving operation information */
- SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), /*!< Card is in programming state */
- SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), /*!< Card is disconnected */
- SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */
-
-}HAL_SD_CardStateTypedef;
-
-/**
- * @brief SD Operation enumeration structure
- */
-typedef enum
-{
- SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */
- SD_READ_MULTIPLE_BLOCK = 1, /*!< Read multiple blocks operation */
- SD_WRITE_SINGLE_BLOCK = 2, /*!< Write single block operation */
- SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */
-
-}HAL_SD_OperationTypedef;
+#define SD_CONTEXT_NONE 0x00000000U /*!< None */
+#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
+#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
+#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
+#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
+#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
+#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
/**
* @}
*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants SD Exported Constants
+/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
* @{
*/
-
-/**
- * @brief SD Commands Index
+#define CARD_SDSC 0x00000000U
+#define CARD_SDHC_SDXC 0x00000001U
+#define CARD_SECURED 0x00000003U
+
+/**
+ * @}
*/
-#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */
-#define SD_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */
-#define SD_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
-#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */
-#define SD_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */
-#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
- operating condition register (OCR) content in the response on the CMD line. */
-#define SD_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
-#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */
-#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
- and asks the card whether card supports voltage. */
-#define SD_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
-#define SD_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */
-#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */
-#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */
-#define SD_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */
-#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14)
-#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */
-#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
- (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
- for SDHS and SDXC. */
-#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
- fixed 512 bytes in case of SDHC and SDXC. */
-#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
- STOP_TRANSMISSION command. */
-#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
-#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */
-#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */
-#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
- fixed 512 bytes in case of SDHC and SDXC. */
-#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
-#define SD_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */
-#define SD_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */
-#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */
-#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */
-#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */
-#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */
-#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */
-#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
- system set by switch function command (CMD6). */
-#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
- Reserved for each command system set by switch function command (CMD6). */
-#define SD_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */
-#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */
-#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */
-#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
- the SET_BLOCK_LEN command. */
-#define SD_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
- than a standard command. */
-#define SD_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
- for general purpose/application specific commands. */
-#define SD_CMD_NO_CMD ((uint8_t)64)
-/**
- * @brief Following commands are SD Card Specific commands.
- * SDIO_APP_CMD should be sent before sending these commands.
+/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
+ * @{
*/
-#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
- widths are given in SCR register. */
-#define SD_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
-#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
- 32bit+CRC data block. */
-#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
- send its operating condition register (OCR) content in the response on the CMD line. */
-#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
-#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */
-#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */
-#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */
-
-/**
- * @brief Following commands are SD Card Specific security commands.
- * SD_CMD_APP_CMD should be sent before sending these commands.
+#define CARD_V1_X 0x00000000U
+#define CARD_V2_X 0x00000001U
+/**
+ * @}
*/
-#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD card only */
-#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD card only */
-#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD card only */
-#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD card only */
-
-/**
- * @brief Supported SD Memory Cards
- */
-#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000)
-#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001)
-#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002)
-#define MULTIMEDIA_CARD ((uint32_t)0x00000003)
-#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004)
-#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005)
-#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006)
-#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007)
+
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SD_Exported_macros SD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
/**
* @brief Enable the SD device.
- * @param __HANDLE__: SD Handle
* @retval None
*/
-#define __HAL_SD_SDIO_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
+#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
/**
* @brief Disable the SD device.
- * @param __HANDLE__: SD Handle
* @retval None
*/
-#define __HAL_SD_SDIO_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
+#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
/**
- * @brief Enable the SDIO DMA transfer.
- * @param __HANDLE__: SD Handle
+ * @brief Enable the SDMMC DMA transfer.
* @retval None
*/
-#define __HAL_SD_SDIO_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
+#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
/**
- * @brief Disable the SDIO DMA transfer.
- * @param __HANDLE__: SD Handle
+ * @brief Disable the SDMMC DMA transfer.
* @retval None
*/
-#define __HAL_SD_SDIO_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
+#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
/**
* @brief Enable the SD device interrupt.
* @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the SDIO interrupt sources to be enabled.
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -449,8 +397,6 @@
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -464,15 +410,14 @@
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
* @retval None
*/
-#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Disable the SD device interrupt.
* @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the SDIO interrupt sources to be disabled.
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -483,8 +428,6 @@
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -497,11 +440,10 @@
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval None
*/
-#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Check whether the specified SD flag is set or not.
@@ -517,7 +459,6 @@
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
* @arg SDIO_FLAG_TXACT: Data transmit in progress
@@ -531,10 +472,9 @@
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
* @retval The new state of SD FLAG (SET or RESET).
*/
-#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Clear the SD's pending flags.
@@ -550,18 +490,16 @@
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
* @retval None
*/
-#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Check whether the specified SD interrupt has occurred or not.
* @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
+ * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
@@ -572,8 +510,6 @@
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -587,14 +523,13 @@
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
* @retval The new state of SD IT (SET or RESET).
*/
-#define __HAL_SD_SDIO_GET_IT (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT ((__HANDLE__)->Instance, __INTERRUPT__)
+#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Clear the SD's interrupt pending bits.
- * @param __HANDLE__ : SD Handle
+ * @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
@@ -605,91 +540,161 @@
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
* @retval None
*/
-#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SD_Exported_Functions
+/** @defgroup SD_Exported_Functions SD Exported Functions
* @{
*/
-
-/* Initialization and de-initialization functions **********************************/
-/** @addtogroup SD_Exported_Functions_Group1
+
+/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
-HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
-HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
/**
* @}
*/
-
-/* I/O operation functions *****************************************************/
-/** @addtogroup SD_Exported_Functions_Group2
+
+/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* Blocking mode: Polling */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t Startaddr, uint64_t Endaddr);
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+/* Non-Blocking mode: IT */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-/* Non-Blocking mode: Interrupt */
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
/* Callback in non blocking modes (DMA) */
-void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
+
+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
+/**
+ * @}
+ */
-/* Non-Blocking mode: DMA */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
-HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
-/**
- * @}
- */
-
-/* Peripheral Control functions ************************************************/
-/** @addtogroup SD_Exported_Functions_Group3
+/** @defgroup SD_Exported_Functions_Group4 SD card related functions
* @{
*/
-HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
-HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
-HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
-HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
+HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
/**
* @}
*/
-
-/* Peripheral State functions **************************************************/
-/** @addtogroup SD_Exported_Functions_Group4
+
+/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
* @{
*/
-HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
-HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
+uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
/**
* @}
*/
+/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
+ * @{
+ */
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup SD_Private_Types SD Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SD_Private_Defines SD Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup SD_Private_Variables SD Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SD_Private_Constants SD Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SD_Private_Macros SD Private Macros
+ * @{
+ */
+
/**
* @}
*/
-
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
/**
* @}
*/
@@ -698,6 +703,9 @@
* @}
*/
+/**
+ * @}
+ */
#ifdef __cplusplus
}
#endif
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_smartcard.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_smartcard.h
index 893bd9e..b116c3d 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_smartcard.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_smartcard.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f1xx_hal_smartcard.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -57,10 +57,9 @@
/* Exported types ------------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
* @{
- */
+ */
-
-/**
+/**
* @brief SMARTCARD Init Structure definition
*/
typedef struct
@@ -108,21 +107,65 @@
}SMARTCARD_InitTypeDef;
/**
- * @brief HAL State structures definition
+ * @brief HAL SMARTCARD State structures definition
+ * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
+ * - gState contains SMARTCARD state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : (Not Used)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
*/
typedef enum
{
- HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
- HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
- HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */
+ HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
+ Value is allowed for gState and RxState */
+ HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+ HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
+ Value is allowed for gState only */
+ HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+ HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+ HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+ HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
+ Value is allowed for gState only */
+ HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
+ Value is allowed for gState only */
}HAL_SMARTCARD_StateTypeDef;
-
/**
* @brief SMARTCARD handle Structure definition
*/
@@ -136,13 +179,13 @@
uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
- uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
+ __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
- uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
+ __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
@@ -150,9 +193,14 @@
HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_SMARTCARD_StateTypeDef State; /*!< SmartCard communication state */
+ __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+
+ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
+ This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
- __IO uint32_t ErrorCode; /*!< SmartCard Error code */
+ __IO uint32_t ErrorCode; /*!< SmartCard Error code */
}SMARTCARD_HandleTypeDef;
/**
@@ -164,26 +212,23 @@
* @{
*/
-/** @defgroup SMARTCARD_Error_Codes SMARTCARD Error Codes
+/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
* @{
*/
-#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
-#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
-#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04) /*!< frame error */
-#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
-#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
-
+#define HAL_SMARTCARD_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_SMARTCARD_ERROR_PE 0x00000001U /*!< Parity error */
+#define HAL_SMARTCARD_ERROR_NE 0x00000002U /*!< Noise error */
+#define HAL_SMARTCARD_ERROR_FE 0x00000004U /*!< Frame error */
+#define HAL_SMARTCARD_ERROR_ORE 0x00000008U /*!< OverRun error */
+#define HAL_SMARTCARD_ERROR_DMA 0x00000010U /*!< DMA transfer error */
/**
* @}
*/
-
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
* @{
*/
#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-
/**
* @}
*/
@@ -219,16 +264,16 @@
/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
* @{
*/
-#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000)
+#define SMARTCARD_POLARITY_LOW 0x00000000U
#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
/**
* @}
*/
-/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
* @{
*/
-#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000)
+#define SMARTCARD_PHASE_1EDGE 0x00000000U
#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
/**
* @}
@@ -237,78 +282,73 @@
/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
* @{
*/
-#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_LASTBIT_DISABLE 0x00000000U
#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
/**
* @}
*/
-/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
+/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
* @{
*/
-#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
-#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000)
+#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
+#define SMARTCARD_NACK_DISABLE 0x00000000U
/**
* @}
*/
-/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
+/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
* @{
*/
-
-#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
-#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
-
+#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
+#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
/**
* @}
*/
-/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
+/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
* @{
*/
-#define SMARTCARD_PRESCALER_SYSCLK_DIV2 ((uint32_t)0x00000001) /*!< SYSCLK divided by 2 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV4 ((uint32_t)0x00000002) /*!< SYSCLK divided by 4 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV6 ((uint32_t)0x00000003) /*!< SYSCLK divided by 6 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV8 ((uint32_t)0x00000004) /*!< SYSCLK divided by 8 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV10 ((uint32_t)0x00000005) /*!< SYSCLK divided by 10 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV12 ((uint32_t)0x00000006) /*!< SYSCLK divided by 12 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV14 ((uint32_t)0x00000007) /*!< SYSCLK divided by 14 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV16 ((uint32_t)0x00000008) /*!< SYSCLK divided by 16 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV18 ((uint32_t)0x00000009) /*!< SYSCLK divided by 18 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV20 ((uint32_t)0x0000000A) /*!< SYSCLK divided by 20 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV22 ((uint32_t)0x0000000B) /*!< SYSCLK divided by 22 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV24 ((uint32_t)0x0000000C) /*!< SYSCLK divided by 24 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV26 ((uint32_t)0x0000000D) /*!< SYSCLK divided by 26 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV28 ((uint32_t)0x0000000E) /*!< SYSCLK divided by 28 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV30 ((uint32_t)0x0000000F) /*!< SYSCLK divided by 30 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV32 ((uint32_t)0x00000010) /*!< SYSCLK divided by 32 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV34 ((uint32_t)0x00000011) /*!< SYSCLK divided by 34 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV36 ((uint32_t)0x00000012) /*!< SYSCLK divided by 36 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV38 ((uint32_t)0x00000013) /*!< SYSCLK divided by 38 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV40 ((uint32_t)0x00000014) /*!< SYSCLK divided by 40 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV42 ((uint32_t)0x00000015) /*!< SYSCLK divided by 42 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV44 ((uint32_t)0x00000016) /*!< SYSCLK divided by 44 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV46 ((uint32_t)0x00000017) /*!< SYSCLK divided by 46 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV48 ((uint32_t)0x00000018) /*!< SYSCLK divided by 48 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV50 ((uint32_t)0x00000019) /*!< SYSCLK divided by 50 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV52 ((uint32_t)0x0000001A) /*!< SYSCLK divided by 52 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV54 ((uint32_t)0x0000001B) /*!< SYSCLK divided by 54 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV56 ((uint32_t)0x0000001C) /*!< SYSCLK divided by 56 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV58 ((uint32_t)0x0000001D) /*!< SYSCLK divided by 58 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV60 ((uint32_t)0x0000001E) /*!< SYSCLK divided by 60 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV62 ((uint32_t)0x0000001F) /*!< SYSCLK divided by 62 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV2 0x00000001U /*!< SYSCLK divided by 2 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV4 0x00000002U /*!< SYSCLK divided by 4 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV6 0x00000003U /*!< SYSCLK divided by 6 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV8 0x00000004U /*!< SYSCLK divided by 8 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV10 0x00000005U /*!< SYSCLK divided by 10 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV12 0x00000006U /*!< SYSCLK divided by 12 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV14 0x00000007U /*!< SYSCLK divided by 14 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV16 0x00000008U /*!< SYSCLK divided by 16 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV18 0x00000009U /*!< SYSCLK divided by 18 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV20 0x0000000AU /*!< SYSCLK divided by 20 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV22 0x0000000BU /*!< SYSCLK divided by 22 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV24 0x0000000CU /*!< SYSCLK divided by 24 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV26 0x0000000DU /*!< SYSCLK divided by 26 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV28 0x0000000EU /*!< SYSCLK divided by 28 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV30 0x0000000FU /*!< SYSCLK divided by 30 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV32 0x00000010U /*!< SYSCLK divided by 32 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV34 0x00000011U /*!< SYSCLK divided by 34 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV36 0x00000012U /*!< SYSCLK divided by 36 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV38 0x00000013U /*!< SYSCLK divided by 38 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV40 0x00000014U /*!< SYSCLK divided by 40 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV42 0x00000015U /*!< SYSCLK divided by 42 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV44 0x00000016U /*!< SYSCLK divided by 44 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV46 0x00000017U /*!< SYSCLK divided by 46 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV48 0x00000018U /*!< SYSCLK divided by 48 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV50 0x00000019U /*!< SYSCLK divided by 50 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV52 0x0000001AU /*!< SYSCLK divided by 52 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV54 0x0000001BU /*!< SYSCLK divided by 54 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV56 0x0000001CU /*!< SYSCLK divided by 56 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV58 0x0000001DU /*!< SYSCLK divided by 58 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV60 0x0000001EU /*!< SYSCLK divided by 60 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV62 0x0000001FU /*!< SYSCLK divided by 62 */
/**
* @}
*/
-
-
-/** @defgroup SMARTCARD_Flags SMARTCARD Flags
+/** @defgroup SmartCard_Flags SMARTCARD Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the SR register
* @{
*/
-
#define SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC)
#define SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
@@ -321,24 +361,20 @@
* @}
*/
-/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition
+/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
* Elements values convention: 0xY000XXXX
- * - XXXX : Interrupt mask (16 bits) in the Y register
- * - Y : Interrupt source register (4 bits)
- * - 0001: CR1 register
- * - 0010: CR3 register
-
- *
+ * - XXXX : Interrupt mask in the XX register
+ * - Y : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 11: CR3 register
* @{
*/
-
-#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
-#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
-#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
-#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
-#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
-#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28 | USART_CR3_EIE))
-
+#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
+#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
/**
* @}
*/
@@ -347,27 +383,26 @@
* @}
*/
-
/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
+/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
* @{
*/
-
-/** @brief Reset SMARTCARD handle state
+/** @brief Reset SMARTCARD handle gstate & RxState
* @param __HANDLE__: specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
*/
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
+ } while(0U)
/** @brief Flush the Smartcard DR register
* @param __HANDLE__: specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
*/
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
+
/** @brief Check whether the specified Smartcard flag is set or not.
* @param __HANDLE__: specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
@@ -392,7 +427,6 @@
* This parameter can be any combination of the following values:
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
- * @retval None
*
* @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun
* error) flags are cleared by software sequence: a read operation to
@@ -401,51 +435,42 @@
* @note TC flag can be also cleared by software sequence: a read operation to
* USART_SR register followed by a write operation to USART_DR register.
* @note TXE flag is cleared only by a write to the USART_DR register.
- *
- * @retval None
*/
#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Clear the SMARTCARD PE pending flag.
* @param __HANDLE__: specifies the USART Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
*/
-#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
-do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- UNUSED(tmpreg); \
-}while(0)
-
-
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+ } while(0U)
/** @brief Clear the SMARTCARD FE pending flag.
* @param __HANDLE__: specifies the USART Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
*/
#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the SMARTCARD NE pending flag.
* @param __HANDLE__: specifies the USART Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
*/
#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the SMARTCARD ORE pending flag.
* @param __HANDLE__: specifies the USART Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
*/
#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the SMARTCARD IDLE pending flag.
* @param __HANDLE__: specifies the USART Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
*/
#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
@@ -459,13 +484,12 @@
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
* @arg SMARTCARD_IT_PE: Parity Error interrupt
- * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @retval None
+ * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overRun error)
*/
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-/** @brief Disable the specified SmartCard interrupts.
+/** @brief Disable the specified SmartCard interrupt.
* @param __HANDLE__: specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
@@ -475,14 +499,13 @@
* @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
* @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
* @arg SMARTCARD_IT_PE: Parity Error interrupt
- * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
+ * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overRun error)
*/
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-/** @brief Check whether the specified SmartCard interrupt has occurred or not.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
+/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
+ * @param __HANDLE__: specifies the SmartCard Handle.
* @param __IT__: specifies the SMARTCARD interrupt source to check.
* This parameter can be one of the following values:
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
@@ -493,135 +516,62 @@
* @arg SMARTCARD_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
/** @brief Enable the USART associated to the SMARTCARD Handle
* @param __HANDLE__: specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_SMARTCARD_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
+ */
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable the USART associated to the SMARTCARD Handle
* @param __HANDLE__: specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
-#define __HAL_SMARTCARD_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
+ */
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-/** @brief Enable the SmartCard DMA request.
+/** @brief Macros to enable the SmartCard DMA request.
* @param __HANDLE__: specifies the SmartCard Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __REQUEST__: specifies the SmartCard DMA request.
- * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
- * @retval None
*/
-#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) (SET_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__)))
+#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
-/** @brief Disable the SmartCard DMA request.
+/** @brief Macros to disable the SmartCard DMA request.
* @param __HANDLE__: specifies the SmartCard Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __REQUEST__: specifies the SmartCard DMA request.
- * This parameter can be one of the following values:
+ * This parameter can be one of the following values:
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
- * @retval None
*/
-#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) (CLEAR_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__)))
-
+#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
/**
* @}
*/
-
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
- * @{
- */
-
-#define SMARTCARD_CR1_REG_INDEX 1
-#define SMARTCARD_CR3_REG_INDEX 3
-
-#define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__)))
-#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100)
-#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100)
-/* UART BRR = mantissa + overflow + fraction
- = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */
-#define SMARTCARD_BRR(_PCLK_, _BAUD_) (((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4) + \
- (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0)) + \
- (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F))
-
-/** Check the Baud rate range.
- * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 72 MHz)
- * divided by the smallest oversampling used on the USART (i.e. 16)
- * __BAUDRATE__: Baud rate set by the configuration function.
- * Return : TRUE or FALSE
- */
-#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
-
-#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
-
-#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
- ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
-
-#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
- ((PARITY) == SMARTCARD_PARITY_ODD))
-
-#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (~((uint32_t)SMARTCARD_MODE_TX_RX))) == 0x00) && \
- ((MODE) != (uint32_t)0x00000000))
-
-#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
-
-#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
-
-#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
- ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
-
-#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
- ((NACK) == SMARTCARD_NACK_DISABLE))
-
-#define IS_SMARTCARD_PRESCALER(PRESCALER) (((PRESCALER) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \
- ((PRESCALER) <= SMARTCARD_PRESCALER_SYSCLK_DIV62) )
-
-/** SMARTCARD interruptions flag mask
- *
- */
-#define SMARTCARD_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
- USART_CR1_IDLEIE | USART_CR3_EIE )
-
-
-/**
- * @}
- */
-
-
/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
- * @{
- */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup SMARTCARD_Exported_Functions
* @{
*/
+/** @addtogroup SMARTCARD_Exported_Functions_Group1
+ * @{
+ */
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
-
/**
* @}
*/
-/** @addtogroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+/** @addtogroup SMARTCARD_Exported_Functions_Group2
* @{
*/
-
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -629,27 +579,91 @@
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc);
+
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
-
+void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsc);
+void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc);
/**
* @}
*/
-/** @addtogroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions
+/** @addtogroup SMARTCARD_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions **************************************************/
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
* @{
*/
-/* Peripheral State and Errors functions functions *****************************/
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
+/** @brief SMARTCARD interruptions flag mask
+ *
+ */
+#define SMARTCARD_IT_MASK 0x0000FFFFU
+#define SMARTCARD_CR1_REG_INDEX 1U
+#define SMARTCARD_CR3_REG_INDEX 3U
/**
* @}
*/
+/* Private macros --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
+ * @{
+ */
+#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
+#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
+ ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
+#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
+ ((PARITY) == SMARTCARD_PARITY_ODD))
+#define IS_SMARTCARD_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
+#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
+#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
+#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
+ ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
+#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
+ ((NACK) == SMARTCARD_NACK_DISABLE))
+#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
+
+#define SMARTCARD_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
+#define SMARTCARD_DIVMANT(_PCLK_, _BAUD_) (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U)
+#define SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_) (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+/* SMARTCARD BRR = mantissa + overflow + fraction
+ = (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
+#define SMARTCARD_BRR(_PCLK_, _BAUD_) (((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
+ (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
+ (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+ * @{
+ */
+
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_spi.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_spi.h
index c131bc7..0712328 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_spi.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_spi.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f1xx_hal_spi.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_SPI_H
@@ -59,19 +59,19 @@
* @{
*/
-/**
- * @brief SPI Configuration Structure definition
+/**
+ * @brief SPI Configuration Structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the SPI operating mode.
- This parameter can be a value of @ref SPI_mode */
+ This parameter can be a value of @ref SPI_Mode */
uint32_t Direction; /*!< Specifies the SPI Directional mode state.
- This parameter can be a value of @ref SPI_Direction_mode */
+ This parameter can be a value of @ref SPI_Direction */
uint32_t DataSize; /*!< Specifies the SPI data size.
- This parameter can be a value of @ref SPI_data_size */
+ This parameter can be a value of @ref SPI_Data_Size */
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
@@ -87,7 +87,7 @@
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler
@note The communication clock is derived from the master
- clock. The slave clock does not need to be set */
+ clock. The slave clock does not need to be set. */
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
@@ -100,7 +100,6 @@
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
-
}SPI_InitTypeDef;
/**
@@ -108,18 +107,16 @@
*/
typedef enum
{
- HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */
- HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */
- HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */
- HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
- HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */
-
+ HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
+ HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
+ HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
+ HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */
}HAL_SPI_StateTypeDef;
-
-/**
+/**
* @brief SPI handle Structure definition
*/
typedef struct __SPI_HandleTypeDef
@@ -130,95 +127,88 @@
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
- uint16_t TxXferSize; /*!< SPI Tx transfer size */
-
- uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
+ uint16_t TxXferSize; /*!< SPI Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
- uint16_t RxXferSize; /*!< SPI Rx transfer size */
+ uint16_t RxXferSize; /*!< SPI Rx Transfer size */
- uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA handle parameters */
+ __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */
void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */
- HAL_LockTypeDef Lock; /*!< SPI locking object */
+ DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
- __IO uint32_t ErrorCode; /*!< SPI Error code */
+ __IO uint32_t ErrorCode; /*!< SPI Error code */
}SPI_HandleTypeDef;
+
/**
* @}
*/
-
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup SPI_Exported_Constants SPI Exported Constants
* @{
*/
-/** @defgroup SPI_Error_Codes SPI Error Codes
+/** @defgroup SPI_Error_Code SPI Error Code
* @{
- */
-#define HAL_SPI_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_SPI_ERROR_MODF ((uint32_t)0x01) /*!< MODF error */
-#define HAL_SPI_ERROR_CRC ((uint32_t)0x02) /*!< CRC error */
-#define HAL_SPI_ERROR_OVR ((uint32_t)0x04) /*!< OVR error */
-#define HAL_SPI_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */
-#define HAL_SPI_ERROR_FLAG ((uint32_t)0x10) /*!< Flag: RXNE,TXE, BSY */
+ */
+#define HAL_SPI_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_SPI_ERROR_MODF 0x00000001U /*!< MODF error */
+#define HAL_SPI_ERROR_CRC 0x00000002U /*!< CRC error */
+#define HAL_SPI_ERROR_OVR 0x00000004U /*!< OVR error */
+#define HAL_SPI_ERROR_FRE 0x00000008U /*!< FRE error */
+#define HAL_SPI_ERROR_DMA 0x00000010U /*!< DMA transfer error */
+#define HAL_SPI_ERROR_FLAG 0x00000020U /*!< Flag: RXNE,TXE, BSY */
/**
* @}
*/
-
-
-
-/** @defgroup SPI_mode SPI mode
+/** @defgroup SPI_Mode SPI Mode
* @{
*/
-#define SPI_MODE_SLAVE ((uint32_t)0x00000000)
+#define SPI_MODE_SLAVE 0x00000000U
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
-
/**
* @}
*/
-/** @defgroup SPI_Direction_mode SPI Direction mode
+/** @defgroup SPI_Direction SPI Direction Mode
* @{
*/
-#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
+#define SPI_DIRECTION_2LINES 0x00000000U
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
-
/**
* @}
*/
-/** @defgroup SPI_data_size SPI data size
+/** @defgroup SPI_Data_Size SPI Data Size
* @{
*/
-#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
+#define SPI_DATASIZE_8BIT 0x00000000U
#define SPI_DATASIZE_16BIT SPI_CR1_DFF
-
/**
* @}
- */
+ */
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
*/
-#define SPI_POLARITY_LOW ((uint32_t)0x00000000)
+#define SPI_POLARITY_LOW 0x00000000U
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
-
/**
* @}
*/
@@ -226,71 +216,65 @@
/** @defgroup SPI_Clock_Phase SPI Clock Phase
* @{
*/
-#define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
+#define SPI_PHASE_1EDGE 0x00000000U
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
-
/**
* @}
*/
-/** @defgroup SPI_Slave_Select_management SPI Slave Select management
+/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
* @{
*/
#define SPI_NSS_SOFT SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
+#define SPI_NSS_HARD_INPUT 0x00000000U
#define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16))
-
/**
* @}
- */
+ */
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
* @{
*/
-#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
-#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2)
-#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_2 0x00000000U
+#define SPI_BAUDRATEPRESCALER_4 SPI_CR1_BR_0
+#define SPI_BAUDRATEPRESCALER_8 SPI_CR1_BR_1
+#define SPI_BAUDRATEPRESCALER_16 (uint32_t)(SPI_CR1_BR_1 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_32 SPI_CR1_BR_2
+#define SPI_BAUDRATEPRESCALER_64 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_0)
+#define SPI_BAUDRATEPRESCALER_128 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1)
+#define SPI_BAUDRATEPRESCALER_256 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
/**
* @}
- */
+ */
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
* @{
*/
-#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
+#define SPI_FIRSTBIT_MSB 0x00000000U
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
-
/**
* @}
*/
-/** @defgroup SPI_TI_mode SPI TI mode disable
- * @brief SPI TI Mode not supported for STM32F1xx family
+/** @defgroup SPI_TI_mode SPI TI Mode
* @{
*/
-#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
-
+#define SPI_TIMODE_DISABLE 0x00000000U
/**
* @}
*/
-
+
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
* @{
*/
-#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
-#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
-
+#define SPI_CRCCALCULATION_DISABLE 0x00000000U
+#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
/**
* @}
*/
-/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
+/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
* @{
*/
#define SPI_IT_TXE SPI_CR2_TXEIE
@@ -300,16 +284,15 @@
* @}
*/
-/** @defgroup SPI_Flag_definition SPI Flag definition
+/** @defgroup SPI_Flags_definition SPI Flags Definition
* @{
*/
-#define SPI_FLAG_RXNE SPI_SR_RXNE
-#define SPI_FLAG_TXE SPI_SR_TXE
-#define SPI_FLAG_CRCERR SPI_SR_CRCERR
-#define SPI_FLAG_MODF SPI_SR_MODF
-#define SPI_FLAG_OVR SPI_SR_OVR
-#define SPI_FLAG_BSY SPI_SR_BSY
-
+#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
+#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
+#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
+#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
+#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
+#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
/**
* @}
*/
@@ -318,25 +301,13 @@
* @}
*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
- * @{
- */
-#define SPI_INVALID_CRC_ERROR 0 /* CRC error wrongly detected */
-#define SPI_VALID_CRC_ERROR 1 /* CRC error is true */
-/**
- * @}
- */
-
-
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SPI_Exported_Macros SPI Exported Macros
* @{
*/
-/** @brief Reset SPI handle state
- * @param __HANDLE__: specifies the SPI handle.
+/** @brief Reset SPI handle state.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
@@ -352,7 +323,7 @@
* @arg SPI_IT_ERR: Error interrupt enable
* @retval None
*/
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
/** @brief Disable the specified SPI interrupts.
* @param __HANDLE__: specifies the SPI handle.
@@ -364,10 +335,10 @@
* @arg SPI_IT_ERR: Error interrupt enable
* @retval None
*/
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
-/** @brief Check if the specified SPI interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the SPI handle.
+/** @brief Check whether the specified SPI interrupt source is enabled or not.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __INTERRUPT__: specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
@@ -379,7 +350,7 @@
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SPI flag is set or not.
- * @param __HANDLE__: specifies the SPI handle.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
@@ -394,191 +365,52 @@
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the SPI CRCERR pending flag.
- * @param __HANDLE__: specifies the SPI handle.
+ * @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
/** @brief Clear the SPI MODF pending flag.
- * @param __HANDLE__: specifies the SPI handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
-do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- tmpreg = CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
- UNUSED(tmpreg); \
-}while(0)
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
+do{ \
+ __IO uint32_t tmpreg_modf = 0x00U; \
+ tmpreg_modf = (__HANDLE__)->Instance->SR; \
+ (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
+ UNUSED(tmpreg_modf); \
+ } while(0U)
/** @brief Clear the SPI OVR pending flag.
- * @param __HANDLE__: specifies the SPI handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
-do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg); \
-}while(0)
-
-
-/** @brief Enables the SPI.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/** @brief Disables the SPI.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/**
- * @}
- */
-
-
-/* Private macros -----------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
- * @{
- */
-
-/** @brief Checks if SPI Mode parameter is in allowed range.
- * @param __MODE__: specifies the SPI Mode.
- * This parameter can be a value of @ref SPI_mode
- * @retval None
- */
-#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER))
-
-/** @brief Checks if SPI Direction Mode parameter is in allowed range.
- * @param __MODE__: specifies the SPI Direction Mode.
- * This parameter can be a value of @ref SPI_Direction_mode
- * @retval None
- */
-#define IS_SPI_DIRECTION_MODE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
- ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
- ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
- * @param __MODE__: specifies the SPI Direction Mode.
- * @retval None
- */
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
- ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief Checks if SPI Direction Mode parameter is 2 lines.
- * @param __MODE__: specifies the SPI Direction Mode.
- * @retval None
- */
-#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
-
-/** @brief Checks if SPI Data Size parameter is in allowed range.
- * @param __DATASIZE__: specifies the SPI Data Size.
- * This parameter can be a value of @ref SPI_data_size
- * @retval None
- */
-#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
- ((__DATASIZE__) == SPI_DATASIZE_8BIT))
-
-/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
- * @param __CPOL__: specifies the SPI serial clock steady state.
- * This parameter can be a value of @ref SPI_Clock_Polarity
- * @retval None
- */
-#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
- ((__CPOL__) == SPI_POLARITY_HIGH))
-
-/** @brief Checks if SPI Clock Phase parameter is in allowed range.
- * @param __CPHA__: specifies the SPI Clock Phase.
- * This parameter can be a value of @ref SPI_Clock_Phase
- * @retval None
- */
-#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
- ((__CPHA__) == SPI_PHASE_2EDGE))
-
-/** @brief Checks if SPI Slave select parameter is in allowed range.
- * @param __NSS__: specifies the SPI Slave Slelect management parameter.
- * This parameter can be a value of @ref SPI_Slave_Select_management
- * @retval None
- */
-#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
- ((__NSS__) == SPI_NSS_HARD_INPUT) || \
- ((__NSS__) == SPI_NSS_HARD_OUTPUT))
-
-/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
- * @param __PRESCALER__: specifies the SPI Baudrate prescaler.
- * This parameter can be a value of @ref SPI_BaudRate_Prescaler
- * @retval None
- */
-#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
- ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
-
-/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
- * @param __BIT__: specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
- * This parameter can be a value of @ref SPI_MSB_LSB_transmission
- * @retval None
- */
-#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
- ((__BIT__) == SPI_FIRSTBIT_LSB))
-
-/** @brief Checks if SPI TI mode parameter is in allowed range.
- * @param __MODE__: specifies the SPI TI mode.
- * This parameter can be a value of @ref SPI_TI_mode
- * @retval None
- */
-#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE)
-
-/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
- * @param __CALCULATION__: specifies the SPI CRC calculation enable state.
- * This parameter can be a value of @ref SPI_CRC_Calculation
- * @retval None
- */
-#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
- ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
-
-/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
- * @param __POLYNOMIAL__: specifies the SPI polynomial value to be used for the CRC calculation.
- * This parameter must be a number between Min_Data = 0 and Max_Data = 65535
- * @retval None
- */
-#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1) && ((__POLYNOMIAL__) <= 0xFFFF))
-
-/** @brief Sets the SPI transmit-only mode.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
+do{ \
+ __IO uint32_t tmpreg_ovr = 0x00U; \
+ tmpreg_ovr = (__HANDLE__)->Instance->DR; \
+ tmpreg_ovr = (__HANDLE__)->Instance->SR; \
+ UNUSED(tmpreg_ovr); \
+ } while(0U)
-/** @brief Sets the SPI receive-only mode.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-/** @brief Resets the CRC calculation of the SPI.
+/** @brief Enable the SPI peripheral.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
-#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
- SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0)
+#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
+/** @brief Disable the SPI peripheral.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
/**
* @}
*/
@@ -588,10 +420,10 @@
* @{
*/
-/* Initialization/de-initialization functions **********************************/
/** @addtogroup SPI_Exported_Functions_Group1
* @{
*/
+/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
@@ -600,10 +432,10 @@
* @}
*/
-/* I/O operation functions *****************************************************/
/** @addtogroup SPI_Exported_Functions_Group2
* @{
*/
+/* I/O operation functions *****************************************************/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
@@ -616,27 +448,29 @@
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
/**
* @}
*/
-
-/* Peripheral State and Control functions **************************************/
/** @addtogroup SPI_Exported_Functions_Group3
* @{
*/
+/* Peripheral State and Error functions ***************************************/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-
+uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
/**
* @}
*/
@@ -645,26 +479,107 @@
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_Private_Constants SPI Private Constants
+ * @{
+ */
+#define SPI_INVALID_CRC_ERROR 0U /* CRC error wrongly detected */
+#define SPI_VALID_CRC_ERROR 1U /* CRC error is true */
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros SPI Private Macros
+ * @{
+ */
-/* Private functions --------------------------------------------------------*/
-/** @addtogroup SPI_Private_Functions
+/** @brief Set the SPI transmit-only mode.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+
+/** @brief Set the SPI receive-only mode.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
+
+/** @brief Reset the CRC calculation of the SPI.
+ * @param __HANDLE__: specifies the SPI Handle.
+ * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+ * @retval None
+ */
+#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
+ (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U)
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+ ((MODE) == SPI_MODE_MASTER))
+
+#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
+ ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+ ((DATASIZE) == SPI_DATASIZE_8BIT))
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+ ((CPOL) == SPI_POLARITY_HIGH))
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+ ((CPHA) == SPI_PHASE_2EDGE))
+
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+ ((NSS) == SPI_NSS_HARD_INPUT) || \
+ ((NSS) == SPI_NSS_HARD_OUTPUT))
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+ ((BIT) == SPI_FIRSTBIT_LSB))
+
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
+ ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SPI_Private_Functions SPI Private Functions
* @{
*/
uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi);
+/**
+ * @}
+ */
/**
* @}
*/
-
-/**
- * @}
- */
-
/**
* @}
*/
-
+
#ifdef __cplusplus
}
#endif
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_sram.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_sram.h
index 783ac6d..b2a31e7 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_sram.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_sram.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_sram.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention
@@ -66,11 +66,11 @@
*/
typedef enum
{
- HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */
- HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */
- HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */
- HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */
- HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */
+ HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
+ HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
+ HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
+ HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
+ HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
}HAL_SRAM_StateTypeDef;
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_tim.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_tim.h
index ce97111..2c6807d 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_tim.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_tim.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_tim.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
@@ -84,6 +84,9 @@
- the number of half PWM period in center-aligned mode
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
@note This parameter is valid only for TIM1 and TIM8. */
+
+ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
+ This parameter can be a value of @ref TIM_AutoReloadPreload */
} TIM_Base_InitTypeDef;
/**
@@ -261,11 +264,11 @@
*/
typedef enum
{
- HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
- HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
- HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+ HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
+ HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
+ HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
}HAL_TIM_StateTypeDef;
/**
@@ -273,11 +276,11 @@
*/
typedef enum
{
- HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
- HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
- HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
- HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
- HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
+ HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
+ HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
+ HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
+ HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
+ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
}HAL_TIM_ActiveChannel;
/**
@@ -285,12 +288,12 @@
*/
typedef struct
{
- TIM_TypeDef *Instance; /*!< Register base address */
- TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
- DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
- This array is accessed by a @ref TIM_DMA_Handle_index */
- HAL_LockTypeDef Lock; /*!< Locking object */
+ TIM_TypeDef *Instance; /*!< Register base address */
+ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
+ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
+ DMA_HandleTypeDef *hdma[7U]; /*!< DMA Handlers array
+ This array is accessed by a @ref TIM_DMA_Handle_index */
+ HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
}TIM_HandleTypeDef;
@@ -306,7 +309,7 @@
/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
* @{
*/
-#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
+#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
/**
@@ -317,7 +320,7 @@
* @{
*/
#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
/**
* @}
*/
@@ -325,7 +328,7 @@
/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
* @{
*/
-#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
@@ -336,7 +339,7 @@
/** @defgroup TIM_Counter_Mode TIM Counter Mode
* @{
*/
-#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
+#define TIM_COUNTERMODE_UP 0x00000000U
#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
@@ -348,17 +351,26 @@
/** @defgroup TIM_ClockDivision TIM ClockDivision
* @{
*/
-#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
+#define TIM_CLOCKDIVISION_DIV1 0x00000000U
#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
/**
* @}
*/
+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
+ * @{
+ */
+#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x0000U /*!< TIMx_ARR register is not buffered */
+#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
+/**
+ * @}
+ */
+
/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
* @{
*/
-#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
+#define TIM_OCMODE_TIMING 0x00000000U
#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
@@ -373,7 +385,7 @@
/** @defgroup TIM_Output_Compare_State TIM Output Compare State
* @{
*/
-#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTSTATE_DISABLE 0x00000000U
#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
/**
* @}
@@ -382,7 +394,7 @@
/** @defgroup TIM_Output_Fast_State TIM Output Fast State
* @{
*/
-#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
+#define TIM_OCFAST_DISABLE 0x00000000U
#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
/**
* @}
@@ -391,7 +403,7 @@
/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
* @{
*/
-#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
+#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U
#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
/**
* @}
@@ -400,7 +412,7 @@
/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
* @{
*/
-#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCPOLARITY_HIGH 0x00000000U
#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
/**
* @}
@@ -409,7 +421,7 @@
/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
* @{
*/
-#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
+#define TIM_OCNPOLARITY_HIGH 0x00000000U
#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
/**
* @}
@@ -419,7 +431,7 @@
* @{
*/
#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
+#define TIM_OCIDLESTATE_RESET 0x00000000U
/**
* @}
*/
@@ -428,7 +440,7 @@
* @{
*/
#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
-#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
+#define TIM_OCNIDLESTATE_RESET 0x00000000U
/**
* @}
*/
@@ -436,11 +448,11 @@
/** @defgroup TIM_Channel TIM Channel
* @{
*/
-#define TIM_CHANNEL_1 ((uint32_t)0x0000)
-#define TIM_CHANNEL_2 ((uint32_t)0x0004)
-#define TIM_CHANNEL_3 ((uint32_t)0x0008)
-#define TIM_CHANNEL_4 ((uint32_t)0x000C)
-#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
+#define TIM_CHANNEL_1 0x00000000U
+#define TIM_CHANNEL_2 0x00000004U
+#define TIM_CHANNEL_3 0x00000008U
+#define TIM_CHANNEL_4 0x0000000CU
+#define TIM_CHANNEL_ALL 0x00000018U
/**
* @}
*/
@@ -450,7 +462,6 @@
*/
#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
-#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
/**
* @}
*/
@@ -470,7 +481,7 @@
/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
* @{
*/
-#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
@@ -482,7 +493,7 @@
* @{
*/
#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
+#define TIM_OPMODE_REPETITIVE 0x00000000U
/**
* @}
*/
@@ -516,7 +527,7 @@
* @{
*/
#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
-#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
+#define TIM_COMMUTATION_SOFTWARE 0x00000000U
/**
* @}
@@ -590,9 +601,9 @@
/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
* @{
*/
-#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
+#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
+#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
/**
@@ -613,9 +624,8 @@
/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
* @{
*/
-#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
-#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
-#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
+#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
+#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
/**
* @}
*/
@@ -624,7 +634,7 @@
* @{
*/
#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
+#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
/**
* @}
*/
@@ -644,7 +654,7 @@
* @{
*/
#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
+#define TIM_OSSR_DISABLE 0x00000000U
/**
* @}
*/
@@ -653,7 +663,7 @@
* @{
*/
#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
+#define TIM_OSSI_DISABLE 0x00000000U
/**
* @}
*/
@@ -661,7 +671,7 @@
/** @defgroup TIM_Lock_level TIM Lock level
* @{
*/
-#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
+#define TIM_LOCKLEVEL_OFF 0x00000000U
#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
@@ -673,7 +683,7 @@
* @{
*/
#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
-#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
+#define TIM_BREAK_DISABLE 0x00000000U
/**
* @}
*/
@@ -681,7 +691,7 @@
/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
* @{
*/
-#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
+#define TIM_BREAKPOLARITY_LOW 0x00000000U
#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
/**
* @}
@@ -690,7 +700,7 @@
* @{
*/
#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
-#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
+#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
/**
* @}
*/
@@ -698,7 +708,7 @@
/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
* @{
*/
-#define TIM_TRGO_RESET ((uint32_t)0x0000)
+#define TIM_TRGO_RESET 0x00000000U
#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
@@ -713,11 +723,11 @@
/** @defgroup TIM_Slave_Mode TIM Slave Mode
* @{
*/
-#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
-#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
-#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
-#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
-#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
+#define TIM_SLAVEMODE_DISABLE 0x00000000U
+#define TIM_SLAVEMODE_RESET 0x00000004U
+#define TIM_SLAVEMODE_GATED 0x00000005U
+#define TIM_SLAVEMODE_TRIGGER 0x00000006U
+#define TIM_SLAVEMODE_EXTERNAL1 0x00000007U
/**
* @}
*/
@@ -725,8 +735,8 @@
/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
* @{
*/
-#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
-#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
+#define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U
+#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
/**
* @}
*/
@@ -734,15 +744,15 @@
/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
* @{
*/
-#define TIM_TS_ITR0 ((uint32_t)0x0000)
-#define TIM_TS_ITR1 ((uint32_t)0x0010)
-#define TIM_TS_ITR2 ((uint32_t)0x0020)
-#define TIM_TS_ITR3 ((uint32_t)0x0030)
-#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
-#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
-#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
-#define TIM_TS_ETRF ((uint32_t)0x0070)
-#define TIM_TS_NONE ((uint32_t)0xFFFF)
+#define TIM_TS_ITR0 0x00000000U
+#define TIM_TS_ITR1 0x00000010U
+#define TIM_TS_ITR2 0x00000020U
+#define TIM_TS_ITR3 0x00000030U
+#define TIM_TS_TI1F_ED 0x00000040U
+#define TIM_TS_TI1FP1 0x00000050U
+#define TIM_TS_TI2FP2 0x00000060U
+#define TIM_TS_ETRF 0x00000070U
+#define TIM_TS_NONE 0x0000FFFFU
/**
* @}
*/
@@ -773,7 +783,7 @@
/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
* @{
*/
-#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
+#define TIM_TI1SELECTION_CH1 0x00000000U
#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
/**
* @}
@@ -782,25 +792,25 @@
/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
* @{
*/
-#define TIM_DMABASE_CR1 (0x00000000)
-#define TIM_DMABASE_CR2 (0x00000001)
-#define TIM_DMABASE_SMCR (0x00000002)
-#define TIM_DMABASE_DIER (0x00000003)
-#define TIM_DMABASE_SR (0x00000004)
-#define TIM_DMABASE_EGR (0x00000005)
-#define TIM_DMABASE_CCMR1 (0x00000006)
-#define TIM_DMABASE_CCMR2 (0x00000007)
-#define TIM_DMABASE_CCER (0x00000008)
-#define TIM_DMABASE_CNT (0x00000009)
-#define TIM_DMABASE_PSC (0x0000000A)
-#define TIM_DMABASE_ARR (0x0000000B)
-#define TIM_DMABASE_RCR (0x0000000C)
-#define TIM_DMABASE_CCR1 (0x0000000D)
-#define TIM_DMABASE_CCR2 (0x0000000E)
-#define TIM_DMABASE_CCR3 (0x0000000F)
-#define TIM_DMABASE_CCR4 (0x00000010)
-#define TIM_DMABASE_BDTR (0x00000011)
-#define TIM_DMABASE_DCR (0x00000012)
+#define TIM_DMABASE_CR1 0x00000000U
+#define TIM_DMABASE_CR2 0x00000001U
+#define TIM_DMABASE_SMCR 0x00000002U
+#define TIM_DMABASE_DIER 0x00000003U
+#define TIM_DMABASE_SR 0x00000004U
+#define TIM_DMABASE_EGR 0x00000005U
+#define TIM_DMABASE_CCMR1 0x00000006U
+#define TIM_DMABASE_CCMR2 0x00000007U
+#define TIM_DMABASE_CCER 0x00000008U
+#define TIM_DMABASE_CNT 0x00000009U
+#define TIM_DMABASE_PSC 0x0000000AU
+#define TIM_DMABASE_ARR 0x0000000BU
+#define TIM_DMABASE_RCR 0x0000000CU
+#define TIM_DMABASE_CCR1 0x0000000DU
+#define TIM_DMABASE_CCR2 0x0000000EU
+#define TIM_DMABASE_CCR3 0x0000000FU
+#define TIM_DMABASE_CCR4 0x00000010U
+#define TIM_DMABASE_BDTR 0x00000011U
+#define TIM_DMABASE_DCR 0x00000012U
/**
* @}
*/
@@ -808,24 +818,24 @@
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
-#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
-#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
-#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
-#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
-#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
-#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
-#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
-#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
-#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
-#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
-#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
-#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
-#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
-#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
-#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
-#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
-#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
-#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
+#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
+#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
+#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
+#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
+#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
+#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
+#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
+#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
+#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
+#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
+#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
+#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
+#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
+#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
+#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
+#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
+#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
+#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
/**
* @}
*/
@@ -833,13 +843,13 @@
/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
* @{
*/
-#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
+#define TIM_DMA_ID_UPDATE ((uint16_t)0x0) /*!< Index of the DMA handle used for Update DMA requests */
+#define TIM_DMA_ID_CC1 ((uint16_t)0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
+#define TIM_DMA_ID_CC2 ((uint16_t)0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
+#define TIM_DMA_ID_CC3 ((uint16_t)0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
+#define TIM_DMA_ID_CC4 ((uint16_t)0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
+#define TIM_DMA_ID_COMMUTATION ((uint16_t)0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
+#define TIM_DMA_ID_TRIGGER ((uint16_t)0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
/**
* @}
*/
@@ -847,10 +857,10 @@
/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
* @{
*/
-#define TIM_CCx_ENABLE ((uint32_t)0x0001)
-#define TIM_CCx_DISABLE ((uint32_t)0x0000)
-#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
-#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
+#define TIM_CCx_ENABLE 0x00000001U
+#define TIM_CCx_DISABLE 0x00000000U
+#define TIM_CCxN_ENABLE 0x00000004U
+#define TIM_CCxN_DISABLE 0x00000000U
/**
* @}
*/
@@ -888,6 +898,9 @@
((DIV) == TIM_CLOCKDIVISION_DIV2) || \
((DIV) == TIM_CLOCKDIVISION_DIV4))
+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
+ ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
+
#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
((MODE) == TIM_OCMODE_PWM2))
@@ -918,17 +931,16 @@
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_ALL))
-
+
#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
-
+ ((CHANNEL) == TIM_CHANNEL_2))
+
#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3))
#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
- ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
- ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
+ ((POLARITY) == TIM_ICPOLARITY_FALLING))
#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
@@ -946,9 +958,9 @@
((MODE) == TIM_ENCODERMODE_TI2) || \
((MODE) == TIM_ENCODERMODE_TI12))
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
@@ -972,10 +984,9 @@
((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
-#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \
- ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
@@ -986,7 +997,7 @@
((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
-#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
((STATE) == TIM_OSSR_DISABLE))
@@ -1052,7 +1063,7 @@
((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
-#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
+#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
@@ -1096,7 +1107,7 @@
((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
/** @brief Set TIM IC prescaler
* @param __HANDLE__: TIM handle
@@ -1106,9 +1117,9 @@
*/
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
/** @brief Reset TIM IC prescaler
* @param __HANDLE__: TIM handle
@@ -1130,9 +1141,9 @@
*/
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
/** @brief Reset TIM IC polarity
* @param __HANDLE__: TIM handle
@@ -1196,14 +1207,14 @@
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
{ \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
{ \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \
} \
- } while(0)
+ } while(0U)
/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
channels have been disabled */
/**
@@ -1214,14 +1225,22 @@
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
+ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
{ \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
+ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
{ \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \
} \
- } while(0)
+ } while(0U)
+
+/**
+ * @brief Disable the TIM main Output.
+ * @param __HANDLE__: TIM handle
+ * @retval None
+ * @note The Main Output Enable of a timer instance is disabled unconditionally
+ */
+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
/**
* @brief Enables the specified TIM interrupt.
@@ -1229,11 +1248,11 @@
* @param __INTERRUPT__: specifies the TIM interrupt source to enable.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
* @arg TIM_IT_TRIGGER: Trigger interrupt
* @arg TIM_IT_BREAK: Break interrupt
* @retval None
@@ -1246,11 +1265,11 @@
* @param __INTERRUPT__: specifies the TIM interrupt source to disable.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
* @arg TIM_IT_TRIGGER: Trigger interrupt
* @arg TIM_IT_BREAK: Break interrupt
* @retval None
@@ -1263,11 +1282,11 @@
* @param __DMA__: specifies the TIM DMA request to enable.
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
* @arg TIM_DMA_TRIGGER: Trigger DMA request
* @retval None
*/
@@ -1279,11 +1298,11 @@
* @param __DMA__: specifies the TIM DMA request to disable.
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
* @arg TIM_DMA_TRIGGER: Trigger DMA request
* @retval None
*/
@@ -1378,7 +1397,7 @@
* @retval None
*/
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
+(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
/**
* @brief Gets the TIM Capture Compare Register value on runtime
@@ -1389,10 +1408,10 @@
* @arg TIM_CHANNEL_2: get capture/compare 2 register value
* @arg TIM_CHANNEL_3: get capture/compare 3 register value
* @arg TIM_CHANNEL_4: get capture/compare 4 register value
- * @retval None
+ * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
*/
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
- (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
+ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
/**
* @brief Sets the TIM Counter Register value on runtime.
@@ -1405,7 +1424,7 @@
/**
* @brief Gets the TIM Counter Register value on runtime.
* @param __HANDLE__: TIM handle.
- * @retval None
+ * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/
#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
((__HANDLE__)->Instance->CNT)
@@ -1421,12 +1440,12 @@
do{ \
(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
- } while(0)
+ } while(0U)
/**
* @brief Gets the TIM Autoreload Register value on runtime
* @param __HANDLE__: TIM handle.
- * @retval None
+ * @retval @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
((__HANDLE__)->Instance->ARR)
@@ -1437,22 +1456,25 @@
* @param __HANDLE__: TIM handle.
* @param __CKD__: specifies the clock division value.
* This parameter can be one of the following value:
- * @arg TIM_CLOCKDIVISION_DIV1
- * @arg TIM_CLOCKDIVISION_DIV2
- * @arg TIM_CLOCKDIVISION_DIV4
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
* @retval None
*/
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
- do{ \
+ do{ \
(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
+ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
(__HANDLE__)->Init.ClockDivision = (__CKD__); \
- } while(0)
+ } while(0U)
/**
* @brief Gets the TIM Clock Division value on runtime
* @param __HANDLE__: TIM handle.
- * @retval None
+ * @retval The clock division can be one of the following values:
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
@@ -1479,7 +1501,7 @@
do{ \
TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0)
+ } while(0U)
/**
* @brief Gets the TIM Input Capture prescaler on runtime
@@ -1490,13 +1512,17 @@
* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
- * @retval None
+ * @retval The input capture prescaler can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
*/
#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
- (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
+ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
/**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
@@ -1543,7 +1569,7 @@
do{ \
TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
- }while(0)
+ }while(0U)
/**
* @}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_tim_ex.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_tim_ex.h
index 7c706f1..8a8a0ce 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_tim_ex.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_tim_ex.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_tim_ex.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of TIM HAL Extension module.
******************************************************************************
* @attention
@@ -66,17 +66,17 @@
typedef struct
{
-
+
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
+
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
+
uint32_t IC1Filter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef;
@@ -134,7 +134,7 @@
/** @defgroup TIMEx_Clock_Filter TIMEx Clock Filter
* @{
*/
-#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF) /*!< BreakDead Time */
+#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU) /*!< BreakDead Time */
/**
* @}
*/
@@ -147,6 +147,39 @@
/* defined(STM32F105xC) || defined(STM32F107xC) */
/* Exported macro ------------------------------------------------------------*/
+/**
+ * @brief Sets the TIM Output compare preload.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
+ ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
+
+/**
+ * @brief Resets the TIM Output compare preload.
+ * @param __HANDLE__: TIM handle.
+ * @param __CHANNEL__: TIM Channels to be configured.
+ * This parameter can be one of the following values:
+ * @arg TIM_CHANNEL_1: TIM Channel 1 selected
+ * @arg TIM_CHANNEL_2: TIM Channel 2 selected
+ * @arg TIM_CHANNEL_3: TIM Channel 3 selected
+ * @arg TIM_CHANNEL_4: TIM Channel 4 selected
+ * @retval None
+ */
+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
+ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
/* Exported functions --------------------------------------------------------*/
/** @addtogroup TIMEx_Exported_Functions
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_uart.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_uart.h
index 35a84e1..aec6c3c 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_uart.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_uart.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_uart.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_UART_H
@@ -52,17 +52,16 @@
/** @addtogroup UART
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup UART_Exported_Types UART Exported Types
* @{
- */
+ */
-
-/**
+/**
* @brief UART Init Structure definition
- */
+ */
typedef struct
{
uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
@@ -82,38 +81,81 @@
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
-
- uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref UART_Mode */
- uint32_t HwFlowCtl; /*!< Specifies wether the hardware flow control mode is enabled
- or disabled.
+ uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref UART_Hardware_Flow_Control */
-
+
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
- This parameter can be a value of @ref UART_Over_Sampling. This feature is not available
- on STM32F1xx family, so OverSampling parameter should always be set to 16. */
+ This parameter can be a value of @ref UART_Over_Sampling. This feature is only available
+ on STM32F100xx family, so OverSampling parameter should always be set to 16. */
}UART_InitTypeDef;
/**
- * @brief HAL UART State structures definition
- */
+ * @brief HAL UART State structures definition
+ * @note HAL UART State value is a combination of 2 different substates: gState and RxState.
+ * - gState contains UART state information related to global Handle management
+ * and also information related to Tx operations.
+ * gState value coding follow below described bitmap :
+ * b7-b6 Error information
+ * 00 : No Error
+ * 01 : (Not Used)
+ * 10 : Timeout
+ * 11 : Error
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized. HAL UART Init function already called)
+ * b4-b3 (not used)
+ * xx : Should be set to 00
+ * b2 Intrinsic process state
+ * 0 : Ready
+ * 1 : Busy (IP busy with some configuration or internal operations)
+ * b1 (not used)
+ * x : Should be set to 0
+ * b0 Tx state
+ * 0 : Ready (no Tx operation ongoing)
+ * 1 : Busy (Tx operation ongoing)
+ * - RxState contains information related to Rx operations.
+ * RxState value coding follow below described bitmap :
+ * b7-b6 (not used)
+ * xx : Should be set to 00
+ * b5 IP initilisation status
+ * 0 : Reset (IP not initialized)
+ * 1 : Init done (IP not initialized)
+ * b4-b2 (not used)
+ * xxx : Should be set to 000
+ * b1 Rx state
+ * 0 : Ready (no Rx operation ongoing)
+ * 1 : Busy (Rx operation ongoing)
+ * b0 (not used)
+ * x : Should be set to 0.
+ */
typedef enum
{
- HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
- HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
- HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_UART_STATE_ERROR = 0x04 /*!< Error */
+ HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
+ Value is allowed for gState and RxState */
+ HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
+ Value is allowed for gState and RxState */
+ HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
+ Value is allowed for gState only */
+ HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
+ Value is allowed for gState only */
+ HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
+ Value is allowed for RxState only */
+ HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
+ Not to be used for neither gState nor RxState.
+ Value is result of combination (Or) between gState and RxState values */
+ HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
+ Value is allowed for gState only */
+ HAL_UART_STATE_ERROR = 0xE0U /*!< Error
+ Value is allowed for gState only */
}HAL_UART_StateTypeDef;
-
/**
- * @brief UART handle Structure definition
- */
+ * @brief UART handle Structure definition
+ */
typedef struct
{
USART_TypeDef *Instance; /*!< UART registers base address */
@@ -124,13 +166,13 @@
uint16_t TxXferSize; /*!< UART Tx Transfer size */
- uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
+ __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
uint16_t RxXferSize; /*!< UART Rx Transfer size */
- uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
+ __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
@@ -138,10 +180,14 @@
HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_UART_StateTypeDef State; /*!< UART communication state */
+ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
+ and also related to Tx operations.
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */
- __IO uint32_t ErrorCode; /*!< UART Error code */
+ __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
+ This parameter can be a value of @ref HAL_UART_StateTypeDef */
+ __IO uint32_t ErrorCode; /*!< UART Error code */
}UART_HandleTypeDef;
/**
@@ -153,56 +199,51 @@
* @{
*/
-/** @defgroup UART_Error_Codes UART Error Codes
+/** @defgroup UART_Error_Code UART Error Code
* @{
*/
-
-#define HAL_UART_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_UART_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
-#define HAL_UART_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
-#define HAL_UART_ERROR_FE ((uint32_t)0x04) /*!< frame error */
-#define HAL_UART_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
-#define HAL_UART_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
-
+#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */
+#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */
+#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */
+#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */
+#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
/**
* @}
*/
-
-
-
-/** @defgroup UART_Word_Length UART Word Length
+/** @defgroup UART_Word_Length UART Word Length
* @{
*/
-#define UART_WORDLENGTH_8B ((uint32_t)0x00000000)
+#define UART_WORDLENGTH_8B 0x00000000U
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
*/
-/** @defgroup UART_Stop_Bits UART Number of Stop Bits
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits
* @{
*/
-#define UART_STOPBITS_1 ((uint32_t)0x00000000)
+#define UART_STOPBITS_1 0x00000000U
#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
/**
* @}
- */
+ */
/** @defgroup UART_Parity UART Parity
* @{
- */
-#define UART_PARITY_NONE ((uint32_t)0x00000000)
+ */
+#define UART_PARITY_NONE 0x00000000U
#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
* @}
- */
+ */
/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
* @{
- */
-#define UART_HWCONTROL_NONE ((uint32_t)0x00000000)
+ */
+#define UART_HWCONTROL_NONE 0x00000000U
#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
@@ -216,41 +257,44 @@
#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-
/**
* @}
*/
-
- /** @defgroup UART_State UART State
+
+/** @defgroup UART_State UART State
* @{
- */
-#define UART_STATE_DISABLE ((uint32_t)0x00000000)
+ */
+#define UART_STATE_DISABLE 0x00000000U
#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
/**
* @}
*/
+
/** @defgroup UART_Over_Sampling UART Over Sampling
* @{
*/
-#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000)
+#define UART_OVERSAMPLING_16 0x00000000U
+#if defined(USART_CR1_OVER8)
+#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
+#endif /* USART_CR1_OVER8 */
/**
* @}
*/
+
/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length
* @{
*/
-#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000)
+#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U
#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
/**
* @}
*/
-
-/** @defgroup UART_WakeUp_functions UART Wakeup Functions
+/** @defgroup UART_WakeUp_functions UART Wakeup Functions
* @{
*/
-#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000)
+#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U
#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
/**
* @}
@@ -279,24 +323,22 @@
* Elements values convention: 0xY000XXXX
* - XXXX : Interrupt mask (16 bits) in the Y register
* - Y : Interrupt source register (2bits)
- * - 0001: CR1 register
- * - 0010: CR2 register
- * - 0011: CR3 register
- *
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
* @{
- */
+ */
-#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
-#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
-#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
-#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
-#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
+#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
+#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
-#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
-#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
-
+#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
+#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
/**
* @}
*/
@@ -305,32 +347,32 @@
* @}
*/
-
/* Exported macro ------------------------------------------------------------*/
/** @defgroup UART_Exported_Macros UART Exported Macros
* @{
*/
-
-/** @brief Reset UART handle state
+/** @brief Reset UART handle gstate & RxState
* @param __HANDLE__: specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
- * @retval None
*/
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
+ (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
+ (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
+ } while(0U)
-/** @brief Flush the UART DR register
+/** @brief Flushs the UART DR register
* @param __HANDLE__: specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
*/
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-/** @brief Check whether the specified UART flag is set or not.
+/** @brief Checks whether the specified UART flag is set or not.
* @param __HANDLE__: specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
+ * This parameter can be UARTx where x: 1, 2, 3, 4 or 5 to select the USART or
+ * UART peripheral.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
@@ -347,7 +389,7 @@
*/
#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-/** @brief Clear the specified UART pending flag.
+/** @brief Clears the specified UART pending flag.
* @param __HANDLE__: specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
@@ -367,58 +409,50 @@
* USART_SR register followed by a write operation to USART_DR register.
* @note TXE flag is cleared only by a write to the USART_DR register.
*
- * @retval None
*/
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-/** @brief Clear the UART PE pending flag.
+/** @brief Clears the UART PE pending flag.
* @param __HANDLE__: specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
- * @retval None
*/
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
-do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- UNUSED(tmpreg); \
-}while(0)
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+ } while(0U)
-
-
-/** @brief Clear the UART FE pending flag.
+/** @brief Clears the UART FE pending flag.
* @param __HANDLE__: specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
- * @retval None
*/
#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-/** @brief Clear the UART NE pending flag.
+/** @brief Clears the UART NE pending flag.
* @param __HANDLE__: specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
- * @retval None
*/
#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-/** @brief Clear the UART ORE pending flag.
+/** @brief Clears the UART ORE pending flag.
* @param __HANDLE__: specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
- * @retval None
*/
#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-/** @brief Clear the UART IDLE pending flag.
+/** @brief Clears the UART IDLE pending flag.
* @param __HANDLE__: specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
- * @retval None
*/
#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
+
/** @brief Enable the specified UART interrupt.
* @param __HANDLE__: specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
@@ -433,13 +467,11 @@
* @arg UART_IT_IDLE: Idle line detection interrupt
* @arg UART_IT_PE: Parity Error interrupt
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @retval None
*/
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
-
/** @brief Disable the specified UART interrupt.
* @param __HANDLE__: specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
@@ -454,13 +486,12 @@
* @arg UART_IT_IDLE: Idle line detection interrupt
* @arg UART_IT_PE: Parity Error interrupt
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @retval None
*/
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
-
-/** @brief Check whether the specified UART interrupt has occurred or not.
+
+/** @brief Checks whether the specified UART interrupt has occurred or not.
* @param __HANDLE__: specifies the UART Handle.
* UART Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
@@ -475,7 +506,7 @@
* @arg UART_IT_ERR: Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == UART_CR2_REG_INDEX)? \
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
/** @brief Enable CTS flow control
@@ -488,15 +519,14 @@
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__: specifies the UART Handle.
- * This parameter can be any USARTx (supporting the HW Flow control feature).
+ * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
* It is used to select the USART peripheral (USART availability and x value depending on device).
- * @retval None
*/
#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
- } while(0)
+ } while(0U)
/** @brief Disable CTS flow control
* This macro allows to disable CTS hardware flow control for a given UART instance,
@@ -508,15 +538,14 @@
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__: specifies the UART Handle.
- * This parameter can be any USARTx (supporting the HW Flow control feature).
+ * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
* It is used to select the USART peripheral (USART availability and x value depending on device).
- * @retval None
*/
#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
- } while(0)
+ } while(0U)
/** @brief Enable RTS flow control
* This macro allows to enable RTS hardware flow control for a given UART instance,
@@ -528,15 +557,14 @@
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__: specifies the UART Handle.
- * This parameter can be any USARTx (supporting the HW Flow control feature).
+ * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
* It is used to select the USART peripheral (USART availability and x value depending on device).
- * @retval None
*/
#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
- } while(0)
+ } while(0U)
/** @brief Disable RTS flow control
* This macro allows to disable RTS hardware flow control for a given UART instance,
@@ -548,124 +576,49 @@
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__: specifies the UART Handle.
- * This parameter can be any USARTx (supporting the HW Flow control feature).
+ * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
* It is used to select the USART peripheral (USART availability and x value depending on device).
- * @retval None
*/
#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
do{ \
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
- } while(0)
+ } while(0U)
+#if defined(USART_CR3_ONEBIT)
+/** @brief macros to enables the UART's one bit sample method
+ * @param __HANDLE__: specifies the UART Handle.
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief macros to disables the UART's one bit sample method
+ * @param __HANDLE__: specifies the UART Handle.
+ * @retval None
+ */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+#endif /* USART_CR3_ONEBIT */
/** @brief Enable UART
* @param __HANDLE__: specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
- */
+ */
#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable UART
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @retval None
+ * @param __HANDLE__: specifies the UART Handle.
*/
#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
/**
* @}
*/
-
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup UART_Private_Macros UART Private Macros
- * @{
- */
-
-#define UART_CR1_REG_INDEX 1
-#define UART_CR2_REG_INDEX 2
-#define UART_CR3_REG_INDEX 3
-
-#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
-#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-/* UART BRR = mantissa + overflow + fraction
- = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */
-#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4) + \
- (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0)) + \
- (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
-#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
- ((LENGTH) == UART_WORDLENGTH_9B))
-#define IS_UART_LIN_WORD_LENGTH(LENGTH) ((LENGTH) == UART_WORDLENGTH_8B)
-
-#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
- ((STOPBITS) == UART_STOPBITS_2))
-
-#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
- ((PARITY) == UART_PARITY_EVEN) || \
- ((PARITY) == UART_PARITY_ODD))
-
-#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
- (((CONTROL) == UART_HWCONTROL_NONE) || \
- ((CONTROL) == UART_HWCONTROL_RTS) || \
- ((CONTROL) == UART_HWCONTROL_CTS) || \
- ((CONTROL) == UART_HWCONTROL_RTS_CTS))
-
-#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)UART_MODE_TX_RX))) == 0x00) && \
- ((MODE) != (uint32_t)0x00000000))
-
-#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
- ((STATE) == UART_STATE_ENABLE))
-
-#define IS_UART_OVERSAMPLING(SAMPLING) ((SAMPLING) == UART_OVERSAMPLING_16)
-#define IS_UART_LIN_OVERSAMPLING(SAMPLING) ((SAMPLING) == UART_OVERSAMPLING_16)
-
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
- ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
-
-#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
- ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
-
-
-/** Check UART Baud rate
- * __BAUDRATE__: Baudrate specified by the user
- * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 72 MHz)
- * divided by the smallest oversampling used on the USART (i.e. 16)
- * Retrun : TRUE or FALSE
- */
-#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
-
-/** Check UART Node Address
- * __ADDRESS__: UART Node address specified by the user
- * UART Node address is used in Multi processor communication for wakeup
- * with address mark detection.
- * This parameter must be a number between Min_Data = 0 and Max_Data = 15
- * Return : TRUE or FALSE
- */
-#define IS_UART_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
-
-/** UART interruptions flag mask
- */
-#define UART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
- USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
-
-/**
- * @}
- */
-
/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup UART_Exported_Functions UART Exported Functions
- * @{
- */
-
-/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup UART_Exported_Functions
* @{
*/
-/* Initialization and de-initialization functions ****************************/
+/** @addtogroup UART_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
@@ -673,16 +626,14 @@
HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
void HAL_UART_MspInit(UART_HandleTypeDef *huart);
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
-
/**
* @}
*/
-/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+/** @addtogroup UART_Exported_Functions_Group2
* @{
*/
-
-/* IO operation functions *****************************************************/
+/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
@@ -692,43 +643,128 @@
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-
+void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
/**
* @}
*/
-/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
+/** @addtogroup UART_Exported_Functions_Group3
* @{
*/
-
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
-
/**
* @}
*/
-/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
+/** @addtogroup UART_Exported_Functions_Group4
* @{
*/
-
-/* Peripheral State and Errors functions **************************************************/
+/* Peripheral State functions **************************************************/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
/**
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+ * @{
+ */
+/** @brief UART interruptions flag mask
+ *
+ */
+#define UART_IT_MASK 0x0000FFFFU
+
+#define UART_CR1_REG_INDEX 1U
+#define UART_CR2_REG_INDEX 2U
+#define UART_CR3_REG_INDEX 3U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
+ ((LENGTH) == UART_WORDLENGTH_9B))
+#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
+ ((STOPBITS) == UART_STOPBITS_2))
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
+ ((PARITY) == UART_PARITY_EVEN) || \
+ ((PARITY) == UART_PARITY_ODD))
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
+ (((CONTROL) == UART_HWCONTROL_NONE) || \
+ ((CONTROL) == UART_HWCONTROL_RTS) || \
+ ((CONTROL) == UART_HWCONTROL_CTS) || \
+ ((CONTROL) == UART_HWCONTROL_RTS_CTS))
+#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
+#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
+ ((STATE) == UART_STATE_ENABLE))
+#if defined(USART_CR1_OVER8)
+#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
+ ((SAMPLING) == UART_OVERSAMPLING_8))
+#endif /* USART_CR1_OVER8 */
+#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
+ ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
+#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
+ ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
+#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
+
+#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
+#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
+#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+/* UART BRR = mantissa + overflow + fraction
+ = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
+#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
+ (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
+ (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
+
+#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
+#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
+#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
+/* UART BRR = mantissa + overflow + fraction
+ = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
+#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
+ ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
+ (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup UART_Private_Functions UART Private Functions
+ * @{
+ */
/**
* @}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_usart.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_usart.h
index 0d8c4b1..6b74082 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_usart.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_usart.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f1xx_hal_usart.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_USART_H
@@ -52,17 +52,16 @@
/** @addtogroup USART
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup USART_Exported_Types USART Exported Types
* @{
- */
+ */
-
-/**
+/**
* @brief USART Init Structure definition
- */
+ */
typedef struct
{
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
@@ -76,14 +75,14 @@
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
- uint32_t Parity; /*!< Specifies the parity mode.
+ uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
-
- uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+
+ uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
@@ -102,68 +101,66 @@
*/
typedef enum
{
- HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
- HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */
- HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_USART_STATE_ERROR = 0x04 /*!< Error */
+ HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not yet initialized */
+ HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
+ HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
+ HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_USART_STATE_ERROR = 0x04U /*!< Error */
}HAL_USART_StateTypeDef;
-
/**
* @brief USART handle Structure definition
*/
typedef struct
{
USART_TypeDef *Instance; /*!< USART registers base address */
-
- USART_InitTypeDef Init; /*!< Usart communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< Usart Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< Usart Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to Usart Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< Usart Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< Usart Rx Transfer Counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< Usart Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< Usart Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_USART_StateTypeDef State; /*!< Usart communication state */
-
- __IO uint32_t ErrorCode; /*!< USART Error code */
-
-}USART_HandleTypeDef;
+ USART_InitTypeDef Init; /*!< Usart communication parameters */
+
+ uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */
+
+ uint16_t TxXferSize; /*!< Usart Tx Transfer size */
+
+ __IO uint16_t TxXferCount; /*!< Usart Tx Transfer Counter */
+
+ uint8_t *pRxBuffPtr; /*!< Pointer to Usart Rx transfer Buffer */
+
+ uint16_t RxXferSize; /*!< Usart Rx Transfer size */
+
+ __IO uint16_t RxXferCount; /*!< Usart Rx Transfer Counter */
+
+ DMA_HandleTypeDef *hdmatx; /*!< Usart Tx DMA Handle parameters */
+
+ DMA_HandleTypeDef *hdmarx; /*!< Usart Rx DMA Handle parameters */
+
+ HAL_LockTypeDef Lock; /*!< Locking object */
+
+ __IO HAL_USART_StateTypeDef State; /*!< Usart communication state */
+
+ __IO uint32_t ErrorCode; /*!< USART Error code */
+}USART_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_Exported_Constants USART Exported constants
+/** @defgroup USART_Exported_Constants USART Exported Constants
* @{
*/
-/** @defgroup USART_Error_Codes USART Error Codes
+/** @defgroup USART_Error_Code USART Error Code
+ * @brief USART Error Code
* @{
*/
-#define HAL_USART_ERROR_NONE ((uint32_t)0x00) /*!< No error */
-#define HAL_USART_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
-#define HAL_USART_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
-#define HAL_USART_ERROR_FE ((uint32_t)0x04) /*!< frame error */
-#define HAL_USART_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
-#define HAL_USART_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
+#define HAL_USART_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_USART_ERROR_PE 0x00000001U /*!< Parity error */
+#define HAL_USART_ERROR_NE 0x00000002U /*!< Noise error */
+#define HAL_USART_ERROR_FE 0x00000004U /*!< Frame error */
+#define HAL_USART_ERROR_ORE 0x00000008U /*!< Overrun error */
+#define HAL_USART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
/**
* @}
*/
@@ -171,8 +168,8 @@
/** @defgroup USART_Word_Length USART Word Length
* @{
*/
-#define USART_WORDLENGTH_8B ((uint32_t)0x00000000)
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
+#define USART_WORDLENGTH_8B 0x00000000U
+#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
/**
* @}
*/
@@ -180,10 +177,10 @@
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{
*/
-#define USART_STOPBITS_1 ((uint32_t)0x00000000)
-#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
-#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
-#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
+#define USART_STOPBITS_1 0x00000000U
+#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
+#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
+#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
/**
* @}
*/
@@ -191,9 +188,9 @@
/** @defgroup USART_Parity USART Parity
* @{
*/
-#define USART_PARITY_NONE ((uint32_t)0x00000000)
-#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+#define USART_PARITY_NONE 0x00000000U
+#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
+#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
* @}
*/
@@ -201,10 +198,9 @@
/** @defgroup USART_Mode USART Mode
* @{
*/
-#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
-#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
-#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-
+#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
+#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
+#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
/**
* @}
*/
@@ -212,8 +208,8 @@
/** @defgroup USART_Clock USART Clock
* @{
*/
-#define USART_CLOCK_DISABLE ((uint32_t)0x00000000)
-#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
+#define USART_CLOCK_DISABLE 0x00000000U
+#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
/**
* @}
*/
@@ -221,8 +217,8 @@
/** @defgroup USART_Clock_Polarity USART Clock Polarity
* @{
*/
-#define USART_POLARITY_LOW ((uint32_t)0x00000000)
-#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
+#define USART_POLARITY_LOW 0x00000000U
+#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
/**
* @}
*/
@@ -230,8 +226,8 @@
/** @defgroup USART_Clock_Phase USART Clock Phase
* @{
*/
-#define USART_PHASE_1EDGE ((uint32_t)0x00000000)
-#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
+#define USART_PHASE_1EDGE 0x00000000U
+#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
/**
* @}
*/
@@ -239,8 +235,8 @@
/** @defgroup USART_Last_Bit USART Last Bit
* @{
*/
-#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000)
-#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
+#define USART_LASTBIT_DISABLE 0x00000000U
+#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
/**
* @}
*/
@@ -248,8 +244,8 @@
/** @defgroup USART_NACK_State USART NACK State
* @{
*/
-#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
-#define USART_NACK_DISABLE ((uint32_t)0x00000000)
+#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
+#define USART_NACK_DISABLE 0x00000000U
/**
* @}
*/
@@ -259,9 +255,6 @@
* - 0xXXXX : Flag mask in the SR register
* @{
*/
-
-#define USART_FLAG_CTS ((uint32_t)USART_SR_CTS)
-#define USART_FLAG_LBD ((uint32_t)USART_SR_LBD)
#define USART_FLAG_TXE ((uint32_t)USART_SR_TXE)
#define USART_FLAG_TC ((uint32_t)USART_SR_TC)
#define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
@@ -276,27 +269,25 @@
/** @defgroup USART_Interrupt_definition USART Interrupts Definition
* Elements values convention: 0xY000XXXX
- * - XXXX : Interrupt mask (16 bits) in the Y register
- * - Y : Interrupt source register (4bits)
- * - 0001: CR1 register
- * - 0010: CR2 register
- * - 0011: CR3 register
+ * - XXXX : Interrupt mask in the XX register
+ * - Y : Interrupt source register (2bits)
+ * - 01: CR1 register
+ * - 10: CR2 register
+ * - 11: CR3 register
*
* @{
*/
-#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_PEIE))
-#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE))
-#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TCIE))
-#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE))
-#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE))
+#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE))
+#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
-#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE))
-#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_EIE))
-
-
+#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
+#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
/**
* @}
*/
@@ -305,21 +296,18 @@
* @}
*/
-
/* Exported macro ------------------------------------------------------------*/
/** @defgroup USART_Exported_Macros USART Exported Macros
* @{
*/
-
/** @brief Reset USART handle state
* @param __HANDLE__: specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
*/
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
-/** @brief Check whether the specified USART flag is set or not.
+/** @brief Checks whether the specified USART flag is set or not.
* @param __HANDLE__: specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __FLAG__: specifies the flag to check.
@@ -334,10 +322,9 @@
* @arg USART_FLAG_PE: Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-/** @brief Clear the specified USART pending flags.
+/** @brief Clears the specified USART pending flags.
* @param __HANDLE__: specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __FLAG__: specifies the flag to check.
@@ -345,62 +332,56 @@
* @arg USART_FLAG_TC: Transmission Complete flag.
* @arg USART_FLAG_RXNE: Receive data register not empty flag.
*
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) flags are cleared by software
+ * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
+ * error) and IDLE (Idle line detected) flags are cleared by software
* sequence: a read operation to USART_SR register followed by a read
* operation to USART_DR register.
* @note RXNE flag can be also cleared by a read to the USART_DR register.
- * @note TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register followed by a write operation to USART_DR register.
- * @note TXE flag is cleared only by a write to the USART_DR register.
+ * @note TC flag can be also cleared by software sequence: a read operation to
+ * USART_SR register followed by a write operation to USART_DR register
+ * @note TXE flag is cleared only by a write to the USART_DR register
*
- * @retval None
*/
-#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Clear the USART PE pending flag.
* @param __HANDLE__: specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
*/
-#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
-do{ \
- __IO uint32_t tmpreg; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- UNUSED(tmpreg); \
-}while(0)
-
+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
+ do{ \
+ __IO uint32_t tmpreg = 0x00U; \
+ tmpreg = (__HANDLE__)->Instance->SR; \
+ tmpreg = (__HANDLE__)->Instance->DR; \
+ UNUSED(tmpreg); \
+ } while(0U)
/** @brief Clear the USART FE pending flag.
* @param __HANDLE__: specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
*/
#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the USART NE pending flag.
* @param __HANDLE__: specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
*/
#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the USART ORE pending flag.
* @param __HANDLE__: specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
+
*/
#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the USART IDLE pending flag.
* @param __HANDLE__: specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
*/
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-/** @brief Enable the specified Usart interrupts.
+/** @brief Enable the specified USART interrupts.
* @param __HANDLE__: specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __INTERRUPT__: specifies the USART interrupt source to enable.
@@ -411,14 +392,13 @@
* @arg USART_IT_IDLE: Idle line detection interrupt
* @arg USART_IT_PE: Parity Error interrupt
* @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @retval None
+ * This parameter can be: ENABLE or DISABLE.
*/
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
-
-/** @brief Disable the specified Usart interrupts.
+/** @brief Disable the specified USART interrupts.
* @param __HANDLE__: specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __INTERRUPT__: specifies the USART interrupt source to disable.
@@ -429,15 +409,13 @@
* @arg USART_IT_IDLE: Idle line detection interrupt
* @arg USART_IT_PE: Parity Error interrupt
* @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @retval None
+ * This parameter can be: ENABLE or DISABLE.
*/
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
- (((__INTERRUPT__) >> 28) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
-
-
-/** @brief Check whether the specified Usart interrupt has occurred or not.
+/** @brief Checks whether the specified USART interrupt has occurred or not.
* @param __HANDLE__: specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @param __IT__: specifies the USART interrupt source to check.
@@ -450,113 +428,43 @@
* @arg USART_IT_PE: Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == USART_CR2_REG_INDEX)? \
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
/** @brief Enable USART
* @param __HANDLE__: specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
- */
+ */
#define __HAL_USART_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
/** @brief Disable USART
* @param __HANDLE__: specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @retval None
*/
#define __HAL_USART_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
-
-
/**
* @}
*/
-
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup USART_Private_Macros USART Private Macros
- * @{
- */
-
-#define USART_CR1_REG_INDEX 1
-#define USART_CR2_REG_INDEX 2
-#define USART_CR3_REG_INDEX 3
-
-#define USART_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__)))
-#define USART_DIVMANT(__PCLK__, __BAUD__) (USART_DIV((__PCLK__), (__BAUD__))/100)
-#define USART_DIVFRAQ(__PCLK__, __BAUD__) (((USART_DIV((__PCLK__), (__BAUD__)) - (USART_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100)
-#define USART_BRR(__PCLK__, __BAUD__) ((USART_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(USART_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F))
-
-/** Check USART Baud rate
- * __BAUDRATE__: Baudrate specified by the user
- * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 72 MHz)
- * divided by the smallest oversampling used on the USART (i.e. 16)
- * return : TRUE or FALSE
- */
-#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001)
-
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
- ((LENGTH) == USART_WORDLENGTH_9B))
-
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
- ((STOPBITS) == USART_STOPBITS_0_5) || \
- ((STOPBITS) == USART_STOPBITS_1_5) || \
- ((STOPBITS) == USART_STOPBITS_2))
-
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
- ((PARITY) == USART_PARITY_EVEN) || \
- ((PARITY) == USART_PARITY_ODD))
-
-#define IS_USART_MODE(MODE) ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00) && ((MODE) != (uint32_t)0x00000000))
-
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
- ((CLOCK) == USART_CLOCK_ENABLE))
-
-#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
-
-#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
-
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
- ((LASTBIT) == USART_LASTBIT_ENABLE))
-
-#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
- ((NACK) == USART_NACK_DISABLE))
-
-/** USART interruptions flag mask
- *
- */
-#define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \
- USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE )
-
-/**
- * @}
- */
-
-
/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup USART_Exported_Functions USART Exported Functions
- * @{
- */
-
-/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @addtogroup USART_Exported_Functions
* @{
*/
-/* Initialization and de-initialization functions ******************************/
+/** @addtogroup USART_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
void HAL_USART_MspInit(USART_HandleTypeDef *husart);
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
-
/**
* @}
*/
-/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
+/** @addtogroup USART_Exported_Functions_Group2
* @{
*/
-
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
@@ -570,6 +478,10 @@
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
+
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
@@ -577,24 +489,90 @@
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
-
+void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
/**
* @}
*/
-/* Peripheral Control functions ***********************************************/
-
-/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
+/** @addtogroup USART_Exported_Functions_Group3
* @{
*/
-
-/* Peripheral State and Error functions ***************************************/
+/* Peripheral State functions ************************************************/
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
+/**
+ * @}
+ */
/**
* @}
*/
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_Private_Constants USART Private Constants
+ * @{
+ */
+/** @brief USART interruptions flag mask
+ *
+ */
+#define USART_IT_MASK 0x0000FFFFU
+
+#define USART_CR1_REG_INDEX 1U
+#define USART_CR2_REG_INDEX 2U
+#define USART_CR3_REG_INDEX 3U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup USART_Private_Macros USART Private Macros
+ * @{
+ */
+#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
+ ((NACK) == USART_NACK_DISABLE))
+
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
+ ((LASTBIT) == USART_LASTBIT_ENABLE))
+
+#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
+
+#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
+
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
+ ((CLOCK) == USART_CLOCK_ENABLE))
+
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
+ ((LENGTH) == USART_WORDLENGTH_9B))
+
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
+ ((STOPBITS) == USART_STOPBITS_0_5) || \
+ ((STOPBITS) == USART_STOPBITS_1_5) || \
+ ((STOPBITS) == USART_STOPBITS_2))
+
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
+ ((PARITY) == USART_PARITY_EVEN) || \
+ ((PARITY) == USART_PARITY_ODD))
+
+#define IS_USART_MODE(MODE) ((((MODE) & 0xFFF3U) == 0x00U) && ((MODE) != 0x00U))
+
+#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
+
+#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
+
+#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
+
+#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
+
+#define USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup USART_Private_Functions USART Private Functions
+ * @{
+ */
/**
* @}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_wwdg.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_wwdg.h
index ce12cf6..c19d67a 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_wwdg.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_hal_wwdg.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_wwdg.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
@@ -55,54 +55,39 @@
*/
/* Exported types ------------------------------------------------------------*/
-
/** @defgroup WWDG_Exported_Types WWDG Exported Types
* @{
*/
-/**
- * @brief WWDG HAL State Structure definition
- */
-typedef enum
-{
- HAL_WWDG_STATE_RESET = 0x00, /*!< WWDG not yet initialized or disabled */
- HAL_WWDG_STATE_READY = 0x01, /*!< WWDG initialized and ready for use */
- HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */
- HAL_WWDG_STATE_TIMEOUT = 0x03, /*!< WWDG timeout state */
- HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */
-}HAL_WWDG_StateTypeDef;
-
/**
- * @brief WWDG Init structure definition
- */
+ * @brief WWDG Init structure definition
+ */
typedef struct
{
- uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
- This parameter can be a value of @ref WWDG_Prescaler */
-
- uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
- This parameter must be a number lower than Max_Data = 0x80 */
-
- uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
- This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+ uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
+ This parameter can be a value of @ref WWDG_Prescaler */
+
+ uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
+ This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
+
+ uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
+ This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
+
+ uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
+ This parameter can be a value of @ref WWDG_EWI_Mode */
}WWDG_InitTypeDef;
-/**
- * @brief WWDG handle Structure definition
- */
+/**
+ * @brief WWDG handle Structure definition
+ */
typedef struct
{
WWDG_TypeDef *Instance; /*!< Register base address */
-
- WWDG_InitTypeDef Init; /*!< WWDG required parameters */
-
- HAL_LockTypeDef Lock; /*!< WWDG locking object */
-
- __IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */
-
-}WWDG_HandleTypeDef;
+ WWDG_InitTypeDef Init; /*!< WWDG required parameters */
+
+}WWDG_HandleTypeDef;
/**
* @}
*/
@@ -115,8 +100,8 @@
/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
* @{
- */
-#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
+ */
+#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
/**
* @}
*/
@@ -124,8 +109,8 @@
/** @defgroup WWDG_Flag_definition WWDG Flag definition
* @brief WWDG Flag definition
* @{
- */
-#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
+ */
+#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
/**
* @}
*/
@@ -133,33 +118,43 @@
/** @defgroup WWDG_Prescaler WWDG Prescaler
* @{
*/
-#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
+ * @{
+ */
+#define WWDG_EWI_DISABLE 0x00000000U /*!< EWI Disable */
+#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
+/**
+ * @}
+ */
/**
* @}
- */
-
-/**
- * @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
/** @defgroup WWDG_Private_Macros WWDG Private Macros
* @{
*/
-#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
- ((__PRESCALER__) == WWDG_PRESCALER_2) || \
- ((__PRESCALER__) == WWDG_PRESCALER_4) || \
- ((__PRESCALER__) == WWDG_PRESCALER_8))
+#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_2) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_4) || \
+ ((__PRESCALER__) == WWDG_PRESCALER_8))
-#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
+#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
-
-#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
+#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
+
+#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
+ ((__MODE__) == WWDG_EWI_DISABLE))
/**
* @}
*/
@@ -171,55 +166,28 @@
* @{
*/
-/** @brief Reset WWDG handle state
- * @param __HANDLE__: WWDG handle
- * @retval None
- */
-#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
-
/**
* @brief Enables the WWDG peripheral.
* @param __HANDLE__: WWDG handle
* @retval None
*/
-#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
-
-/**
- * @brief Disables the WWDG peripheral.
- * @param __HANDLE__: WWDG handle
- * @note WARNING: This is a dummy macro for HAL code alignment.
- * Once enable, WWDG Peripheral cannot be disabled except by a system reset.
- * @retval None
- */
-#define __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */
+#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
/**
* @brief Enables the WWDG early wakeup interrupt.
* @param __HANDLE__: WWDG handle
- * @param __INTERRUPT__: specifies the interrupt to enable.
+ * @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
* @note Once enabled this interrupt cannot be disabled except by a system reset.
* @retval None
*/
-#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
/**
- * @brief Disables the WWDG early wakeup interrupt.
- * @param __HANDLE__: WWDG handle
- * @param __INTERRUPT__: specifies the interrupt to disable.
- * This parameter can be one of the following values:
- * @arg WWDG_IT_EWI: Early wakeup interrupt
- * @note WARNING: This is a dummy macro for HAL code alignment.
- * Once enabled this interrupt cannot be disabled except by a system reset.
- * @retval None
- */
-#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */
-
-/**
- * @brief Gets the selected WWDG's it status.
- * @param __HANDLE__: WWDG handle
- * @param __INTERRUPT__: specifies the it to check.
+ * @brief Checks whether the selected WWDG interrupt has occurred or not.
+ * @param __HANDLE__ WWDG handle
+ * @param __INTERRUPT__ specifies the it to check.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
* @retval The new state of WWDG_FLAG (SET or RESET).
@@ -236,9 +204,9 @@
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
/**
- * @brief Gets the selected WWDG's flag status.
- * @param __HANDLE__: WWDG handle
- * @param __FLAG__: specifies the flag to check.
+ * @brief Check whether the specified WWDG flag is set or not.
+ * @param __HANDLE__ WWDG handle
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval The new state of WWDG_FLAG (SET or RESET).
@@ -253,7 +221,7 @@
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval None
*/
-#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
/** @brief Checks if the specified WWDG interrupt source is enabled or disabled.
* @param __HANDLE__: WWDG Handle.
@@ -266,10 +234,9 @@
/**
* @}
- */
+ */
/* Exported functions --------------------------------------------------------*/
-
/** @addtogroup WWDG_Exported_Functions
* @{
*/
@@ -278,51 +245,35 @@
* @{
*/
/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
-HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
-
+HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/**
* @}
*/
-
+
/** @addtogroup WWDG_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
-HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
-void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
+void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
+/**
+ * @}
+ */
/**
* @}
*/
-/** @addtogroup WWDG_Exported_Functions_Group3
- * @{
+/**
+ * @}
*/
-/* Peripheral State functions **************************************************/
-HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
/**
* @}
- */
+ */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
#ifdef __cplusplus
}
#endif
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_adc.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_adc.h
new file mode 100644
index 0000000..b0c7a49
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_adc.h
@@ -0,0 +1,3950 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_adc.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of ADC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_ADC_H
+#define __STM32F1xx_LL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC3)
+
+/** @defgroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+ * @{
+ */
+
+/* Internal mask for ADC group regular sequencer: */
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
+/* - sequencer register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group regular sequencer configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SQR1_REGOFFSET 0x00000000U
+#define ADC_SQR2_REGOFFSET 0x00000100U
+#define ADC_SQR3_REGOFFSET 0x00000200U
+#define ADC_SQR4_REGOFFSET 0x00000300U
+
+#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group regular sequencer bits information to be inserted */
+/* into ADC group regular sequencer ranks literals definition. */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
+
+/* Internal mask for ADC group injected sequencer: */
+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
+/* - data register offset */
+/* - offset register offset */
+/* - sequencer rank bits position into the selected register */
+
+/* Internal register offset for ADC group injected data register */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JDR1_REGOFFSET 0x00000000U
+#define ADC_JDR2_REGOFFSET 0x00000100U
+#define ADC_JDR3_REGOFFSET 0x00000200U
+#define ADC_JDR4_REGOFFSET 0x00000300U
+
+/* Internal register offset for ADC group injected offset configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JOFR1_REGOFFSET 0x00000000U
+#define ADC_JOFR2_REGOFFSET 0x00001000U
+#define ADC_JOFR3_REGOFFSET 0x00002000U
+#define ADC_JOFR4_REGOFFSET 0x00003000U
+
+#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
+#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Internal mask for ADC channel: */
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
+/* - channel identifier defined by number */
+/* - channel differentiation between external channels (connected to */
+/* GPIO pins) and internal channels (connected to internal paths) */
+/* - channel sampling time defined by SMPRx register offset */
+/* and SMPx bits positions into SMPRx register */
+#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
+#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
+
+/* Channel differentiation between external and internal channels */
+#define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
+
+/* Internal register offset for ADC channel sampling time configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SMPR1_REGOFFSET 0x00000000U
+#define ADC_SMPR2_REGOFFSET 0x02000000U
+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
+
+/* Definition of channels ID number information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_NUMBER 0x00000000U
+#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
+#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
+#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
+#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
+#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
+#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
+#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
+
+/* Definition of channels sampling time information to be inserted into */
+/* channels literals definition. */
+#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
+#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
+#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
+#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
+#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
+#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
+#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
+#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
+#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
+#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
+#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
+#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
+#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
+#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
+#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
+#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
+#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
+#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
+
+/* Internal mask for ADC analog watchdog: */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
+/* (concatenation of multiple bits used in different analog watchdogs, */
+/* (feature of several watchdogs not available on all STM32 families)). */
+/* - analog watchdog 1: monitored channel defined by number, */
+/* selection of ADC group (ADC groups regular and-or injected). */
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET 0x00000000U
+
+#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
+
+#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
+#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
+#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
+
+/* ADC registers bits positions */
+#define ADC_CR1_DUALMOD_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: isolate bits with the
+ * selected mask and shift them to the register LSB
+ * (shift mask on register position bit 0).
+ * @param __BITS__ Bits in register 32 bits
+ * @param __MASK__ Mask in register 32 bits
+ * @retval Bits in register 32 bits
+ */
+#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
+ (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Pointer to register address
+ */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of ADC common parameters
+ * and multimode
+ * (all ADC instances belonging to the same ADC common instance).
+ * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
+ * is conditioned to ADC instances state (all ADC instances
+ * sharing the same ADC common instance):
+ * All ADC instances sharing the same ADC common instance must be
+ * disabled.
+ */
+typedef struct
+{
+ uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
+ This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
+} LL_ADC_CommonInitTypeDef;
+/**
+ * @brief Structure definition of some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
+ This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
+
+ uint32_t SequencersScanMode; /*!< Set ADC scan selection.
+ This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
+ This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+ @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
+ (only trigger polarity available on this STM32 serie).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+ @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group regular sequencer is enabled
+ (scan length of 2 ranks or more).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
+ This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
+ Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
+
+ uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
+ This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+ * @brief Structure definition of some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
+ @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
+ (only trigger polarity available on this STM32 serie).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
+
+ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
+ @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
+
+ uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
+ @note This parameter has an effect only if group injected sequencer is enabled
+ (scan length of 2 ranks or more).
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
+
+ uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
+ This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
+ Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
+
+ This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
+
+} LL_ADC_INJ_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+ * @{
+ */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+ * @brief Flags defines which can be used with LL_ADC_ReadReg function
+ * @{
+ */
+#define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
+#define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
+#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
+#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_FLAG_EOS_MST ADC_SR_EOC /*!< ADC flag ADC multimode master group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
+#define LL_ADC_FLAG_EOS_SLV ADC_SR_EOC /*!< ADC flag ADC multimode slave group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */
+#define LL_ADC_FLAG_JEOS_MST ADC_SR_JEOC /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_FLAG_JEOS_SLV ADC_SR_JEOC /*!< ADC flag ADC multimode slave group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */
+#define LL_ADC_FLAG_AWD1_MST ADC_SR_AWD /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
+#define LL_ADC_FLAG_AWD1_SLV ADC_SR_AWD /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave (on STM32F1, this flag must be read from ADC instance slave: ADC2) */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+ * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
+ * @{
+ */
+#define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
+#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
+#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
+ * @{
+ */
+/* List of ADC registers intended to be used (most commonly) with */
+/* DMA transfer. */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
+#define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
+ * @{
+ */
+/* Note: Other measurement paths to internal channels may be available */
+/* (connections to other peripherals). */
+/* If they are not listed below, they do not require any specific */
+/* path enable. In this case, Access to measurement path is done */
+/* only by selecting the corresponding ADC internal channel. */
+#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
+ * @{
+ */
+#define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
+ * @{
+ */
+#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
+ * @{
+ */
+#define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
+#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
+ * @{
+ */
+#define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
+ * @{
+ */
+#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
+#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
+#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
+#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
+#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
+#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
+#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
+#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
+#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
+#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
+#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
+#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
+#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
+#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
+#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
+#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
+#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
+#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
+#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F1, ADC channel available only on ADC instance: ADC1. */
+#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
+ * @{
+ */
+/* ADC group regular external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */
+#define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+/* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 0x00000000U /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
+/* XL-density devices. */
+/* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */
+/* A remap of trigger must be done at top level (refer to */
+/* AFIO peripheral). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).*/
+#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#if defined (STM32F103xE) || defined (STM32F103xG)
+/* ADC group regular external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
+ * @{
+ */
+#define LL_ADC_REG_TRIG_EXT_RISING ADC_CR2_EXTTRIG /*!< ADC group regular conversion trigger polarity set to rising edge */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
+* @{
+*/
+#define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
+ * @{
+ */
+#define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
+#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
+#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
+#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
+#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
+#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
+#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
+#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
+#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
+#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
+ * @{
+ */
+/* ADC group injected external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */
+#define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger internal: SW start. */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 0x00000000U /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+/* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+/* Note: TIM8_CH4 is available on ADC1 and ADC2 only in high-density and */
+/* XL-density devices. */
+/* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */
+/* A remap of trigger must be done at top level (refer to */
+/* AFIO peripheral). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). */
+#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
+#if defined (STM32F103xE) || defined (STM32F103xG)
+/* ADC group injected external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
+#endif
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
+ * @{
+ */
+#define LL_ADC_INJ_TRIG_EXT_RISING ADC_CR2_JEXTTRIG /*!< ADC group injected conversion trigger polarity set to rising edge */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
+* @{
+*/
+#define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
+/**
+ * @}
+ */
+
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
+ * @{
+ */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */
+#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
+ * @{
+ */
+#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */
+#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */
+#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */
+#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
+ * @{
+ */
+#define LL_ADC_SAMPLINGTIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */
+#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 28.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0) /*!< Sampling time 55.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1) /*!< Sampling time 71.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 239.5 ADC clock cycles */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+ * @{
+ */
+#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
+ * @{
+ */
+#define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
+#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
+#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
+ * @{
+ */
+#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
+/**
+ * @}
+ */
+
+#if !defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
+ * @{
+ */
+#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
+/**
+ * @}
+ */
+#endif
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
+ * @{
+ */
+#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
+#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES" on other STM32 devices)) */
+#define LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */
+#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected simultaneous slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */
+#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
+#define LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) + group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) + group injected simultaneous */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
+ * @{
+ */
+#define LL_ADC_MULTI_MASTER ( ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: ADC master */
+#define LL_ADC_MULTI_SLAVE (ADC_DR_ADC2DATA ) /*!< In multimode, selection among several ADC instances: ADC slave */
+#define LL_ADC_MULTI_MASTER_SLAVE (ADC_DR_ADC2DATA | ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
+/**
+ * @}
+ */
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+
+/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
+ * @note Only ADC IP HW delays are defined in ADC LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
+/* not timeout values. */
+/* Timeout values for ADC operations are dependent to device clock */
+/* configuration (system clock versus ADC clock), */
+/* and therefore must be defined in user application. */
+/* Indications for estimation of ADC timeout delays, for this */
+/* STM32 serie: */
+/* - ADC enable time: maximum delay is 1us */
+/* (refer to device datasheet, parameter "tSTAB") */
+/* - ADC conversion time: duration depending on ADC clock and ADC */
+/* configuration. */
+/* (refer to device reference manual, section "Timing") */
+
+/* Delay for temperature sensor stabilization time. */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSTART"). */
+/* Unit: us */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (10U) /*!< Delay for internal voltage reference stabilization time */
+
+/* Delay required between ADC disable and ADC calibration start. */
+/* Note: On this STM32 serie, before starting a calibration, */
+/* ADC must be disabled. */
+/* A minimum number of ADC clock cycles are required */
+/* between ADC disable state and calibration start. */
+/* Refer to literal @ref LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES. */
+/* Wait time can be computed in user application by waiting for the */
+/* equivalent number of CPU cycles, by taking into account */
+/* ratio of CPU clock versus ADC clock prescalers. */
+/* Unit: ADC clock cycles. */
+#define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between ADC disable and ADC calibration start */
+
+/* Delay required between end of ADC Enable and the start of ADC calibration. */
+/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
+/* are required between the end of ADC enable and the start of ADC */
+/* calibration. */
+/* Wait time can be computed in user application by waiting for the */
+/* equivalent number of CPU cycles, by taking into account */
+/* ratio of CPU clock versus ADC clock prescalers. */
+/* Unit: ADC clock cycles. */
+#define LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between end of ADC enable and the start of ADC calibration */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+ * @{
+ */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in ADC register
+ * @param __INSTANCE__ ADC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get ADC channel number in decimal format
+ * from literals LL_ADC_CHANNEL_x.
+ * @note Example:
+ * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+ * will return decimal number "4".
+ * @note The input can be a value from functions where a channel
+ * number is returned, either defined with number
+ * or with bitfield (only one bit must be set).
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F1, parameter available only on ADC instance: ADC1.
+ * @retval Value between Min_Data=0 and Max_Data=18
+ */
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+
+/**
+ * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+ * from number in decimal format.
+ * @note Example:
+ * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+ * will return a data equivalent to "LL_ADC_CHANNEL_4".
+ * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) <= 9U) \
+ ? ( \
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ ) \
+ : \
+ ( \
+ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
+ (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
+ ) \
+ )
+
+/**
+ * @brief Helper macro to determine whether the selected channel
+ * corresponds to literal definitions of driver.
+ * @note The different literal definitions of ADC channels are:
+ * - ADC internal channel:
+ * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+ * - ADC external channel (channel connected to a GPIO pin):
+ * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+ * @note The channel parameter must be a value defined from literal
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+ * must not be a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F1, parameter available only on ADC instance: ADC1.
+ * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
+ * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+ */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
+
+/**
+ * @brief Helper macro to convert a channel defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * to its equivalent parameter definition of a ADC external channel
+ * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+ * @note The channel parameter can be, additionally to a value
+ * defined from parameter definition of a ADC internal channel
+ * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is returned
+ * from ADC registers.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F1, parameter available only on ADC instance: ADC1.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
+ ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+
+/**
+ * @brief Helper macro to determine whether the internal channel
+ * selected is available on the ADC instance selected.
+ * @note The channel parameter must be a value defined from parameter
+ * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+ * LL_ADC_CHANNEL_TEMPSENSOR, ...),
+ * must not be a value defined from parameter definition of
+ * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+ * or a value from functions where a channel number is
+ * returned from ADC registers,
+ * because internal and external channels share the same channel
+ * number in ADC registers. The differentiation is made only with
+ * parameters definitions of driver.
+ * @param __ADC_INSTANCE__ ADC instance
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F1, parameter available only on ADC instance: ADC1.
+ * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+ * Value "1" if the internal channel selected is available on the ADC instance selected.
+ */
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
+ (((__ADC_INSTANCE__) == ADC1) \
+ ? ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
+ ) \
+ : \
+ (0U) \
+ )
+
+/**
+ * @brief Helper macro to define ADC analog watchdog parameter:
+ * define a single channel to monitor with analog watchdog
+ * from sequencer channel and groups definition.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+ * Example:
+ * LL_ADC_SetAnalogWDMonitChannels(
+ * ADC1, LL_ADC_AWD1,
+ * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ * @param __GROUP__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_GROUP_REGULAR
+ * @arg @ref LL_ADC_GROUP_INJECTED
+ * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
+ *
+ * (1) On STM32F1, parameter available only on ADC instance: ADC1.
+ */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
+ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
+ : \
+ ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
+ ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
+ : \
+ (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
+ )
+
+/**
+ * @brief Helper macro to set the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 12 bits.
+ * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to set the value of
+ * analog watchdog threshold high (on 8 bits):
+ * LL_ADC_SetAnalogWDThresholds
+ * (< ADCx param >,
+ * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
+/* This macro has been kept anyway for compatibility with other */
+/* STM32 families featuring different ADC resolutions. */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+ ((__AWD_THRESHOLD__) << (0U))
+
+/**
+ * @brief Helper macro to get the value of ADC analog watchdog threshold high
+ * or low in function of ADC resolution, when ADC resolution is
+ * different of 12 bits.
+ * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+ * Example, with a ADC resolution of 8 bits, to get the value of
+ * analog watchdog threshold high (on 8 bits):
+ * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+ * (LL_ADC_RESOLUTION_8B,
+ * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
+ * );
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
+/* This macro has been kept anyway for compatibility with other */
+/* STM32 families featuring different ADC resolutions. */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
+ (__AWD_THRESHOLD_12_BITS__)
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Helper macro to get the ADC multimode conversion data of ADC master
+ * or ADC slave from raw value with both ADC conversion data concatenated.
+ * @note This macro is intended to be used when multimode transfer by DMA
+ * is enabled.
+ * In this case the transferred data need to processed with this macro
+ * to separate the conversion data of ADC master and ADC slave.
+ * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
+ (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_DR_DATA)
+#endif
+
+/**
+ * @brief Helper macro to select the ADC common instance
+ * to which is belonging the selected ADC instance.
+ * @note ADC common register instance can be used for:
+ * - Set parameters common to several ADC instances
+ * - Multimode (for devices with several ADC instances)
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On STM32F1, there is no common ADC instance.
+ * However, ADC instance ADC1 has a role of common ADC instance
+ * for ADC1 and ADC2:
+ * this instance is used to manage internal channels
+ * and multimode (these features are managed in ADC common
+ * instances on some other STM32 devices).
+ * ADC instance ADC3 (if available on the selected device)
+ * has no ADC common instance.
+ * @param __ADCx__ ADC instance
+ * @retval ADC common register instance
+ */
+#if defined(ADC1) && defined(ADC2) && defined(ADC3)
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
+ ? ( \
+ (ADC12_COMMON) \
+ ) \
+ : \
+ ( \
+ (0U) \
+ ) \
+ )
+#elif defined(ADC1) && defined(ADC2)
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ (ADC12_COMMON)
+#else
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
+ (ADC1_COMMON)
+#endif
+
+/**
+ * @brief Helper macro to check if all ADC instances sharing the same
+ * ADC common instance are disabled.
+ * @note This check is required by functions with setting conditioned to
+ * ADC state:
+ * All ADC instances of the ADC common group must be disabled.
+ * Refer to functions having argument "ADCxy_COMMON" as parameter.
+ * @note On devices with only 1 ADC common instance, parameter of this macro
+ * is useless and can be ignored (parameter kept for compatibility
+ * with devices featuring several ADC common instances).
+ * @note On STM32F1, there is no common ADC instance.
+ * However, ADC instance ADC1 has a role of common ADC instance
+ * for ADC1 and ADC2:
+ * this instance is used to manage internal channels
+ * and multimode (these features are managed in ADC common
+ * instances on some other STM32 devices).
+ * ADC instance ADC3 (if available on the selected device)
+ * has no ADC common instance.
+ * @param __ADCXY_COMMON__ ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Value "0" if all ADC instances sharing the same ADC common instance
+ * are disabled.
+ * Value "1" if at least one ADC instance sharing the same ADC common instance
+ * is enabled.
+ */
+#if defined(ADC1) && defined(ADC2) && defined(ADC3)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (((__ADCXY_COMMON__) == ADC12_COMMON) \
+ ? ( \
+ (LL_ADC_IsEnabled(ADC1) | \
+ LL_ADC_IsEnabled(ADC2) ) \
+ ) \
+ : \
+ ( \
+ LL_ADC_IsEnabled(ADC3) \
+ ) \
+ )
+#elif defined(ADC1) && defined(ADC2)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ (LL_ADC_IsEnabled(ADC1) | \
+ LL_ADC_IsEnabled(ADC2) )
+#else
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
+ LL_ADC_IsEnabled(ADC1)
+#endif
+
+/**
+ * @brief Helper macro to define the ADC conversion data full-scale digital
+ * value corresponding to the selected ADC resolution.
+ * @note ADC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ (0xFFFU)
+
+
+/**
+ * @brief Helper macro to calculate the voltage (unit: mVolt)
+ * corresponding to a ADC conversion data (unit: digital value).
+ * @note Analog reference voltage (Vref+) must be known from
+ * user board environment or can be calculated using ADC measurement.
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
+ * (unit: digital value).
+ * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+ __ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+ )
+
+
+/**
+ * @brief Helper macro to calculate the temperature (unit: degree Celsius)
+ * from ADC conversion data of internal temperature sensor.
+ * @note Computation is using temperature sensor typical values
+ * (refer to device datasheet).
+ * @note Calculation formula:
+ * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+ * / Avg_Slope + CALx_TEMP
+ * with TS_ADC_DATA = temperature sensor raw data measured by ADC
+ * (unit: digital value)
+ * Avg_Slope = temperature sensor slope
+ * (unit: uV/Degree Celsius)
+ * TS_TYP_CALx_VOLT = temperature sensor digital value at
+ * temperature CALx_TEMP (unit: mV)
+ * Caution: Calculation relevancy under reserve the temperature sensor
+ * of the current device has characteristics in line with
+ * datasheet typical values.
+ * If temperature sensor calibration values are available on
+ * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+ * temperature calculation will be more accurate using
+ * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+ * @note As calculation input, the analog reference voltage (Vref+) must be
+ * defined as it impacts the ADC LSB equivalent voltage.
+ * @note Analog reference voltage (Vref+) must be known from
+ * user board environment or can be calculated using ADC measurement.
+ * @note ADC measurement data must correspond to a resolution of 12bits
+ * (full scale digital value 4095). If not the case, the data must be
+ * preliminarily rescaled to an equivalent resolution of 12 bits.
+ * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
+ * On STM32F1, refer to device datasheet parameter "Avg_Slope".
+ * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
+ * On STM32F1, refer to device datasheet parameter "V25".
+ * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
+ * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
+ * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
+ * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
+ * This parameter can be one of the following values:
+ * @arg @ref LL_ADC_RESOLUTION_12B
+ * @retval Temperature (unit: degree Celsius)
+ */
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+ __TEMPSENSOR_TYP_CALX_V__,\
+ __TEMPSENSOR_CALX_TEMP__,\
+ __VREFANALOG_VOLTAGE__,\
+ __TEMPSENSOR_ADC_DATA__,\
+ __ADC_RESOLUTION__) \
+ ((( ( \
+ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
+ * 1000) \
+ - \
+ (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
+ * 1000) \
+ ) \
+ ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
+ ) + (__TEMPSENSOR_CALX_TEMP__) \
+ )
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+ * @{
+ */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+ * @{
+ */
+/* Note: LL ADC functions to set DMA transfer are located into sections of */
+/* configuration of ADC instance, groups and multimode (if available): */
+/* @ref LL_ADC_REG_SetDMATransfer(), ... */
+
+/**
+ * @brief Function to help to configure DMA transfer from ADC: retrieve the
+ * ADC register address from ADC instance and a list of ADC registers
+ * intended to be used (most commonly) with DMA transfer.
+ * @note These ADC registers are data registers:
+ * when ADC conversion data is available in ADC data registers,
+ * ADC generates a DMA transfer request.
+ * @note This macro is intended to be used with LL DMA driver, refer to
+ * function "LL_DMA_ConfigAddresses()".
+ * Example:
+ * LL_DMA_ConfigAddresses(DMA1,
+ * LL_DMA_CHANNEL_1,
+ * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+ * (uint32_t)&< array or variable >,
+ * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+ * @note For devices with several ADC: in multimode, some devices
+ * use a different data register outside of ADC instance scope
+ * (common data register). This macro manages this register difference,
+ * only ADC instance has to be set as parameter.
+ * @note On STM32F1, only ADC instances ADC1 and ADC3 have DMA transfer
+ * capability, not ADC2 (ADC2 and ADC3 instances not available on
+ * all devices).
+ * @note On STM32F1, multimode can be used only with ADC1 and ADC2, not ADC3.
+ * Therefore, the corresponding parameter of data transfer
+ * for multimode can be used only with ADC1 and ADC2.
+ * (ADC2 and ADC3 instances not available on all devices).
+ * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
+ * @param ADCx ADC instance
+ * @param Register This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+ * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
+ *
+ * (1) Available on devices with several ADC instances.
+ * @retval ADC register address
+ */
+#if defined(ADC_MULTIMODE_SUPPORT)
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+ register uint32_t data_reg_addr = 0U;
+
+ if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
+ {
+ /* Retrieve address of register DR */
+ data_reg_addr = (uint32_t)&(ADCx->DR);
+ }
+ else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
+ {
+ /* Retrieve address of register of multimode data */
+ data_reg_addr = (uint32_t)&(ADC12_COMMON->DR);
+ }
+
+ return data_reg_addr;
+}
+#else
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+{
+ /* Retrieve address of register DR */
+ return (uint32_t)&(ADCx->DR);
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
+ * @{
+ */
+
+/**
+ * @brief Set parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @note Stabilization time of measurement path to internal channel:
+ * After enabling internal paths, before starting ADC conversion,
+ * a delay is required for internal voltage reference and
+ * temperature sensor stabilization time.
+ * Refer to device datasheet.
+ * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+ * @note ADC internal channel sampling time constraint:
+ * For ADC conversion of internal channels,
+ * a sampling time minimum value is required.
+ * Refer to device datasheet.
+ * @rmtoll CR2 TSVREFE LL_ADC_SetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param PathInternal This parameter can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+ MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal);
+}
+
+/**
+ * @brief Get parameter common to several ADC: measurement path to internal
+ * channels (VrefInt, temperature sensor, ...).
+ * @note One or several values can be selected.
+ * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+ * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+ * @rmtoll CR2 TSVREFE LL_ADC_GetCommonPathInternalCh
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be a combination of the following values:
+ * @arg @ref LL_ADC_PATH_INTERNAL_NONE
+ * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+ * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Set ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
+ * @param ADCx ADC instance
+ * @param DataAlignment This parameter can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
+{
+ MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
+}
+
+/**
+ * @brief Get ADC conversion data alignment.
+ * @note Refer to reference manual for alignments formats
+ * dependencies to ADC resolutions.
+ * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+ * @arg @ref LL_ADC_DATA_ALIGN_LEFT
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
+}
+
+/**
+ * @brief Set ADC sequencers scan mode, for all ADC groups
+ * (group regular, group injected).
+ * @note According to sequencers scan mode :
+ * - If disabled: ADC conversion is performed in unitary conversion
+ * mode (one channel converted, that defined in rank 1).
+ * Configuration of sequencers of all ADC groups
+ * (sequencer scan length, ...) is discarded: equivalent to
+ * scan length of 1 rank.
+ * - If enabled: ADC conversions are performed in sequence conversions
+ * mode, according to configuration of sequencers of
+ * each ADC group (sequencer scan length, ...).
+ * Refer to function @ref LL_ADC_REG_SetSequencerLength()
+ * and to function @ref LL_ADC_INJ_SetSequencerLength().
+ * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
+ * @param ADCx ADC instance
+ * @param ScanMode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
+}
+
+/**
+ * @brief Get ADC sequencers scan mode, for all ADC groups
+ * (group regular, group injected).
+ * @note According to sequencers scan mode :
+ * - If disabled: ADC conversion is performed in unitary conversion
+ * mode (one channel converted, that defined in rank 1).
+ * Configuration of sequencers of all ADC groups
+ * (sequencer scan length, ...) is discarded: equivalent to
+ * scan length of 1 rank.
+ * - If enabled: ADC conversions are performed in sequence conversions
+ * mode, according to configuration of sequencers of
+ * each ADC group (sequencer scan length, ...).
+ * Refer to function @ref LL_ADC_REG_SetSequencerLength()
+ * and to function @ref LL_ADC_INJ_SetSequencerLength().
+ * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Set ADC group regular conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note On this STM32 serie, external trigger is set with trigger polarity:
+ * rising edge (only trigger polarity available on this STM32 serie).
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3)
+ *
+ * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
+ * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
+ * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
+ * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+/* Note: On this STM32 serie, ADC group regular external trigger edge */
+/* is used to perform a ADC conversion start. */
+/* This function does not set external trigger edge. */
+/* This feature is set using function */
+/* @ref LL_ADC_REG_StartConversionExtTrig(). */
+ MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note To determine whether group regular trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3)
+ * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3)
+ *
+ * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
+ * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
+ * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
+ * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL));
+}
+
+/**
+ * @brief Get ADC group regular conversion trigger source internal (SW start)
+ or external.
+ * @note In case of group regular trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_REG_GetTriggerSource().
+ * @rmtoll CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE));
+}
+
+
+/**
+ * @brief Set ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note On this STM32 serie, group regular sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group regular sequencer length and scan direction.
+ * @note Description of ADC group regular sequencer features:
+ * - For devices with sequencer fully configurable
+ * (function "LL_ADC_REG_SetSequencerRanks()" available):
+ * sequencer length and each rank affectation to a channel
+ * are configurable.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerRanks()".
+ * - For devices with sequencer not fully configurable
+ * (function "LL_ADC_REG_SetSequencerChannels()" available):
+ * sequencer length and each rank affectation to a channel
+ * are defined by channel number.
+ * This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence is
+ * defined by number of channels set in the sequence,
+ * rank of each channel is fixed by channel HW number.
+ * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from lowest channel number to
+ * highest channel number).
+ * Sequencer ranks are selected using
+ * function "LL_ADC_REG_SetSequencerChannels()".
+ * @note On this STM32 serie, group regular sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+ * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+}
+
+/**
+ * @brief Set ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @note It is not possible to enable both ADC auto-injected mode
+ * and ADC group regular sequencer discontinuous mode.
+ * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
+ * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group regular sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
+ * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+ * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
+}
+
+/**
+ * @brief Set ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note This function performs configuration of:
+ * - Channels ordering into each rank of scan sequence:
+ * whatever channel can be placed into whatever rank.
+ * @note On this STM32 serie, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
+ * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
+ * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
+ * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F1, parameter available only on ADC instance: ADC1.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register and register position depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+}
+
+/**
+ * @brief Get ADC group regular sequence: channel on the selected
+ * scan sequence rank.
+ * @note On this STM32 serie, ADC group regular sequencer is
+ * fully configurable: sequencer length and each rank
+ * affectation to a channel are configurable.
+ * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
+ * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
+ * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
+ * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_RANK_1
+ * @arg @ref LL_ADC_REG_RANK_2
+ * @arg @ref LL_ADC_REG_RANK_3
+ * @arg @ref LL_ADC_REG_RANK_4
+ * @arg @ref LL_ADC_REG_RANK_5
+ * @arg @ref LL_ADC_REG_RANK_6
+ * @arg @ref LL_ADC_REG_RANK_7
+ * @arg @ref LL_ADC_REG_RANK_8
+ * @arg @ref LL_ADC_REG_RANK_9
+ * @arg @ref LL_ADC_REG_RANK_10
+ * @arg @ref LL_ADC_REG_RANK_11
+ * @arg @ref LL_ADC_REG_RANK_12
+ * @arg @ref LL_ADC_REG_RANK_13
+ * @arg @ref LL_ADC_REG_RANK_14
+ * @arg @ref LL_ADC_REG_RANK_15
+ * @arg @ref LL_ADC_REG_RANK_16
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
+
+ return (uint32_t) (READ_BIT(*preg,
+ ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+ >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
+ );
+}
+
+/**
+ * @brief Set ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @note It is not possible to enable both ADC group regular
+ * continuous mode and sequencer discontinuous mode.
+ * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
+ * @param ADCx ADC instance
+ * @param Continuous This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+{
+ MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
+}
+
+/**
+ * @brief Get ADC continuous conversion mode on ADC group regular.
+ * @note Description of ADC continuous conversion mode:
+ * - single mode: one conversion per trigger
+ * - continuous mode: after the first trigger, following
+ * conversions launched successively automatically.
+ * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_CONV_SINGLE
+ * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
+}
+
+/**
+ * @brief Set ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer
+ * @param ADCx ADC instance
+ * @param DMATransfer This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+{
+ MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer);
+}
+
+/**
+ * @brief Get ADC group regular conversion data transfer: no transfer or
+ * transfer by DMA, and DMA requests mode.
+ * @note If transfer by DMA selected, specifies the DMA requests
+ * mode:
+ * - Limited mode (One shot mode): DMA transfer requests are stopped
+ * when number of DMA data transfers (number of
+ * ADC conversions) is reached.
+ * This ADC mode is intended to be used with DMA mode non-circular.
+ * - Unlimited mode: DMA transfer requests are unlimited,
+ * whatever number of DMA data transfers (number of
+ * ADC conversions).
+ * This ADC mode is intended to be used with DMA mode circular.
+ * @note If ADC DMA requests mode is set to unlimited and DMA is set to
+ * mode non-circular:
+ * when DMA transfers size will be reached, DMA will stop transfers of
+ * ADC conversions data ADC will raise an overrun error
+ * (overrun flag and interruption if enabled).
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_ADC_DMA_GetRegAddr().
+ * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+ * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Set ADC group injected conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note On this STM32 serie, external trigger is set with trigger polarity:
+ * rising edge (only trigger polarity available on this STM32 serie).
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource
+ * @param ADCx ADC instance
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3)
+ *
+ * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
+ * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
+ * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
+ * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+/* Note: On this STM32 serie, ADC group injected external trigger edge */
+/* is used to perform a ADC conversion start. */
+/* This function does not set external trigger edge. */
+/* This feature is set using function */
+/* @ref LL_ADC_INJ_StartConversionExtTrig(). */
+ MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source:
+ * internal (SW start) or from external IP (timer event,
+ * external interrupt line).
+ * @note To determine whether group injected trigger source is
+ * internal (SW start) or external, without detail
+ * of which peripheral is selected as external trigger,
+ * (equivalent to
+ * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+ * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3)
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3)
+ *
+ * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
+ * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
+ * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
+ * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL));
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger source internal (SW start)
+ or external
+ * @note In case of group injected trigger source set to external trigger,
+ * to determine which peripheral is selected as external trigger,
+ * use function @ref LL_ADC_INJ_GetTriggerSource.
+ * @rmtoll CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart
+ * @param ADCx ADC instance
+ * @retval Value "0" if trigger source external trigger
+ * Value "1" if trigger source SW start.
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE);
+}
+
+/**
+ * @brief Set ADC group injected sequencer length and scan direction.
+ * @note This function performs configuration of:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note On this STM32 serie, group injected sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
+ * @param ADCx ADC instance
+ * @param SequencerNbRanks This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+ MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+}
+
+/**
+ * @brief Get ADC group injected sequencer length and scan direction.
+ * @note This function retrieves:
+ * - Sequence length: Number of ranks in the scan sequence.
+ * - Sequence direction: Unless specified in parameters, sequencer
+ * scan direction is forward (from rank 1 to rank n).
+ * @note On this STM32 serie, group injected sequencer configuration
+ * is conditioned to ADC instance sequencer mode.
+ * If ADC instance sequencer mode is disabled, sequencers of
+ * all groups (group regular, group injected) can be configured
+ * but their execution is disabled (limited to rank 1).
+ * Refer to function @ref LL_ADC_SetSequencersScanMode().
+ * @note Sequencer disabled is equivalent to sequencer of 1 rank:
+ * ADC conversion on only 1 channel.
+ * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+ * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+}
+
+/**
+ * @brief Set ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
+ * @param ADCx ADC instance
+ * @param SeqDiscont This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
+}
+
+/**
+ * @brief Get ADC group injected sequencer discontinuous mode:
+ * sequence subdivided and scan conversions interrupted every selected
+ * number of ranks.
+ * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+ * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
+}
+
+/**
+ * @brief Set ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * TempSensor, ...), measurement paths to internal channels must be
+ * enabled separately.
+ * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F1, parameter available only on ADC instance: ADC1.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+ /* Set bits with content of parameter "Channel" with bits position */
+ /* in register depending on parameter "Rank". */
+ /* Parameters "Rank" and "Channel" are used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
+
+ MODIFY_REG(ADCx->JSQR,
+ ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
+ (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));
+}
+
+/**
+ * @brief Get ADC group injected sequence: channel on the selected
+ * sequence rank.
+ * @note Depending on devices and packages, some channels may not be available.
+ * Refer to device datasheet for channels availability.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
+ * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
+ * (1) For ADC channel read back from ADC register,
+ * comparison with internal channel parameter to be done
+ * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
+
+ return (uint32_t)(READ_BIT(ADCx->JSQR,
+ ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
+ >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
+ );
+}
+
+/**
+ * @brief Set ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @note This mode can be used to extend number of data registers
+ * updated after one ADC conversion trigger and with data
+ * permanently kept (not erased by successive conversions of scan of
+ * ADC sequencer ranks), up to 5 data registers:
+ * 1 data register on ADC group regular, 4 data registers
+ * on ADC group injected.
+ * @note If ADC group injected injected trigger source is set to an
+ * external trigger, this feature must be must be set to
+ * independent trigger.
+ * ADC group injected automatic trigger is compliant only with
+ * group injected trigger source set to SW start, without any
+ * further action on ADC group injected conversion start or stop:
+ * in this case, ADC group injected is controlled only
+ * from ADC group regular.
+ * @note It is not possible to enable both ADC group injected
+ * auto-injected mode and sequencer discontinuous mode.
+ * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
+ * @param ADCx ADC instance
+ * @param TrigAuto This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
+{
+ MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
+}
+
+/**
+ * @brief Get ADC group injected conversion trigger:
+ * independent or from ADC group regular.
+ * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+ * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
+}
+
+/**
+ * @brief Set ADC group injected offset.
+ * @note It sets:
+ * - ADC group injected rank to which the offset programmed
+ * will be applied
+ * - Offset level (offset to be subtracted from the raw
+ * converted data).
+ * Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @note Offset cannot be enabled or disabled.
+ * To emulate offset disabled, set an offset value equal to 0.
+ * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
+ * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
+ * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
+ * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_JOFR1_JOFFSET1,
+ OffsetLevel);
+}
+
+/**
+ * @brief Get ADC group injected offset.
+ * @note It gives offset level (offset to be subtracted from the raw converted data).
+ * Caution: Offset format is dependent to ADC resolution:
+ * offset has to be left-aligned on bit 11, the LSB (right bits)
+ * are set to 0.
+ * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
+ * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
+ * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
+ * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_JOFR1_JOFFSET1)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+ * @{
+ */
+
+/**
+ * @brief Set sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note In case of internal channel (VrefInt, TempSensor, ...) to be
+ * converted:
+ * sampling time constraints must be respected (sampling time can be
+ * adjusted in function of ADC clock frequency and sampling time
+ * setting).
+ * Refer to device datasheet for timings values (parameters TS_vrefint,
+ * TS_temp, ...).
+ * @note Conversion time is the addition of sampling time and processing time.
+ * Refer to reference manual for ADC processing time of
+ * this STM32 serie.
+ * @note In case of ADC conversion of internal channel (VrefInt,
+ * temperature sensor, ...), a sampling time minimum value
+ * is required.
+ * Refer to device datasheet.
+ * @rmtoll SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
+ * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
+ * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F1, parameter available only on ADC instance: ADC1.
+ * @param SamplingTime This parameter can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
+{
+ /* Set bits with content of parameter "SamplingTime" with bits position */
+ /* in register and register position depending on parameter "Channel". */
+ /* Parameter "Channel" is used with masks because containing */
+ /* other bits reserved for other purpose. */
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
+ SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get sampling time of the selected ADC channel
+ * Unit: ADC clock cycles.
+ * @note On this device, sampling time is on channel scope: independently
+ * of channel mapped on ADC group regular or injected.
+ * @note Conversion time is the addition of sampling time and processing time.
+ * Refer to reference manual for ADC processing time of
+ * this STM32 serie.
+ * @rmtoll SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
+ * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
+ * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
+ * @param ADCx ADC instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_ADC_CHANNEL_0
+ * @arg @ref LL_ADC_CHANNEL_1
+ * @arg @ref LL_ADC_CHANNEL_2
+ * @arg @ref LL_ADC_CHANNEL_3
+ * @arg @ref LL_ADC_CHANNEL_4
+ * @arg @ref LL_ADC_CHANNEL_5
+ * @arg @ref LL_ADC_CHANNEL_6
+ * @arg @ref LL_ADC_CHANNEL_7
+ * @arg @ref LL_ADC_CHANNEL_8
+ * @arg @ref LL_ADC_CHANNEL_9
+ * @arg @ref LL_ADC_CHANNEL_10
+ * @arg @ref LL_ADC_CHANNEL_11
+ * @arg @ref LL_ADC_CHANNEL_12
+ * @arg @ref LL_ADC_CHANNEL_13
+ * @arg @ref LL_ADC_CHANNEL_14
+ * @arg @ref LL_ADC_CHANNEL_15
+ * @arg @ref LL_ADC_CHANNEL_16
+ * @arg @ref LL_ADC_CHANNEL_17
+ * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
+ * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
+ *
+ * (1) On STM32F1, parameter available only on ADC instance: ADC1.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
+ * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
+ >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+ * @{
+ */
+
+/**
+ * @brief Set ADC analog watchdog monitored channels:
+ * a single channel or all channels,
+ * on ADC groups regular and-or injected.
+ * @note Once monitored channels are selected, analog watchdog
+ * is enabled.
+ * @note In case of need to define a single channel to monitor
+ * with analog watchdog from sequencer channel definition,
+ * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+ * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
+ * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
+ * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @param AWDChannelGroup This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
+ * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
+ *
+ * (1) On STM32F1, parameter available only on ADC instance: ADC1.
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
+{
+ MODIFY_REG(ADCx->CR1,
+ (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
+ AWDChannelGroup);
+}
+
+/**
+ * @brief Get ADC analog watchdog monitored channel.
+ * @note Usage of the returned channel number:
+ * - To reinject this channel into another function LL_ADC_xxx:
+ * the returned channel number is only partly formatted on definition
+ * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+ * with parts of literals LL_ADC_CHANNEL_x or using
+ * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Then the selected literal LL_ADC_CHANNEL_x can be used
+ * as parameter for another function.
+ * - To get the channel number in decimal format:
+ * process the returned value with the helper macro
+ * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+ * Applicable only when the analog watchdog is set to monitor
+ * one channel.
+ * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
+ * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
+ * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
+ * @param ADCx ADC instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_AWD_DISABLE
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
+ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
+ * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
+{
+ return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
+}
+
+/**
+ * @brief Set ADC analog watchdog threshold value of threshold
+ * high or low.
+ * @note On this STM32 serie, there is only 1 kind of analog watchdog
+ * instance:
+ * - AWD standard (instance AWD1):
+ * - channels monitored: can monitor 1 channel or all channels.
+ * - groups monitored: ADC groups regular and-or injected.
+ * - resolution: resolution is not limited (corresponds to
+ * ADC resolution configured).
+ * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
+ * LTR LT LL_ADC_SetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+
+ MODIFY_REG(*preg,
+ ADC_HTR_HT,
+ AWDThresholdValue);
+}
+
+/**
+ * @brief Get ADC analog watchdog threshold value of threshold high or
+ * threshold low.
+ * @note In case of ADC resolution different of 12 bits,
+ * analog watchdog thresholds data require a specific shift.
+ * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+ * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
+ * LTR LT LL_ADC_GetAnalogWDThresholds
+ * @param ADCx ADC instance
+ * @param AWDThresholdsHighLow This parameter can be one of the following values:
+ * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+ * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+*/
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
+
+ return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
+ * @{
+ */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Set ADC multimode configuration to operate in independent mode
+ * or multimode (for devices with several ADC instances).
+ * @note If multimode configuration: the selected ADC instance is
+ * either master or slave depending on hardware.
+ * Refer to reference manual.
+ * @rmtoll CR1 DUALMOD LL_ADC_SetMultimode
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param Multimode This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_INDEPENDENT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
+{
+ MODIFY_REG(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD, Multimode);
+}
+
+/**
+ * @brief Get ADC multimode configuration to operate in independent mode
+ * or multimode (for devices with several ADC instances).
+ * @note If multimode configuration: the selected ADC instance is
+ * either master or slave depending on hardware.
+ * Refer to reference manual.
+ * @rmtoll CR1 DUALMOD LL_ADC_GetMultimode
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_INDEPENDENT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+ * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM
+ * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM
+ */
+__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (uint32_t)(READ_BIT(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD));
+}
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+ * @{
+ */
+
+/**
+ * @brief Enable the selected ADC instance.
+ * @note On this STM32 serie, after ADC enable, a delay for
+ * ADC internal analog stabilization is required before performing a
+ * ADC conversion start.
+ * Refer to device datasheet, parameter tSTAB.
+ * @rmtoll CR2 ADON LL_ADC_Enable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR2, ADC_CR2_ADON);
+}
+
+/**
+ * @brief Disable the selected ADC instance.
+ * @rmtoll CR2 ADON LL_ADC_Disable
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
+}
+
+/**
+ * @brief Get the selected ADC instance enable state.
+ * @rmtoll CR2 ADON LL_ADC_IsEnabled
+ * @param ADCx ADC instance
+ * @retval 0: ADC is disabled, 1: ADC is enabled.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
+}
+
+/**
+ * @brief Start ADC calibration in the mode single-ended
+ * or differential (for devices with differential mode available).
+ * @note On this STM32 serie, before starting a calibration,
+ * ADC must be disabled.
+ * A minimum number of ADC clock cycles are required
+ * between ADC disable state and calibration start.
+ * Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES.
+ * @note On this STM32 serie, hardware prerequisite before starting a calibration:
+ the ADC must have been in power-on state for at least
+ two ADC clock cycles.
+ * @rmtoll CR2 CAL LL_ADC_StartCalibration
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR2, ADC_CR2_CAL);
+}
+
+/**
+ * @brief Get ADC calibration state.
+ * @rmtoll CR2 CAL LL_ADC_IsCalibrationOnGoing
+ * @param ADCx ADC instance
+ * @retval 0: calibration complete, 1: calibration in progress.
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR2, ADC_CR2_CAL) == (ADC_CR2_CAL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+ * @{
+ */
+
+/**
+ * @brief Start ADC group regular conversion.
+ * @note On this STM32 serie, this function is relevant only for
+ * internal trigger (SW start), not for external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * start must be performed using function
+ * @ref LL_ADC_REG_StartConversionExtTrig().
+ * (if external trigger edge would have been set during ADC other
+ * settings, ADC conversion would start at trigger event
+ * as soon as ADC is enabled).
+ * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
+}
+
+/**
+ * @brief Start ADC group regular conversion from external trigger.
+ * @note ADC conversion will start at next trigger event (on the selected
+ * trigger edge) following the ADC start conversion command.
+ * @note On this STM32 serie, this function is relevant for
+ * ADC conversion start from external trigger.
+ * If internal trigger (SW start) is needed, perform ADC conversion
+ * start using function @ref LL_ADC_REG_StartConversionSWStart().
+ * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+ SET_BIT(ADCx->CR2, ExternalTriggerEdge);
+}
+
+/**
+ * @brief Stop ADC group regular conversion from external trigger.
+ * @note No more ADC conversion will start at next trigger event
+ * following the ADC stop conversion command.
+ * If a conversion is on-going, it will be completed.
+ * @note On this STM32 serie, there is no specific command
+ * to stop a conversion on-going or to stop ADC converting
+ * in continuous mode. These actions can be performed
+ * using function @ref LL_ADC_Disable().
+ * @rmtoll CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTSEL);
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_REG_ReadConversionData32.
+ * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
+ * @param ADCx ADC instance
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
+{
+ return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Get ADC multimode conversion data of ADC master, ADC slave
+ * or raw data with ADC master and slave concatenated.
+ * @note If raw data with ADC master and slave concatenated is retrieved,
+ * a macro is available to get the conversion data of
+ * ADC master or ADC slave: see helper macro
+ * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+ * (however this macro is mainly intended for multimode
+ * transfer by DMA, because this function can do the same
+ * by getting multimode conversion data of ADC master or ADC slave
+ * separately).
+ * @rmtoll DR DATA LL_ADC_REG_ReadMultiConversionData32\n
+ * DR ADC2DATA LL_ADC_REG_ReadMultiConversionData32
+ * @param ADCx ADC instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param ConversionData This parameter can be one of the following values:
+ * @arg @ref LL_ADC_MULTI_MASTER
+ * @arg @ref LL_ADC_MULTI_SLAVE
+ * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_TypeDef *ADCx, uint32_t ConversionData)
+{
+ return (uint32_t)(READ_BIT(ADCx->DR,
+ ADC_DR_ADC2DATA)
+ >> POSITION_VAL(ConversionData)
+ );
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
+ * @{
+ */
+
+/**
+ * @brief Start ADC group injected conversion.
+ * @note On this STM32 serie, this function is relevant only for
+ * internal trigger (SW start), not for external trigger:
+ * - If ADC trigger has been set to software start, ADC conversion
+ * starts immediately.
+ * - If ADC trigger has been set to external trigger, ADC conversion
+ * start must be performed using function
+ * @ref LL_ADC_INJ_StartConversionExtTrig().
+ * (if external trigger edge would have been set during ADC other
+ * settings, ADC conversion would start at trigger event
+ * as soon as ADC is enabled).
+ * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
+}
+
+/**
+ * @brief Start ADC group injected conversion from external trigger.
+ * @note ADC conversion will start at next trigger event (on the selected
+ * trigger edge) following the ADC start conversion command.
+ * @note On this STM32 serie, this function is relevant for
+ * ADC conversion start from external trigger.
+ * If internal trigger (SW start) is needed, perform ADC conversion
+ * start using function @ref LL_ADC_INJ_StartConversionSWStart().
+ * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
+ * @param ExternalTriggerEdge This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+ SET_BIT(ADCx->CR2, ExternalTriggerEdge);
+}
+
+/**
+ * @brief Stop ADC group injected conversion from external trigger.
+ * @note No more ADC conversion will start at next trigger event
+ * following the ADC stop conversion command.
+ * If a conversion is on-going, it will be completed.
+ * @note On this STM32 serie, there is no specific command
+ * to stop a conversion on-going or to stop ADC converting
+ * in continuous mode. These actions can be performed
+ * using function @ref LL_ADC_Disable().
+ * @rmtoll CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTSEL);
+}
+
+/**
+ * @brief Get ADC group regular conversion data, range fit for
+ * all ADC configurations: all ADC resolutions and
+ * all oversampling increased data width (for devices
+ * with feature oversampling).
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint32_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @brief Get ADC group injected conversion data, range fit for
+ * ADC resolution 12 bits.
+ * @note For devices with feature oversampling: Oversampling
+ * can increase data width, function for extended range
+ * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+ * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
+ * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
+ * @param ADCx ADC instance
+ * @param Rank This parameter can be one of the following values:
+ * @arg @ref LL_ADC_INJ_RANK_1
+ * @arg @ref LL_ADC_INJ_RANK_2
+ * @arg @ref LL_ADC_INJ_RANK_3
+ * @arg @ref LL_ADC_INJ_RANK_4
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
+
+ return (uint16_t)(READ_BIT(*preg,
+ ADC_JDR1_JDATA)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+ * @{
+ */
+
+/**
+ * @brief Get flag ADC group regular end of sequence conversions.
+ * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
+}
+
+
+/**
+ * @brief Get flag ADC group injected end of sequence conversions.
+ * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
+}
+
+/**
+ * @brief Get flag ADC analog watchdog 1 flag
+ * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
+}
+
+/**
+ * @brief Clear flag ADC group regular end of sequence conversions.
+ * @rmtoll SR EOC LL_ADC_ClearFlag_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOS);
+}
+
+
+/**
+ * @brief Clear flag ADC group injected end of sequence conversions.
+ * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
+}
+
+/**
+ * @brief Clear flag ADC analog watchdog 1.
+ * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+{
+ WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+ * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
+ * @rmtoll SR EOC LL_ADC_IsActiveFlag_MST_EOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCxy_COMMON->SR, ADC_SR_EOC) == (ADC_SR_EOC));
+}
+
+/**
+ * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
+ * @rmtoll SR EOC LL_ADC_IsActiveFlag_SLV_EOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
+
+ return (READ_BIT(*preg, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
+}
+
+
+/**
+ * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
+ * @rmtoll SR JEOC LL_ADC_IsActiveFlag_MST_JEOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADC1->SR, ADC_SR_JEOC) == (ADC_SR_JEOC));
+}
+
+/**
+ * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
+ * @rmtoll SR JEOC LL_ADC_IsActiveFlag_SLV_JEOS
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
+
+ return (READ_BIT(*preg, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
+}
+
+/**
+ * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
+ * @rmtoll SR AWD LL_ADC_IsActiveFlag_MST_AWD1
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ return (READ_BIT(ADC1->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
+}
+
+/**
+ * @brief Get flag multimode analog watchdog 1 of the ADC slave.
+ * @rmtoll SR AWD LL_ADC_IsActiveFlag_SLV_AWD1
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
+
+ return (READ_BIT(*preg, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
+}
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+ * @{
+ */
+
+/**
+ * @brief Enable interruption ADC group regular end of sequence conversions.
+ * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ SET_BIT(ADCx->CR1, ADC_CR1_EOCIE);
+}
+
+
+/**
+ * @brief Enable interruption ADC group injected end of sequence conversions.
+ * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Enable interruption ADC analog watchdog 1.
+ * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Disable interruption ADC group regular end of sequence conversions.
+ * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ CLEAR_BIT(ADCx->CR1, ADC_CR1_EOCIE);
+}
+
+
+/**
+ * @brief Disable interruption ADC group injected end of sequence conversions.
+ * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
+}
+
+/**
+ * @brief Disable interruption ADC analog watchdog 1.
+ * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+{
+ CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
+}
+
+/**
+ * @brief Get state of interruption ADC group regular end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group regular */
+ /* end of unitary conversion. */
+ /* Flag noted as "EOC" is corresponding to flag "EOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
+}
+
+
+/**
+ * @brief Get state of interruption ADC group injected end of sequence conversions
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
+{
+ /* Note: on this STM32 serie, there is no flag ADC group injected */
+ /* end of unitary conversion. */
+ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
+ /* in other STM32 families). */
+ return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
+}
+
+/**
+ * @brief Get state of interruption ADC analog watchdog 1
+ * (0: interrupt disabled, 1: interrupt enabled).
+ * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
+ * @param ADCx ADC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
+{
+ return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization of some features of ADC common parameters and multimode */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+
+/* De-initialization of ADC instance, ADC group regular and ADC group injected */
+/* (availability of ADC group injected depends on STM32 families) */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
+
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group injected */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 || ADC2 || ADC3 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_ADC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_bus.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_bus.h
new file mode 100644
index 0000000..c28b643
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_bus.h
@@ -0,0 +1,1033 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_bus.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of BUS LL module.
+
+ @verbatim
+ ##### RCC Limitations #####
+ ==============================================================================
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
+ from/to registers.
+ (+) This delay depends on the peripheral mapping.
+ (++) AHB & APB peripherals, 1 dummy read is necessary
+
+ [..]
+ Workarounds:
+ (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+ inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_BUS_H
+#define __STM32F1xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+#if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST)
+#define RCC_AHBRSTR_SUPPORT
+#endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+ * @{
+ */
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
+#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
+#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
+#if defined(DMA2)
+#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
+#endif /*DMA2*/
+#if defined(ETH)
+#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHBENR_ETHMACEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHBENR_ETHMACRXEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHBENR_ETHMACTXEN
+#endif /*ETH*/
+#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
+#if defined(FSMC_Bank1)
+#define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
+#endif /*FSMC_Bank1*/
+#if defined(USB_OTG_FS)
+#define LL_AHB1_GRP1_PERIPH_OTGFS RCC_AHBENR_OTGFSEN
+#endif /*USB_OTG_FS*/
+#if defined(SDIO)
+#define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN
+#endif /*SDIO*/
+#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
+#define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN
+#if defined(CAN1)
+#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
+#endif /*CAN1*/
+#if defined(CAN2)
+#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
+#endif /*CAN2*/
+#if defined(CEC)
+#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
+#endif /*CEC*/
+#if defined(DAC)
+#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
+#endif /*DAC*/
+#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
+#if defined(I2C2)
+#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
+#endif /*I2C2*/
+#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
+#if defined(SPI2)
+#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
+#endif /*SPI2*/
+#if defined(SPI3)
+#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
+#endif /*SPI3*/
+#if defined(TIM12)
+#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
+#endif /*TIM12*/
+#if defined(TIM13)
+#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
+#endif /*TIM13*/
+#if defined(TIM14)
+#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
+#endif /*TIM14*/
+#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
+#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
+#if defined(TIM4)
+#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
+#endif /*TIM4*/
+#if defined(TIM5)
+#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
+#endif /*TIM5*/
+#if defined(TIM6)
+#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
+#endif /*TIM6*/
+#if defined(TIM7)
+#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
+#endif /*TIM7*/
+#if defined(UART4)
+#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
+#endif /*UART4*/
+#if defined(UART5)
+#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
+#endif /*UART5*/
+#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
+#if defined(USART3)
+#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
+#endif /*USART3*/
+#if defined(USB)
+#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
+#endif /*USB*/
+#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
+ * @{
+ */
+#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
+#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
+#if defined(ADC2)
+#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
+#endif /*ADC2*/
+#if defined(ADC3)
+#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
+#endif /*ADC3*/
+#define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN
+#define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN
+#define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN
+#define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN
+#define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN
+#if defined(GPIOE)
+#define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN
+#endif /*GPIOE*/
+#if defined(GPIOF)
+#define LL_APB2_GRP1_PERIPH_GPIOF RCC_APB2ENR_IOPFEN
+#endif /*GPIOF*/
+#if defined(GPIOG)
+#define LL_APB2_GRP1_PERIPH_GPIOG RCC_APB2ENR_IOPGEN
+#endif /*GPIOG*/
+#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
+#if defined(TIM10)
+#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
+#endif /*TIM10*/
+#if defined(TIM11)
+#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
+#endif /*TIM11*/
+#if defined(TIM15)
+#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
+#endif /*TIM15*/
+#if defined(TIM16)
+#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
+#endif /*TIM16*/
+#if defined(TIM17)
+#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
+#endif /*TIM17*/
+#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
+#if defined(TIM8)
+#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
+#endif /*TIM8*/
+#if defined(TIM9)
+#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
+#endif /*TIM9*/
+#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+ * @{
+ */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+ * @{
+ */
+
+/**
+ * @brief Enable AHB1 peripherals clock.
+ * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR SDIOEN LL_AHB1_GRP1_EnableClock\n
+ * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->AHBENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->AHBENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if AHB1 peripheral clock is enabled or not
+ * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock\n
+ * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable AHB1 peripherals clock.
+ * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR SDIOEN LL_AHB1_GRP1_DisableClock\n
+ * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+ * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
+ * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHBENR, Periphs);
+}
+
+#if defined(RCC_AHBRSTR_SUPPORT)
+/**
+ * @brief Force AHB1 peripherals reset.
+ * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
+ * AHBRSTR OTGFSRST LL_AHB1_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->AHBRSTR, Periphs);
+}
+
+/**
+ * @brief Release AHB1 peripherals reset.
+ * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
+ * AHBRSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+ * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->AHBRSTR, Periphs);
+}
+#endif /* RCC_AHBRSTR_SUPPORT */
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+ * @{
+ */
+
+/**
+ * @brief Enable APB1 peripherals clock.
+ * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
+ * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_BKP
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB1 peripheral clock is enabled or not
+ * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
+ * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_BKP
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable APB1 peripherals clock.
+ * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
+ * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_BKP
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1ENR, Periphs);
+}
+
+/**
+ * @brief Force APB1 peripherals reset.
+ * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
+ * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_BKP
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+ * @brief Release APB1 peripherals reset.
+ * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
+ * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB1_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB1_GRP1_PERIPH_BKP
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+ * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_PWR
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART2
+ * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
+ * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+ * @{
+ */
+
+/**
+ * @brief Enable APB2 peripherals clock.
+ * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR AFIOEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR IOPAEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR IOPBEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR IOPCEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR IOPDEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR IOPEEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR IOPFEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR IOPGEN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB2ENR, Periphs);
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+ (void)tmpreg;
+}
+
+/**
+ * @brief Check if APB2 peripheral clock is enabled or not
+ * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR AFIOEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR IOPAEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR IOPBEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR IOPCEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR IOPDEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR IOPEEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR IOPFEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR IOPGEN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ *
+ * (*) value not defined in all devices.
+ * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+ return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
+}
+
+/**
+ * @brief Disable APB2 peripherals clock.
+ * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR AFIOEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR IOPAEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR IOPBEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR IOPCEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR IOPDEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR IOPEEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR IOPFEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR IOPGEN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
+ * APB2ENR USART1EN LL_APB2_GRP1_DisableClock
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+ * @brief Force APB2 peripherals reset.
+ * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR ADC2RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR ADC3RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR AFIORST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR IOPARST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR IOPBRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR IOPCRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR IOPDRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR IOPERST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR IOPFRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR IOPGRST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+ SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @brief Release APB2 peripherals reset.
+ * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR ADC2RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR ADC3RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR AFIORST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR IOPARST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR IOPBRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR IOPCRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR IOPDRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR IOPERST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR IOPFRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR IOPGRST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
+ * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_APB2_GRP1_PERIPH_ALL
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
+ * @arg @ref LL_APB2_GRP1_PERIPH_USART1
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+ CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_BUS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_cortex.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_cortex.h
new file mode 100644
index 0000000..74a3203
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_cortex.h
@@ -0,0 +1,658 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_cortex.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of CORTEX LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL CORTEX driver contains a set of generic APIs that can be
+ used by user:
+ (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+ functions
+ (+) Low power mode configuration (SCB register of Cortex-MCU)
+ (+) MPU API to configure and enable regions
+ (MPU services provided only on some devices)
+ (+) API to access to MCU info (CPUID register)
+ (+) API to enable fault handler (SHCSR accesses)
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_CORTEX_H
+#define __STM32F1xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup CORTEX_LL CORTEX
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+ * @{
+ */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+ * @{
+ */
+#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
+/**
+ * @}
+ */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+ * @{
+ */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+ * @{
+ */
+#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
+#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
+#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
+#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
+#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
+#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
+#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
+#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+ * @{
+ */
+#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+ * @{
+ */
+#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+ * @{
+ */
+#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+ * @{
+ */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+ * @{
+ */
+#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
+/**
+ * @}
+ */
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+ * @{
+ */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+ * @{
+ */
+
+/**
+ * @brief This function checks if the Systick counter flag is active or not.
+ * @note It can be used in timeout function on application side.
+ * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+ return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
+}
+
+/**
+ * @brief Configures the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+ if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
+ {
+ SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ }
+ else
+ {
+ CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+ }
+}
+
+/**
+ * @brief Get the SysTick clock source
+ * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+ * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+ return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+ * @brief Enable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Disable SysTick exception request
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+ * @brief Checks if the SYSTICK interrupt is enabled or disabled.
+ * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+ return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+ * @{
+ */
+
+/**
+ * @brief Processor uses sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+ /* Clear SLEEPDEEP bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Processor uses deep sleep as its low power mode
+ * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+ /* Set SLEEPDEEP bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+ * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
+ * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+ * empty main application.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+ /* Set SLEEPONEXIT bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Do not sleep when returning to Thread mode.
+ * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+ /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+ * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
+ * processor.
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+ /* Set SEVEONPEND bit of Cortex System Control Register */
+ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+ * excluded
+ * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+ /* Clear SEVEONPEND bit of Cortex System Control Register */
+ CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+ * @{
+ */
+
+/**
+ * @brief Enable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+ /* Enable the system handler fault */
+ SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @brief Disable a fault in System handler control register (SHCSR)
+ * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
+ * @param Fault This parameter can be a combination of the following values:
+ * @arg @ref LL_HANDLER_FAULT_USG
+ * @arg @ref LL_HANDLER_FAULT_BUS
+ * @arg @ref LL_HANDLER_FAULT_MEM
+ * @retval None
+ */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+ /* Disable the system handler fault */
+ CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+ * @{
+ */
+
+/**
+ * @brief Get Implementer code
+ * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
+ * @retval Value should be equal to 0x41 for ARM
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+ * @brief Get Variant number (The r value in the rnpn product revision identifier)
+ * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
+ * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+ * @brief Get Constant number
+ * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
+ * @retval Value should be equal to 0xF for Cortex-M3 devices
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+ * @brief Get Part number
+ * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
+ * @retval Value should be equal to 0xC23 for Cortex-M3
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+ * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+ * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
+ * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
+ */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+ return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+ * @}
+ */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+ * @{
+ */
+
+/**
+ * @brief Enable MPU with input options
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
+ * @param Options This parameter can be one of the following values:
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+ * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+ * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+ * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+ /* Enable the MPU*/
+ WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+ /* Ensure MPU settings take effects */
+ __DSB();
+ /* Sequence instruction fetches using update settings */
+ __ISB();
+}
+
+/**
+ * @brief Disable MPU
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+ /* Make sure outstanding transfers are done */
+ __DMB();
+ /* Disable MPU*/
+ WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+ * @brief Check if MPU is enabled or not
+ * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+ return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
+}
+
+/**
+ * @brief Enable a MPU region
+ * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Enable the MPU region */
+ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Configure and enable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR REGION LL_MPU_ConfigRegion\n
+ * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
+ * MPU_RASR XN LL_MPU_ConfigRegion\n
+ * MPU_RASR AP LL_MPU_ConfigRegion\n
+ * MPU_RASR S LL_MPU_ConfigRegion\n
+ * MPU_RASR C LL_MPU_ConfigRegion\n
+ * MPU_RASR B LL_MPU_ConfigRegion\n
+ * MPU_RASR SIZE LL_MPU_ConfigRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @param Address Value of region base address
+ * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+ * @param Attributes This parameter can be a combination of the following values:
+ * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+ * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+ * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+ * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+ * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+ * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+ * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+ * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+ * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+ * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+ * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+ * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+ * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Set base address */
+ WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+ /* Configure MPU */
+ WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
+}
+
+/**
+ * @brief Disable a region
+ * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
+ * MPU_RASR ENABLE LL_MPU_DisableRegion
+ * @param Region This parameter can be one of the following values:
+ * @arg @ref LL_MPU_REGION_NUMBER0
+ * @arg @ref LL_MPU_REGION_NUMBER1
+ * @arg @ref LL_MPU_REGION_NUMBER2
+ * @arg @ref LL_MPU_REGION_NUMBER3
+ * @arg @ref LL_MPU_REGION_NUMBER4
+ * @arg @ref LL_MPU_REGION_NUMBER5
+ * @arg @ref LL_MPU_REGION_NUMBER6
+ * @arg @ref LL_MPU_REGION_NUMBER7
+ * @retval None
+ */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+ /* Set Region number */
+ WRITE_REG(MPU->RNR, Region);
+ /* Disable the MPU region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @}
+ */
+
+#endif /* __MPU_PRESENT */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_CORTEX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_crc.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_crc.h
new file mode 100644
index 0000000..e6bc9b3
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_crc.h
@@ -0,0 +1,212 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_crc.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of CRC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_CRC_H
+#define __STM32F1xx_LL_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined(CRC)
+
+/** @defgroup CRC_LL CRC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
+ * @{
+ */
+
+/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in CRC register
+ * @param __INSTANCE__ CRC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in CRC register
+ * @param __INSTANCE__ CRC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
+ * @{
+ */
+
+/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
+ * @{
+ */
+
+/**
+ * @brief Reset the CRC calculation unit.
+ * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
+ * @param CRCx CRC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
+{
+ WRITE_REG(CRCx->CR, CRC_CR_RESET);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CRC_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Write given 32-bit data to the CRC calculator
+ * @rmtoll DR DR LL_CRC_FeedData32
+ * @param CRCx CRC Instance
+ * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
+{
+ WRITE_REG(CRCx->DR, InData);
+}
+
+/**
+ * @brief Return current CRC calculation result. 32 bits value is returned.
+ * @rmtoll DR DR LL_CRC_ReadData32
+ * @param CRCx CRC Instance
+ * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
+ */
+__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->DR));
+}
+
+/**
+ * @brief Return data stored in the Independent Data(IDR) register.
+ * @note This register can be used as a temporary storage location for one byte.
+ * @rmtoll IDR IDR LL_CRC_Read_IDR
+ * @param CRCx CRC Instance
+ * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
+ */
+__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
+{
+ return (uint32_t)(READ_REG(CRCx->IDR));
+}
+
+/**
+ * @brief Store data in the Independent Data(IDR) register.
+ * @note This register can be used as a temporary storage location for one byte.
+ * @rmtoll IDR IDR LL_CRC_Write_IDR
+ * @param CRCx CRC Instance
+ * @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
+{
+ *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
+}
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(CRC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_CRC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_dac.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_dac.h
new file mode 100644
index 0000000..d3a3b7d
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_dac.h
@@ -0,0 +1,1349 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_dac.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of DAC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_DAC_H
+#define __STM32F1xx_LL_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (DAC)
+
+/** @defgroup DAC_LL DAC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Constants DAC Private Constants
+ * @{
+ */
+
+/* Internal masks for DAC channels definition */
+/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
+/* - channel bits position into register CR */
+/* - channel bits position into register SWTRIG */
+/* - channel register offset of data holding register DHRx */
+/* - channel register offset of data output register DORx */
+#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
+#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
+#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
+
+#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
+#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
+
+#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
+#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
+#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
+#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
+#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
+#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
+
+#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
+#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
+#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
+
+/* DAC registers bits positions */
+#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
+#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
+#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
+
+/* Miscellaneous data */
+#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Macros DAC Private Macros
+ * @{
+ */
+
+/**
+ * @brief Driver macro reserved for internal use: isolate bits with the
+ * selected mask and shift them to the register LSB
+ * (shift mask on register position bit 0).
+ * @param __BITS__ Bits in register 32 bits
+ * @param __MASK__ Mask in register 32 bits
+ * @retval Bits in register 32 bits
+*/
+#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
+ (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
+
+/**
+ * @brief Driver macro reserved for internal use: set a pointer to
+ * a register from a register basis from which an offset
+ * is applied.
+ * @param __REG__ Register basis from which the offset is applied.
+ * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+ * @retval Pointer to register address
+*/
+#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
+ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
+
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief Structure definition of some features of DAC instance.
+ */
+typedef struct
+{
+ uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
+ This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
+
+ uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
+ This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
+
+ uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
+ If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
+ If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
+ @note If waveform automatic generation mode is disabled, this parameter is discarded.
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
+
+ uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
+ This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
+
+ This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
+
+} LL_DAC_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
+ * @{
+ */
+
+/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
+ * @brief Flags defines which can be used with LL_DAC_ReadReg function
+ * @{
+ */
+/* DAC channel 1 flags */
+#if defined(DAC_SR_DMAUDR1)
+#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
+#endif /* DAC_SR_DMAUDR1 */
+
+/* DAC channel 2 flags */
+#if defined(DAC_SR_DMAUDR2)
+#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
+#endif /* DAC_SR_DMAUDR2 */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_IT DAC interruptions
+ * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
+ * @{
+ */
+#if defined(DAC_CR_DMAUDRIE1)
+#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
+#endif /* DAC_CR_DMAUDRIE1 */
+#if defined(DAC_CR_DMAUDRIE2)
+#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
+#endif /* DAC_CR_DMAUDRIE2 */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_CHANNEL DAC channels
+ * @{
+ */
+#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
+#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
+ * @{
+ */
+#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
+#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
+ * @{
+ */
+#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
+#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
+#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
+ * @{
+ */
+#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
+ * @{
+ */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
+ * @{
+ */
+#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
+#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
+/**
+ * @}
+ */
+
+
+/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
+ * @{
+ */
+#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
+#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
+ * @{
+ */
+/* List of DAC registers intended to be used (most commonly) with */
+/* DMA transfer. */
+/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
+#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
+#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
+#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
+ * @note Only DAC IP HW delays are defined in DAC LL driver driver,
+ * not timeout values.
+ * For details on delays values, refer to descriptions in source code
+ * above each literal definition.
+ * @{
+ */
+
+/* Delay for DAC channel voltage settling time from DAC channel startup */
+/* (transition from disable to enable). */
+/* Note: DAC channel startup time depends on board application environment: */
+/* impedance connected to DAC channel output. */
+/* The delay below is specified under conditions: */
+/* - voltage maximum transition (lowest to highest value) */
+/* - until voltage reaches final value +-1LSB */
+/* - DAC channel output buffer enabled */
+/* - load impedance of 5kOhm (min), 50pF (max) */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tWAKEUP"). */
+/* Unit: us */
+#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+
+/* Delay for DAC channel voltage settling time. */
+/* Note: DAC channel startup time depends on board application environment: */
+/* impedance connected to DAC channel output. */
+/* The delay below is specified under conditions: */
+/* - voltage maximum transition (lowest to highest value) */
+/* - until voltage reaches final value +-1LSB */
+/* - DAC channel output buffer enabled */
+/* - load impedance of 5kOhm min, 50pF max */
+/* Literal set to maximum value (refer to device datasheet, */
+/* parameter "tSETTLING"). */
+/* Unit: us */
+#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
+ * @{
+ */
+
+/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in DAC register
+ * @param __INSTANCE__ DAC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DAC register
+ * @param __INSTANCE__ DAC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
+ * @{
+ */
+
+/**
+ * @brief Helper macro to get DAC channel number in decimal format
+ * from literals LL_DAC_CHANNEL_x.
+ * Example:
+ * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
+ * will return decimal number "1".
+ * @note The input can be a value from functions where a channel
+ * number is returned.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval 1...2
+ */
+#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
+ ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
+
+/**
+ * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
+ * from number in decimal format.
+ * Example:
+ * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
+ * will return a data equivalent to "LL_DAC_CHANNEL_1".
+ * @note If the input parameter does not correspond to a DAC channel,
+ * this macro returns value '0'.
+ * @param __DECIMAL_NB__ 1...2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ */
+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
+ (((__DECIMAL_NB__) == 1U) \
+ ? ( \
+ LL_DAC_CHANNEL_1 \
+ ) \
+ : \
+ (((__DECIMAL_NB__) == 2U) \
+ ? ( \
+ LL_DAC_CHANNEL_2 \
+ ) \
+ : \
+ ( \
+ 0 \
+ ) \
+ ) \
+ )
+
+/**
+ * @brief Helper macro to define the DAC conversion data full-scale digital
+ * value corresponding to the selected DAC resolution.
+ * @note DAC conversion data full-scale corresponds to voltage range
+ * determined by analog voltage references Vref+ and Vref-
+ * (refer to reference manual).
+ * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_DAC_RESOLUTION_12B
+ * @arg @ref LL_DAC_RESOLUTION_8B
+ * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+ */
+#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
+
+/**
+ * @brief Helper macro to calculate the DAC conversion data (unit: digital
+ * value) corresponding to a voltage (unit: mVolt).
+ * @note This helper macro is intended to provide input data in voltage
+ * rather than digital value,
+ * to be used with LL DAC functions such as
+ * @ref LL_DAC_ConvertData12RightAligned().
+ * @note Analog reference voltage (Vref+) must be either known from
+ * user board environment or can be calculated using ADC measurement
+ * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+ * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+ * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
+ * (unit: mVolt).
+ * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
+ * @arg @ref LL_DAC_RESOLUTION_12B
+ * @arg @ref LL_DAC_RESOLUTION_8B
+ * @retval DAC conversion data (unit: digital value)
+ */
+#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
+ __DAC_VOLTAGE__,\
+ __DAC_RESOLUTION__) \
+ ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
+ / (__VREFANALOG_VOLTAGE__) \
+ )
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
+ * @{
+ */
+/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
+ * @{
+ */
+
+/**
+ * @brief Set the conversion trigger source for the selected DAC channel.
+ * @note For conversion trigger source to be effective, DAC trigger
+ * must be enabled using function @ref LL_DAC_EnableTrigger().
+ * @note To set conversion trigger source, DAC channel must be disabled.
+ * Otherwise, the setting is discarded.
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
+ * CR TSEL2 LL_DAC_SetTriggerSource
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param TriggerSource This parameter can be one of the following values:
+ * @arg @ref LL_DAC_TRIG_SOFTWARE
+ * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the conversion trigger source for the selected DAC channel.
+ * @note For conversion trigger source to be effective, DAC trigger
+ * must be enabled using function @ref LL_DAC_EnableTrigger().
+ * @note Availability of parameters of trigger sources from timer
+ * depends on timers availability on the selected device.
+ * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
+ * CR TSEL2 LL_DAC_GetTriggerSource
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_TRIG_SOFTWARE
+ * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+ * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the waveform automatic generation mode
+ * for the selected DAC channel.
+ * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
+ * CR WAVE2 LL_DAC_SetWaveAutoGeneration
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param WaveAutoGeneration This parameter can be one of the following values:
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the waveform automatic generation mode
+ * for the selected DAC channel.
+ * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
+ * CR WAVE2 LL_DAC_GetWaveAutoGeneration
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+ * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the noise waveform generation for the selected DAC channel:
+ * Noise mode and parameters LFSR (linear feedback shift register).
+ * @note For wave generation to be effective, DAC channel
+ * wave generation mode must be enabled using
+ * function @ref LL_DAC_SetWaveAutoGeneration().
+ * @note This setting can be set when the selected DAC channel is disabled
+ * (otherwise, the setting operation is ignored).
+ * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
+ * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param NoiseLFSRMask This parameter can be one of the following values:
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Set the noise waveform generation for the selected DAC channel:
+ * Noise mode and parameters LFSR (linear feedback shift register).
+ * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
+ * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+ * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the triangle waveform generation for the selected DAC channel:
+ * triangle mode and amplitude.
+ * @note For wave generation to be effective, DAC channel
+ * wave generation mode must be enabled using
+ * function @ref LL_DAC_SetWaveAutoGeneration().
+ * @note This setting can be set when the selected DAC channel is disabled
+ * (otherwise, the setting operation is ignored).
+ * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
+ * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param TriangleAmplitude This parameter can be one of the following values:
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Set the triangle waveform generation for the selected DAC channel:
+ * triangle mode and amplitude.
+ * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
+ * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+ * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @brief Set the output buffer for the selected DAC channel.
+ * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
+ * CR BOFF2 LL_DAC_SetOutputBuffer
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param OutputBuffer This parameter can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
+{
+ MODIFY_REG(DACx->CR,
+ DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+ OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get the output buffer state for the selected DAC channel.
+ * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
+ * CR BOFF2 LL_DAC_GetOutputBuffer
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+ * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+ */
+__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DAC DMA transfer request of the selected channel.
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_DAC_DMA_GetRegAddr().
+ * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
+ * CR DMAEN2 LL_DAC_EnableDMAReq
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC DMA transfer request of the selected channel.
+ * @note To configure DMA source address (peripheral address),
+ * use function @ref LL_DAC_DMA_GetRegAddr().
+ * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
+ * CR DMAEN2 LL_DAC_DisableDMAReq
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC DMA transfer request state of the selected channel.
+ * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
+ * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
+ * CR DMAEN2 LL_DAC_IsDMAReqEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (READ_BIT(DACx->CR,
+ DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+ * @brief Function to help to configure DMA transfer to DAC: retrieve the
+ * DAC register address from DAC instance and a list of DAC registers
+ * intended to be used (most commonly) with DMA transfer.
+ * @note These DAC registers are data holding registers:
+ * when DAC conversion is requested, DAC generates a DMA transfer
+ * request to have data available in DAC data holding registers.
+ * @note This macro is intended to be used with LL DMA driver, refer to
+ * function "LL_DMA_ConfigAddresses()".
+ * Example:
+ * LL_DMA_ConfigAddresses(DMA1,
+ * LL_DMA_CHANNEL_1,
+ * (uint32_t)&< array or variable >,
+ * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
+ * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
+ * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
+ * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param Register This parameter can be one of the following values:
+ * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
+ * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
+ * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
+ * @retval DAC register address
+ */
+__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
+{
+ /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
+ /* DAC channel selected. */
+ return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
+}
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
+ * @{
+ */
+
+/**
+ * @brief Enable DAC selected channel.
+ * @rmtoll CR EN1 LL_DAC_Enable\n
+ * CR EN2 LL_DAC_Enable
+ * @note After enable from off state, DAC channel requires a delay
+ * for output voltage to reach accuracy +/- 1 LSB.
+ * Refer to device datasheet, parameter "tWAKEUP".
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC selected channel.
+ * @rmtoll CR EN1 LL_DAC_Disable\n
+ * CR EN2 LL_DAC_Disable
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC enable state of the selected channel.
+ * (0: DAC channel is disabled, 1: DAC channel is enabled)
+ * @rmtoll CR EN1 LL_DAC_IsEnabled\n
+ * CR EN2 LL_DAC_IsEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (READ_BIT(DACx->CR,
+ DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+ * @brief Enable DAC trigger of the selected channel.
+ * @note - If DAC trigger is disabled, DAC conversion is performed
+ * automatically once the data holding register is updated,
+ * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+ * @ref LL_DAC_ConvertData12RightAligned(), ...
+ * - If DAC trigger is enabled, DAC conversion is performed
+ * only when a hardware of software trigger event is occurring.
+ * Select trigger source using
+ * function @ref LL_DAC_SetTriggerSource().
+ * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
+ * CR TEN2 LL_DAC_EnableTrigger
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Disable DAC trigger of the selected channel.
+ * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
+ * CR TEN2 LL_DAC_DisableTrigger
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ CLEAR_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+ * @brief Get DAC trigger state of the selected channel.
+ * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
+ * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
+ * CR TEN2 LL_DAC_IsTriggerEnabled
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ return (READ_BIT(DACx->CR,
+ DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+ == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
+}
+
+/**
+ * @brief Trig DAC conversion by software for the selected DAC channel.
+ * @note Preliminarily, DAC trigger must be set to software trigger
+ * using function @ref LL_DAC_SetTriggerSource()
+ * with parameter "LL_DAC_TRIGGER_SOFTWARE".
+ * and DAC trigger must be enabled using
+ * function @ref LL_DAC_EnableTrigger().
+ * @note For devices featuring DAC with 2 channels: this function
+ * can perform a SW start of both DAC channels simultaneously.
+ * Two channels can be selected as parameter.
+ * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
+ * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
+ * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can a combination of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ SET_BIT(DACx->SWTRIGR,
+ (DAC_Channel & DAC_SWTR_CHX_MASK));
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (LSB aligned on bit 0),
+ * for the selected DAC channel.
+ * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
+ * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+ register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ DAC_DHR12R1_DACC1DHR,
+ Data);
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (MSB aligned on bit 15),
+ * for the selected DAC channel.
+ * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
+ * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+ register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ DAC_DHR12L1_DACC1DHR,
+ Data);
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 8 bits left alignment (LSB aligned on bit 0),
+ * for the selected DAC channel.
+ * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
+ * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+ register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
+
+ MODIFY_REG(*preg,
+ DAC_DHR8R1_DACC1DHR,
+ Data);
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (LSB aligned on bit 0),
+ * for both DAC channels.
+ * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
+ * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
+ * @param DACx DAC instance
+ * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+ MODIFY_REG(DACx->DHR12RD,
+ (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
+ ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 12 bits left alignment (MSB aligned on bit 15),
+ * for both DAC channels.
+ * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
+ * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
+ * @param DACx DAC instance
+ * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+ /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
+ /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
+ /* the 4 LSB must be taken into account for the shift value. */
+ MODIFY_REG(DACx->DHR12LD,
+ (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
+ ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
+}
+
+/**
+ * @brief Set the data to be loaded in the data holding register
+ * in format 8 bits left alignment (LSB aligned on bit 0),
+ * for both DAC channels.
+ * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
+ * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
+ * @param DACx DAC instance
+ * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
+ * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
+{
+ MODIFY_REG(DACx->DHR8RD,
+ (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
+ ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+/**
+ * @brief Retrieve output data currently generated for the selected DAC channel.
+ * @note Whatever alignment and resolution settings
+ * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+ * @ref LL_DAC_ConvertData12RightAligned(), ...),
+ * output data format is 12 bits right aligned (LSB aligned on bit 0).
+ * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
+ * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+ register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
+
+ return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+#if defined(DAC_SR_DMAUDR1)
+/**
+ * @brief Get DAC underrun flag for DAC channel 1
+ * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
+}
+#endif /* DAC_SR_DMAUDR1 */
+
+#if defined(DAC_SR_DMAUDR2)
+/**
+ * @brief Get DAC underrun flag for DAC channel 2
+ * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
+}
+#endif /* DAC_SR_DMAUDR2 */
+
+#if defined(DAC_SR_DMAUDR1)
+/**
+ * @brief Clear DAC underrun flag for DAC channel 1
+ * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
+{
+ WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
+}
+#endif /* DAC_SR_DMAUDR1 */
+
+#if defined(DAC_SR_DMAUDR2)
+/**
+ * @brief Clear DAC underrun flag for DAC channel 2
+ * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
+{
+ WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
+}
+#endif /* DAC_SR_DMAUDR2 */
+
+/**
+ * @}
+ */
+/** @defgroup DAC_LL_EF_IT_Management IT management
+ * @{
+ */
+
+#if defined(DAC_CR_DMAUDRIE1)
+/**
+ * @brief Enable DMA underrun interrupt for DAC channel 1
+ * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+ SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+#endif /* DAC_CR_DMAUDRIE1 */
+
+#if defined(DAC_CR_DMAUDRIE2)
+/**
+ * @brief Enable DMA underrun interrupt for DAC channel 2
+ * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+ SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+#endif /* DAC_CR_DMAUDRIE2 */
+
+#if defined(DAC_CR_DMAUDRIE1)
+/**
+ * @brief Disable DMA underrun interrupt for DAC channel 1
+ * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+ CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+#endif /* DAC_CR_DMAUDRIE1 */
+
+#if defined(DAC_CR_DMAUDRIE2)
+/**
+ * @brief Disable DMA underrun interrupt for DAC channel 2
+ * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
+ * @param DACx DAC instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+ CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+#endif /* DAC_CR_DMAUDRIE2 */
+
+#if defined(DAC_CR_DMAUDRIE1)
+/**
+ * @brief Get DMA underrun interrupt for DAC channel 1
+ * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
+}
+#endif /* DAC_CR_DMAUDRIE1 */
+
+#if defined(DAC_CR_DMAUDRIE2)
+/**
+ * @brief Get DMA underrun interrupt for DAC channel 2
+ * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
+ * @param DACx DAC instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+ return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
+}
+#endif /* DAC_CR_DMAUDRIE2 */
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
+ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
+void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DAC */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_dma.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_dma.h
new file mode 100644
index 0000000..fda0a07
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_dma.h
@@ -0,0 +1,1978 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_dma.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of DMA LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_DMA_H
+#define __STM32F1xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+ * @{
+ */
+/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
+static const uint8_t CHANNEL_OFFSET_TAB[] =
+{
+ (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
+ (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
+};
+/**
+ * @}
+ */
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_Private_Macros DMA Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+ * @{
+ */
+typedef struct
+{
+ uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
+ or as Source base address in case of memory to memory transfer direction.
+
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+ uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
+ or as Destination base address in case of memory to memory transfer direction.
+
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+ uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
+ from memory to memory or from peripheral to memory.
+ This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+
+ uint32_t Mode; /*!< Specifies the normal or circular operation mode.
+ This parameter can be a value of @ref DMA_LL_EC_MODE
+ @note: The circular buffer mode cannot be used if the memory to memory
+ data transfer direction is configured on the selected Channel
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+
+ uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref DMA_LL_EC_PERIPH
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+
+ uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+ is incremented or not.
+ This parameter can be a value of @ref DMA_LL_EC_MEMORY
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+
+ uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+
+ uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+ in case of memory to memory transfer direction.
+ This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+
+ uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
+ The data unit is equal to the source buffer configuration set in PeripheralSize
+ or MemorySize parameters depending in the transfer direction.
+ This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+
+ uint32_t Priority; /*!< Specifies the channel priority level.
+ This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+ This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
+
+} LL_DMA_InitTypeDef;
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+ * @{
+ */
+/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_DMA_WriteReg function
+ * @{
+ */
+#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
+#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
+#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
+#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
+#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
+#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
+#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
+#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
+#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
+#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
+#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
+#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
+#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
+#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
+#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
+#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
+#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
+#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
+#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
+#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
+#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
+#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_DMA_ReadReg function
+ * @{
+ */
+#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
+#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
+#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
+#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
+#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
+#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
+#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
+#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
+#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
+#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
+#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
+#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
+#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
+#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
+#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
+#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
+#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
+#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
+#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
+#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
+#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
+#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
+#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
+#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
+#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
+#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
+#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
+#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
+ * @{
+ */
+#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
+#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
+#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+ * @{
+ */
+#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
+#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
+#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
+#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
+#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
+#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
+#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
+#endif /*USE_FULL_LL_DRIVER*/
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
+ * @{
+ */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MODE Transfer mode
+ * @{
+ */
+#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
+#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
+ * @{
+ */
+#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
+#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
+ * @{
+ */
+#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
+#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
+ * @{
+ */
+#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
+#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
+ * @{
+ */
+#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
+#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
+ * @{
+ */
+#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
+#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
+#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
+#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+ * @{
+ */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+ * @{
+ */
+/**
+ * @brief Write a value in DMA register
+ * @param __INSTANCE__ DMA Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in DMA register
+ * @param __INSTANCE__ DMA Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
+ * @{
+ */
+
+/**
+ * @brief Convert DMAx_Channely into DMAx
+ * @param __CHANNEL_INSTANCE__ DMAx_Channely
+ * @retval DMAx
+ */
+#if defined(DMA2)
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
+#else
+#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
+#endif
+
+/**
+ * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
+ * @param __CHANNEL_INSTANCE__ DMAx_Channely
+ * @retval LL_DMA_CHANNEL_y
+ */
+#if defined (DMA2)
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#else
+#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
+ LL_DMA_CHANNEL_7)
+#endif
+
+/**
+ * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
+ * @param __DMA_INSTANCE__ DMAx
+ * @param __CHANNEL__ LL_DMA_CHANNEL_y
+ * @retval DMAx_Channely
+ */
+#if defined (DMA2)
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ DMA1_Channel7)
+#else
+#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
+ DMA1_Channel7)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+ * @{
+ */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Enable DMA channel.
+ * @rmtoll CCR EN LL_DMA_EnableChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
+}
+
+/**
+ * @brief Disable DMA channel.
+ * @rmtoll CCR EN LL_DMA_DisableChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
+}
+
+/**
+ * @brief Check if DMA channel is enabled or disabled.
+ * @rmtoll CCR EN LL_DMA_IsEnabledChannel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_EN) == (DMA_CCR_EN));
+}
+
+/**
+ * @brief Configure all parameters link to DMA transfer.
+ * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
+ * CCR MEM2MEM LL_DMA_ConfigTransfer\n
+ * CCR CIRC LL_DMA_ConfigTransfer\n
+ * CCR PINC LL_DMA_ConfigTransfer\n
+ * CCR MINC LL_DMA_ConfigTransfer\n
+ * CCR PSIZE LL_DMA_ConfigTransfer\n
+ * CCR MSIZE LL_DMA_ConfigTransfer\n
+ * CCR PL LL_DMA_ConfigTransfer
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
+ * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+ * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
+ * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
+ Configuration);
+}
+
+/**
+ * @brief Set Data transfer direction (read from peripheral or from memory).
+ * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
+ * CCR MEM2MEM LL_DMA_SetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
+}
+
+/**
+ * @brief Get Data transfer direction (read from peripheral or from memory).
+ * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
+ * CCR MEM2MEM LL_DMA_GetDataTransferDirection
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_DIR | DMA_CCR_MEM2MEM));
+}
+
+/**
+ * @brief Set DMA mode circular or normal.
+ * @note The circular buffer mode cannot be used if the memory-to-memory
+ * data transfer is configured on the selected Channel.
+ * @rmtoll CCR CIRC LL_DMA_SetMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MODE_NORMAL
+ * @arg @ref LL_DMA_MODE_CIRCULAR
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
+ Mode);
+}
+
+/**
+ * @brief Get DMA mode circular or normal.
+ * @rmtoll CCR CIRC LL_DMA_GetMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MODE_NORMAL
+ * @arg @ref LL_DMA_MODE_CIRCULAR
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_CIRC));
+}
+
+/**
+ * @brief Set Peripheral increment mode.
+ * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PERIPH_INCREMENT
+ * @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
+ PeriphOrM2MSrcIncMode);
+}
+
+/**
+ * @brief Get Peripheral increment mode.
+ * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PERIPH_INCREMENT
+ * @arg @ref LL_DMA_PERIPH_NOINCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_PINC));
+}
+
+/**
+ * @brief Set Memory increment mode.
+ * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MEMORY_INCREMENT
+ * @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
+ MemoryOrM2MDstIncMode);
+}
+
+/**
+ * @brief Get Memory increment mode.
+ * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MEMORY_INCREMENT
+ * @arg @ref LL_DMA_MEMORY_NOINCREMENT
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_MINC));
+}
+
+/**
+ * @brief Set Peripheral size.
+ * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE
+ * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_PDATAALIGN_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
+ PeriphOrM2MSrcDataSize);
+}
+
+/**
+ * @brief Get Peripheral size.
+ * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PDATAALIGN_BYTE
+ * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_PDATAALIGN_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_PSIZE));
+}
+
+/**
+ * @brief Set Memory size.
+ * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE
+ * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_MDATAALIGN_WORD
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
+ MemoryOrM2MDstDataSize);
+}
+
+/**
+ * @brief Get Memory size.
+ * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_MDATAALIGN_BYTE
+ * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+ * @arg @ref LL_DMA_MDATAALIGN_WORD
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_MSIZE));
+}
+
+/**
+ * @brief Set Channel priority level.
+ * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param Priority This parameter can be one of the following values:
+ * @arg @ref LL_DMA_PRIORITY_LOW
+ * @arg @ref LL_DMA_PRIORITY_MEDIUM
+ * @arg @ref LL_DMA_PRIORITY_HIGH
+ * @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
+ Priority);
+}
+
+/**
+ * @brief Get Channel priority level.
+ * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DMA_PRIORITY_LOW
+ * @arg @ref LL_DMA_PRIORITY_MEDIUM
+ * @arg @ref LL_DMA_PRIORITY_HIGH
+ * @arg @ref LL_DMA_PRIORITY_VERYHIGH
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_PL));
+}
+
+/**
+ * @brief Set Number of data to transfer.
+ * @note This action has no effect if
+ * channel is enabled.
+ * @rmtoll CNDTR NDT LL_DMA_SetDataLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
+{
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
+ DMA_CNDTR_NDT, NbData);
+}
+
+/**
+ * @brief Get Number of data to transfer.
+ * @note Once the channel is enabled, the return value indicate the
+ * remaining bytes to be transmitted.
+ * @rmtoll CNDTR NDT LL_DMA_GetDataLength
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
+ DMA_CNDTR_NDT));
+}
+
+/**
+ * @brief Configure the Source and Destination addresses.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
+ * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
+ * CMAR MA LL_DMA_ConfigAddresses
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @param Direction This parameter can be one of the following values:
+ * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+ * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
+ uint32_t DstAddress, uint32_t Direction)
+{
+ /* Direction Memory to Periph */
+ if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+ {
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
+ }
+ /* Direction Periph to Memory and Memory to Memory */
+ else
+ {
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
+ }
+}
+
+/**
+ * @brief Set the Memory address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
+}
+
+/**
+ * @brief Set the Peripheral address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
+{
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
+}
+
+/**
+ * @brief Get Memory address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
+}
+
+/**
+ * @brief Get Peripheral address.
+ * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+ * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
+}
+
+/**
+ * @brief Set the Memory to Memory Source address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
+}
+
+/**
+ * @brief Set the Memory to Memory Destination address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @note This API must not be called when the DMA channel is enabled.
+ * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
+{
+ WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
+}
+
+/**
+ * @brief Get the Memory to Memory Source address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
+}
+
+/**
+ * @brief Get the Memory to Memory Destination address.
+ * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+ * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Channel 1 global interrupt flag.
+ * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
+}
+
+/**
+ * @brief Get Channel 2 global interrupt flag.
+ * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
+}
+
+/**
+ * @brief Get Channel 3 global interrupt flag.
+ * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
+}
+
+/**
+ * @brief Get Channel 4 global interrupt flag.
+ * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
+}
+
+/**
+ * @brief Get Channel 5 global interrupt flag.
+ * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
+}
+
+/**
+ * @brief Get Channel 6 global interrupt flag.
+ * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
+}
+
+/**
+ * @brief Get Channel 7 global interrupt flag.
+ * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
+}
+
+/**
+ * @brief Get Channel 1 transfer complete flag.
+ * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
+}
+
+/**
+ * @brief Get Channel 2 transfer complete flag.
+ * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
+}
+
+/**
+ * @brief Get Channel 3 transfer complete flag.
+ * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
+}
+
+/**
+ * @brief Get Channel 4 transfer complete flag.
+ * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
+}
+
+/**
+ * @brief Get Channel 5 transfer complete flag.
+ * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
+}
+
+/**
+ * @brief Get Channel 6 transfer complete flag.
+ * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
+}
+
+/**
+ * @brief Get Channel 7 transfer complete flag.
+ * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
+}
+
+/**
+ * @brief Get Channel 1 half transfer flag.
+ * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
+}
+
+/**
+ * @brief Get Channel 2 half transfer flag.
+ * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
+}
+
+/**
+ * @brief Get Channel 3 half transfer flag.
+ * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
+}
+
+/**
+ * @brief Get Channel 4 half transfer flag.
+ * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
+}
+
+/**
+ * @brief Get Channel 5 half transfer flag.
+ * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
+}
+
+/**
+ * @brief Get Channel 6 half transfer flag.
+ * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
+}
+
+/**
+ * @brief Get Channel 7 half transfer flag.
+ * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
+}
+
+/**
+ * @brief Get Channel 1 transfer error flag.
+ * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
+}
+
+/**
+ * @brief Get Channel 2 transfer error flag.
+ * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
+}
+
+/**
+ * @brief Get Channel 3 transfer error flag.
+ * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
+}
+
+/**
+ * @brief Get Channel 4 transfer error flag.
+ * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
+}
+
+/**
+ * @brief Get Channel 5 transfer error flag.
+ * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
+}
+
+/**
+ * @brief Get Channel 6 transfer error flag.
+ * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
+}
+
+/**
+ * @brief Get Channel 7 transfer error flag.
+ * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
+ * @param DMAx DMAx Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+{
+ return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
+}
+
+/**
+ * @brief Clear Channel 1 global interrupt flag.
+ * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
+}
+
+/**
+ * @brief Clear Channel 2 global interrupt flag.
+ * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
+}
+
+/**
+ * @brief Clear Channel 3 global interrupt flag.
+ * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
+}
+
+/**
+ * @brief Clear Channel 4 global interrupt flag.
+ * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
+}
+
+/**
+ * @brief Clear Channel 5 global interrupt flag.
+ * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
+}
+
+/**
+ * @brief Clear Channel 6 global interrupt flag.
+ * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
+}
+
+/**
+ * @brief Clear Channel 7 global interrupt flag.
+ * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
+}
+
+/**
+ * @brief Clear Channel 1 transfer complete flag.
+ * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
+}
+
+/**
+ * @brief Clear Channel 2 transfer complete flag.
+ * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
+}
+
+/**
+ * @brief Clear Channel 3 transfer complete flag.
+ * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
+}
+
+/**
+ * @brief Clear Channel 4 transfer complete flag.
+ * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
+}
+
+/**
+ * @brief Clear Channel 5 transfer complete flag.
+ * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
+}
+
+/**
+ * @brief Clear Channel 6 transfer complete flag.
+ * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
+}
+
+/**
+ * @brief Clear Channel 7 transfer complete flag.
+ * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
+}
+
+/**
+ * @brief Clear Channel 1 half transfer flag.
+ * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
+}
+
+/**
+ * @brief Clear Channel 2 half transfer flag.
+ * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
+}
+
+/**
+ * @brief Clear Channel 3 half transfer flag.
+ * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
+}
+
+/**
+ * @brief Clear Channel 4 half transfer flag.
+ * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
+}
+
+/**
+ * @brief Clear Channel 5 half transfer flag.
+ * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
+}
+
+/**
+ * @brief Clear Channel 6 half transfer flag.
+ * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
+}
+
+/**
+ * @brief Clear Channel 7 half transfer flag.
+ * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
+}
+
+/**
+ * @brief Clear Channel 1 transfer error flag.
+ * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
+}
+
+/**
+ * @brief Clear Channel 2 transfer error flag.
+ * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
+}
+
+/**
+ * @brief Clear Channel 3 transfer error flag.
+ * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
+}
+
+/**
+ * @brief Clear Channel 4 transfer error flag.
+ * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
+}
+
+/**
+ * @brief Clear Channel 5 transfer error flag.
+ * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
+}
+
+/**
+ * @brief Clear Channel 6 transfer error flag.
+ * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
+}
+
+/**
+ * @brief Clear Channel 7 transfer error flag.
+ * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
+ * @param DMAx DMAx Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+{
+ WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable Transfer complete interrupt.
+ * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+ * @brief Enable Half transfer interrupt.
+ * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+ * @brief Enable Transfer error interrupt.
+ * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+ * @brief Disable Transfer complete interrupt.
+ * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
+}
+
+/**
+ * @brief Disable Half transfer interrupt.
+ * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
+}
+
+/**
+ * @brief Disable Transfer error interrupt.
+ * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
+}
+
+/**
+ * @brief Check if Transfer complete Interrupt is enabled.
+ * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_TCIE) == (DMA_CCR_TCIE));
+}
+
+/**
+ * @brief Check if Half transfer Interrupt is enabled.
+ * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_HTIE) == (DMA_CCR_HTIE));
+}
+
+/**
+ * @brief Check if Transfer error Interrupt is enabled.
+ * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ DMA_CCR_TEIE) == (DMA_CCR_TEIE));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_exti.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_exti.h
new file mode 100644
index 0000000..38e3378
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_exti.h
@@ -0,0 +1,906 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_exti.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of EXTI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_EXTI_H
+#define __STM32F1xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+ * @{
+ */
+typedef struct
+{
+
+ uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+ This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+ FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+
+ uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+ uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+ * @{
+ */
+#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
+#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
+#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
+#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
+#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
+#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
+#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
+#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
+#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
+#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
+#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
+#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
+#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
+#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
+#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
+#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
+#if defined(EXTI_IMR_IM16)
+#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
+#endif
+#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
+#if defined(EXTI_IMR_IM18)
+#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
+#endif
+#if defined(EXTI_IMR_IM19)
+#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
+#endif
+#if defined(EXTI_IMR_IM20)
+#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
+#endif
+#if defined(EXTI_IMR_IM21)
+#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
+#endif
+#if defined(EXTI_IMR_IM22)
+#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
+#endif
+#if defined(EXTI_IMR_IM23)
+#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
+#endif
+#if defined(EXTI_IMR_IM24)
+#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
+#endif
+#if defined(EXTI_IMR_IM25)
+#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
+#endif
+#if defined(EXTI_IMR_IM26)
+#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
+#endif
+#if defined(EXTI_IMR_IM27)
+#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
+#endif
+#if defined(EXTI_IMR_IM28)
+#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
+#endif
+#if defined(EXTI_IMR_IM29)
+#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
+#endif
+#if defined(EXTI_IMR_IM30)
+#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
+#endif
+#if defined(EXTI_IMR_IM31)
+#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
+#endif
+#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
+
+
+#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_EXTI_MODE_IT ((uint8_t)0x00) /*!< Interrupt Mode */
+#define LL_EXTI_MODE_EVENT ((uint8_t)0x01) /*!< Event Mode */
+#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02) /*!< Interrupt & Event Mode */
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+ * @{
+ */
+#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03) /*!< Trigger Rising & Falling Mode */
+
+/**
+ * @}
+ */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+ * @{
+ */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in EXTI register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in EXTI register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->IMR, ExtiLine);
+}
+
+/**
+ * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->IMR, ExtiLine);
+}
+
+
+/**
+ * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+ * @note The reset value for the direct or internal lines (see RM)
+ * is set to 1 in order to enable the interrupt by default.
+ * Bits are set automatically at Power on.
+ * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->EMR, ExtiLine);
+
+}
+
+
+/**
+ * @brief Disable ExtiLine Event request for Lines in range 0 to 31
+ * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->EMR, ExtiLine);
+}
+
+
+/**
+ * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+ * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
+ * @param ExtiLine This parameter can be one of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_17
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @arg @ref LL_EXTI_LINE_ALL_0_31
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
+
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+
+/**
+ * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a rising edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_RTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+
+/**
+ * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+ * @{
+ */
+
+/**
+ * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for
+ * the same interrupt line. In this case, both generate a trigger
+ * condition.
+ * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->FTSR, ExtiLine);
+}
+
+
+/**
+ * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+ * @note The configurable wakeup lines are edge-triggered. No glitch must be
+ * generated on these lines. If a Falling edge on a configurable interrupt
+ * line occurs during a write operation in the EXTI_FTSR register, the
+ * pending bit is not set.
+ * Rising and falling edge triggers can be set for the same interrupt line.
+ * In this case, both generate a trigger condition.
+ * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+ CLEAR_BIT(EXTI->FTSR, ExtiLine);
+}
+
+
+/**
+ * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
+ * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+ * @{
+ */
+
+/**
+ * @brief Generate a software Interrupt Event for Lines in range 0 to 31
+ * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
+ * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
+ * resulting in an interrupt request generation.
+ * This bit is cleared by clearing the corresponding bit in the EXTI_PR
+ * register (by writing a 1 into the bit)
+ * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+ SET_BIT(EXTI->SWIER, ExtiLine);
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+ return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+ * @brief Read ExtLine Combination Flag for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval @note This bit is set when the selected edge event arrives on the interrupt
+ */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+ return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
+}
+
+
+/**
+ * @brief Clear ExtLine Flags for Lines in range 0 to 31
+ * @note This bit is set when the selected edge event arrives on the interrupt
+ * line. This bit is cleared by writing a 1 to the bit.
+ * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
+ * @param ExtiLine This parameter can be a combination of the following values:
+ * @arg @ref LL_EXTI_LINE_0
+ * @arg @ref LL_EXTI_LINE_1
+ * @arg @ref LL_EXTI_LINE_2
+ * @arg @ref LL_EXTI_LINE_3
+ * @arg @ref LL_EXTI_LINE_4
+ * @arg @ref LL_EXTI_LINE_5
+ * @arg @ref LL_EXTI_LINE_6
+ * @arg @ref LL_EXTI_LINE_7
+ * @arg @ref LL_EXTI_LINE_8
+ * @arg @ref LL_EXTI_LINE_9
+ * @arg @ref LL_EXTI_LINE_10
+ * @arg @ref LL_EXTI_LINE_11
+ * @arg @ref LL_EXTI_LINE_12
+ * @arg @ref LL_EXTI_LINE_13
+ * @arg @ref LL_EXTI_LINE_14
+ * @arg @ref LL_EXTI_LINE_15
+ * @arg @ref LL_EXTI_LINE_16
+ * @arg @ref LL_EXTI_LINE_18
+ * @arg @ref LL_EXTI_LINE_19
+ * @note Please check each device line mapping for EXTI Line availability
+ * @retval None
+ */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+ WRITE_REG(EXTI->PR, ExtiLine);
+}
+
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+uint32_t LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* EXTI */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_EXTI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_fsmc.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_fsmc.h
index af34f38..b47bcb7 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_fsmc.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_fsmc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f1xx_ll_fsmc.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of FSMC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -56,206 +56,6 @@
* @{
*/
-/** @addtogroup FSMC_LL_Private_Macros
- * @{
- */
-
-#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
- ((__BANK__) == FSMC_NORSRAM_BANK2) || \
- ((__BANK__) == FSMC_NORSRAM_BANK3) || \
- ((__BANK__) == FSMC_NORSRAM_BANK4))
-
-#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
- ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
-
-#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
- ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
- ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
-
-#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
- ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
-
-#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
- ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
-
-#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
- ((__MODE__) == FSMC_ACCESS_MODE_B) || \
- ((__MODE__) == FSMC_ACCESS_MODE_C) || \
- ((__MODE__) == FSMC_ACCESS_MODE_D))
-
-#define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \
- ((__BANK__) == FSMC_NAND_BANK3))
-
-#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
- ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
-
-#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
-
-#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
- ((__STATE__) == FSMC_NAND_ECC_ENABLE))
-
-#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
-
-/** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time
- * @{
- */
-#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time
- * @{
- */
-#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Setup_Time FSMC_Setup_Time
- * @{
- */
-#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time
- * @{
- */
-#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time
- * @{
- */
-#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FSMC_HiZ_Setup_Time FSMC_HiZ_Setup_Time
- * @{
- */
-#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
- * @{
- */
-
-#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
- * @{
- */
-
-#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_NAND_Device_Instance FSMC NAND Device Instance
- * @{
- */
-#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
-/**
- * @}
- */
-
-/** @defgroup FSMC_PCCARD_Device_Instance FSMC PCCARD Device Instance
- * @{
- */
-#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
-
-/**
- * @}
- */
-#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
- ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
-
-#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
- ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
-
-#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
- ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
-
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
- ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
-
-#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
- ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
-
-#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
- ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
-
-#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
- ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
-
-#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
- ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
-
-#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
-
-/** @defgroup FSMC_Data_Latency FSMC Data Latency
- * @{
- */
-#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
- * @{
- */
-#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
- * @{
- */
-#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
- * @{
- */
-#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
- * @{
- */
-#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
-/**
- * @}
- */
-
-/**
- * @}
- */
/* Exported typedef ----------------------------------------------------------*/
@@ -263,18 +63,8 @@
* @{
*/
-#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
-#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
-#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
-
-#define FSMC_NORSRAM_DEVICE FSMC_Bank1
-#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
-#define FSMC_NAND_DEVICE FSMC_Bank2_3
-#define FSMC_PCCARD_DEVICE FSMC_Bank4
-
/**
- * @brief FSMC_NORSRAM Configuration Structure definition
+ * @brief FSMC NORSRAM Configuration Structure definition
*/
typedef struct
{
@@ -329,7 +119,7 @@
}FSMC_NORSRAM_InitTypeDef;
/**
- * @brief FSMC_NORSRAM Timing parameters structure definition
+ * @brief FSMC NORSRAM Timing parameters structure definition
*/
typedef struct
{
@@ -368,30 +158,30 @@
with synchronous burst mode enable */
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FSMC_Access_Mode */
+ This parameter can be a value of @ref FSMC_Access_Mode */
}FSMC_NORSRAM_TimingTypeDef;
#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
/**
- * @brief FSMC_NAND Configuration Structure definition
+ * @brief FSMC NAND Configuration Structure definition
*/
typedef struct
{
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
- This parameter can be a value of @ref FSMC_NAND_Bank */
+ This parameter can be a value of @ref FSMC_NAND_Bank */
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
- This parameter can be any value of @ref FSMC_Wait_feature */
+ This parameter can be any value of @ref FSMC_Wait_feature */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FSMC_NAND_Data_Width */
+ This parameter can be any value of @ref FSMC_NAND_Data_Width */
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FSMC_ECC */
+ This parameter can be any value of @ref FSMC_ECC */
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FSMC_ECC_Page_Size */
+ This parameter can be any value of @ref FSMC_ECC_Page_Size */
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
@@ -404,7 +194,7 @@
}FSMC_NAND_InitTypeDef;
/**
- * @brief FSMC_NAND_PCCARD Timing parameters structure definition
+ * @brief FSMC NAND/PCCARD Timing parameters structure definition
*/
typedef struct
{
@@ -435,15 +225,13 @@
}FSMC_NAND_PCC_TimingTypeDef;
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
/**
- * @brief FSMC_NAND Configuration Structure definition
+ * @brief FSMC NAND Configuration Structure definition
*/
typedef struct
{
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
- This parameter can be any value of @ref FSMC_Wait_feature */
+ This parameter can be any value of @ref FSMC_Wait_feature */
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
@@ -454,7 +242,6 @@
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
}FSMC_PCCARD_InitTypeDef;
-
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
/**
* @}
@@ -469,15 +256,13 @@
/** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants
* @{
*/
-
/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
* @{
*/
-#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
-#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
-#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
-#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
-
+#define FSMC_NORSRAM_BANK1 0x00000000U
+#define FSMC_NORSRAM_BANK2 0x00000002U
+#define FSMC_NORSRAM_BANK3 0x00000004U
+#define FSMC_NORSRAM_BANK4 0x00000006U
/**
* @}
*/
@@ -485,10 +270,8 @@
/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
* @{
*/
-
-#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
+#define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN)
-
/**
* @}
*/
@@ -496,11 +279,9 @@
/** @defgroup FSMC_Memory_Type FSMC Memory Type
* @{
*/
-
-#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
+#define FSMC_MEMORY_TYPE_SRAM 0x00000000U
#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0)
#define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1)
-
/**
* @}
*/
@@ -508,11 +289,9 @@
/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
* @{
*/
-
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0)
#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1)
-
/**
* @}
*/
@@ -520,9 +299,8 @@
/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
* @{
*/
-
#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN)
-#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
+#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
/**
* @}
*/
@@ -530,22 +308,17 @@
/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
* @{
*/
-
-#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
+#define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN)
-
/**
* @}
*/
-
/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
* @{
*/
-
-#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
+#define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL)
-
/**
* @}
*/
@@ -553,10 +326,8 @@
/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
* @{
*/
-
-#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
+#define FSMC_WRAP_MODE_DISABLE 0x00000000U
#define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD)
-
/**
* @}
*/
@@ -564,10 +335,8 @@
/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
* @{
*/
-
-#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
+#define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG)
-
/**
* @}
*/
@@ -575,10 +344,8 @@
/** @defgroup FSMC_Write_Operation FSMC Write Operation
* @{
*/
-
-#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
+#define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN)
-
/**
* @}
*/
@@ -586,10 +353,8 @@
/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
* @{
*/
-
-#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
+#define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN)
-
/**
* @}
*/
@@ -597,10 +362,8 @@
/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
* @{
*/
-
-#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
+#define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD)
-
/**
* @}
*/
@@ -608,10 +371,8 @@
/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
* @{
*/
-
-#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
+#define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT)
-
/**
* @}
*/
@@ -619,10 +380,8 @@
/** @defgroup FSMC_Write_Burst FSMC Write Burst
* @{
*/
-
-#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
+#define FSMC_WRITE_BURST_DISABLE 0x00000000U
#define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW)
-
/**
* @}
*/
@@ -630,12 +389,10 @@
/** @defgroup FSMC_Access_Mode FSMC Access Mode
* @{
*/
-
-#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000)
+#define FSMC_ACCESS_MODE_A 0x00000000U
#define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0)
#define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1)
#define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1))
-
/**
* @}
*/
@@ -648,13 +405,11 @@
/** @defgroup FSMC_NAND_Controller FSMC NAND and PCCARD Controller
* @{
*/
-
/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
* @{
*/
-#define FSMC_NAND_BANK2 ((uint32_t)0x00000010)
-#define FSMC_NAND_BANK3 ((uint32_t)0x00000100)
-
+#define FSMC_NAND_BANK2 0x00000010U
+#define FSMC_NAND_BANK3 0x00000100U
/**
* @}
*/
@@ -662,9 +417,8 @@
/** @defgroup FSMC_Wait_feature FSMC Wait feature
* @{
*/
-#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
+#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)FSMC_PCRx_PWAITEN)
-
/**
* @}
*/
@@ -672,7 +426,7 @@
/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
* @{
*/
-#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
+#define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FSMC_PCRx_PTYP)
/**
* @}
@@ -681,9 +435,8 @@
/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
* @{
*/
-#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
+#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_PCRx_PWID_0)
-
/**
* @}
*/
@@ -691,9 +444,8 @@
/** @defgroup FSMC_ECC FSMC NAND ECC
* @{
*/
-#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
+#define FSMC_NAND_ECC_DISABLE 0x00000000U
#define FSMC_NAND_ECC_ENABLE ((uint32_t)FSMC_PCRx_ECCEN)
-
/**
* @}
*/
@@ -701,38 +453,12 @@
/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
* @{
*/
-#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
+#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FSMC_PCRx_ECCPS_0)
#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FSMC_PCRx_ECCPS_1)
#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_1)
#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FSMC_PCRx_ECCPS_2)
#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_2)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Interrupt_definition FSMC Interrupt definition
- * @brief FSMC Interrupt definition
- * @{
- */
-#define FSMC_IT_RISING_EDGE ((uint32_t)FSMC_SRx_IREN)
-#define FSMC_IT_LEVEL ((uint32_t)FSMC_SRx_ILEN)
-#define FSMC_IT_FALLING_EDGE ((uint32_t)FSMC_SRx_IFEN)
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_Flag_definition FSMC Flag definition
- * @brief FSMC Flag definition
- * @{
- */
-#define FSMC_FLAG_RISING_EDGE ((uint32_t)FSMC_SRx_IRS)
-#define FSMC_FLAG_LEVEL ((uint32_t)FSMC_SRx_ILS)
-#define FSMC_FLAG_FALLING_EDGE ((uint32_t)FSMC_SRx_IFS)
-#define FSMC_FLAG_FEMPT ((uint32_t)FSMC_SRx_FEMPT)
-
/**
* @}
*/
@@ -742,33 +468,71 @@
*/
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
+/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
+ * @brief FSMC Interrupt definition
+ * @{
+ */
+#define FSMC_IT_RISING_EDGE ((uint32_t)FSMC_SRx_IREN)
+#define FSMC_IT_LEVEL ((uint32_t)FSMC_SRx_ILEN)
+#define FSMC_IT_FALLING_EDGE ((uint32_t)FSMC_SRx_IFEN)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
+ * @brief FSMC Flag definition
+ * @{
+ */
+#define FSMC_FLAG_RISING_EDGE ((uint32_t)FSMC_SRx_IRS)
+#define FSMC_FLAG_LEVEL ((uint32_t)FSMC_SRx_ILS)
+#define FSMC_FLAG_FALLING_EDGE ((uint32_t)FSMC_SRx_IFS)
+#define FSMC_FLAG_FEMPT ((uint32_t)FSMC_SRx_FEMPT)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
+ * @{
+ */
+#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
+#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
+#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
+
+#define FSMC_NORSRAM_DEVICE FSMC_Bank1
+#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
+#define FSMC_NAND_DEVICE FSMC_Bank2_3
+#define FSMC_PCCARD_DEVICE FSMC_Bank4
+/**
+ * @}
+ */
+
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
-
/** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros
* @{
*/
-/** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros
- * @brief macros to handle NOR device enable/disable and read/write operations
- * @{
- */
+/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
+ * @brief macros to handle NOR device enable/disable and read/write operations
+ * @{
+ */
/**
* @brief Enable the NORSRAM device access.
- * @param __INSTANCE__ FSMC_NORSRAM Instance
- * @param __BANK__ FSMC_NORSRAM Bank
+ * @param __INSTANCE__: FSMC_NORSRAM Instance
+ * @param __BANK__: FSMC_NORSRAM Bank
* @retval none
*/
#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
/**
* @brief Disable the NORSRAM device access.
- * @param __INSTANCE__ FSMC_NORSRAM Instance
- * @param __BANK__ FSMC_NORSRAM Bank
+ * @param __INSTANCE__: FSMC_NORSRAM Instance
+ * @param __BANK__: FSMC_NORSRAM Bank
* @retval none
*/
#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
@@ -778,48 +542,46 @@
*/
#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
-/** @defgroup FSMC_NAND_Macros FSMC NAND Macros
- * @brief macros to handle NAND device enable/disable
- * @{
- */
+/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
+ * @brief macros to handle NAND device enable/disable
+ * @{
+ */
/**
* @brief Enable the NAND device access.
- * @param __INSTANCE__ FSMC_NAND Instance
- * @param __BANK__ FSMC_NAND Bank
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
* @retval None
*/
#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
- SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
+ SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
/**
* @brief Disable the NAND device access.
- * @param __INSTANCE__ FSMC_NAND Instance
- * @param __BANK__ FSMC_NAND Bank
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
* @retval None
*/
#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
- CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
-
+ CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
/**
* @}
*/
-/** @defgroup FSMC_PCCARD_Macros FSMC PCCARD Macros
- * @brief macros to handle PCCARD read/write operations
- * @{
- */
-
+/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
+ * @brief macros to handle PCCARD read/write operations
+ * @{
+ */
/**
* @brief Enable the PCCARD device access.
- * @param __INSTANCE__ FSMC_PCCARD Instance
+ * @param __INSTANCE__: FSMC_PCCARD Instance
* @retval None
*/
#define __FSMC_PCCARD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
/**
* @brief Disable the PCCARD device access.
- * @param __INSTANCE__ FSMC_PCCARD Instance
+ * @param __INSTANCE__: FSMC_PCCARD Instance
* @retval None
*/
#define __FSMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
@@ -827,20 +589,20 @@
* @}
*/
-/** @defgroup FSMC_Interrupt FSMC Interrupt
- * @brief macros to handle FSMC interrupts
- * @{
- */
+/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
+ * @brief macros to handle FSMC flags and interrupts
+ * @{
+ */
/**
* @brief Enable the NAND device interrupt.
- * @param __INSTANCE__ FSMC_NAND Instance
- * @param __BANK__ FSMC_NAND Bank
- * @param __INTERRUPT__ FSMC_NAND interrupt
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @param __INTERRUPT__: FSMC_NAND interrupt
* This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
- * @arg FSMC_IT_LEVEL Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
@@ -848,13 +610,13 @@
/**
* @brief Disable the NAND device interrupt.
- * @param __INSTANCE__ FSMC_NAND Instance
- * @param __BANK__ FSMC_NAND Bank
- * @param __INTERRUPT__ FSMC_NAND interrupt
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @param __INTERRUPT__: FSMC_NAND interrupt
* This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
- * @arg FSMC_IT_LEVEL Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
@@ -862,29 +624,28 @@
/**
* @brief Get flag status of the NAND device.
- * @param __INSTANCE__ FSMC_NAND Instance
- * @param __BANK__ FSMC_NAND Bank
- * @param __FLAG__ FSMC_NAND flag
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__ : FSMC_NAND Bank
+ * @param __FLAG__ : FSMC_NAND flag
* This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT FIFO empty flag.
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
-
/**
* @brief Clear flag status of the NAND device.
- * @param __INSTANCE__ FSMC_NAND Instance
- * @param __BANK__ FSMC_NAND Bank
- * @param __FLAG__ FSMC_NAND flag
+ * @param __INSTANCE__: FSMC_NAND Instance
+ * @param __BANK__: FSMC_NAND Bank
+ * @param __FLAG__: FSMC_NAND flag
* This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT FIFO empty flag.
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval None
*/
#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
@@ -892,50 +653,50 @@
/**
* @brief Enable the PCCARD device interrupt.
- * @param __INSTANCE__ FSMC_PCCARD Instance
- * @param __INTERRUPT__ FSMC_PCCARD interrupt
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __INTERRUPT__: FSMC_PCCARD interrupt
* This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
- * @arg FSMC_IT_LEVEL Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
/**
* @brief Disable the PCCARD device interrupt.
- * @param __INSTANCE__ FSMC_PCCARD Instance
- * @param __INTERRUPT__ FSMC_PCCARD interrupt
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __INTERRUPT__: FSMC_PCCARD interrupt
* This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE Interrupt rising edge.
- * @arg FSMC_IT_LEVEL Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE Interrupt falling edge.
+ * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
+ * @arg FSMC_IT_LEVEL: Interrupt level.
+ * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
/**
* @brief Get flag status of the PCCARD device.
- * @param __INSTANCE__ FSMC_PCCARD Instance
- * @param __FLAG__ FSMC_PCCARD flag
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __FLAG__: FSMC_PCCARD flag
* This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT FIFO empty flag.
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
/**
* @brief Clear flag status of the PCCARD device.
- * @param __INSTANCE__ FSMC_PCCARD Instance
- * @param __FLAG__ FSMC_PCCARD flag
+ * @param __INSTANCE__: FSMC_PCCARD Instance
+ * @param __FLAG__: FSMC_PCCARD flag
* This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT FIFO empty flag.
+ * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
+ * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
+ * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
+ * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval None
*/
#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
@@ -943,46 +704,296 @@
/**
* @}
*/
-
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
/**
* @}
*/
+/** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros
+ * @{
+ */
+#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK2) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK3) || \
+ ((__BANK__) == FSMC_NORSRAM_BANK4))
+
+#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
+ ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
+
+#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
+ ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
+ ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
+
+#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
+
+#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
+ ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
+
+#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_B) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_C) || \
+ ((__MODE__) == FSMC_ACCESS_MODE_D))
+
+#define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \
+ ((__BANK__) == FSMC_NAND_BANK3))
+
+#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
+ ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
+
+#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
+ ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
+
+#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
+ ((__STATE__) == FSMC_NAND_ECC_ENABLE))
+
+#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+
+/** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time
+ * @{
+ */
+#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time
+ * @{
+ */
+#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Setup_Time FSMC_Setup_Time
+ * @{
+ */
+#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255U)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time
+ * @{
+ */
+#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255U)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time
+ * @{
+ */
+#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255U)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_HiZ_Setup_Time FSMC_HiZ_Setup_Time
+ * @{
+ */
+#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255U)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
+ * @{
+ */
+#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
+ * @{
+ */
+#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_NAND_Device_Instance FSMC NAND Device Instance
+ * @{
+ */
+#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_PCCARD_Device_Instance FSMC PCCARD Device Instance
+ * @{
+ */
+#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
+
+/**
+ * @}
+ */
+#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
+ ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
+
+#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
+ ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
+
+#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
+ ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
+
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
+ ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
+
+#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
+ ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
+
+#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
+ ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
+
+#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
+ ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
+
+#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
+ ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
+
+#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
+
+/** @defgroup FSMC_Data_Latency FSMC Data Latency
+ * @{
+ */
+#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
+ * @{
+ */
+#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
+ * @{
+ */
+#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
+ * @{
+ */
+#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
+ * @{
+ */
+#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
+ * @{
+ */
+
+/* ----------------------- FSMC registers bit mask --------------------------- */
+#if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
+/* --- PCR Register ---*/
+/* PCR register clear mask */
+#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN | \
+ FSMC_PCRx_PTYP | FSMC_PCRx_PWID | \
+ FSMC_PCRx_ECCEN | FSMC_PCRx_TCLR | \
+ FSMC_PCRx_TAR | FSMC_PCRx_ECCPS))
+
+/* --- PMEM Register ---*/
+/* PMEM register clear mask */
+#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEMx_MEMSETx | FSMC_PMEMx_MEMWAITx |\
+ FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx))
+
+/* --- PATT Register ---*/
+/* PATT register clear mask */
+#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATTx_ATTSETx | FSMC_PATTx_ATTWAITx |\
+ FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx))
+
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
+/* --- BCR Register ---*/
+/* BCR register clear mask */
+#define BCR_CLEAR_MASK ((uint32_t)(FSMC_BCRx_FACCEN | FSMC_BCRx_MUXEN | \
+ FSMC_BCRx_MTYP | FSMC_BCRx_MWID | \
+ FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL | \
+ FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \
+ FSMC_BCRx_WREN | FSMC_BCRx_WAITEN | \
+ FSMC_BCRx_EXTMOD | FSMC_BCRx_ASYNCWAIT | \
+ FSMC_BCRx_CBURSTRW))
+/* --- BTR Register ---*/
+/* BTR register clear mask */
+#define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD |\
+ FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
+ FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT |\
+ FSMC_BTRx_ACCMOD))
+
+/* --- BWTR Register ---*/
+/* BWTR register clear mask */
+#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
+#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \
+ FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \
+ FSMC_BWTRx_BUSTURN))
+#else
+#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \
+ FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \
+ FSMC_BWTRx_CLKDIV | FSMC_BWTRx_DATLAT))
+#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
+
+/* --- PIO4 Register ---*/
+/* PIO4 register clear mask */
+#define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | \
+ FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FSMC_LL_Exported_Functions
- * @{
- */
+ * @{
+ */
/** @addtogroup FSMC_NORSRAM
- * @{
- */
+ * @{
+ */
/** @addtogroup FSMC_NORSRAM_Group1
- * @{
- */
-
+ * @{
+ */
/* FSMC_NORSRAM Controller functions ******************************************/
/* Initialization/de-initialization functions */
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
-
/**
* @}
*/
/** @addtogroup FSMC_NORSRAM_Group2
- * @{
- */
-
+ * @{
+ */
/* FSMC_NORSRAM Control functions */
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-
/**
* @}
*/
@@ -993,33 +1004,29 @@
#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
/** @addtogroup FSMC_NAND
- * @{
- */
+ * @{
+ */
/* FSMC_NAND Controller functions **********************************************/
/* Initialization/de-initialization functions */
/** @addtogroup FSMC_NAND_Exported_Functions_Group1
- * @{
- */
-
+ * @{
+ */
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
-
/**
* @}
*/
/* FSMC_NAND Control functions */
/** @addtogroup FSMC_NAND_Exported_Functions_Group2
- * @{
- */
-
+ * @{
+ */
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
-
/**
* @}
*/
@@ -1029,21 +1036,19 @@
*/
/** @addtogroup FSMC_PCCARD
- * @{
- */
+ * @{
+ */
/* FSMC_PCCARD Controller functions ********************************************/
/* Initialization/de-initialization functions */
/** @addtogroup FSMC_PCCARD_Exported_Functions_Group1
- * @{
- */
-
+ * @{
+ */
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
-
/**
* @}
*/
@@ -1051,8 +1056,8 @@
/**
* @}
*/
-
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
+
/**
* @}
*/
@@ -1060,7 +1065,6 @@
/**
* @}
*/
-
#endif /* FSMC_BANK1 */
/**
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_gpio.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_gpio.h
new file mode 100644
index 0000000..6035560
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_gpio.h
@@ -0,0 +1,2381 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_gpio.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of GPIO LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_GPIO_H
+#define __STM32F1xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
+
+/** @defgroup GPIO_LL GPIO
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_LL_Private_Constants GPIO Private Constants
+ * @{
+ */
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL GPIO Init Structure definition
+ */
+typedef struct
+{
+ uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+ uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
+
+ uint32_t Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+ uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+ uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+ This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+ GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
+}LL_GPIO_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+ * @{
+ */
+#define LL_GPIO_PIN_0 (GPIO_BSRR_BS0 << 8) | 0x00000001U /*!< Select pin 0 */
+#define LL_GPIO_PIN_1 (GPIO_BSRR_BS1 << 8) | 0x00000002U /*!< Select pin 1 */
+#define LL_GPIO_PIN_2 (GPIO_BSRR_BS2 << 8) | 0x00000004U /*!< Select pin 2 */
+#define LL_GPIO_PIN_3 (GPIO_BSRR_BS3 << 8) | 0x00000008U /*!< Select pin 3 */
+#define LL_GPIO_PIN_4 (GPIO_BSRR_BS4 << 8) | 0x00000010U /*!< Select pin 4 */
+#define LL_GPIO_PIN_5 (GPIO_BSRR_BS5 << 8) | 0x00000020U /*!< Select pin 5 */
+#define LL_GPIO_PIN_6 (GPIO_BSRR_BS6 << 8) | 0x00000040U /*!< Select pin 6 */
+#define LL_GPIO_PIN_7 (GPIO_BSRR_BS7 << 8) | 0x00000080U /*!< Select pin 7 */
+#define LL_GPIO_PIN_8 (GPIO_BSRR_BS8 << 8) | 0x04000001U /*!< Select pin 8 */
+#define LL_GPIO_PIN_9 (GPIO_BSRR_BS9 << 8) | 0x04000002U /*!< Select pin 9 */
+#define LL_GPIO_PIN_10 (GPIO_BSRR_BS10 << 8) | 0x04000004U /*!< Select pin 10 */
+#define LL_GPIO_PIN_11 (GPIO_BSRR_BS11 << 8) | 0x04000008U /*!< Select pin 11 */
+#define LL_GPIO_PIN_12 (GPIO_BSRR_BS12 << 8) | 0x04000010U /*!< Select pin 12 */
+#define LL_GPIO_PIN_13 (GPIO_BSRR_BS13 << 8) | 0x04000020U /*!< Select pin 13 */
+#define LL_GPIO_PIN_14 (GPIO_BSRR_BS14 << 8) | 0x04000040U /*!< Select pin 14 */
+#define LL_GPIO_PIN_15 (GPIO_BSRR_BS15 << 8) | 0x04000080U /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \
+ LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \
+ LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \
+ LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \
+ LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \
+ LL_GPIO_PIN_15) /*!< Select all pins */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+ * @{
+ */
+#define LL_GPIO_MODE_ANALOG 0x00000000U /*!< Select analog mode */
+#define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /*!< Select floating mode */
+#define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /*!< Select general purpose output mode */
+#define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0) /*!< Select alternate function mode */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+ * @{
+ */
+#define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /*!< Select open-drain as output type */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+ * @{
+ */
+#define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /*!< Select Output mode, max speed 10 MHz */
+#define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /*!< Select Output mode, max speed 20 MHz */
+#define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /*!< Select Output mode, max speed 50 MHz */
+/**
+ * @}
+ */
+
+#define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /*!< Select I/O low output speed */
+#define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /*!< Select I/O high output speed */
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+ * @{
+ */
+#define LL_GPIO_PULL_DOWN 0x00000000U /*!< Select I/O pull down */
+#define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /*!< Select I/O pull up */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin
+ * @{
+ */
+
+#define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
+#define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
+#define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
+#define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
+#define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
+#define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
+#define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
+#define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
+#define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
+#define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
+#define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
+#define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
+#define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
+#define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
+#define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
+#define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port
+ * @{
+ */
+
+#define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
+#define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
+#define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
+#define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
+#define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT
+ * @{
+ */
+#define LL_GPIO_AF_EXTI_PORTA (uint32_t)0 /*!< EXTI PORT A */
+#define LL_GPIO_AF_EXTI_PORTB (uint32_t)1 /*!< EXTI PORT B */
+#define LL_GPIO_AF_EXTI_PORTC (uint32_t)2 /*!< EXTI PORT C */
+#define LL_GPIO_AF_EXTI_PORTD (uint32_t)3 /*!< EXTI PORT D */
+#define LL_GPIO_AF_EXTI_PORTE (uint32_t)4 /*!< EXTI PORT E */
+#define LL_GPIO_AF_EXTI_PORTF (uint32_t)5 /*!< EXTI PORT F */
+#define LL_GPIO_AF_EXTI_PORTG (uint32_t)6 /*!< EXTI PORT G */
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE
+ * @{
+ */
+#define LL_GPIO_AF_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /*!< EXTI_POSITION_0 | EXTICR[0] */
+#define LL_GPIO_AF_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /*!< EXTI_POSITION_4 | EXTICR[0] */
+#define LL_GPIO_AF_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /*!< EXTI_POSITION_8 | EXTICR[0] */
+#define LL_GPIO_AF_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /*!< EXTI_POSITION_12 | EXTICR[0] */
+#define LL_GPIO_AF_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /*!< EXTI_POSITION_0 | EXTICR[1] */
+#define LL_GPIO_AF_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /*!< EXTI_POSITION_4 | EXTICR[1] */
+#define LL_GPIO_AF_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /*!< EXTI_POSITION_8 | EXTICR[1] */
+#define LL_GPIO_AF_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /*!< EXTI_POSITION_12 | EXTICR[1] */
+#define LL_GPIO_AF_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /*!< EXTI_POSITION_0 | EXTICR[2] */
+#define LL_GPIO_AF_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /*!< EXTI_POSITION_4 | EXTICR[2] */
+#define LL_GPIO_AF_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /*!< EXTI_POSITION_8 | EXTICR[2] */
+#define LL_GPIO_AF_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /*!< EXTI_POSITION_12 | EXTICR[2] */
+#define LL_GPIO_AF_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /*!< EXTI_POSITION_0 | EXTICR[3] */
+#define LL_GPIO_AF_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /*!< EXTI_POSITION_4 | EXTICR[3] */
+#define LL_GPIO_AF_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /*!< EXTI_POSITION_8 | EXTICR[3] */
+#define LL_GPIO_AF_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /*!< EXTI_POSITION_12 | EXTICR[3] */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in GPIO register
+ * @param __INSTANCE__ GPIO Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+ * @{
+ */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+ * @{
+ */
+
+/**
+ * @brief Configure gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
+ * Alternate function Output.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll CRL CNFy LL_GPIO_SetPinMode
+ * @rmtoll CRL MODEy LL_GPIO_SetPinMode
+ * @rmtoll CRH CNFy LL_GPIO_SetPinMode
+ * @rmtoll CRH MODEy LL_GPIO_SetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ * @arg @ref LL_GPIO_MODE_FLOATING
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
+ MODIFY_REG(*pReg, ((GPIO_CRL_CNF0|GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+ * @brief Return gpio mode for a dedicated pin on dedicated port.
+ * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
+ * Alternate function Output.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll CRL CNFy LL_GPIO_GetPinMode
+ * @rmtoll CRL MODEy LL_GPIO_GetPinMode
+ * @rmtoll CRH CNFy LL_GPIO_GetPinMode
+ * @rmtoll CRH MODEy LL_GPIO_GetPinMode
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_MODE_ANALOG
+ * @arg @ref LL_GPIO_MODE_FLOATING
+ * @arg @ref LL_GPIO_MODE_INPUT
+ * @arg @ref LL_GPIO_MODE_OUTPUT
+ * @arg @ref LL_GPIO_MODE_ALTERNATE
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
+ return (uint32_t)(READ_BIT(*pReg,
+ ((GPIO_CRL_CNF0|GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+}
+
+/**
+ * @brief Configure gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium or Fast speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll CRL MODEy LL_GPIO_SetPinSpeed
+ * @rmtoll CRH MODEy LL_GPIO_SetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Speed This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
+ MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)),
+ (Speed << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+ * @brief Return gpio speed for a dedicated pin on dedicated port.
+ * @note I/O speed can be Low, Medium, Fast or High speed.
+ * @note Warning: only one pin can be passed as parameter.
+ * @note Refer to datasheet for frequency specifications and the power
+ * supply and load conditions for each speed.
+ * @rmtoll CRL MODEy LL_GPIO_GetPinSpeed
+ * @rmtoll CRH MODEy LL_GPIO_GetPinSpeed
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_SPEED_FREQ_LOW
+ * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+ * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
+ return (uint32_t)(READ_BIT(*pReg,
+ (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+}
+
+/**
+ * @brief Configure gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @rmtoll CRL MODEy LL_GPIO_SetPinOutputType
+ * @rmtoll CRH MODEy LL_GPIO_SetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @param OutputType This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
+ MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)),
+ (OutputType << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+ * @brief Return gpio output type for several pins on dedicated port.
+ * @note Output type as to be set when gpio pin is in output or
+ * alternate modes. Possible type are Push-pull or Open-drain.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll CRL MODEy LL_GPIO_GetPinOutputType
+ * @rmtoll CRH MODEy LL_GPIO_GetPinOutputType
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+ * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24)));
+ return (uint32_t)(READ_BIT(*pReg,
+ (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+
+}
+
+/**
+ * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll ODR ODR LL_GPIO_SetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @param Pull This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_DOWN
+ * @arg @ref LL_GPIO_PULL_UP
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+ MODIFY_REG(GPIOx->ODR, (Pin>>8) , Pull << (POSITION_VAL(Pin>>8)));
+}
+
+/**
+ * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+ * @note Warning: only one pin can be passed as parameter.
+ * @rmtoll ODR ODR LL_GPIO_GetPinPull
+ * @param GPIOx GPIO Port
+ * @param Pin This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_PULL_DOWN
+ * @arg @ref LL_GPIO_PULL_UP
+ */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+ return (uint32_t)(READ_BIT(GPIOx->ODR,
+ (GPIO_ODR_ODR0 << (POSITION_VAL(Pin>>8)))) >> (POSITION_VAL(Pin>>8)));
+}
+
+/**
+ * @brief Lock configuration of several pins for a dedicated port.
+ * @note When the lock sequence has been applied on a port bit, the
+ * value of this port bit can no longer be modified until the
+ * next reset.
+ * @note Each lock bit freezes a specific configuration register
+ * (control and alternate function registers).
+ * @rmtoll LCKR LCKK LL_GPIO_LockPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ __IO uint32_t temp;
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> 8) & 0x0000FFFFU));
+ WRITE_REG(GPIOx->LCKR, ((PinMask >>8 ) & 0x0000FFFFU));
+ WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask>>8) & 0x0000FFFFU));
+ temp = READ_REG(GPIOx->LCKR);
+ (void) temp;
+}
+
+/**
+ * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+ * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return (READ_BIT(GPIOx->LCKR, ((PinMask >> 8 ) & 0x0000FFFFU)) == ((PinMask >>8 ) & 0x0000FFFFU));
+}
+
+/**
+ * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
+ * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
+ * @param GPIOx GPIO Port
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+ return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+ * @{
+ */
+
+/**
+ * @brief Return full input data register value for a dedicated port.
+ * @rmtoll IDR IDy LL_GPIO_ReadInputPort
+ * @param GPIOx GPIO Port
+ * @retval Input data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+ return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return (READ_BIT(GPIOx->IDR, (PinMask >> 8 ) & 0x0000FFFFU) == ((PinMask >> 8 ) & 0x0000FFFFU));
+}
+
+/**
+ * @brief Write output data register for the port.
+ * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
+ * @param GPIOx GPIO Port
+ * @param PortValue Level value for each pin of the port
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+ WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+ * @brief Return full output data register value for a dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
+ * @param GPIOx GPIO Port
+ * @retval Output data register value of port
+ */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+ return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+ * @brief Return if input data level for several pins of dedicated port is high or low.
+ * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ return (READ_BIT(GPIOx->ODR, (PinMask >> 8 ) & 0x0000FFFFU) == ((PinMask >> 8 ) & 0x0000FFFFU));
+}
+
+/**
+ * @brief Set several pins to high level on dedicated gpio port.
+ * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->BSRR, (PinMask >> 8) & 0x0000FFFFU);
+}
+
+/**
+ * @brief Set several pins to low level on dedicated gpio port.
+ * @rmtoll BRR BRy LL_GPIO_ResetOutputPin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->BRR, (PinMask >> 8 ) & 0x0000FFFFU);
+}
+
+/**
+ * @brief Toggle data value for several pin of dedicated port.
+ * @rmtoll ODR ODy LL_GPIO_TogglePin
+ * @param GPIOx GPIO Port
+ * @param PinMask This parameter can be a combination of the following values:
+ * @arg @ref LL_GPIO_PIN_0
+ * @arg @ref LL_GPIO_PIN_1
+ * @arg @ref LL_GPIO_PIN_2
+ * @arg @ref LL_GPIO_PIN_3
+ * @arg @ref LL_GPIO_PIN_4
+ * @arg @ref LL_GPIO_PIN_5
+ * @arg @ref LL_GPIO_PIN_6
+ * @arg @ref LL_GPIO_PIN_7
+ * @arg @ref LL_GPIO_PIN_8
+ * @arg @ref LL_GPIO_PIN_9
+ * @arg @ref LL_GPIO_PIN_10
+ * @arg @ref LL_GPIO_PIN_11
+ * @arg @ref LL_GPIO_PIN_12
+ * @arg @ref LL_GPIO_PIN_13
+ * @arg @ref LL_GPIO_PIN_14
+ * @arg @ref LL_GPIO_PIN_15
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ ((PinMask >> 8 ) & 0x0000FFFFU));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping
+ * @brief This section propose definition to remap the alternate function to some other port/pins.
+ * @{
+ */
+
+/**
+ * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
+ * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1
+ * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
+ * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1
+ * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
+}
+
+/**
+ * @brief Check if SPI1 has been remaped or not
+ * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP));
+}
+
+/**
+ * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
+ * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1
+ * @note ENABLE: Remap (SCL/PB8, SDA/PB9)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
+ * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1
+ * @note DISABLE: No remap (SCL/PB6, SDA/PB7)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
+}
+
+/**
+ * @brief Check if I2C1 has been remaped or not
+ * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP));
+}
+
+/**
+ * @brief Enable the remapping of USART1 alternate function TX and RX.
+ * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1
+ * @note ENABLE: Remap (TX/PB6, RX/PB7)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of USART1 alternate function TX and RX.
+ * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1
+ * @note DISABLE: No remap (TX/PA9, RX/PA10)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
+}
+
+/**
+ * @brief Check if USART1 has been remaped or not
+ * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP));
+}
+
+/**
+ * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
+ * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2
+ * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
+ * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2
+ * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
+}
+
+/**
+ * @brief Check if USART2 has been remaped or not
+ * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP));
+}
+
+#if defined (AFIO_MAPR_USART3_REMAP)
+/**
+ * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3
+ * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_FULLREMAP);
+}
+
+/**
+ * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3
+ * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_PARTIALREMAP);
+}
+
+/**
+ * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
+ * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3
+ * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_NOREMAP);
+}
+#endif
+
+/**
+ * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1
+ * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_FULLREMAP);
+}
+
+/**
+ * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1
+ * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
+ * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1
+ * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_NOREMAP);
+}
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2
+ * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_FULLREMAP);
+}
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2
+ * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2);
+}
+
+/**
+ * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2
+ * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1);
+}
+
+/**
+ * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
+ * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2
+ * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_NOREMAP);
+}
+
+/**
+ * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
+ * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3
+ * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
+ * @note TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_FULLREMAP);
+}
+
+/**
+ * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
+ * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3
+ * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
+ * @note TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
+ * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3
+ * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
+ * @note TIM3_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_NOREMAP);
+}
+
+#if defined(AFIO_MAPR_TIM4_REMAP)
+/**
+ * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
+ * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4
+ * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
+ * @note TIM4_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
+}
+/**
+ * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
+ * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4
+ * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
+ * @note TIM4_ETR on PE0 is not re-mapped.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
+}
+
+/**
+ * @brief Check if TIM4 has been remaped or not
+ * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1
+ * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP1);
+}
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1
+ * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP2);
+}
+
+/**
+ * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
+ * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1
+ * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP3);
+}
+#endif
+
+/**
+ * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
+ * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
+ * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
+ * on 100-pin and 144-pin packages, no need for remapping).
+ * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01
+ * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
+ * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
+ * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
+ * on 100-pin and 144-pin packages, no need for remapping).
+ * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01
+ * @note DISABLE: No remapping of PD0 and PD1
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
+}
+
+/**
+ * @brief Check if PD01 has been remaped or not
+ * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP));
+}
+
+#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
+/**
+ * @brief Enable the remapping of TIM5CH4.
+ * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4
+ * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
+ * @note This function is available only in high density value line devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM5CH4.
+ * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4
+ * @note DISABLE: TIM5_CH4 is connected to PA3
+ * @note This function is available only in high density value line devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
+}
+
+/**
+ * @brief Check if TIM5CH4 has been remaped or not
+ * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR_ETH_REMAP)
+/**
+ * @brief Enable the remapping of Ethernet MAC connections with the PHY.
+ * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH
+ * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of Ethernet MAC connections with the PHY.
+ * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH
+ * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
+}
+
+/**
+ * @brief Check if ETH has been remaped or not
+ * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR_CAN2_REMAP)
+
+/**
+ * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
+ * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2
+ * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
+}
+/**
+ * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
+ * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2
+ * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
+}
+
+/**
+ * @brief Check if CAN2 has been remaped or not
+ * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR_MII_RMII_SEL)
+/**
+ * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
+ * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII
+ * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
+}
+
+/**
+ * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
+ * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII
+ * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
+}
+#endif
+
+#if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
+/**
+ * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
+ * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ
+ * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
+ * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ
+ * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
+}
+
+/**
+ * @brief Check if ADC1_ETRGINJ has been remaped or not
+ * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP)
+/**
+ * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
+ * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG
+ * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
+ * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG
+ * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
+}
+
+/**
+ * @brief Check if ADC1_ETRGREG has been remaped or not
+ * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
+ * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ
+ * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
+ * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ
+ * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
+}
+
+/**
+ * @brief Check if ADC2_ETRGINJ has been remaped or not
+ * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP));
+}
+#endif
+
+#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG
+ * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG
+ * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
+}
+
+/**
+ * @brief Check if ADC2_ETRGREG has been remaped or not
+ * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP));
+}
+#endif
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ
+ * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void)
+{
+ CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET);
+}
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST
+ * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void)
+{
+ CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST);
+}
+
+/**
+ * @brief Enable the Serial wire JTAG configuration
+ * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG
+ * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void)
+{
+ CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE);
+}
+
+/**
+ * @brief Disable the Serial wire JTAG configuration
+ * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ
+ * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void)
+{
+ CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE);
+}
+
+#if defined(AFIO_MAPR_SPI3_REMAP)
+
+/**
+ * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
+ * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3
+ * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
+ * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3
+ * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
+}
+
+/**
+ * @brief Check if SPI3 has been remaped or not
+ * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void)
+{
+ return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
+
+/**
+ * @brief Control of TIM2_ITR1 internal mapping.
+ * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB
+ * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
+}
+
+/**
+ * @brief Control of TIM2_ITR1 internal mapping.
+ * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH
+ * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
+}
+#endif
+
+#if defined(AFIO_MAPR_PTP_PPS_REMAP)
+
+/**
+ * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS
+ * @note ENABLE: PTP_PPS is output on PB5 pin.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void)
+{
+ SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
+ * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS
+ * @note DISABLE: PTP_PPS not output on PB5 pin.
+ * @note This bit is available only in connectivity line devices and is reserved otherwise.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void)
+{
+ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM9_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
+ * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9
+ * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
+ * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9
+ * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
+}
+
+/**
+ * @brief Check if TIM9_CH1 and TIM9_CH2 have been remaped or not
+ * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM10_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM10_CH1.
+ * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10
+ * @note ENABLE: Remap (TIM10_CH1 on PF6).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM10_CH1.
+ * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10
+ * @note DISABLE: No remap (TIM10_CH1 on PB8).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
+}
+
+/**
+ * @brief Check if TIM10_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM11_REMAP)
+/**
+ * @brief Enable the remapping of TIM11_CH1.
+ * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11
+ * @note ENABLE: Remap (TIM11_CH1 on PF7).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM11_CH1.
+ * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11
+ * @note DISABLE: No remap (TIM11_CH1 on PB9).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
+}
+
+/**
+ * @brief Check if TIM11_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM13_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM13_CH1.
+ * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13
+ * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM13_CH1.
+ * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13
+ * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
+}
+
+/**
+ * @brief Check if TIM13_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM14_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM14_CH1.
+ * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14
+ * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM14_CH1.
+ * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14
+ * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
+}
+
+/**
+ * @brief Check if TIM14_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
+
+/**
+ * @brief Controls the use of the optional FSMC_NADV signal.
+ * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV
+ * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
+}
+
+/**
+ * @brief Controls the use of the optional FSMC_NADV signal.
+ * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV
+ * @note CONNECTED: The NADV signal is connected to the output (default).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM15_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
+ * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15
+ * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
+}
+/**
+ * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
+ * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15
+ * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
+}
+
+/**
+ * @brief Check if TIM15_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM16_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM16_CH1.
+ * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16
+ * @note ENABLE: Remap (TIM16_CH1 on PA6).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM16_CH1.
+ * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16
+ * @note DISABLE: No remap (TIM16_CH1 on PB8).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
+}
+
+/**
+ * @brief Check if TIM16_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM17_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM17_CH1.
+ * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17
+ * @note ENABLE: Remap (TIM17_CH1 on PA7).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM17_CH1.
+ * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17
+ * @note DISABLE: No remap (TIM17_CH1 on PB9).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
+}
+
+/**
+ * @brief Check if TIM17_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_CEC_REMAP)
+
+/**
+ * @brief Enable the remapping of CEC.
+ * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC
+ * @note ENABLE: Remap (CEC on PB10).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of CEC.
+ * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC
+ * @note DISABLE: No remap (CEC on PB8).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
+}
+
+/**
+ * @brief Check if CEC has been remaped or not
+ * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
+ * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA
+ * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
+}
+
+/**
+ * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
+ * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA
+ * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
+}
+
+/**
+ * @brief Check if TIM1DMA has been remaped or not
+ * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
+
+/**
+ * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
+ * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA
+ * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
+}
+
+/**
+ * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
+ * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA
+ * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
+}
+
+/**
+ * @brief Check if TIM67DACDMA has been remaped or not
+ * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_TIM12_REMAP)
+
+/**
+ * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
+ * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12
+ * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
+}
+
+/**
+ * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
+ * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12
+ * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
+}
+
+/**
+ * @brief Check if TIM12_CH1 has been remaped or not
+ * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP));
+}
+#endif
+
+#if defined(AFIO_MAPR2_MISC_REMAP)
+
+/**
+ * @brief Miscellaneous features remapping.
+ * This bit is set and cleared by software. It controls miscellaneous features.
+ * The DMA2 channel 5 interrupt position in the vector table.
+ * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
+ * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC
+ * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
+ * selected as DAC Trigger 3, TIM15 triggers TIM1/3.
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void)
+{
+ SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
+}
+
+/**
+ * @brief Miscellaneous features remapping.
+ * This bit is set and cleared by software. It controls miscellaneous features.
+ * The DMA2 channel 5 interrupt position in the vector table.
+ * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
+ * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC
+ * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
+ * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
+ * @note This bit is available only in high density value line devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void)
+{
+ CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
+}
+
+/**
+ * @brief Check if MISC has been remaped or not
+ * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void)
+{
+ return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP));
+}
+#endif
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration
+ * @brief This section propose definition to Configure EVENTOUT Cortex feature .
+ * @{
+ */
+
+/**
+ * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
+ * @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n
+ * EVCR PIN LL_GPIO_AF_ConfigEventout
+ * @param LL_GPIO_PortSource This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E
+ * @param LL_GPIO_PinSource This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14
+ * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15
+ * @retval None
+*/
+__STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource)
+{
+ MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (LL_GPIO_PortSource) | (LL_GPIO_PinSource));
+}
+
+/**
+ * @brief Enables the Event Output.
+ * @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_EnableEventout(void)
+{
+ SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
+}
+
+/**
+ * @brief Disables the Event Output.
+ * @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_DisableEventout(void)
+{
+ CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
+}
+
+/**
+ * @}
+ */
+/** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt
+ * @brief This section Configure source input for the EXTI external interrupt .
+ * @{
+ */
+
+/**
+ * @brief Configure source input for the EXTI external interrupt.
+ * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n
+ * AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n
+ * AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n
+ * AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource
+ * @param Port This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_EXTI_PORTA
+ * @arg @ref LL_GPIO_AF_EXTI_PORTB
+ * @arg @ref LL_GPIO_AF_EXTI_PORTC
+ * @arg @ref LL_GPIO_AF_EXTI_PORTD
+ * @arg @ref LL_GPIO_AF_EXTI_PORTE
+ * @arg @ref LL_GPIO_AF_EXTI_PORTF
+ * @arg @ref LL_GPIO_AF_EXTI_PORTG
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_EXTI_LINE0
+ * @arg @ref LL_GPIO_AF_EXTI_LINE1
+ * @arg @ref LL_GPIO_AF_EXTI_LINE2
+ * @arg @ref LL_GPIO_AF_EXTI_LINE3
+ * @arg @ref LL_GPIO_AF_EXTI_LINE4
+ * @arg @ref LL_GPIO_AF_EXTI_LINE5
+ * @arg @ref LL_GPIO_AF_EXTI_LINE6
+ * @arg @ref LL_GPIO_AF_EXTI_LINE7
+ * @arg @ref LL_GPIO_AF_EXTI_LINE8
+ * @arg @ref LL_GPIO_AF_EXTI_LINE9
+ * @arg @ref LL_GPIO_AF_EXTI_LINE10
+ * @arg @ref LL_GPIO_AF_EXTI_LINE11
+ * @arg @ref LL_GPIO_AF_EXTI_LINE12
+ * @arg @ref LL_GPIO_AF_EXTI_LINE13
+ * @arg @ref LL_GPIO_AF_EXTI_LINE14
+ * @arg @ref LL_GPIO_AF_EXTI_LINE15
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+ MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
+}
+
+/**
+ * @brief Get the configured defined for specific EXTI Line
+ * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n
+ * AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n
+ * AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n
+ * AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource
+ * @param Line This parameter can be one of the following values:
+ * @arg @ref LL_GPIO_AF_EXTI_LINE0
+ * @arg @ref LL_GPIO_AF_EXTI_LINE1
+ * @arg @ref LL_GPIO_AF_EXTI_LINE2
+ * @arg @ref LL_GPIO_AF_EXTI_LINE3
+ * @arg @ref LL_GPIO_AF_EXTI_LINE4
+ * @arg @ref LL_GPIO_AF_EXTI_LINE5
+ * @arg @ref LL_GPIO_AF_EXTI_LINE6
+ * @arg @ref LL_GPIO_AF_EXTI_LINE7
+ * @arg @ref LL_GPIO_AF_EXTI_LINE8
+ * @arg @ref LL_GPIO_AF_EXTI_LINE9
+ * @arg @ref LL_GPIO_AF_EXTI_LINE10
+ * @arg @ref LL_GPIO_AF_EXTI_LINE11
+ * @arg @ref LL_GPIO_AF_EXTI_LINE12
+ * @arg @ref LL_GPIO_AF_EXTI_LINE13
+ * @arg @ref LL_GPIO_AF_EXTI_LINE14
+ * @arg @ref LL_GPIO_AF_EXTI_LINE15
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_GPIO_AF_EXTI_PORTA
+ * @arg @ref LL_GPIO_AF_EXTI_PORTB
+ * @arg @ref LL_GPIO_AF_EXTI_PORTC
+ * @arg @ref LL_GPIO_AF_EXTI_PORTD
+ * @arg @ref LL_GPIO_AF_EXTI_PORTE
+ * @arg @ref LL_GPIO_AF_EXTI_PORTF
+ * @arg @ref LL_GPIO_AF_EXTI_PORTG
+ */
+__STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line)
+{
+ return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_i2c.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_i2c.h
new file mode 100644
index 0000000..98081dd
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_i2c.h
@@ -0,0 +1,1802 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_i2c.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of I2C LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_I2C_H
+#define __STM32F1xx_LL_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (I2C1) || defined (I2C2)
+
+/** @defgroup I2C_LL I2C
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_LL_Private_Constants I2C Private Constants
+ * @{
+ */
+
+/* Defines used to perform compute and check in the macros */
+#define LL_I2C_MAX_SPEED_STANDARD 100000U
+#define LL_I2C_MAX_SPEED_FAST 400000U
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_Private_Macros I2C Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
+ * @{
+ */
+typedef struct
+{
+ uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
+ This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
+
+ uint32_t ClockSpeed; /*!< Specifies the clock frequency.
+ This parameter must be set to a value lower than 400kHz (in Hz)
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
+ or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
+
+ uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
+ This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
+
+ uint32_t OwnAddress1; /*!< Specifies the device own address 1.
+ This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+
+ uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
+
+ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
+ This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
+
+ This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+} LL_I2C_InitTypeDef;
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
+ * @{
+ */
+
+/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_I2C_ReadReg function
+ * @{
+ */
+#define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */
+#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
+ Address matched flag (slave mode) */
+#define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */
+#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */
+#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */
+#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */
+#define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */
+#define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */
+#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */
+#define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */
+#define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */
+#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
+#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
+#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */
+#define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */
+#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */
+#define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */
+#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */
+#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */
+#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */
+#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
+ * @{
+ */
+#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */
+#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */
+#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
+ * @{
+ */
+#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */
+#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
+ * @{
+ */
+#define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */
+#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
+ * @{
+ */
+#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */
+#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
+ * @{
+ */
+#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
+#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */
+#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */
+#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
+ * @{
+ */
+#define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */
+#define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
+ * @{
+ */
+#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */
+#define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
+ * @{
+ */
+
+/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in I2C register
+ * @param __INSTANCE__ I2C Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in I2C register
+ * @param __INSTANCE__ I2C Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+ * @{
+ */
+
+/**
+ * @brief Convert Peripheral Clock Frequency in Mhz.
+ * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
+ * @retval Value of peripheral clock (in Mhz)
+ */
+#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
+
+/**
+ * @brief Convert Peripheral Clock Frequency in Hz.
+ * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
+ * @retval Value of peripheral clock (in Hz)
+ */
+#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
+
+/**
+ * @brief Compute I2C Clock rising time.
+ * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
+ * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
+ * @retval Value between Min_Data=0x02 and Max_Data=0x3F
+ */
+#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
+
+/**
+ * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
+ * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
+ * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
+ * @param __DUTYCYCLE__ This parameter can be one of the following values:
+ * @arg @ref LL_I2C_DUTYCYCLE_2
+ * @arg @ref LL_I2C_DUTYCYCLE_16_9
+ * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
+ */
+#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
+ (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
+ (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
+
+/**
+ * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
+ * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
+ * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
+ * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
+ */
+#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
+
+/**
+ * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
+ * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
+ * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
+ * @param __DUTYCYCLE__ This parameter can be one of the following values:
+ * @arg @ref LL_I2C_DUTYCYCLE_2
+ * @arg @ref LL_I2C_DUTYCYCLE_16_9
+ * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
+ */
+#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
+ (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
+ (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
+
+/**
+ * @brief Get the Least significant bits of a 10-Bits address.
+ * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+/**
+ * @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
+ * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
+ * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
+ */
+#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
+
+/**
+ * @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
+ * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
+ * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
+ */
+#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
+ * @{
+ */
+
+/** @defgroup I2C_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable I2C peripheral (PE = 1).
+ * @rmtoll CR1 PE LL_I2C_Enable
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+ * @brief Disable I2C peripheral (PE = 0).
+ * @rmtoll CR1 PE LL_I2C_Disable
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+ * @brief Check if the I2C peripheral is enabled or disabled.
+ * @rmtoll CR1 PE LL_I2C_IsEnabled
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
+}
+
+
+/**
+ * @brief Enable DMA transmission requests.
+ * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
+}
+
+/**
+ * @brief Disable DMA transmission requests.
+ * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
+}
+
+/**
+ * @brief Check if DMA transmission requests are enabled or disabled.
+ * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
+}
+
+/**
+ * @brief Enable DMA reception requests.
+ * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
+}
+
+/**
+ * @brief Disable DMA reception requests.
+ * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
+}
+
+/**
+ * @brief Check if DMA reception requests are enabled or disabled.
+ * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer.
+ * @rmtoll DR DR LL_I2C_DMA_GetRegAddr
+ * @param I2Cx I2C Instance.
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t) & (I2Cx->DR);
+}
+
+/**
+ * @brief Enable Clock stretching.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Disable Clock stretching.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+}
+
+/**
+ * @brief Check if Clock stretching is enabled or disabled.
+ * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
+}
+
+/**
+ * @brief Enable General Call.
+ * @note When enabled the Address 0x00 is ACKed.
+ * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
+}
+
+/**
+ * @brief Disable General Call.
+ * @note When disabled the Address 0x00 is NACKed.
+ * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
+}
+
+/**
+ * @brief Check if General Call is enabled or disabled.
+ * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
+}
+
+/**
+ * @brief Set the Own Address1.
+ * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
+ * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
+ * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
+ * OAR1 ADDMODE LL_I2C_SetOwnAddress1
+ * @param I2Cx I2C Instance.
+ * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
+ * @param OwnAddrSize This parameter can be one of the following values:
+ * @arg @ref LL_I2C_OWNADDRESS1_7BIT
+ * @arg @ref LL_I2C_OWNADDRESS1_10BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
+{
+ MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
+}
+
+/**
+ * @brief Set the 7bits Own Address2.
+ * @note This action has no effect if own address2 is enabled.
+ * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
+{
+ MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
+}
+
+/**
+ * @brief Enable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
+}
+
+/**
+ * @brief Disable acknowledge on Own Address2 match address.
+ * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
+}
+
+/**
+ * @brief Check if Own Address1 acknowledge is enabled or disabled.
+ * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
+}
+
+/**
+ * @brief Configure the Peripheral clock frequency.
+ * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
+ * @param I2Cx I2C Instance.
+ * @param PeriphClock Peripheral Clock (in Hz)
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
+}
+
+/**
+ * @brief Get the Peripheral clock frequency.
+ * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
+ * @param I2Cx I2C Instance.
+ * @retval Value of Peripheral Clock (in Hz)
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
+}
+
+/**
+ * @brief Configure the Duty cycle (Fast mode only).
+ * @rmtoll CCR DUTY LL_I2C_SetDutyCycle
+ * @param I2Cx I2C Instance.
+ * @param DutyCycle This parameter can be one of the following values:
+ * @arg @ref LL_I2C_DUTYCYCLE_2
+ * @arg @ref LL_I2C_DUTYCYCLE_16_9
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
+{
+ MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
+}
+
+/**
+ * @brief Get the Duty cycle (Fast mode only).
+ * @rmtoll CCR DUTY LL_I2C_GetDutyCycle
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_DUTYCYCLE_2
+ * @arg @ref LL_I2C_DUTYCYCLE_16_9
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
+}
+
+/**
+ * @brief Configure the I2C master clock speed mode.
+ * @rmtoll CCR FS LL_I2C_SetClockSpeedMode
+ * @param I2Cx I2C Instance.
+ * @param ClockSpeedMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
+ * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
+{
+ MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
+}
+
+/**
+ * @brief Get the the I2C master speed mode.
+ * @rmtoll CCR FS LL_I2C_GetClockSpeedMode
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
+ * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
+}
+
+/**
+ * @brief Configure the SCL, SDA rising time.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll TRISE TRISE LL_I2C_SetRiseTime
+ * @param I2Cx I2C Instance.
+ * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
+{
+ MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
+}
+
+/**
+ * @brief Get the SCL, SDA rising time.
+ * @rmtoll TRISE TRISE LL_I2C_GetRiseTime
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x02 and Max_Data=0x3F
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
+}
+
+/**
+ * @brief Configure the SCL high and low period.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CCR CCR LL_I2C_SetClockPeriod
+ * @param I2Cx I2C Instance.
+ * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
+{
+ MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
+}
+
+/**
+ * @brief Get the SCL high and low period.
+ * @rmtoll CCR CCR LL_I2C_GetClockPeriod
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
+}
+
+/**
+ * @brief Configure the SCL speed.
+ * @note This bit can only be programmed when the I2C is disabled (PE = 0).
+ * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
+ * TRISE TRISE LL_I2C_ConfigSpeed\n
+ * CCR FS LL_I2C_ConfigSpeed\n
+ * CCR DUTY LL_I2C_ConfigSpeed\n
+ * CCR CCR LL_I2C_ConfigSpeed
+ * @param I2Cx I2C Instance.
+ * @param PeriphClock Peripheral Clock (in Hz)
+ * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
+ * @param DutyCycle This parameter can be one of the following values:
+ * @arg @ref LL_I2C_DUTYCYCLE_2
+ * @arg @ref LL_I2C_DUTYCYCLE_16_9
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
+ uint32_t DutyCycle)
+{
+ register uint32_t freqrange = 0x0U;
+ register uint32_t clockconfig = 0x0U;
+
+ /* Compute frequency range */
+ freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
+
+ /* Configure I2Cx: Frequency range register */
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
+
+ /* Configure I2Cx: Rise Time register */
+ MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
+
+ /* Configure Speed mode, Duty Cycle and Clock control register value */
+ if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
+ {
+ /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
+ clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \
+ __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \
+ DutyCycle;
+ }
+ else
+ {
+ /* Set Speed mode at standard for Clock Speed request in standard clock range */
+ clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \
+ __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
+ }
+
+ /* Configure I2Cx: Clock control register */
+ MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
+}
+
+/**
+ * @brief Configure peripheral mode.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 SMBUS LL_I2C_SetMode\n
+ * CR1 SMBTYPE LL_I2C_SetMode\n
+ * CR1 ENARP LL_I2C_SetMode
+ * @param I2Cx I2C Instance.
+ * @param PeripheralMode This parameter can be one of the following values:
+ * @arg @ref LL_I2C_MODE_I2C
+ * @arg @ref LL_I2C_MODE_SMBUS_HOST
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
+{
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
+}
+
+/**
+ * @brief Get peripheral mode.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 SMBUS LL_I2C_GetMode\n
+ * CR1 SMBTYPE LL_I2C_GetMode\n
+ * CR1 ENARP LL_I2C_GetMode
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_MODE_I2C
+ * @arg @ref LL_I2C_MODE_SMBUS_HOST
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
+ * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
+}
+
+/**
+ * @brief Enable SMBus alert (Host or Device mode)
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is drived low and
+ * Alert Response Address Header acknowledge is enabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is supported.
+ * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
+}
+
+/**
+ * @brief Disable SMBus alert (Host or Device mode)
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note SMBus Device mode:
+ * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
+ * Alert Response Address Header acknowledge is disabled.
+ * SMBus Host mode:
+ * - SMBus Alert pin management is not supported.
+ * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
+}
+
+/**
+ * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
+}
+
+/**
+ * @brief Enable SMBus Packet Error Calculation (PEC).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
+}
+
+/**
+ * @brief Disable SMBus Packet Error Calculation (PEC).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
+}
+
+/**
+ * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable TXE interrupt.
+ * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
+ * CR2 ITBUFEN LL_I2C_EnableIT_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
+}
+
+/**
+ * @brief Disable TXE interrupt.
+ * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
+ * CR2 ITBUFEN LL_I2C_DisableIT_TX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
+}
+
+/**
+ * @brief Check if the TXE Interrupt is enabled or disabled.
+ * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
+ * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
+}
+
+/**
+ * @brief Enable RXNE interrupt.
+ * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
+ * CR2 ITBUFEN LL_I2C_EnableIT_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
+}
+
+/**
+ * @brief Disable RXNE interrupt.
+ * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
+ * CR2 ITBUFEN LL_I2C_DisableIT_RX
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
+}
+
+/**
+ * @brief Check if the RXNE Interrupt is enabled or disabled.
+ * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
+ * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
+}
+
+/**
+ * @brief Enable Events interrupts.
+ * @note Any of these events will generate interrupt :
+ * Start Bit (SB)
+ * Address sent, Address matched (ADDR)
+ * 10-bit header sent (ADD10)
+ * Stop detection (STOPF)
+ * Byte transfer finished (BTF)
+ *
+ * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
+ * Receive buffer not empty (RXNE)
+ * Transmit buffer empty (TXE)
+ * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
+}
+
+/**
+ * @brief Disable Events interrupts.
+ * @note Any of these events will generate interrupt :
+ * Start Bit (SB)
+ * Address sent, Address matched (ADDR)
+ * 10-bit header sent (ADD10)
+ * Stop detection (STOPF)
+ * Byte transfer finished (BTF)
+ * Receive buffer not empty (RXNE)
+ * Transmit buffer empty (TXE)
+ * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
+}
+
+/**
+ * @brief Check if Events interrupts are enabled or disabled.
+ * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
+}
+
+/**
+ * @brief Enable Buffer interrupts.
+ * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
+ * Receive buffer not empty (RXNE)
+ * Transmit buffer empty (TXE)
+ * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
+}
+
+/**
+ * @brief Disable Buffer interrupts.
+ * @note Any of these Buffer events will generate interrupt :
+ * Receive buffer not empty (RXNE)
+ * Transmit buffer empty (TXE)
+ * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
+}
+
+/**
+ * @brief Check if Buffer interrupts are enabled or disabled.
+ * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
+}
+
+/**
+ * @brief Enable Error interrupts.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Bus Error detection (BERR)
+ * Arbitration Loss (ARLO)
+ * Acknowledge Failure(AF)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (SMBALERT)
+ * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
+}
+
+/**
+ * @brief Disable Error interrupts.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note Any of these errors will generate interrupt :
+ * Bus Error detection (BERR)
+ * Arbitration Loss (ARLO)
+ * Acknowledge Failure(AF)
+ * Overrun/Underrun (OVR)
+ * SMBus Timeout detection (TIMEOUT)
+ * SMBus PEC error detection (PECERR)
+ * SMBus Alert pin event detection (SMBALERT)
+ * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
+}
+
+/**
+ * @brief Check if Error interrupts are enabled or disabled.
+ * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
+ * @{
+ */
+
+/**
+ * @brief Indicate the status of Transmit data register empty flag.
+ * @note RESET: When next data is written in Transmit data register.
+ * SET: When Transmit data register is empty.
+ * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
+}
+
+/**
+ * @brief Indicate the status of Byte Transfer Finished flag.
+ * RESET: When Data byte transfer not done.
+ * SET: When Data byte transfer succeeded.
+ * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
+}
+
+/**
+ * @brief Indicate the status of Receive data register not empty flag.
+ * @note RESET: When Receive data register is read.
+ * SET: When the received data is copied in Receive data register.
+ * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
+}
+
+/**
+ * @brief Indicate the status of Start Bit (master mode).
+ * @note RESET: When No Start condition.
+ * SET: When Start condition is generated.
+ * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
+}
+
+/**
+ * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
+ * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
+}
+
+/**
+ * @brief Indicate the status of 10-bit header sent (master mode).
+ * @note RESET: When no ADD10 event occured.
+ * SET: When the master has sent the first address byte (header).
+ * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
+}
+
+/**
+ * @brief Indicate the status of Acknowledge failure flag.
+ * @note RESET: No acknowledge failure.
+ * SET: When an acknowledge failure is received after a byte transmission.
+ * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
+}
+
+/**
+ * @brief Indicate the status of Stop detection flag (slave mode).
+ * @note RESET: Clear default value.
+ * SET: When a Stop condition is detected.
+ * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
+}
+
+/**
+ * @brief Indicate the status of Bus error flag.
+ * @note RESET: Clear default value.
+ * SET: When a misplaced Start or Stop condition is detected.
+ * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
+}
+
+/**
+ * @brief Indicate the status of Arbitration lost flag.
+ * @note RESET: Clear default value.
+ * SET: When arbitration lost.
+ * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
+}
+
+/**
+ * @brief Indicate the status of Overrun/Underrun flag.
+ * @note RESET: Clear default value.
+ * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
+ * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
+}
+
+/**
+ * @brief Indicate the status of SMBus PEC error flag in reception.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
+}
+
+/**
+ * @brief Indicate the status of SMBus Timeout detection flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
+}
+
+/**
+ * @brief Indicate the status of SMBus alert flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
+}
+
+/**
+ * @brief Indicate the status of Bus Busy flag.
+ * @note RESET: Clear default value.
+ * SET: When a Start condition is detected.
+ * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
+}
+
+/**
+ * @brief Indicate the status of Dual flag.
+ * @note RESET: Received address matched with OAR1.
+ * SET: Received address matched with OAR2.
+ * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
+}
+
+/**
+ * @brief Indicate the status of SMBus Host address reception (Slave mode).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: No SMBus Host address
+ * SET: SMBus Host address received.
+ * @note This status is cleared by hardware after a STOP condition or repeated START condition.
+ * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
+}
+
+/**
+ * @brief Indicate the status of SMBus Device default address reception (Slave mode).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note RESET: No SMBus Device default address
+ * SET: SMBus Device default address received.
+ * @note This status is cleared by hardware after a STOP condition or repeated START condition.
+ * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
+}
+
+/**
+ * @brief Indicate the status of General call address reception (Slave mode).
+ * @note RESET: No Generall call address
+ * SET: General call address received.
+ * @note This status is cleared by hardware after a STOP condition or repeated START condition.
+ * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
+}
+
+/**
+ * @brief Indicate the status of Master/Slave flag.
+ * @note RESET: Slave Mode.
+ * SET: Master Mode.
+ * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
+}
+
+/**
+ * @brief Clear Address Matched flag.
+ * @note Clearing this flag is done by a read access to the I2Cx_SR1
+ * register followed by a read access to the I2Cx_SR2 register.
+ * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = I2Cx->SR1;
+ (void) tmpreg;
+ tmpreg = I2Cx->SR2;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear Acknowledge failure flag.
+ * @rmtoll SR1 AF LL_I2C_ClearFlag_AF
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
+}
+
+/**
+ * @brief Clear Stop detection flag.
+ * @note Clearing this flag is done by a read access to the I2Cx_SR1
+ * register followed by a write access to I2Cx_CR1 register.
+ * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
+ * CR1 PE LL_I2C_ClearFlag_STOP
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = I2Cx->SR1;
+ (void) tmpreg;
+ SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+}
+
+/**
+ * @brief Clear Bus error flag.
+ * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
+}
+
+/**
+ * @brief Clear Arbitration lost flag.
+ * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
+}
+
+/**
+ * @brief Clear Overrun/Underrun flag.
+ * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
+}
+
+/**
+ * @brief Clear SMBus PEC error flag.
+ * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
+}
+
+/**
+ * @brief Clear SMBus Timeout detection flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
+}
+
+/**
+ * @brief Clear SMBus Alert flag.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Enable Reset of I2C peripheral.
+ * @rmtoll CR1 SWRST LL_I2C_EnableReset
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
+}
+
+/**
+ * @brief Disable Reset of I2C peripheral.
+ * @rmtoll CR1 SWRST LL_I2C_DisableReset
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
+}
+
+/**
+ * @brief Check if the I2C peripheral is under reset state or not.
+ * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
+}
+
+/**
+ * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+ * @note Usage in Slave or Master mode.
+ * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
+ * @param I2Cx I2C Instance.
+ * @param TypeAcknowledge This parameter can be one of the following values:
+ * @arg @ref LL_I2C_ACK
+ * @arg @ref LL_I2C_NACK
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
+{
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
+}
+
+/**
+ * @brief Generate a START or RESTART condition
+ * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
+ * This action has no effect when RELOAD is set.
+ * @rmtoll CR1 START LL_I2C_GenerateStartCondition
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_START);
+}
+
+/**
+ * @brief Generate a STOP condition after the current byte transfer (master mode).
+ * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
+}
+
+/**
+ * @brief Enable bit POS (master/host mode).
+ * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
+ * @rmtoll CR1 POS LL_I2C_EnableBitPOS
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_POS);
+}
+
+/**
+ * @brief Disable bit POS (master/host mode).
+ * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
+ * @rmtoll CR1 POS LL_I2C_DisableBitPOS
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
+}
+
+/**
+ * @brief Check if bit POS is enabled or disabled.
+ * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
+}
+
+/**
+ * @brief Indicate the value of transfer direction.
+ * @note RESET: Bus is in read transfer (peripheral point of view).
+ * SET: Bus is in write transfer (peripheral point of view).
+ * @rmtoll SR2 TRA LL_I2C_GetTransferDirection
+ * @param I2Cx I2C Instance.
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2C_DIRECTION_WRITE
+ * @arg @ref LL_I2C_DIRECTION_READ
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
+}
+
+/**
+ * @brief Enable DMA last transfer.
+ * @note This action mean that next DMA EOT is the last transfer.
+ * @rmtoll CR2 LAST LL_I2C_EnableLastDMA
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
+}
+
+/**
+ * @brief Disable DMA last transfer.
+ * @note This action mean that next DMA EOT is not the last transfer.
+ * @rmtoll CR2 LAST LL_I2C_DisableLastDMA
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
+}
+
+/**
+ * @brief Check if DMA last transfer is enabled or disabled.
+ * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
+}
+
+/**
+ * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @note This feature is cleared by hardware when the PEC byte is transferred or compared,
+ * or by a START or STOP condition, it is also cleared by software.
+ * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
+}
+
+/**
+ * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
+}
+
+/**
+ * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
+ * @param I2Cx I2C Instance.
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
+{
+ return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
+}
+
+/**
+ * @brief Get the SMBus Packet Error byte calculated.
+ * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * SMBus feature is supported by the I2Cx Instance.
+ * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
+{
+ return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
+}
+
+/**
+ * @brief Read Receive Data register.
+ * @rmtoll DR DR LL_I2C_ReceiveData8
+ * @param I2Cx I2C Instance.
+ * @retval Value between Min_Data=0x0 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
+{
+ return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
+}
+
+/**
+ * @brief Write in Transmit Data Register .
+ * @rmtoll DR DR LL_I2C_TransmitData8
+ * @param I2Cx I2C Instance.
+ * @param Data Value between Min_Data=0x0 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
+{
+ MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
+uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
+
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* I2C1 || I2C2 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_iwdg.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_iwdg.h
new file mode 100644
index 0000000..2605939
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_iwdg.h
@@ -0,0 +1,329 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_iwdg.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of IWDG LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_IWDG_H
+#define __STM32F1xx_LL_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined(IWDG)
+
+/** @defgroup IWDG_LL IWDG
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
+ * @{
+ */
+
+#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
+#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
+#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
+#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
+ * @{
+ */
+
+/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_IWDG_ReadReg function
+ * @{
+ */
+#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
+#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
+ * @{
+ */
+#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
+#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
+#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
+#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
+#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
+#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
+#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
+ * @{
+ */
+
+/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in IWDG register
+ * @param __INSTANCE__ IWDG Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in IWDG register
+ * @param __INSTANCE__ IWDG Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
+ * @{
+ */
+/** @defgroup IWDG_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Start the Independent Watchdog
+ * @note Except if the hardware watchdog option is selected
+ * @rmtoll KR KEY LL_IWDG_Enable
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * @rmtoll KR KEY LL_IWDG_ReloadCounter
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
+}
+
+/**
+ * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+ * @rmtoll KR KEY LL_IWDG_EnableWriteAccess
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
+}
+
+/**
+ * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
+ * @rmtoll KR KEY LL_IWDG_DisableWriteAccess
+ * @param IWDGx IWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
+{
+ WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
+}
+
+/**
+ * @brief Select the prescaler of the IWDG
+ * @rmtoll PR PR LL_IWDG_SetPrescaler
+ * @param IWDGx IWDG Instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_IWDG_PRESCALER_4
+ * @arg @ref LL_IWDG_PRESCALER_8
+ * @arg @ref LL_IWDG_PRESCALER_16
+ * @arg @ref LL_IWDG_PRESCALER_32
+ * @arg @ref LL_IWDG_PRESCALER_64
+ * @arg @ref LL_IWDG_PRESCALER_128
+ * @arg @ref LL_IWDG_PRESCALER_256
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
+{
+ WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
+}
+
+/**
+ * @brief Get the selected prescaler of the IWDG
+ * @rmtoll PR PR LL_IWDG_GetPrescaler
+ * @param IWDGx IWDG Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_IWDG_PRESCALER_4
+ * @arg @ref LL_IWDG_PRESCALER_8
+ * @arg @ref LL_IWDG_PRESCALER_16
+ * @arg @ref LL_IWDG_PRESCALER_32
+ * @arg @ref LL_IWDG_PRESCALER_64
+ * @arg @ref LL_IWDG_PRESCALER_128
+ * @arg @ref LL_IWDG_PRESCALER_256
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
+{
+ return (uint32_t)(READ_REG(IWDGx->PR));
+}
+
+/**
+ * @brief Specify the IWDG down-counter reload value
+ * @rmtoll RLR RL LL_IWDG_SetReloadCounter
+ * @param IWDGx IWDG Instance
+ * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
+{
+ WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
+}
+
+/**
+ * @brief Get the specified IWDG down-counter reload value
+ * @rmtoll RLR RL LL_IWDG_GetReloadCounter
+ * @param IWDGx IWDG Instance
+ * @retval Value between Min_Data=0 and Max_Data=0x0FFF
+ */
+__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
+{
+ return (uint32_t)(READ_REG(IWDGx->RLR));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if flag Prescaler Value Update is set or not
+ * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
+{
+ return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
+}
+
+/**
+ * @brief Check if flag Reload Value Update is set or not
+ * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
+ * @param IWDGx IWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
+{
+ return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
+}
+
+
+/**
+ * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
+ * @rmtoll SR PVU LL_IWDG_IsReady\n
+ * SR RVU LL_IWDG_IsReady
+ * @param IWDGx IWDG Instance
+ * @retval State of bits (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
+{
+ return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U);
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* IWDG) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_IWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_pwr.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_pwr.h
new file mode 100644
index 0000000..a1ad470
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_pwr.h
@@ -0,0 +1,458 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_pwr.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of PWR LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_PWR_H
+#define __STM32F1xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+ * @{
+ */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_WriteReg function
+ * @{
+ */
+#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
+#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_PWR_ReadReg function
+ * @{
+ */
+#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
+#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
+#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
+#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */
+/**
+ * @}
+ */
+
+
+/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
+ * @{
+ */
+#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
+ * @{
+ */
+#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
+#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
+ * @{
+ */
+#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
+#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
+#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
+#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
+#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
+#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
+#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
+#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
+/**
+ * @}
+ */
+/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
+ * @{
+ */
+#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+ * @{
+ */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in PWR register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in PWR register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+ * @{
+ */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable access to the backup domain
+ * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+ * @brief Disable access to the backup domain
+ * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+ * @brief Check if the backup domain is enabled
+ * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
+}
+
+/**
+ * @brief Set voltage Regulator mode during deep sleep mode
+ * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
+ * @param RegulMode This parameter can be one of the following values:
+ * @arg @ref LL_PWR_REGU_DSMODE_MAIN
+ * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
+{
+ MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
+}
+
+/**
+ * @brief Get voltage Regulator mode during deep sleep mode
+ * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_REGU_DSMODE_MAIN
+ * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
+}
+
+/**
+ * @brief Set Power Down mode when CPU enters deepsleep
+ * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
+ * @rmtoll CR LPDS LL_PWR_SetPowerMode
+ * @param PDMode This parameter can be one of the following values:
+ * @arg @ref LL_PWR_MODE_STOP_MAINREGU
+ * @arg @ref LL_PWR_MODE_STOP_LPREGU
+ * @arg @ref LL_PWR_MODE_STANDBY
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
+{
+ MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
+}
+
+/**
+ * @brief Get Power Down mode when CPU enters deepsleep
+ * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
+ * @rmtoll CR LPDS LL_PWR_GetPowerMode
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_MODE_STOP_MAINREGU
+ * @arg @ref LL_PWR_MODE_STOP_LPREGU
+ * @arg @ref LL_PWR_MODE_STANDBY
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
+}
+
+/**
+ * @brief Configure the voltage threshold detected by the Power Voltage Detector
+ * @rmtoll CR PLS LL_PWR_SetPVDLevel
+ * @param PVDLevel This parameter can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+ MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
+}
+
+/**
+ * @brief Get the voltage threshold detection
+ * @rmtoll CR PLS LL_PWR_GetPVDLevel
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_PWR_PVDLEVEL_0
+ * @arg @ref LL_PWR_PVDLEVEL_1
+ * @arg @ref LL_PWR_PVDLEVEL_2
+ * @arg @ref LL_PWR_PVDLEVEL_3
+ * @arg @ref LL_PWR_PVDLEVEL_4
+ * @arg @ref LL_PWR_PVDLEVEL_5
+ * @arg @ref LL_PWR_PVDLEVEL_6
+ * @arg @ref LL_PWR_PVDLEVEL_7
+ */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+ return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
+}
+
+/**
+ * @brief Enable Power Voltage Detector
+ * @rmtoll CR PVDE LL_PWR_EnablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+ * @brief Disable Power Voltage Detector
+ * @rmtoll CR PVDE LL_PWR_DisablePVD
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+ CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+ * @brief Check if Power Voltage Detector is enabled
+ * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+ return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
+}
+
+/**
+ * @brief Enable the WakeUp PINx functionality
+ * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+ SET_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+ * @brief Disable the WakeUp PINx functionality
+ * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+ CLEAR_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+ * @brief Check if the WakeUp PINx functionality is enabled
+ * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin
+ * @param WakeUpPin This parameter can be one of the following values:
+ * @arg @ref LL_PWR_WAKEUP_PIN1
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+ return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get Wake-up Flag
+ * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
+}
+
+/**
+ * @brief Get Standby Flag
+ * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
+}
+
+/**
+ * @brief Indicate whether VDD voltage is below the selected PVD threshold
+ * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+ return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
+}
+
+/**
+ * @brief Clear Standby Flag
+ * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_CSBF);
+}
+
+/**
+ * @brief Clear Wake-up Flags
+ * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
+{
+ SET_BIT(PWR->CR, PWR_CR_CWUF);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(PWR) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_rcc.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_rcc.h
new file mode 100644
index 0000000..c87d565
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_rcc.h
@@ -0,0 +1,2309 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_rcc.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of RCC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_RCC_H
+#define __STM32F1xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+ * @{
+ */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+ * @{
+ */
+
+/**
+ * @brief RCC Clocks Frequency Structure
+ */
+typedef struct
+{
+ uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
+ uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
+ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
+ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
+} LL_RCC_ClocksTypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+ * @{
+ */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+ * @brief Defines used to adapt values of different oscillators
+ * @note These values could be modified in the user environment according to
+ * HW set-up.
+ * @{
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined (LSE_VALUE)
+#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined (LSI_VALUE)
+#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
+ * @brief Flags defines which can be used with LL_RCC_WriteReg function
+ * @{
+ */
+#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
+#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
+#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
+#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
+#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
+#define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC /*!< PLL3(PLLI2S) Ready Interrupt Clear */
+#define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC /*!< PLL2 Ready Interrupt Clear */
+#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_RCC_ReadReg function
+ * @{
+ */
+#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
+#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
+#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
+#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
+#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
+#define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /*!< PLL3(PLLI2S) Ready Interrupt flag */
+#define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */
+#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
+#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
+#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
+#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
+#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
+#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
+#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
+ * @{
+ */
+#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
+#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
+#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
+#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
+#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
+#define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /*!< PLL3(PLLI2S) Ready Interrupt Enable */
+#define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /*!< PLL2 Ready Interrupt Enable */
+/**
+ * @}
+ */
+
+#if defined(RCC_CFGR2_PREDIV2)
+/** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor
+ * @{
+ */
+#define LL_RCC_HSE_PREDIV2_DIV_1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */
+#define LL_RCC_HSE_PREDIV2_DIV_2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */
+#define LL_RCC_HSE_PREDIV2_DIV_3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */
+#define LL_RCC_HSE_PREDIV2_DIV_4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */
+#define LL_RCC_HSE_PREDIV2_DIV_5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */
+#define LL_RCC_HSE_PREDIV2_DIV_6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */
+#define LL_RCC_HSE_PREDIV2_DIV_7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */
+#define LL_RCC_HSE_PREDIV2_DIV_8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */
+#define LL_RCC_HSE_PREDIV2_DIV_9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */
+#define LL_RCC_HSE_PREDIV2_DIV_10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
+#define LL_RCC_HSE_PREDIV2_DIV_11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
+#define LL_RCC_HSE_PREDIV2_DIV_12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
+#define LL_RCC_HSE_PREDIV2_DIV_13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
+#define LL_RCC_HSE_PREDIV2_DIV_14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
+#define LL_RCC_HSE_PREDIV2_DIV_15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
+#define LL_RCC_HSE_PREDIV2_DIV_16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR2_PREDIV2 */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
+ * @{
+ */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
+ * @{
+ */
+#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
+ * @{
+ */
+#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
+#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
+#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
+#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
+ * @{
+ */
+#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
+#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
+#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
+#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
+ * @{
+ */
+#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */
+#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */
+#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */
+#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */
+#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/
+#if defined(RCC_CFGR_MCOSEL_PLL2CLK)
+#define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCOSEL_PLL2 /*!< PLL2 clock selected as MCO source*/
+#endif /* RCC_CFGR_MCOSEL_PLL2CLK */
+#if defined(RCC_CFGR_MCOSEL_PLL3CLK_DIV2)
+#define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCOSEL_PLL3_DIV2 /*!< PLLI2S clock divided by 2 selected as MCO source*/
+#endif /* RCC_CFGR_MCOSEL_PLL3CLK_DIV2 */
+#if defined(RCC_CFGR_MCOSEL_EXT_HSE)
+#define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCOSEL_EXT_HSE /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
+#endif /* RCC_CFGR_MCOSEL_EXT_HSE */
+#if defined(RCC_CFGR_MCOSEL_PLL3CLK)
+#define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCOSEL_PLL3CLK /*!< PLLI2S clock selected as MCO source */
+#endif /* RCC_CFGR_MCOSEL_PLL3CLK */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+ * @{
+ */
+#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
+#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+#if defined(RCC_CFGR2_I2S2SRC)
+/** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection
+ * @{
+ */
+#define LL_RCC_I2S2_CLKSOURCE_SYSCLK RCC_CFGR2_I2S2SRC /*!< System clock (SYSCLK) selected as I2S2 clock entry */
+#define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S2 clock entry */
+#define LL_RCC_I2S3_CLKSOURCE_SYSCLK RCC_CFGR2_I2S3SRC /*!< System clock (SYSCLK) selected as I2S3 clock entry */
+#define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S3 clock entry */
+/**
+ * @}
+ */
+#endif /* RCC_CFGR2_I2S2SRC */
+
+#if defined(USB_OTG_FS) || defined(USB)
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
+ * @{
+ */
+#if defined(RCC_CFGR_USBPRE)
+#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */
+#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /*!< PLL clock is divided by 1.5 */
+#endif /*RCC_CFGR_USBPRE*/
+#if defined(RCC_CFGR_OTGFSPRE)
+#define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */
+#define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /*!< PLL clock is divided by 3 */
+#endif /*RCC_CFGR_OTGFSPRE*/
+/**
+ * @}
+ */
+#endif /* USB_OTG_FS || USB */
+
+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection
+ * @{
+ */
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/
+#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/
+/**
+ * @}
+ */
+
+#if defined(RCC_CFGR2_I2S2SRC)
+/** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source
+ * @{
+ */
+#define LL_RCC_I2S2_CLKSOURCE RCC_CFGR2_I2S2SRC /*!< I2S2 Clock source selection */
+#define LL_RCC_I2S3_CLKSOURCE RCC_CFGR2_I2S3SRC /*!< I2S3 Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* RCC_CFGR2_I2S2SRC */
+
+#if defined(USB_OTG_FS) || defined(USB)
+/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
+ * @{
+ */
+#define LL_RCC_USB_CLKSOURCE 0x00400000U /*!< USB Clock source selection */
+/**
+ * @}
+ */
+
+#endif /* USB_OTG_FS || USB */
+
+/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
+ * @{
+ */
+#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
+ * @{
+ */
+#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
+ * @{
+ */
+#if defined(RCC_CFGR_PLLMULL2)
+#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2 /*!< PLL input clock*2 */
+#endif /*RCC_CFGR_PLLMULL2*/
+#if defined(RCC_CFGR_PLLMULL3)
+#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3 /*!< PLL input clock*3 */
+#endif /*RCC_CFGR_PLLMULL3*/
+#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4 /*!< PLL input clock*4 */
+#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5 /*!< PLL input clock*5 */
+#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6 /*!< PLL input clock*6 */
+#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7 /*!< PLL input clock*7 */
+#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8 /*!< PLL input clock*8 */
+#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9 /*!< PLL input clock*9 */
+#if defined(RCC_CFGR_PLLMULL6_5)
+#define LL_RCC_PLL_MUL_6_5 RCC_CFGR_PLLMULL6_5 /*!< PLL input clock*6 */
+#else
+#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10 /*!< PLL input clock*10 */
+#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11 /*!< PLL input clock*11 */
+#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12 /*!< PLL input clock*12 */
+#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13 /*!< PLL input clock*13 */
+#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14 /*!< PLL input clock*14 */
+#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15 /*!< PLL input clock*15 */
+#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16 /*!< PLL input clock*16 */
+#endif /*RCC_CFGR_PLLMULL6_5*/
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
+ * @{
+ */
+#define LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE/PREDIV1 clock selected as PLL entry clock source */
+#if defined(RCC_CFGR2_PREDIV1SRC)
+#define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/PREDIV1 clock selected as PLL entry clock source */
+#endif /*RCC_CFGR2_PREDIV1SRC*/
+
+#define LL_RCC_PLLSOURCE_HSE_DIV_1 RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */
+#if defined(RCC_CFGR2_PREDIV1)
+#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */
+#if defined(RCC_CFGR2_PREDIV1SRC)
+#define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/2 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/3 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/4 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/5 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/6 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/7 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/8 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/9 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/10 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/11 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/12 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/13 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/14 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/15 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/16 clock selected as PLL entry clock source */
+#endif /*RCC_CFGR2_PREDIV1SRC*/
+#else
+#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE) /*!< HSE/2 clock selected as PLL entry clock source */
+#endif /*RCC_CFGR2_PREDIV1*/
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
+ * @{
+ */
+#if defined(RCC_CFGR2_PREDIV1)
+#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /*!< PREDIV1 input clock not divided */
+#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /*!< PREDIV1 input clock divided by 2 */
+#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /*!< PREDIV1 input clock divided by 3 */
+#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV1_DIV4 /*!< PREDIV1 input clock divided by 4 */
+#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /*!< PREDIV1 input clock divided by 5 */
+#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV1_DIV6 /*!< PREDIV1 input clock divided by 6 */
+#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV1_DIV7 /*!< PREDIV1 input clock divided by 7 */
+#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV1_DIV8 /*!< PREDIV1 input clock divided by 8 */
+#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV1_DIV9 /*!< PREDIV1 input clock divided by 9 */
+#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV1_DIV10 /*!< PREDIV1 input clock divided by 10 */
+#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV1_DIV11 /*!< PREDIV1 input clock divided by 11 */
+#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV1_DIV12 /*!< PREDIV1 input clock divided by 12 */
+#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV1_DIV13 /*!< PREDIV1 input clock divided by 13 */
+#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV1_DIV14 /*!< PREDIV1 input clock divided by 14 */
+#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /*!< PREDIV1 input clock divided by 15 */
+#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /*!< PREDIV1 input clock divided by 16 */
+#else
+#define LL_RCC_PREDIV_DIV_1 0x00000000U /*!< HSE divider clock clock not divided */
+#define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided by 2 for PLL entry */
+#endif /*RCC_CFGR2_PREDIV1*/
+/**
+ * @}
+ */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL
+ * @{
+ */
+#define LL_RCC_PLLI2S_MUL_8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
+#define LL_RCC_PLLI2S_MUL_9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
+#define LL_RCC_PLLI2S_MUL_10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
+#define LL_RCC_PLLI2S_MUL_11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
+#define LL_RCC_PLLI2S_MUL_12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
+#define LL_RCC_PLLI2S_MUL_13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
+#define LL_RCC_PLLI2S_MUL_14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
+#define LL_RCC_PLLI2S_MUL_16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
+#define LL_RCC_PLLI2S_MUL_20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
+/**
+ * @}
+ */
+
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL
+ * @{
+ */
+#define LL_RCC_PLL2_MUL_8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
+#define LL_RCC_PLL2_MUL_9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
+#define LL_RCC_PLL2_MUL_10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
+#define LL_RCC_PLL2_MUL_11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
+#define LL_RCC_PLL2_MUL_12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
+#define LL_RCC_PLL2_MUL_13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
+#define LL_RCC_PLL2_MUL_14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
+#define LL_RCC_PLL2_MUL_16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
+#define LL_RCC_PLL2_MUL_20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
+/**
+ * @}
+ */
+
+#endif /* RCC_PLL2_SUPPORT */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+ * @{
+ */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in RCC register
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in RCC register
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+ * @{
+ */
+
+#if defined(RCC_CFGR_PLLMULL6_5)
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Prediv1)
+ * @param __PLLMUL__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_6_5
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
+ (((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \
+ ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos) + 2U)) :\
+ (((__INPUTFREQ__) * 13U) / 2U))
+
+#else
+/**
+ * @brief Helper macro to calculate the PLLCLK frequency
+ * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator ());
+ * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2)
+ * @param __PLLMUL__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2
+ * @arg @ref LL_RCC_PLL_MUL_3
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_10
+ * @arg @ref LL_RCC_PLL_MUL_11
+ * @arg @ref LL_RCC_PLL_MUL_12
+ * @arg @ref LL_RCC_PLL_MUL_13
+ * @arg @ref LL_RCC_PLL_MUL_14
+ * @arg @ref LL_RCC_PLL_MUL_15
+ * @arg @ref LL_RCC_PLL_MUL_16
+ * @retval PLL clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U))
+#endif /* RCC_CFGR_PLLMULL6_5 */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLLI2S frequency
+ * @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
+ * @param __INPUTFREQ__ PLLI2S Input frequency (based on HSE value)
+ * @param __PLLI2SMUL__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2S_MUL_8
+ * @arg @ref LL_RCC_PLLI2S_MUL_9
+ * @arg @ref LL_RCC_PLLI2S_MUL_10
+ * @arg @ref LL_RCC_PLLI2S_MUL_11
+ * @arg @ref LL_RCC_PLLI2S_MUL_12
+ * @arg @ref LL_RCC_PLLI2S_MUL_13
+ * @arg @ref LL_RCC_PLLI2S_MUL_14
+ * @arg @ref LL_RCC_PLLI2S_MUL_16
+ * @arg @ref LL_RCC_PLLI2S_MUL_20
+ * @param __PLLI2SDIV__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
+ * @retval PLLI2S clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> RCC_CFGR2_PLL3MUL_Pos) + 2U)) / (((__PLLI2SDIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/**
+ * @brief Helper macro to calculate the PLL2 frequency
+ * @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
+ * @param __INPUTFREQ__ PLL2 Input frequency (based on HSE value)
+ * @param __PLL2MUL__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL2_MUL_8
+ * @arg @ref LL_RCC_PLL2_MUL_9
+ * @arg @ref LL_RCC_PLL2_MUL_10
+ * @arg @ref LL_RCC_PLL2_MUL_11
+ * @arg @ref LL_RCC_PLL2_MUL_12
+ * @arg @ref LL_RCC_PLL2_MUL_13
+ * @arg @ref LL_RCC_PLL2_MUL_14
+ * @arg @ref LL_RCC_PLL2_MUL_16
+ * @arg @ref LL_RCC_PLL2_MUL_20
+ * @param __PLL2DIV__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
+ * @retval PLL2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> RCC_CFGR2_PLL2MUL_Pos) + 2U)) / (((__PLL2DIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
+#endif /* RCC_PLL2_SUPPORT */
+
+/**
+ * @brief Helper macro to calculate the HCLK frequency
+ * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
+ * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
+ * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
+ * @param __AHBPRESCALER__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval HCLK clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
+
+/**
+ * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
+ * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
+ * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB1PRESCALER__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
+
+/**
+ * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
+ * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
+ * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
+ * @param __HCLKFREQ__ HCLK frequency
+ * @param __APB2PRESCALER__: This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval PCLK2 clock frequency (in Hz)
+ */
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+ * @{
+ */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+ * @{
+ */
+
+/**
+ * @brief Enable the Clock Security System.
+ * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+ * @brief Enable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Disable HSE external oscillator (HSE Bypass)
+ * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+ * @brief Enable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+ * @brief Disable HSE crystal oscillator (HSE ON)
+ * @rmtoll CR HSEON LL_RCC_HSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+ * @brief Check if HSE oscillator Ready
+ * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
+}
+
+#if defined(RCC_CFGR2_PREDIV2)
+/**
+ * @brief Get PREDIV2 division factor
+ * @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2));
+}
+#endif /* RCC_CFGR2_PREDIV2 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+ * @{
+ */
+
+/**
+ * @brief Enable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+ * @brief Disable HSI oscillator
+ * @rmtoll CR HSION LL_RCC_HSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+ * @brief Check if HSI clock is ready
+ * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
+}
+
+/**
+ * @brief Get HSI Calibration value
+ * @note When HSITRIM is written, HSICAL is updated with the sum of
+ * HSITRIM and the factory trim value
+ * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
+ * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
+}
+
+/**
+ * @brief Set HSI Calibration trimming
+ * @note user-programmable trimming value that is added to the HSICAL
+ * @note Default value is 16, which, when added to the HSICAL value,
+ * should trim the HSI to 16 MHz +/- 1 %
+ * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
+ * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
+}
+
+/**
+ * @brief Get HSI Calibration trimming
+ * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
+ * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
+ */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSE LSE
+ * @{
+ */
+
+/**
+ * @brief Enable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Disable Low Speed External (LSE) crystal.
+ * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+ * @brief Enable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Disable external clock source (LSE bypass).
+ * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+ * @brief Check if LSE oscillator Ready
+ * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+ return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+ * @{
+ */
+
+/**
+ * @brief Enable LSI Oscillator
+ * @rmtoll CSR LSION LL_RCC_LSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+ SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+ * @brief Disable LSI Oscillator
+ * @rmtoll CSR LSION LL_RCC_LSI_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+ * @brief Check if LSI is Ready
+ * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_System System
+ * @{
+ */
+
+/**
+ * @brief Configure the system clock source
+ * @rmtoll CFGR SW LL_RCC_SetSysClkSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+ * @brief Get the system clock source
+ * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+ * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+ * @brief Set AHB prescaler
+ * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+}
+
+/**
+ * @brief Set APB1 prescaler
+ * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+}
+
+/**
+ * @brief Set APB2 prescaler
+ * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+}
+
+/**
+ * @brief Get AHB prescaler
+ * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_SYSCLK_DIV_1
+ * @arg @ref LL_RCC_SYSCLK_DIV_2
+ * @arg @ref LL_RCC_SYSCLK_DIV_4
+ * @arg @ref LL_RCC_SYSCLK_DIV_8
+ * @arg @ref LL_RCC_SYSCLK_DIV_16
+ * @arg @ref LL_RCC_SYSCLK_DIV_64
+ * @arg @ref LL_RCC_SYSCLK_DIV_128
+ * @arg @ref LL_RCC_SYSCLK_DIV_256
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+}
+
+/**
+ * @brief Get APB1 prescaler
+ * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB1_DIV_1
+ * @arg @ref LL_RCC_APB1_DIV_2
+ * @arg @ref LL_RCC_APB1_DIV_4
+ * @arg @ref LL_RCC_APB1_DIV_8
+ * @arg @ref LL_RCC_APB1_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+}
+
+/**
+ * @brief Get APB2 prescaler
+ * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_APB2_DIV_1
+ * @arg @ref LL_RCC_APB2_DIV_2
+ * @arg @ref LL_RCC_APB2_DIV_4
+ * @arg @ref LL_RCC_APB2_DIV_8
+ * @arg @ref LL_RCC_APB2_DIV_16
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+ * @{
+ */
+
+/**
+ * @brief Configure MCOx
+ * @rmtoll CFGR MCO LL_RCC_ConfigMCO
+ * @param MCOxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
+ * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
+ * @arg @ref LL_RCC_MCO1SOURCE_HSI
+ * @arg @ref LL_RCC_MCO1SOURCE_HSE
+ * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
+ * @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*)
+ * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*)
+ * @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*)
+ * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+ * @{
+ */
+
+#if defined(RCC_CFGR2_I2S2SRC)
+/**
+ * @brief Configure I2Sx clock source
+ * @rmtoll CFGR2 I2S2SRC LL_RCC_SetI2SClockSource\n
+ * CFGR2 I2S3SRC LL_RCC_SetI2SClockSource
+ * @param I2SxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
+ * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
+{
+ MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U));
+}
+#endif /* RCC_CFGR2_I2S2SRC */
+
+#if defined(USB_OTG_FS) || defined(USB)
+/**
+ * @brief Configure USB clock source
+ * @rmtoll CFGR OTGFSPRE LL_RCC_SetUSBClockSource\n
+ * CFGR USBPRE LL_RCC_SetUSBClockSource
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
+{
+#if defined(RCC_CFGR_USBPRE)
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
+#else /*RCC_CFGR_OTGFSPRE*/
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource);
+#endif /*RCC_CFGR_USBPRE*/
+}
+#endif /* USB_OTG_FS || USB */
+
+/**
+ * @brief Configure ADC clock source
+ * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
+}
+
+#if defined(RCC_CFGR2_I2S2SRC)
+/**
+ * @brief Get I2Sx clock source
+ * @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n
+ * CFGR2 I2S3SRC LL_RCC_GetI2SClockSource
+ * @param I2Sx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE
+ * @arg @ref LL_RCC_I2S3_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
+ * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
+ * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx);
+}
+#endif /* RCC_CFGR2_I2S2SRC */
+
+#if defined(USB_OTG_FS) || defined(USB)
+/**
+ * @brief Get USBx clock source
+ * @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n
+ * CFGR USBPRE LL_RCC_GetUSBClockSource
+ * @param USBx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
+ * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
+ *
+ * (*) value not defined in all devices
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
+}
+#endif /* USB_OTG_FS || USB */
+
+/**
+ * @brief Get ADCx clock source
+ * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource
+ * @param ADCx This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSOURCE
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
+ * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+ * @{
+ */
+
+/**
+ * @brief Set RTC Clock Source
+ * @note Once the RTC clock source has been selected, it cannot be changed any more unless
+ * the Backup domain is reset. The BDRST bit can be used to reset them.
+ * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+ MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+ * @brief Get RTC Clock Source
+ * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+ * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+ * @brief Enable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Disable RTC
+ * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+ * @brief Check if RTC has been enabled or not
+ * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+ return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
+}
+
+/**
+ * @brief Force the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+ SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @brief Release the Backup domain reset
+ * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+ CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_PLL PLL
+ * @{
+ */
+
+/**
+ * @brief Enable PLL
+ * @rmtoll CR PLLON LL_RCC_PLL_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+ * @brief Disable PLL
+ * @note Cannot be disabled if the PLL clock is used as the system clock
+ * @rmtoll CR PLLON LL_RCC_PLL_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+ * @brief Check if PLL Ready
+ * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
+}
+
+/**
+ * @brief Configure PLL used for SYSCLK Domain
+ * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS\n
+ * CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS
+ * @param Source This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*)
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*)
+ *
+ * (*) value not defined in all devices
+ * @param PLLMul This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2 (*)
+ * @arg @ref LL_RCC_PLL_MUL_3 (*)
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_6_5 (*)
+ * @arg @ref LL_RCC_PLL_MUL_10 (*)
+ * @arg @ref LL_RCC_PLL_MUL_11 (*)
+ * @arg @ref LL_RCC_PLL_MUL_12 (*)
+ * @arg @ref LL_RCC_PLL_MUL_13 (*)
+ * @arg @ref LL_RCC_PLL_MUL_14 (*)
+ * @arg @ref LL_RCC_PLL_MUL_15 (*)
+ * @arg @ref LL_RCC_PLL_MUL_16 (*)
+ *
+ * (*) value not defined in all devices
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL,
+ (Source & (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)) | PLLMul);
+#if defined(RCC_CFGR2_PREDIV1)
+#if defined(RCC_CFGR2_PREDIV1SRC)
+ MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC),
+ (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U));
+#else
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1));
+#endif /*RCC_CFGR2_PREDIV1SRC*/
+#endif /*RCC_CFGR2_PREDIV1*/
+}
+
+/**
+ * @brief Get the oscillator used as PLL clock source.
+ * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource\n
+ * CFGR2 PREDIV1SRC LL_RCC_PLL_GetMainSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*)
+ *
+ * (*) value not defined in all devices
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+{
+#if defined(RCC_CFGR2_PREDIV1SRC)
+ register uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC);
+ register uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U);
+ return (uint32_t)(pllsrc | predivsrc);
+#else
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
+#endif /*RCC_CFGR2_PREDIV1SRC*/
+}
+
+/**
+ * @brief Get PLL multiplication Factor
+ * @rmtoll CFGR PLLMULL LL_RCC_PLL_GetMultiplicator
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLL_MUL_2 (*)
+ * @arg @ref LL_RCC_PLL_MUL_3 (*)
+ * @arg @ref LL_RCC_PLL_MUL_4
+ * @arg @ref LL_RCC_PLL_MUL_5
+ * @arg @ref LL_RCC_PLL_MUL_6
+ * @arg @ref LL_RCC_PLL_MUL_7
+ * @arg @ref LL_RCC_PLL_MUL_8
+ * @arg @ref LL_RCC_PLL_MUL_9
+ * @arg @ref LL_RCC_PLL_MUL_6_5 (*)
+ * @arg @ref LL_RCC_PLL_MUL_10 (*)
+ * @arg @ref LL_RCC_PLL_MUL_11 (*)
+ * @arg @ref LL_RCC_PLL_MUL_12 (*)
+ * @arg @ref LL_RCC_PLL_MUL_13 (*)
+ * @arg @ref LL_RCC_PLL_MUL_14 (*)
+ * @arg @ref LL_RCC_PLL_MUL_15 (*)
+ * @arg @ref LL_RCC_PLL_MUL_16 (*)
+ *
+ * (*) value not defined in all devices
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMULL));
+}
+
+/**
+ * @brief Get PREDIV1 division factor for the main PLL
+ * @note They can be written only when the PLL is disabled
+ * @rmtoll CFGR2 PREDIV1 LL_RCC_PLL_GetPrediv\n
+ * CFGR2 PLLXTPRE LL_RCC_PLL_GetPrediv
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PREDIV_DIV_1
+ * @arg @ref LL_RCC_PREDIV_DIV_2
+ * @arg @ref LL_RCC_PREDIV_DIV_3 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_4 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_5 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_6 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_7 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_8 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_9 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_10 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_11 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_12 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_13 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_14 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_15 (*)
+ * @arg @ref LL_RCC_PREDIV_DIV_16 (*)
+ *
+ * (*) value not defined in all devices
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
+{
+#if defined(RCC_CFGR2_PREDIV1)
+ return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1));
+#else
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE));
+#endif /*RCC_CFGR2_PREDIV1*/
+}
+
+/**
+ * @}
+ */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
+ * @{
+ */
+
+/**
+ * @brief Enable PLLI2S
+ * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLL3ON);
+}
+
+/**
+ * @brief Disable PLLI2S
+ * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
+}
+
+/**
+ * @brief Check if PLLI2S Ready
+ * @rmtoll CR PLL3RDY LL_RCC_PLLI2S_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY));
+}
+
+/**
+ * @brief Configure PLLI2S used for I2S Domain
+ * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLLI2S\n
+ * CFGR2 PLL3MUL LL_RCC_PLL_ConfigDomain_PLLI2S
+ * @param Divider This parameter can be one of the following values:
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
+ * @param Multiplicator This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2S_MUL_8
+ * @arg @ref LL_RCC_PLLI2S_MUL_9
+ * @arg @ref LL_RCC_PLLI2S_MUL_10
+ * @arg @ref LL_RCC_PLLI2S_MUL_11
+ * @arg @ref LL_RCC_PLLI2S_MUL_12
+ * @arg @ref LL_RCC_PLLI2S_MUL_13
+ * @arg @ref LL_RCC_PLLI2S_MUL_14
+ * @arg @ref LL_RCC_PLLI2S_MUL_16
+ * @arg @ref LL_RCC_PLLI2S_MUL_20
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLI2S(uint32_t Divider, uint32_t Multiplicator)
+{
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator);
+}
+
+/**
+ * @brief Get PLLI2S Multiplication Factor
+ * @rmtoll CFGR2 PLL3MUL LL_RCC_PLLI2S_GetMultiplicator
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLI2S_MUL_8
+ * @arg @ref LL_RCC_PLLI2S_MUL_9
+ * @arg @ref LL_RCC_PLLI2S_MUL_10
+ * @arg @ref LL_RCC_PLLI2S_MUL_11
+ * @arg @ref LL_RCC_PLLI2S_MUL_12
+ * @arg @ref LL_RCC_PLLI2S_MUL_13
+ * @arg @ref LL_RCC_PLLI2S_MUL_14
+ * @arg @ref LL_RCC_PLLI2S_MUL_16
+ * @arg @ref LL_RCC_PLLI2S_MUL_20
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMultiplicator(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL));
+}
+
+/**
+ * @}
+ */
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/** @defgroup RCC_LL_EF_PLL2 PLL2
+ * @{
+ */
+
+/**
+ * @brief Enable PLL2
+ * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_PLL2ON);
+}
+
+/**
+ * @brief Disable PLL2
+ * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL2_Disable(void)
+{
+ CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
+}
+
+/**
+ * @brief Check if PLL2 Ready
+ * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
+{
+ return (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY));
+}
+
+/**
+ * @brief Configure PLL2 used for PLL2 Domain
+ * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLL2\n
+ * CFGR2 PLL2MUL LL_RCC_PLL_ConfigDomain_PLL2
+ * @param Divider This parameter can be one of the following values:
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
+ * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
+ * @param Multiplicator This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLL2_MUL_8
+ * @arg @ref LL_RCC_PLL2_MUL_9
+ * @arg @ref LL_RCC_PLL2_MUL_10
+ * @arg @ref LL_RCC_PLL2_MUL_11
+ * @arg @ref LL_RCC_PLL2_MUL_12
+ * @arg @ref LL_RCC_PLL2_MUL_13
+ * @arg @ref LL_RCC_PLL2_MUL_14
+ * @arg @ref LL_RCC_PLL2_MUL_16
+ * @arg @ref LL_RCC_PLL2_MUL_20
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLL2(uint32_t Divider, uint32_t Multiplicator)
+{
+ MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL, Divider | Multiplicator);
+}
+
+/**
+ * @brief Get PLL2 Multiplication Factor
+ * @rmtoll CFGR2 PLL2MUL LL_RCC_PLL2_GetMultiplicator
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLL2_MUL_8
+ * @arg @ref LL_RCC_PLL2_MUL_9
+ * @arg @ref LL_RCC_PLL2_MUL_10
+ * @arg @ref LL_RCC_PLL2_MUL_11
+ * @arg @ref LL_RCC_PLL2_MUL_12
+ * @arg @ref LL_RCC_PLL2_MUL_13
+ * @arg @ref LL_RCC_PLL2_MUL_14
+ * @arg @ref LL_RCC_PLL2_MUL_16
+ * @arg @ref LL_RCC_PLL2_MUL_20
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetMultiplicator(void)
+{
+ return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL));
+}
+
+/**
+ * @}
+ */
+#endif /* RCC_PLL2_SUPPORT */
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Clear LSI ready interrupt flag
+ * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
+}
+
+/**
+ * @brief Clear LSE ready interrupt flag
+ * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
+}
+
+/**
+ * @brief Clear HSI ready interrupt flag
+ * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
+}
+
+/**
+ * @brief Clear HSE ready interrupt flag
+ * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
+}
+
+/**
+ * @brief Clear PLL ready interrupt flag
+ * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Clear PLLI2S ready interrupt flag
+ * @rmtoll CIR PLL3RDYC LL_RCC_ClearFlag_PLLI2SRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYC);
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/**
+ * @brief Clear PLL2 ready interrupt flag
+ * @rmtoll CIR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYC);
+}
+#endif /* RCC_PLL2_SUPPORT */
+
+/**
+ * @brief Clear Clock security system interrupt flag
+ * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_CSSC);
+}
+
+/**
+ * @brief Check if LSI ready interrupt occurred or not
+ * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
+}
+
+/**
+ * @brief Check if LSE ready interrupt occurred or not
+ * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
+}
+
+/**
+ * @brief Check if HSI ready interrupt occurred or not
+ * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
+}
+
+/**
+ * @brief Check if HSE ready interrupt occurred or not
+ * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
+}
+
+/**
+ * @brief Check if PLL ready interrupt occurred or not
+ * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Check if PLLI2S ready interrupt occurred or not
+ * @rmtoll CIR PLL3RDYF LL_RCC_IsActiveFlag_PLLI2SRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYF) == (RCC_CIR_PLL3RDYF));
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/**
+ * @brief Check if PLL2 ready interrupt occurred or not
+ * @rmtoll CIR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYF) == (RCC_CIR_PLL2RDYF));
+}
+#endif /* RCC_PLL2_SUPPORT */
+
+/**
+ * @brief Check if Clock security system interrupt occurred or not
+ * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
+}
+
+/**
+ * @brief Check if RCC flag Independent Watchdog reset is set or not.
+ * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Low Power reset is set or not.
+ * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Pin reset is set or not.
+ * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
+}
+
+/**
+ * @brief Check if RCC flag POR/PDR reset is set or not.
+ * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Software reset is set or not.
+ * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
+}
+
+/**
+ * @brief Check if RCC flag Window Watchdog reset is set or not.
+ * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
+{
+ return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
+}
+
+/**
+ * @brief Set RMVF bit to clear the reset flags.
+ * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+ * @{
+ */
+
+/**
+ * @brief Enable LSI ready interrupt
+ * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+ * @brief Enable LSE ready interrupt
+ * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+ * @brief Enable HSI ready interrupt
+ * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+ * @brief Enable HSE ready interrupt
+ * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+ * @brief Enable PLL ready interrupt
+ * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Enable PLLI2S ready interrupt
+ * @rmtoll CIR PLL3RDYIE LL_RCC_EnableIT_PLLI2SRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/**
+ * @brief Enable PLL2 ready interrupt
+ * @rmtoll CIR PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
+{
+ SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
+}
+#endif /* RCC_PLL2_SUPPORT */
+
+/**
+ * @brief Disable LSI ready interrupt
+ * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+ * @brief Disable LSE ready interrupt
+ * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+ * @brief Disable HSI ready interrupt
+ * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+ * @brief Disable HSE ready interrupt
+ * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+ * @brief Disable PLL ready interrupt
+ * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Disable PLLI2S ready interrupt
+ * @rmtoll CIR PLL3RDYIE LL_RCC_DisableIT_PLLI2SRDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/**
+ * @brief Disable PLL2 ready interrupt
+ * @rmtoll CIR PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
+{
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
+}
+#endif /* RCC_PLL2_SUPPORT */
+
+/**
+ * @brief Checks if LSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
+}
+
+/**
+ * @brief Checks if LSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
+}
+
+/**
+ * @brief Checks if HSI ready interrupt source is enabled or disabled.
+ * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
+}
+
+/**
+ * @brief Checks if HSE ready interrupt source is enabled or disabled.
+ * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
+}
+
+/**
+ * @brief Checks if PLL ready interrupt source is enabled or disabled.
+ * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
+ * @rmtoll CIR PLL3RDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE) == (RCC_CIR_PLL3RDYIE));
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLL2_SUPPORT)
+/**
+ * @brief Checks if PLL2 ready interrupt source is enabled or disabled.
+ * @rmtoll CIR PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
+{
+ return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE) == (RCC_CIR_PLL2RDYIE));
+}
+#endif /* RCC_PLL2_SUPPORT */
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+ * @{
+ */
+ErrorStatus LL_RCC_DeInit(void);
+/**
+ * @}
+ */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+ * @{
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+#if defined(RCC_CFGR2_I2S2SRC)
+uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
+#endif /* RCC_CFGR2_I2S2SRC */
+#if defined(USB_OTG_FS) || defined(USB)
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+#endif /* USB_OTG_FS || USB */
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* RCC */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_RCC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_rtc.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_rtc.h
new file mode 100644
index 0000000..4d15712
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_rtc.h
@@ -0,0 +1,1021 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_rtc.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of RTC LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_RTC_H
+#define __STM32F1xx_LL_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined(RTC)
+
+/** @defgroup RTC_LL RTC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_Private_Macros RTC Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief RTC Init structures definition
+ */
+typedef struct
+{
+ uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_SetAsynchPrescaler(). */
+
+ uint32_t OutPutSource; /*!< Specifies which signal will be routed to the RTC Tamper pin.
+ This parameter can be a value of @ref LL_RTC_Output_Source
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RTC_SetOutputSource(). */
+
+} LL_RTC_InitTypeDef;
+
+/**
+ * @brief RTC Time structure definition
+ */
+typedef struct
+{
+ uint8_t Hours; /*!< Specifies the RTC Time Hours.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 23 */
+
+ uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+ uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+} LL_RTC_TimeTypeDef;
+
+
+/**
+ * @brief RTC Alarm structure definition
+ */
+typedef struct
+{
+ LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */
+
+} LL_RTC_AlarmTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
+ * @{
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EC_FORMAT FORMAT
+ * @{
+ */
+#define LL_RTC_FORMAT_BIN (0x000000000U) /*!< Binary data format */
+#define LL_RTC_FORMAT_BCD (0x000000001U) /*!< BCD data format */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup RTC_LL_EC_BKP BACKUP
+ * @{
+ */
+#if RTC_BKP_NUMBER > 0
+#define LL_RTC_BKP_DR1 (0x00000001U)
+#define LL_RTC_BKP_DR2 (0x00000002U)
+#define LL_RTC_BKP_DR3 (0x00000003U)
+#define LL_RTC_BKP_DR4 (0x00000004U)
+#define LL_RTC_BKP_DR5 (0x00000005U)
+#define LL_RTC_BKP_DR6 (0x00000006U)
+#define LL_RTC_BKP_DR7 (0x00000007U)
+#define LL_RTC_BKP_DR8 (0x00000008U)
+#define LL_RTC_BKP_DR9 (0x00000009U)
+#define LL_RTC_BKP_DR10 (0x0000000AU)
+#endif /* RTC_BKP_NUMBER > 0 */
+#if RTC_BKP_NUMBER > 10
+#define LL_RTC_BKP_DR11 (0x0000000BU)
+#define LL_RTC_BKP_DR12 (0x0000000CU)
+#define LL_RTC_BKP_DR13 (0x0000000DU)
+#define LL_RTC_BKP_DR14 (0x0000000EU)
+#define LL_RTC_BKP_DR15 (0x0000000FU)
+#define LL_RTC_BKP_DR16 (0x00000010U)
+#define LL_RTC_BKP_DR17 (0x00000011U)
+#define LL_RTC_BKP_DR18 (0x00000012U)
+#define LL_RTC_BKP_DR19 (0x00000013U)
+#define LL_RTC_BKP_DR20 (0x00000014U)
+#define LL_RTC_BKP_DR21 (0x00000015U)
+#define LL_RTC_BKP_DR22 (0x00000016U)
+#define LL_RTC_BKP_DR23 (0x00000017U)
+#define LL_RTC_BKP_DR24 (0x00000018U)
+#define LL_RTC_BKP_DR25 (0x00000019U)
+#define LL_RTC_BKP_DR26 (0x0000001AU)
+#define LL_RTC_BKP_DR27 (0x0000001BU)
+#define LL_RTC_BKP_DR28 (0x0000001CU)
+#define LL_RTC_BKP_DR29 (0x0000001DU)
+#define LL_RTC_BKP_DR30 (0x0000001EU)
+#define LL_RTC_BKP_DR31 (0x0000001FU)
+#define LL_RTC_BKP_DR32 (0x00000020U)
+#define LL_RTC_BKP_DR33 (0x00000021U)
+#define LL_RTC_BKP_DR34 (0x00000022U)
+#define LL_RTC_BKP_DR35 (0x00000023U)
+#define LL_RTC_BKP_DR36 (0x00000024U)
+#define LL_RTC_BKP_DR37 (0x00000025U)
+#define LL_RTC_BKP_DR38 (0x00000026U)
+#define LL_RTC_BKP_DR39 (0x00000027U)
+#define LL_RTC_BKP_DR40 (0x00000028U)
+#define LL_RTC_BKP_DR41 (0x00000029U)
+#define LL_RTC_BKP_DR42 (0x0000002AU)
+#endif /* RTC_BKP_NUMBER > 10 */
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EC_TAMPLEVEL Tamper Active Level
+ * @{
+ */
+#define LL_RTC_TAMPER_ACTIVELEVEL_LOW BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
+#define LL_RTC_TAMPER_ACTIVELEVEL_HIGH (0x00000000U) /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
+
+/**
+ * @}
+ */
+
+/** @defgroup LL_RTC_Output_Source Clock Source to output on the Tamper Pin
+ * @{
+ */
+#define LL_RTC_CALIB_OUTPUT_NONE (0x00000000U) /*!< Calibration output disabled */
+#define LL_RTC_CALIB_OUTPUT_RTCCLOCK BKP_RTCCR_CCO /*!< Calibration output is RTC Clock with a frequency divided by 64 on the TAMPER Pin */
+#define LL_RTC_CALIB_OUTPUT_ALARM BKP_RTCCR_ASOE /*!< Calibration output is Alarm pulse signal on the TAMPER pin */
+#define LL_RTC_CALIB_OUTPUT_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Calibration output is Second pulse signal on the TAMPER pin*/
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
+ * @{
+ */
+
+/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in RTC register
+ * @param __INSTANCE__ RTC Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in RTC register
+ * @param __INSTANCE__ RTC Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EM_Convert Convert helper Macros
+ * @{
+ */
+
+/**
+ * @brief Helper macro to convert a value from 2 digit decimal format to BCD format
+ * @param __VALUE__ Byte to be converted
+ * @retval Converted byte
+ */
+#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
+
+/**
+ * @brief Helper macro to convert a value from BCD format to 2 digit decimal format
+ * @param __VALUE__ BCD value to be converted
+ * @retval Converted byte
+ */
+#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
+ * @{
+ */
+
+/** @defgroup RTC_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Set Asynchronous prescaler factor
+ * @rmtoll PRLH PRL LL_RTC_SetAsynchPrescaler\n
+ * @rmtoll PRLL PRL LL_RTC_SetAsynchPrescaler\n
+ * @param RTCx RTC Instance
+ * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0xFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
+{
+ MODIFY_REG(RTCx->PRLH, RTC_PRLH_PRL, (AsynchPrescaler >> 16));
+ MODIFY_REG(RTCx->PRLL, RTC_PRLL_PRL, (AsynchPrescaler & RTC_PRLL_PRL));
+}
+
+/**
+ * @brief Get Asynchronous prescaler factor
+ * @rmtoll DIVH DIV LL_RTC_GetDivider\n
+ * @rmtoll DIVL DIV LL_RTC_GetDivider\n
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data = 0 and Max_Data = 0xFFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetDivider(RTC_TypeDef *RTCx)
+{
+ register uint16_t Highprescaler = 0 , Lowprescaler = 0;
+ Highprescaler = READ_REG(RTCx->DIVH & RTC_DIVH_RTC_DIV);
+ Lowprescaler = READ_REG(RTCx->DIVL & RTC_DIVL_RTC_DIV);
+
+ return (((uint32_t) Highprescaler << 16U) | Lowprescaler);
+}
+
+/**
+ * @brief Set Output Source
+ * @rmtoll RTCCR CCO LL_RTC_SetOutputSource
+ * @rmtoll RTCCR ASOE LL_RTC_SetOutputSource
+ * @rmtoll RTCCR ASOS LL_RTC_SetOutputSource
+ * @param BKPx BKP Instance
+ * @param OutputSource This parameter can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+ * @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK
+ * @arg @ref LL_RTC_CALIB_OUTPUT_ALARM
+ * @arg @ref LL_RTC_CALIB_OUTPUT_SECOND
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_SetOutputSource(BKP_TypeDef *BKPx, uint32_t OutputSource)
+{
+ MODIFY_REG(BKPx->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), OutputSource);
+}
+
+/**
+ * @brief Get Output Source
+ * @rmtoll RTCCR CCO LL_RTC_GetOutPutSource
+ * @rmtoll RTCCR ASOE LL_RTC_GetOutPutSource
+ * @rmtoll RTCCR ASOS LL_RTC_GetOutPutSource
+ * @param BKPx BKP Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
+ * @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK
+ * @arg @ref LL_RTC_CALIB_OUTPUT_ALARM
+ * @arg @ref LL_RTC_CALIB_OUTPUT_SECOND
+ */
+__STATIC_INLINE uint32_t LL_RTC_GetOutPutSource(BKP_TypeDef *BKPx)
+{
+ return (uint32_t)(READ_BIT(BKPx->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS)));
+}
+
+/**
+ * @brief Enable the write protection for RTC registers.
+ * @rmtoll CRL CNF LL_RTC_EnableWriteProtection
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CRL, RTC_CRL_CNF);
+}
+
+/**
+ * @brief Disable the write protection for RTC registers.
+ * @rmtoll CRL RTC_CRL_CNF LL_RTC_DisableWriteProtection
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CRL, RTC_CRL_CNF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Time Time
+ * @{
+ */
+
+/**
+ * @brief Set time counter in BCD format
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function)
+ * @rmtoll CNTH CNT LL_RTC_TIME_Set\n
+ * CNTL CNT LL_RTC_TIME_Set\n
+ * @param RTCx RTC Instance
+ * @param TimeCounter Value between Min_Data=0x00 and Max_Data=0xFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TIME_Set(RTC_TypeDef *RTCx, uint32_t TimeCounter)
+{
+ /* Set RTC COUNTER MSB word */
+ WRITE_REG(RTCx->CNTH, (TimeCounter >> 16U));
+ /* Set RTC COUNTER LSB word */
+ WRITE_REG(RTCx->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT));
+}
+
+/**
+ * @brief Get time counter in BCD format
+ * @rmtoll CNTH CNT LL_RTC_TIME_Get\n
+ * CNTL CNT LL_RTC_TIME_Get\n
+ * @param RTCx RTC Instance
+ * @retval Value between Min_Data = 0 and Max_Data = 0xFFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
+{
+ register uint16_t high = 0, low = 0;
+
+ high = READ_REG(RTCx->CNTH & RTC_CNTH_RTC_CNT);
+ low = READ_REG(RTCx->CNTL & RTC_CNTL_RTC_CNT);
+ return ((uint32_t)(((uint32_t) high << 16U) | low));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_ALARM ALARM
+ * @{
+ */
+
+/**
+ * @brief Set Alarm Counter
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll ALRH ALR LL_RTC_ALARM_Set\n
+ * @rmtoll ALRL ALR LL_RTC_ALARM_Set\n
+ * @param RTCx RTC Instance
+ * @param AlarmCounter Value between Min_Data=0x00 and Max_Data=0xFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ALARM_Set(RTC_TypeDef *RTCx, uint32_t AlarmCounter)
+{
+ /* Set RTC COUNTER MSB word */
+ WRITE_REG(RTCx->ALRH, (AlarmCounter >> 16));
+ /* Set RTC COUNTER LSB word */
+ WRITE_REG(RTCx->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR));
+}
+
+/**
+ * @brief Get Alarm Counter
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll ALRH ALR LL_RTC_ALARM_Get\n
+ * @rmtoll ALRL ALR LL_RTC_ALARM_Get\n
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_RTC_ALARM_Get(RTC_TypeDef *RTCx)
+{
+ register uint16_t high = 0, low = 0;
+
+ high = READ_REG(RTCx->ALRH & RTC_ALRH_RTC_ALR);
+ low = READ_REG(RTCx->ALRL & RTC_ALRL_RTC_ALR);
+
+ return (((uint32_t) high << 16U) | low);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Tamper Tamper
+ * @{
+ */
+
+/**
+ * @brief Enable RTC_TAMPx input detection
+ * @rmtoll CR TPE LL_RTC_TAMPER_Enable\n
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_Enable(BKP_TypeDef *BKPx)
+{
+ SET_BIT(BKPx->CR, BKP_CR_TPE);
+}
+
+/**
+ * @brief Disable RTC_TAMPx Tamper
+ * @rmtoll CR TPE LL_RTC_TAMPER_Disable\n
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_Disable(BKP_TypeDef *BKPx)
+{
+ CLEAR_BIT(BKP->CR, BKP_CR_TPE);
+}
+
+/**
+ * @brief Enable Active level for Tamper input
+ * @rmtoll CR TPAL LL_RTC_TAMPER_SetActiveLevel\n
+ * @param BKPx BKP Instance
+ * @param Tamper This parameter can be a combination of the following values:
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_LOW
+ * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_TAMPER_SetActiveLevel(BKP_TypeDef *BKPx, uint32_t Tamper)
+{
+ MODIFY_REG(BKPx->CR, BKP_CR_TPAL, Tamper);
+}
+
+/**
+ * @brief Disable Active level for Tamper input
+ * @rmtoll CR TPAL LL_RTC_TAMPER_SetActiveLevel\n
+ * @retval None
+ */
+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetActiveLevel(BKP_TypeDef *BKPx)
+{
+ return (uint32_t)(READ_BIT(BKPx->CR, BKP_CR_TPAL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
+ * @{
+ */
+
+/**
+ * @brief Writes a data in a specified RTC Backup data register.
+ * @rmtoll BKPDR DR LL_RTC_BKP_SetRegister
+ * @param BKPx BKP Instance
+ * @param BackupRegister This parameter can be one of the following values:
+ * @arg @ref LL_RTC_BKP_DR1
+ * @arg @ref LL_RTC_BKP_DR2
+ * @arg @ref LL_RTC_BKP_DR3
+ * @arg @ref LL_RTC_BKP_DR4
+ * @arg @ref LL_RTC_BKP_DR5
+ * @arg @ref LL_RTC_BKP_DR6
+ * @arg @ref LL_RTC_BKP_DR7
+ * @arg @ref LL_RTC_BKP_DR8
+ * @arg @ref LL_RTC_BKP_DR9
+ * @arg @ref LL_RTC_BKP_DR10
+ * @arg @ref LL_RTC_BKP_DR11 (*)
+ * @arg @ref LL_RTC_BKP_DR12 (*)
+ * @arg @ref LL_RTC_BKP_DR13 (*)
+ * @arg @ref LL_RTC_BKP_DR14 (*)
+ * @arg @ref LL_RTC_BKP_DR15 (*)
+ * @arg @ref LL_RTC_BKP_DR16 (*)
+ * @arg @ref LL_RTC_BKP_DR17 (*)
+ * @arg @ref LL_RTC_BKP_DR18 (*)
+ * @arg @ref LL_RTC_BKP_DR19 (*)
+ * @arg @ref LL_RTC_BKP_DR20 (*)
+ * @arg @ref LL_RTC_BKP_DR21 (*)
+ * @arg @ref LL_RTC_BKP_DR22 (*)
+ * @arg @ref LL_RTC_BKP_DR23 (*)
+ * @arg @ref LL_RTC_BKP_DR24 (*)
+ * @arg @ref LL_RTC_BKP_DR25 (*)
+ * @arg @ref LL_RTC_BKP_DR26 (*)
+ * @arg @ref LL_RTC_BKP_DR27 (*)
+ * @arg @ref LL_RTC_BKP_DR28 (*)
+ * @arg @ref LL_RTC_BKP_DR29 (*)
+ * @arg @ref LL_RTC_BKP_DR30 (*)
+ * @arg @ref LL_RTC_BKP_DR31 (*)
+ * @arg @ref LL_RTC_BKP_DR32 (*)
+ * @arg @ref LL_RTC_BKP_DR33 (*)
+ * @arg @ref LL_RTC_BKP_DR34 (*)
+ * @arg @ref LL_RTC_BKP_DR35 (*)
+ * @arg @ref LL_RTC_BKP_DR36 (*)
+ * @arg @ref LL_RTC_BKP_DR37 (*)
+ * @arg @ref LL_RTC_BKP_DR38 (*)
+ * @arg @ref LL_RTC_BKP_DR39 (*)
+ * @arg @ref LL_RTC_BKP_DR40 (*)
+ * @arg @ref LL_RTC_BKP_DR41 (*)
+ * @arg @ref LL_RTC_BKP_DR42 (*)
+ * (*) value not defined in all devices.
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_BKP_SetRegister(BKP_TypeDef *BKPx, uint32_t BackupRegister, uint32_t Data)
+{
+ register uint32_t tmp = 0U;
+
+ tmp = (uint32_t)BKP_BASE;
+ tmp += (BackupRegister * 4U);
+
+ /* Write the specified register */
+ *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+ * @brief Reads data from the specified RTC Backup data Register.
+ * @rmtoll BKPDR DR LL_RTC_BKP_GetRegister
+ * @param BKPx BKP Instance
+ * @param BackupRegister This parameter can be one of the following values:
+ * @arg @ref LL_RTC_BKP_DR1
+ * @arg @ref LL_RTC_BKP_DR2
+ * @arg @ref LL_RTC_BKP_DR3
+ * @arg @ref LL_RTC_BKP_DR4
+ * @arg @ref LL_RTC_BKP_DR5
+ * @arg @ref LL_RTC_BKP_DR6
+ * @arg @ref LL_RTC_BKP_DR7
+ * @arg @ref LL_RTC_BKP_DR8
+ * @arg @ref LL_RTC_BKP_DR9
+ * @arg @ref LL_RTC_BKP_DR10
+ * @arg @ref LL_RTC_BKP_DR11 (*)
+ * @arg @ref LL_RTC_BKP_DR12 (*)
+ * @arg @ref LL_RTC_BKP_DR13 (*)
+ * @arg @ref LL_RTC_BKP_DR14 (*)
+ * @arg @ref LL_RTC_BKP_DR15 (*)
+ * @arg @ref LL_RTC_BKP_DR16 (*)
+ * @arg @ref LL_RTC_BKP_DR17 (*)
+ * @arg @ref LL_RTC_BKP_DR18 (*)
+ * @arg @ref LL_RTC_BKP_DR19 (*)
+ * @arg @ref LL_RTC_BKP_DR20 (*)
+ * @arg @ref LL_RTC_BKP_DR21 (*)
+ * @arg @ref LL_RTC_BKP_DR22 (*)
+ * @arg @ref LL_RTC_BKP_DR23 (*)
+ * @arg @ref LL_RTC_BKP_DR24 (*)
+ * @arg @ref LL_RTC_BKP_DR25 (*)
+ * @arg @ref LL_RTC_BKP_DR26 (*)
+ * @arg @ref LL_RTC_BKP_DR27 (*)
+ * @arg @ref LL_RTC_BKP_DR28 (*)
+ * @arg @ref LL_RTC_BKP_DR29 (*)
+ * @arg @ref LL_RTC_BKP_DR30 (*)
+ * @arg @ref LL_RTC_BKP_DR31 (*)
+ * @arg @ref LL_RTC_BKP_DR32 (*)
+ * @arg @ref LL_RTC_BKP_DR33 (*)
+ * @arg @ref LL_RTC_BKP_DR34 (*)
+ * @arg @ref LL_RTC_BKP_DR35 (*)
+ * @arg @ref LL_RTC_BKP_DR36 (*)
+ * @arg @ref LL_RTC_BKP_DR37 (*)
+ * @arg @ref LL_RTC_BKP_DR38 (*)
+ * @arg @ref LL_RTC_BKP_DR39 (*)
+ * @arg @ref LL_RTC_BKP_DR40 (*)
+ * @arg @ref LL_RTC_BKP_DR41 (*)
+ * @arg @ref LL_RTC_BKP_DR42 (*)
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
+ */
+__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(BKP_TypeDef *BKPx, uint32_t BackupRegister)
+{
+ register uint32_t tmp = 0U;
+
+ tmp = (uint32_t)BKP_BASE;
+ tmp += (BackupRegister * 4U);
+
+ /* Read the specified register */
+ return ((*(__IO uint32_t *)tmp) & BKP_DR1_D);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_Calibration Calibration
+ * @{
+ */
+
+/**
+ * @brief Set the coarse digital calibration
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function)
+ * @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n
+ * @param BKPx RTC Instance
+ * @param Value value of coarse calibration expressed in ppm (coded on 5 bits)
+ * @note This Calibration value should be between 0 and 121 when using positive sign with a 4-ppm step.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_CAL_SetCoarseDigital(BKP_TypeDef* BKPx, uint32_t Value)
+{
+ MODIFY_REG(BKPx->RTCCR,BKP_RTCCR_CAL, Value);
+}
+
+/**
+ * @brief Get the coarse digital calibration value
+ * @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n
+ * @param BKPx BKP Instance
+ * @retval value of coarse calibration expressed in ppm (coded on 5 bits)
+ */
+__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigital(BKP_TypeDef *BKPx)
+{
+ return (uint32_t)(READ_BIT(BKPx->RTCCR, BKP_RTCCR_CAL));
+}
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Get RTC_TAMPI Interruption detection flag
+ * @rmtoll CSR TIF LL_RTC_IsActiveFlag_TAMPI
+ * @param BKPx BKP Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMPI(BKP_TypeDef *BKPx)
+{
+ return (READ_BIT(BKPx->CSR, BKP_CSR_TIF) == (BKP_CSR_TIF));
+}
+
+/**
+ * @brief Clear RTC_TAMP Interruption detection flag
+ * @rmtoll CSR CTI LL_RTC_ClearFlag_TAMPI
+ * @param BKPx BKP Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMPI(BKP_TypeDef *BKPx)
+{
+ SET_BIT(BKPx->CSR, BKP_CSR_CTI);
+}
+
+/**
+ * @brief Get RTC_TAMPE Event detection flag
+ * @rmtoll CSR TEF LL_RTC_IsActiveFlag_TAMPE
+ * @param BKPx BKP Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMPE(BKP_TypeDef *BKPx)
+{
+ return (READ_BIT(BKPx->CSR, BKP_CSR_TEF) == (BKP_CSR_TEF));
+}
+
+/**
+ * @brief Clear RTC_TAMPE Even detection flag
+ * @rmtoll CSR CTE LL_RTC_ClearFlag_TAMPE
+ * @param BKPx BKP Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_TAMPE(BKP_TypeDef *BKPx)
+{
+ SET_BIT(BKPx->CSR, BKP_CSR_CTE);
+}
+
+/**
+ * @brief Get Alarm flag
+ * @rmtoll CRL ALRF LL_RTC_IsActiveFlag_ALR
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALR(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CRL, RTC_CRL_ALRF) == (RTC_CRL_ALRF));
+}
+
+/**
+ * @brief Clear Alarm flag
+ * @rmtoll CRL ALRF LL_RTC_ClearFlag_ALR
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_ALR(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CRL, RTC_CRL_ALRF);
+}
+
+/**
+ * @brief Get Registers synchronization flag
+ * @rmtoll CRL RSF LL_RTC_IsActiveFlag_RS
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CRL, RTC_CRL_RSF) == (RTC_CRL_RSF));
+}
+
+/**
+ * @brief Clear Registers synchronization flag
+ * @rmtoll CRL RSF LL_RTC_ClearFlag_RS
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CRL, RTC_CRL_RSF);
+}
+
+/**
+ * @brief Get Registers OverFlow flag
+ * @rmtoll CRL OWF LL_RTC_IsActiveFlag_OW
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_OW(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CRL, RTC_CRL_OWF) == (RTC_CRL_OWF));
+}
+
+/**
+ * @brief Clear Registers OverFlow flag
+ * @rmtoll CRL OWF LL_RTC_ClearFlag_OW
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_OW(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CRL, RTC_CRL_OWF);
+}
+
+/**
+ * @brief Get Registers synchronization flag
+ * @rmtoll CRL SECF LL_RTC_IsActiveFlag_SEC
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SEC(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CRL, RTC_CRL_SECF) == (RTC_CRL_SECF));
+}
+
+/**
+ * @brief Clear Registers synchronization flag
+ * @rmtoll CRL SECF LL_RTC_ClearFlag_SEC
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_ClearFlag_SEC(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CRL, RTC_CRL_SECF);
+}
+
+/**
+ * @brief Get RTC Operation OFF status flag
+ * @rmtoll CRL RTOFF LL_RTC_IsActiveFlag_RTOF
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RTOF(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CRL, RTC_CRL_RTOFF) == (RTC_CRL_RTOFF));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup RTC_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable Alarm interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CRH ALRIE LL_RTC_EnableIT_ALR
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_ALR(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CRH, RTC_CRH_ALRIE);
+}
+
+/**
+ * @brief Disable Alarm interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CRH ALRIE LL_RTC_DisableIT_ALR
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_ALR(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CRH, RTC_CRH_ALRIE);
+}
+
+/**
+ * @brief Check if Alarm interrupt is enabled or not
+ * @rmtoll CRH ALRIE LL_RTC_IsEnabledIT_ALR
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALR(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CRH, RTC_CRH_ALRIE) == (RTC_CRH_ALRIE));
+}
+
+/**
+ * @brief Enable Second Interrupt interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CRH SECIE LL_RTC_EnableIT_SEC
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_SEC(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CRH, RTC_CRH_SECIE);
+}
+
+/**
+ * @brief Disable Second interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CRH SECIE LL_RTC_DisableIT_SEC
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_SEC(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CRH, RTC_CRH_SECIE);
+}
+
+/**
+ * @brief Check if Second interrupt is enabled or not
+ * @rmtoll CRH SECIE LL_RTC_IsEnabledIT_SEC
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SEC(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CRH, RTC_CRH_SECIE) == (RTC_CRH_SECIE));
+}
+
+/**
+ * @brief Enable OverFlow interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CRH OWIE LL_RTC_EnableIT_OW
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_OW(RTC_TypeDef *RTCx)
+{
+ SET_BIT(RTCx->CRH, RTC_CRH_OWIE);
+}
+
+/**
+ * @brief Disable OverFlow interrupt
+ * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
+ * @rmtoll CRH OWIE LL_RTC_DisableIT_OW
+ * @param RTCx RTC Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_OW(RTC_TypeDef *RTCx)
+{
+ CLEAR_BIT(RTCx->CRH, RTC_CRH_OWIE);
+}
+
+/**
+ * @brief Check if OverFlow interrupt is enabled or not
+ * @rmtoll CRH OWIE LL_RTC_IsEnabledIT_OW
+ * @param RTCx RTC Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_OW(RTC_TypeDef *RTCx)
+{
+ return (READ_BIT(RTCx->CRH, RTC_CRH_OWIE) == (RTC_CRH_OWIE));
+}
+
+/**
+ * @brief Enable Tamper interrupt
+ * @rmtoll CSR TPIE LL_RTC_EnableIT_TAMP
+ * @param BKPx BKP Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_EnableIT_TAMP(BKP_TypeDef *BKPx)
+{
+ SET_BIT(BKPx->CSR,BKP_CSR_TPIE);
+}
+
+/**
+ * @brief Disable Tamper interrupt
+ * @rmtoll CSR TPIE LL_RTC_EnableIT_TAMP
+ * @param BKPx BKP Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_RTC_DisableIT_TAMP(BKP_TypeDef *BKPx)
+{
+ CLEAR_BIT(BKPx->CSR,BKP_CSR_TPIE);
+}
+
+/**
+ * @brief Check if all the TAMPER interrupts are enabled or not
+ * @rmtoll CSR TPIE LL_RTC_IsEnabledIT_TAMP
+ * @param BKPx BKP Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(BKP_TypeDef *BKPx)
+{
+ return (READ_BIT(BKPx->CSR,BKP_CSR_TPIE) == BKP_CSR_TPIE);
+}
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
+void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
+void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
+ErrorStatus LL_RTC_ALARM_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+void LL_RTC_ALARM_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
+ErrorStatus LL_RTC_TIME_SetCounter(RTC_TypeDef *RTCx, uint32_t TimeCounter);
+ErrorStatus LL_RTC_ALARM_SetCounter(RTC_TypeDef *RTCx, uint32_t AlarmCounter);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RTC) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_sdmmc.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_sdmmc.h
index b37a264..3473134 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_sdmmc.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_sdmmc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f1xx_ll_sdmmc.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of low layer SDMMC HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -147,11 +147,201 @@
/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
* @{
*/
+#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */
+#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */
+#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */
+#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */
+#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */
+#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */
+#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */
+#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */
+#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
+ number of transferred bytes does not match the block length */
+#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */
+#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */
+#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
+ command or if there was an attempt to access a locked card */
+#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */
+#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */
+#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */
+#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */
+#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */
+#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */
+#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */
+#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */
+#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */
+#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */
+#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
+ of erase sequence command was received */
+#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */
+#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */
+#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */
+#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */
+#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */
+#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */
+#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */
+#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */
+#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */
-/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
+/**
+ * @brief SDMMC Commands Index
+ */
+#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */
+#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
+#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */
+#define SDMMC_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
+ operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
+#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */
+#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
+ and asks the card whether card supports voltage. */
+#define SDMMC_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
+#define SDMMC_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */
+#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */
+#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */
+#define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */
+#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /*!< Reserved */
+#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */
+#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
+ (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
+ for SDHS and SDXC. */
+#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+ fixed 512 bytes in case of SDHC and SDXC. */
+#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
+ STOP_TRANSMISSION command. */
+#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
+#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */
+#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
+ fixed 512 bytes in case of SDHC and SDXC. */
+#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
+#define SDMMC_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */
+#define SDMMC_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */
+#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */
+#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */
+#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */
+#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */
+#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */
+#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
+ system set by switch function command (CMD6). */
+#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
+ Reserved for each command system set by switch function command (CMD6). */
+#define SDMMC_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */
+#define SDMMC_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */
+#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */
+#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
+ the SET_BLOCK_LEN command. */
+#define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
+ than a standard command. */
+#define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
+ for general purpose/application specific commands. */
+#define SDMMC_CMD_NO_CMD ((uint8_t)64) /*!< No command */
+
+/**
+ * @brief Following commands are SD Card Specific commands.
+ * SDMMC_APP_CMD should be sent before sending these commands.
+ */
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
+ widths are given in SCR register. */
+#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
+ 32bit+CRC data block. */
+#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
+ send its operating condition register (OCR) content in the response on the CMD line. */
+#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
+#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */
+#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */
+#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */
+
+/**
+ * @brief Following commands are SD Card Specific security commands.
+ * SDMMC_CMD_APP_CMD should be sent before sending these commands.
+ */
+#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43)
+#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44)
+#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
+#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
+#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
+#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
+#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
+#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
+#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
+
+/**
+ * @brief Masks for errors Card Status R1 (OCR Register)
+ */
+#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
+#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
+#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
+#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
+#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
+#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
+#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
+#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
+#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
+#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
+#define SDMMC_OCR_CC_ERROR 0x00100000U
+#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
+#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
+#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
+#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
+#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
+#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
+#define SDMMC_OCR_ERASE_RESET 0x00002000U
+#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
+#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
+
+/**
+ * @brief Masks for R6 Response
+ */
+#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
+#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
+#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
+
+#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
+#define SDMMC_HIGH_CAPACITY 0x40000000U
+#define SDMMC_STD_CAPACITY 0x00000000U
+#define SDMMC_CHECK_PATTERN 0x000001AAU
+
+#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
+
+#define SDMMC_MAX_TRIAL 0x0000FFFFU
+
+#define SDMMC_ALLZERO 0x00000000U
+
+#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
+#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
+#define SDMMC_CARD_LOCKED 0x02000000U
+
+#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
+
+#define SDMMC_0TO7BITS 0x000000FFU
+#define SDMMC_8TO15BITS 0x0000FF00U
+#define SDMMC_16TO23BITS 0x00FF0000U
+#define SDMMC_24TO31BITS 0xFF000000U
+#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
+
+#define SDMMC_HALFFIFO 0x00000008U
+#define SDMMC_HALFFIFOBYTES 0x00000020U
+
+/**
+ * @brief Command Class supported
+ */
+#define SDIO_CCCC_ERASE 0x00000020U
+
+#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
+#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
+
+
+/** @defgroup SDIO_LL_Clock_Edge Clock Edge
* @{
*/
-#define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
+#define SDIO_CLOCK_EDGE_RISING 0x00000000U
#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
@@ -160,10 +350,10 @@
* @}
*/
-/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
+/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
* @{
*/
-#define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
+#define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U
#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
@@ -172,10 +362,10 @@
* @}
*/
-/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
+/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
* @{
*/
-#define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
+#define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U
#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
@@ -184,10 +374,10 @@
* @}
*/
-/** @defgroup SDMMC_LL_Bus_Wide Bus Width
+/** @defgroup SDIO_LL_Bus_Wide Bus Width
* @{
*/
-#define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
+#define SDIO_BUS_WIDE_1B 0x00000000U
#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
@@ -198,10 +388,10 @@
* @}
*/
-/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
+/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
* @{
*/
-#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
+#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U
#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
@@ -210,26 +400,26 @@
* @}
*/
-/** @defgroup SDMMC_LL_Clock_Division Clock Division
+/** @defgroup SDIO_LL_Clock_Division Clock Division
* @{
*/
-#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
+#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
/**
* @}
*/
-/** @defgroup SDMMC_LL_Command_Index Command Index
+/** @defgroup SDIO_LL_Command_Index Command Index
* @{
*/
-#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
/**
* @}
*/
-/** @defgroup SDMMC_LL_Response_Type Response Type
+/** @defgroup SDIO_LL_Response_Type Response Type
* @{
*/
-#define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
+#define SDIO_RESPONSE_NO 0x00000000U
#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
@@ -240,10 +430,10 @@
* @}
*/
-/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
+/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
* @{
*/
-#define SDIO_WAIT_NO ((uint32_t)0x00000000)
+#define SDIO_WAIT_NO 0x00000000U
#define SDIO_WAIT_IT SDIO_CMD_WAITINT
#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
@@ -254,10 +444,10 @@
* @}
*/
-/** @defgroup SDMMC_LL_CPSM_State CPSM State
+/** @defgroup SDIO_LL_CPSM_State CPSM State
* @{
*/
-#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
+#define SDIO_CPSM_DISABLE 0x00000000U
#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
@@ -266,13 +456,13 @@
* @}
*/
-/** @defgroup SDMMC_LL_Response_Registers Response Register
+/** @defgroup SDIO_LL_Response_Registers Response Register
* @{
*/
-#define SDIO_RESP1 ((uint32_t)0x00000000)
-#define SDIO_RESP2 ((uint32_t)0x00000004)
-#define SDIO_RESP3 ((uint32_t)0x00000008)
-#define SDIO_RESP4 ((uint32_t)0x0000000C)
+#define SDIO_RESP1 0x00000000U
+#define SDIO_RESP2 0x00000004U
+#define SDIO_RESP3 0x00000008U
+#define SDIO_RESP4 0x0000000CU
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
((RESP) == SDIO_RESP2) || \
@@ -282,18 +472,18 @@
* @}
*/
-/** @defgroup SDMMC_LL_Data_Length Data Lenght
+/** @defgroup SDIO_LL_Data_Length Data Lenght
* @{
*/
-#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
/**
* @}
*/
-/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
+/** @defgroup SDIO_LL_Data_Block_Size Data Block Size
* @{
*/
-#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
+#define SDIO_DATABLOCK_SIZE_1B 0x00000000U
#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
#define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)
@@ -328,10 +518,10 @@
* @}
*/
-/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
+/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
* @{
*/
-#define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
+#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U
#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
@@ -340,10 +530,10 @@
* @}
*/
-/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
+/** @defgroup SDIO_LL_Transfer_Type Transfer Type
* @{
*/
-#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
+#define SDIO_TRANSFER_MODE_BLOCK 0x00000000U
#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
@@ -352,10 +542,10 @@
* @}
*/
-/** @defgroup SDMMC_LL_DPSM_State DPSM State
+/** @defgroup SDIO_LL_DPSM_State DPSM State
* @{
*/
-#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
+#define SDIO_DPSM_DISABLE 0x00000000U
#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
@@ -364,10 +554,10 @@
* @}
*/
-/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
+/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
* @{
*/
-#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
+#define SDIO_READ_WAIT_MODE_DATA2 0x00000000U
#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
@@ -376,7 +566,7 @@
* @}
*/
-/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
+/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
* @{
*/
#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
@@ -403,7 +593,6 @@
#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
-
/**
* @}
*/
@@ -435,25 +624,82 @@
#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
-
+#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
+ SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\
+ SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\
+ SDIO_FLAG_DBCKEND))
/**
* @}
*/
/**
* @}
- */
+ */
/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
+/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
* @{
*/
-
-/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
- * @brief SDMMC_LL registers bit address in the alias region
+
+/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
* @{
*/
-
+/* ------------ SDIO registers bit address in the alias region -------------- */
+#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
+
+/* --- CLKCR Register ---*/
+/* Alias word address of CLKEN bit */
+#define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
+#define CLKEN_BITNUMBER 0x08U
+#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
+
+/* --- CMD Register ---*/
+/* Alias word address of SDIOSUSPEND bit */
+#define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
+#define SDIOSUSPEND_BITNUMBER 0x0BU
+#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
+
+/* Alias word address of ENCMDCOMPL bit */
+#define ENCMDCOMPL_BITNUMBER 0x0CU
+#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
+
+/* Alias word address of NIEN bit */
+#define NIEN_BITNUMBER 0x0DU
+#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
+
+/* Alias word address of ATACMD bit */
+#define ATACMD_BITNUMBER 0x0EU
+#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
+
+/* --- DCTRL Register ---*/
+/* Alias word address of DMAEN bit */
+#define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
+#define DMAEN_BITNUMBER 0x03U
+#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
+
+/* Alias word address of RWSTART bit */
+#define RWSTART_BITNUMBER 0x08U
+#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
+
+/* Alias word address of RWSTOP bit */
+#define RWSTOP_BITNUMBER 0x09U
+#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
+
+/* Alias word address of RWMOD bit */
+#define RWMOD_BITNUMBER 0x0AU
+#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
+
+/* Alias word address of SDIOEN bit */
+#define SDIOEN_BITNUMBER 0x0BU
+#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_LL_Register Bits And Addresses Definitions
+ * @brief SDIO_LL registers bit address in the alias region
+ * @{
+ */
/* ---------------------- SDIO registers bit mask --------------------------- */
/* --- CLKCR Register ---*/
/* CLKCR register clear mask */
@@ -484,38 +730,38 @@
/**
* @}
*/
-
-/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+
+/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
/**
* @brief Enable the SDIO device.
* @param __INSTANCE__: SDIO Instance
* @retval None
*/
-#define __SDIO_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDIO_CLKCR_CLKEN)
+#define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
/**
* @brief Disable the SDIO device.
* @param __INSTANCE__: SDIO Instance
* @retval None
*/
-#define __SDIO_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDIO_CLKCR_CLKEN)
+#define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
/**
* @brief Enable the SDIO DMA transfer.
- * @param None
+ * @param __INSTANCE__: SDIO Instance
* @retval None
*/
-#define __SDIO_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_DMAEN)
+#define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
/**
* @brief Disable the SDIO DMA transfer.
- * @param None
+ * @param __INSTANCE__: SDIO Instance
* @retval None
*/
-#define __SDIO_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_DMAEN)
+#define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
/**
* @brief Enable the SDIO device interrupt.
@@ -531,8 +777,6 @@
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -545,8 +789,7 @@
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval None
*/
#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
@@ -565,8 +808,6 @@
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -579,8 +820,7 @@
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
* @retval None
*/
#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
@@ -599,7 +839,6 @@
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_CMDACT: Command transfer in progress
* @arg SDIO_FLAG_TXACT: Data transmit in progress
@@ -613,10 +852,9 @@
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
* @retval The new state of SDIO_FLAG (SET or RESET).
*/
-#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
+#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
/**
@@ -633,13 +871,11 @@
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
* @retval None
*/
-#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
+#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
/**
* @brief Checks whether the specified SDIO interrupt has occurred or not.
@@ -655,8 +891,6 @@
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
@@ -670,10 +904,9 @@
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
* @retval The new state of SDIO_IT (SET or RESET).
*/
-#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
+#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clears the SDIO's interrupt pending bits.
@@ -689,120 +922,110 @@
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
- * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
- * bus mode interrupt
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
* @retval None
*/
-#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
+#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
/**
* @brief Enable Start the SD I/O Read Wait operation.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
-#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_RWSTART)
+#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
/**
* @brief Disable Start the SD I/O Read Wait operations.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
-#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_RWSTART)
+#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
/**
* @brief Enable Start the SD I/O Read Wait operation.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
-#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_RWSTOP)
+#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
/**
* @brief Disable Stop the SD I/O Read Wait operations.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
-#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_RWSTOP)
+#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
/**
* @brief Enable the SD I/O Mode Operation.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
-#define __SDIO_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_SDIOEN)
+#define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
/**
* @brief Disable the SD I/O Mode Operation.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
-#define __SDIO_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_SDIOEN)
+#define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
/**
* @brief Enable the SD I/O Suspend command sending.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
-#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_SDIOSUSPEND)
+#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
/**
* @brief Disable the SD I/O Suspend command sending.
* @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
-#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_SDIOSUSPEND)
-
+#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
/**
* @brief Enable the command completion signal.
- * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
-#define __SDIO_CEATA_CMD_COMPLETION_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_ENCMDCOMPL)
+#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
/**
* @brief Disable the command completion signal.
- * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
-#define __SDIO_CEATA_CMD_COMPLETION_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_ENCMDCOMPL)
+#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
/**
* @brief Enable the CE-ATA interrupt.
- * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
-#define __SDIO_CEATA_ENABLE_IT(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_NIEN)
+#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
/**
* @brief Disable the CE-ATA interrupt.
- * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
-#define __SDIO_CEATA_DISABLE_IT(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_NIEN)
+#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
/**
* @brief Enable send CE-ATA command (CMD61).
- * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
-#define __SDIO_CEATA_SENDCMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_CEATACMD)
+#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
/**
* @brief Disable send CE-ATA command (CMD61).
- * @param __INSTANCE__ : Pointer to SDIO register base
* @retval None
*/
-#define __SDIO_CEATA_SENDCMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_CEATACMD)
+#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
/**
* @}
*/
-
+
/**
* @}
*/
-
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SDMMC_LL_Exported_Functions
* @{
@@ -842,12 +1065,40 @@
uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
/* Data path state machine (DPSM) management functions */
-HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
+HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
-/* SDIO Cards mode management functions */
-HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
+/* SDMMC Cards mode management functions */
+HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
+
+/* SDMMC Commands management functions */
+uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
+uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
+uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
+uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
+uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
+uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
+uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType);
+uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
+uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
+uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
+uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
+
+uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
+uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
+uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
/**
* @}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_spi.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_spi.h
new file mode 100644
index 0000000..c8c6061
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_spi.h
@@ -0,0 +1,1922 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_spi.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of SPI LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_SPI_H
+#define __STM32F1xx_LL_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3)
+
+/** @defgroup SPI_LL SPI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief SPI Init structures definition
+ */
+typedef struct
+{
+ uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
+ This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
+
+ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
+ This parameter can be a value of @ref SPI_LL_EC_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
+
+ uint32_t DataWidth; /*!< Specifies the SPI data width.
+ This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
+
+ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
+ This parameter can be a value of @ref SPI_LL_EC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
+
+ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
+ This parameter can be a value of @ref SPI_LL_EC_PHASE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
+
+ uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
+ This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
+
+ uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
+ This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
+ @note The communication clock is derived from the master clock. The slave clock does not need to be set.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
+
+ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
+ This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
+
+ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
+ This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
+
+ This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+
+ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
+
+} LL_SPI_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
+ * @{
+ */
+
+/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_SPI_ReadReg function
+ * @{
+ */
+#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
+#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
+#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
+#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
+#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
+#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
+#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
+ * @{
+ */
+#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
+#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
+#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_MODE Operation Mode
+ * @{
+ */
+#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
+#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
+/**
+ * @}
+ */
+
+
+/** @defgroup SPI_LL_EC_PHASE Clock Phase
+ * @{
+ */
+#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
+#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
+#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
+ * @{
+ */
+#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
+#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
+ * @{
+ */
+#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
+#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
+ * @{
+ */
+#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
+#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
+#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
+#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
+ * @{
+ */
+#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
+#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
+#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
+#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
+ * @{
+ */
+#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
+ * @{
+ */
+
+/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in SPI register
+ * @param __INSTANCE__ SPI Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
+ * @{
+ */
+
+/** @defgroup SPI_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Enable SPI peripheral
+ * @rmtoll CR1 SPE LL_SPI_Enable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Disable SPI peripheral
+ * @note When disabling the SPI, follow the procedure described in the Reference Manual.
+ * @rmtoll CR1 SPE LL_SPI_Disable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+}
+
+/**
+ * @brief Check if SPI peripheral is enabled
+ * @rmtoll CR1 SPE LL_SPI_IsEnabled
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
+}
+
+/**
+ * @brief Set SPI operation mode to Master or Slave
+ * @note This bit should not be changed when communication is ongoing.
+ * @rmtoll CR1 MSTR LL_SPI_SetMode\n
+ * CR1 SSI LL_SPI_SetMode
+ * @param SPIx SPI Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
+}
+
+/**
+ * @brief Get SPI operation mode (Master or Slave)
+ * @rmtoll CR1 MSTR LL_SPI_GetMode\n
+ * CR1 SSI LL_SPI_GetMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_MODE_MASTER
+ * @arg @ref LL_SPI_MODE_SLAVE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
+}
+
+
+/**
+ * @brief Set clock phase
+ * @note This bit should not be changed when communication is ongoing.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
+ * @param SPIx SPI Instance
+ * @param ClockPhase This parameter can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
+}
+
+/**
+ * @brief Get clock phase
+ * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_PHASE_1EDGE
+ * @arg @ref LL_SPI_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
+}
+
+/**
+ * @brief Set clock polarity
+ * @note This bit should not be changed when communication is ongoing.
+ * This bit is not used in SPI TI mode.
+ * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
+ * @param SPIx SPI Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
+}
+
+/**
+ * @brief Get clock polarity
+ * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_POLARITY_LOW
+ * @arg @ref LL_SPI_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
+}
+
+/**
+ * @brief Set baud rate prescaler
+ * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
+ * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @param BaudRate This parameter can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
+}
+
+/**
+ * @brief Get baud rate prescaler
+ * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
+ * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
+}
+
+/**
+ * @brief Set transfer bit order
+ * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
+ * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @param BitOrder This parameter can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
+}
+
+/**
+ * @brief Get transfer bit order
+ * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_LSB_FIRST
+ * @arg @ref LL_SPI_MSB_FIRST
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
+}
+
+/**
+ * @brief Set transfer direction mode
+ * @note For Half-Duplex mode, Rx Direction is set by default.
+ * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
+ * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
+ * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
+ * CR1 BIDIOE LL_SPI_SetTransferDirection
+ * @param SPIx SPI Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
+}
+
+/**
+ * @brief Get transfer direction mode
+ * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
+ * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
+ * CR1 BIDIOE LL_SPI_GetTransferDirection
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_FULL_DUPLEX
+ * @arg @ref LL_SPI_SIMPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_RX
+ * @arg @ref LL_SPI_HALF_DUPLEX_TX
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
+}
+
+/**
+ * @brief Set frame data width
+ * @rmtoll CR1 DFF LL_SPI_SetDataWidth
+ * @param SPIx SPI Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
+}
+
+/**
+ * @brief Get frame data width
+ * @rmtoll CR1 DFF LL_SPI_GetDataWidth
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_DATAWIDTH_8BIT
+ * @arg @ref LL_SPI_DATAWIDTH_16BIT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_CRC_Management CRC Management
+ * @{
+ */
+
+/**
+ * @brief Enable CRC
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+ * @brief Disable CRC
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
+}
+
+/**
+ * @brief Check if CRC is enabled
+ * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
+ * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
+}
+
+/**
+ * @brief Set CRCNext to transfer CRC on the line
+ * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
+ * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
+}
+
+/**
+ * @brief Set polynomial for CRC calculation
+ * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
+{
+ WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
+}
+
+/**
+ * @brief Get polynomial for CRC calculation
+ * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->CRCPR));
+}
+
+/**
+ * @brief Get Rx CRC
+ * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->RXCRCR));
+}
+
+/**
+ * @brief Get Tx CRC
+ * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
+ * @param SPIx SPI Instance
+ * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_REG(SPIx->TXCRCR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
+ * @{
+ */
+
+/**
+ * @brief Set NSS mode
+ * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
+ * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
+ * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
+ * @param SPIx SPI Instance
+ * @param NSS This parameter can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
+{
+ MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
+ MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
+}
+
+/**
+ * @brief Get NSS mode
+ * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
+ * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_SPI_NSS_SOFT
+ * @arg @ref LL_SPI_NSS_HARD_INPUT
+ * @arg @ref LL_SPI_NSS_HARD_OUTPUT
+ */
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+{
+ register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
+ register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
+ return (Ssm | Ssoe);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Check if Rx buffer is not empty
+ * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
+}
+
+/**
+ * @brief Check if Tx buffer is empty
+ * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
+}
+
+/**
+ * @brief Get CRC error flag
+ * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
+}
+
+/**
+ * @brief Get mode fault error flag
+ * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
+}
+
+/**
+ * @brief Get overrun error flag
+ * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
+}
+
+/**
+ * @brief Get busy flag
+ * @note The BSY flag is cleared under any one of the following conditions:
+ * -When the SPI is correctly disabled
+ * -When a fault is detected in Master mode (MODF bit set to 1)
+ * -In Master mode, when it finishes a data transmission and no new data is ready to be
+ * sent
+ * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
+ * each data transfer.
+ * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
+}
+
+
+/**
+ * @brief Clear CRC error flag
+ * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
+}
+
+/**
+ * @brief Clear mode fault error flag
+ * @note Clearing this flag is done by a read access to the SPIx_SR
+ * register followed by a write access to the SPIx_CR1 register
+ * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void) tmpreg;
+ tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear overrun error flag
+ * @note Clearing this flag is done by a read access to the SPIx_DR
+ * register followed by a read access to the SPIx_SR register
+ * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->DR;
+ (void) tmpreg;
+ tmpreg = SPIx->SR;
+ (void) tmpreg;
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable error interrupt
+ * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+ * @brief Enable Rx buffer not empty interrupt
+ * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+ * @brief Enable Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+ * @brief Disable error interrupt
+ * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
+ * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
+}
+
+/**
+ * @brief Disable Rx buffer not empty interrupt
+ * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
+}
+
+/**
+ * @brief Disable Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
+}
+
+/**
+ * @brief Check if error interrupt is enabled
+ * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
+}
+
+/**
+ * @brief Check if Rx buffer not empty interrupt is enabled
+ * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
+}
+
+/**
+ * @brief Check if Tx buffer empty interrupt
+ * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DMA_Management DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
+}
+
+/**
+ * @brief Enable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+ * @brief Disable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
+ * @param SPIx SPI Instance
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
+{
+ return (uint32_t) & (SPIx->DR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EF_DATA_Management DATA Management
+ * @{
+ */
+
+/**
+ * @brief Read 8-Bits in the data register
+ * @rmtoll DR DR LL_SPI_ReceiveData8
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
+{
+ return (uint8_t)(READ_REG(SPIx->DR));
+}
+
+/**
+ * @brief Read 16-Bits in the data register
+ * @rmtoll DR DR LL_SPI_ReceiveData16
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
+{
+ return (uint16_t)(READ_REG(SPIx->DR));
+}
+
+/**
+ * @brief Write 8-Bits in the data register
+ * @rmtoll DR DR LL_SPI_TransmitData8
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
+{
+ SPIx->DR = TxData;
+}
+
+/**
+ * @brief Write 16-Bits in the data register
+ * @rmtoll DR DR LL_SPI_TransmitData16
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+ SPIx->DR = TxData;
+}
+
+/**
+ * @}
+ */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#if defined(SPI_I2S_SUPPORT)
+/** @defgroup I2S_LL I2S
+ * @{
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief I2S Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t Mode; /*!< Specifies the I2S operating mode.
+ This parameter can be a value of @ref I2S_LL_EC_MODE
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
+
+ uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_STANDARD
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
+
+
+ uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
+
+
+ uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
+ This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
+
+ This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
+
+
+ uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
+ This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
+
+ Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
+ and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
+
+
+ uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
+ This parameter can be a value of @ref I2S_LL_EC_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
+
+} LL_I2S_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
+ * @{
+ */
+
+/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_I2S_ReadReg function
+ * @{
+ */
+#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
+#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
+#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
+#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
+#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
+#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
+/**
+ * @}
+ */
+
+/** @defgroup SPI_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
+ * @{
+ */
+#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
+#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
+#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
+ * @{
+ */
+#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
+#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
+#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
+#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
+#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_STANDARD I2s Standard
+ * @{
+ */
+#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
+#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
+#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
+#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
+#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_MODE Operation Mode
+ * @{
+ */
+#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
+#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
+#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
+#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
+ * @{
+ */
+#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
+#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
+ * @{
+ */
+#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
+#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
+ * @{
+ */
+
+#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
+#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
+#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
+#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
+#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
+#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
+#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
+#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
+#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
+#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
+ * @{
+ */
+
+/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in I2S register
+ * @param __INSTANCE__ I2S Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in I2S register
+ * @param __INSTANCE__ I2S Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
+ * @{
+ */
+
+/** @defgroup I2S_LL_EF_Configuration Configuration
+ * @{
+ */
+
+/**
+ * @brief Select I2S mode and Enable I2S peripheral
+ * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
+ * I2SCFGR I2SE LL_I2S_Enable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+ * @brief Disable I2S peripheral
+ * @rmtoll I2SCFGR I2SE LL_I2S_Disable
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
+}
+
+/**
+ * @brief Check if I2S peripheral is enabled
+ * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
+}
+
+/**
+ * @brief Set I2S data frame length
+ * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
+ * I2SCFGR CHLEN LL_I2S_SetDataFormat
+ * @param SPIx SPI Instance
+ * @param DataFormat This parameter can be one of the following values:
+ * @arg @ref LL_I2S_DATAFORMAT_16B
+ * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+ * @arg @ref LL_I2S_DATAFORMAT_24B
+ * @arg @ref LL_I2S_DATAFORMAT_32B
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
+}
+
+/**
+ * @brief Get I2S data frame length
+ * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
+ * I2SCFGR CHLEN LL_I2S_GetDataFormat
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_DATAFORMAT_16B
+ * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
+ * @arg @ref LL_I2S_DATAFORMAT_24B
+ * @arg @ref LL_I2S_DATAFORMAT_32B
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
+}
+
+/**
+ * @brief Set I2S clock polarity
+ * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
+ * @param SPIx SPI Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_POLARITY_LOW
+ * @arg @ref LL_I2S_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
+{
+ SET_BIT(SPIx->I2SCFGR, ClockPolarity);
+}
+
+/**
+ * @brief Get I2S clock polarity
+ * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_POLARITY_LOW
+ * @arg @ref LL_I2S_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
+}
+
+/**
+ * @brief Set I2S standard protocol
+ * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
+ * I2SCFGR PCMSYNC LL_I2S_SetStandard
+ * @param SPIx SPI Instance
+ * @param Standard This parameter can be one of the following values:
+ * @arg @ref LL_I2S_STANDARD_PHILIPS
+ * @arg @ref LL_I2S_STANDARD_MSB
+ * @arg @ref LL_I2S_STANDARD_LSB
+ * @arg @ref LL_I2S_STANDARD_PCM_SHORT
+ * @arg @ref LL_I2S_STANDARD_PCM_LONG
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
+}
+
+/**
+ * @brief Get I2S standard protocol
+ * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
+ * I2SCFGR PCMSYNC LL_I2S_GetStandard
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_STANDARD_PHILIPS
+ * @arg @ref LL_I2S_STANDARD_MSB
+ * @arg @ref LL_I2S_STANDARD_LSB
+ * @arg @ref LL_I2S_STANDARD_PCM_SHORT
+ * @arg @ref LL_I2S_STANDARD_PCM_LONG
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
+}
+
+/**
+ * @brief Set I2S transfer mode
+ * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
+ * @param SPIx SPI Instance
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_I2S_MODE_SLAVE_TX
+ * @arg @ref LL_I2S_MODE_SLAVE_RX
+ * @arg @ref LL_I2S_MODE_MASTER_TX
+ * @arg @ref LL_I2S_MODE_MASTER_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
+{
+ MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
+}
+
+/**
+ * @brief Get I2S transfer mode
+ * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_MODE_SLAVE_TX
+ * @arg @ref LL_I2S_MODE_SLAVE_RX
+ * @arg @ref LL_I2S_MODE_MASTER_TX
+ * @arg @ref LL_I2S_MODE_MASTER_RX
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
+}
+
+/**
+ * @brief Set I2S linear prescaler
+ * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
+ * @param SPIx SPI Instance
+ * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
+{
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
+}
+
+/**
+ * @brief Get I2S linear prescaler
+ * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
+ * @param SPIx SPI Instance
+ * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
+}
+
+/**
+ * @brief Set I2S parity prescaler
+ * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
+ * @param SPIx SPI Instance
+ * @param PrescalerParity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
+{
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
+}
+
+/**
+ * @brief Get I2S parity prescaler
+ * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
+ * @param SPIx SPI Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
+{
+ return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
+}
+
+/**
+ * @brief Enable the master clock ouput (Pin MCK)
+ * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
+{
+ SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+ * @brief Disable the master clock ouput (Pin MCK)
+ * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
+{
+ CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
+}
+
+/**
+ * @brief Check if the master clock ouput (Pin MCK) is enabled
+ * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_FLAG FLAG Management
+ * @{
+ */
+
+/**
+ * @brief Check if Rx buffer is not empty
+ * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_RXNE(SPIx);
+}
+
+/**
+ * @brief Check if Tx buffer is empty
+ * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_TXE(SPIx);
+}
+
+/**
+ * @brief Get busy flag
+ * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_BSY(SPIx);
+}
+
+/**
+ * @brief Get overrun error flag
+ * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsActiveFlag_OVR(SPIx);
+}
+
+/**
+ * @brief Get underrun error flag
+ * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
+}
+
+/**
+ * @brief Get channel side flag.
+ * @note 0: Channel Left has to be transmitted or has been received\n
+ * 1: Channel Right has to be transmitted or has been received\n
+ * It has no significance in PCM mode.
+ * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
+{
+ return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
+}
+
+/**
+ * @brief Clear overrun error flag
+ * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_ClearFlag_OVR(SPIx);
+}
+
+/**
+ * @brief Clear underrun error flag
+ * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = SPIx->SR;
+ (void)tmpreg;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_IT Interrupt Management
+ * @{
+ */
+
+/**
+ * @brief Enable error IT
+ * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+ * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_ERR(SPIx);
+}
+
+/**
+ * @brief Enable Rx buffer not empty IT
+ * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Enable Tx buffer empty IT
+ * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableIT_TXE(SPIx);
+}
+
+/**
+ * @brief Disable error IT
+ * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
+ * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_ERR(SPIx);
+}
+
+/**
+ * @brief Disable Rx buffer not empty IT
+ * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Disable Tx buffer empty IT
+ * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableIT_TXE(SPIx);
+}
+
+/**
+ * @brief Check if ERR IT is enabled
+ * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_ERR(SPIx);
+}
+
+/**
+ * @brief Check if RXNE IT is enabled
+ * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_RXNE(SPIx);
+}
+
+/**
+ * @brief Check if TXE IT is enabled
+ * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledIT_TXE(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_DMA DMA Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Disable DMA Rx
+ * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Check if DMA Rx is enabled
+ * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledDMAReq_RX(SPIx);
+}
+
+/**
+ * @brief Enable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_EnableDMAReq_TX(SPIx);
+}
+
+/**
+ * @brief Disable DMA Tx
+ * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ LL_SPI_DisableDMAReq_TX(SPIx);
+}
+
+/**
+ * @brief Check if DMA Tx is enabled
+ * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
+ * @param SPIx SPI Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_IsEnabledDMAReq_TX(SPIx);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2S_LL_EF_DATA DATA Management
+ * @{
+ */
+
+/**
+ * @brief Read 16-Bits in data register
+ * @rmtoll DR DR LL_I2S_ReceiveData16
+ * @param SPIx SPI Instance
+ * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_ReceiveData16(SPIx);
+}
+
+/**
+ * @brief Write 16-Bits in data register
+ * @rmtoll DR DR LL_I2S_TransmitData16
+ * @param SPIx SPI Instance
+ * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
+{
+ LL_SPI_TransmitData16(SPIx, TxData);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_system.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_system.h
new file mode 100644
index 0000000..7f204c2
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_system.h
@@ -0,0 +1,592 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_system.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of SYSTEM LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL SYSTEM driver contains a set of generic APIs that can be
+ used by user:
+ (+) Some of the FLASH features need to be handled in the SYSTEM file.
+ (+) Access to DBGCMU registers
+ (+) Access to SYSCFG registers
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_SYSTEM_H
+#define __STM32F1xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (FLASH) || defined (DBGMCU)
+
+/** @defgroup SYSTEM_LL SYSTEM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+ * @{
+ */
+
+
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+ * @{
+ */
+#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+ * @{
+ */
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
+#if defined(DBGMCU_CR_DBG_TIM5_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM5_STOP */
+#if defined(DBGMCU_CR_DBG_TIM6_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM6_STOP */
+#if defined(DBGMCU_CR_DBG_TIM7_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM7_STOP */
+#if defined(DBGMCU_CR_DBG_TIM12_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM12_STOP */
+#if defined(DBGMCU_CR_DBG_TIM13_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM13_STOP */
+#if defined(DBGMCU_CR_DBG_TIM14_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM14_STOP */
+#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_CR_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_STOP /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_STOP /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#if defined(DBGMCU_CR_DBG_CAN1_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
+#endif /* DBGMCU_CR_DBG_CAN1_STOP */
+#if defined(DBGMCU_CR_DBG_CAN2_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
+#endif /* DBGMCU_CR_DBG_CAN2_STOP */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+ * @{
+ */
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
+#if defined(DBGMCU_CR_DBG_TIM8_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_CAN1_STOP */
+#if defined(DBGMCU_CR_DBG_TIM9_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM9_STOP */
+#if defined(DBGMCU_CR_DBG_TIM10_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM10_STOP */
+#if defined(DBGMCU_CR_DBG_TIM11_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM11_STOP */
+#if defined(DBGMCU_CR_DBG_TIM15_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM15_STOP */
+#if defined(DBGMCU_CR_DBG_TIM16_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM16_STOP */
+#if defined(DBGMCU_CR_DBG_TIM17_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
+#endif /* DBGMCU_CR_DBG_TIM17_STOP */
+/**
+ * @}
+ */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+ * @{
+ */
+#if defined(FLASH_ACR_LATENCY)
+#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
+#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
+#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
+#else
+#endif /* FLASH_ACR_LATENCY */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+ * @{
+ */
+
+
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+ * @{
+ */
+
+/**
+ * @brief Return the device identifier
+ * @note For Low Density devices, the device ID is 0x412
+ * @note For Medium Density devices, the device ID is 0x410
+ * @note For High Density devices, the device ID is 0x414
+ * @note For XL Density devices, the device ID is 0x430
+ * @note For Connectivity Line devices, the device ID is 0x418
+ * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+ * @brief Return the device revision identifier
+ * @note This field indicates the revision of the device.
+ For example, it is read as revA -> 0x1000,for Low Density devices
+ For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
+ For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
+ For example, it is read as revA or 1 -> 0x1003,for XL Density devices
+ For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices
+ * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
+ * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
+}
+
+/**
+ * @brief Enable the Debug Module during SLEEP mode
+ * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Disable the Debug Module during SLEEP mode
+ * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+ * @brief Enable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Disable the Debug Module during STOP mode
+ * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+ * @brief Enable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Disable the Debug Module during STANDBY mode
+ * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+ * @brief Set Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
+ * @param PinAssignment This parameter can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
+{
+ MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
+}
+
+/**
+ * @brief Get Trace pin assignment control
+ * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
+ * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_DBGMCU_TRACE_NONE
+ * @arg @ref LL_DBGMCU_TRACE_ASYNCH
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+ * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
+{
+ return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
+}
+
+/**
+ * @brief Freeze APB1 peripherals (group1 peripherals)
+ * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->CR, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB1 peripherals (group1 peripherals)
+ * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+ * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
+ * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->CR, Periphs);
+}
+
+/**
+ * @brief Freeze APB2 peripherals
+ * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+ SET_BIT(DBGMCU->CR, Periphs);
+}
+
+/**
+ * @brief Unfreeze APB2 peripherals
+ * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+ * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
+ * @param Periphs This parameter can be a combination of the following values:
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
+ * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
+ *
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+ CLEAR_BIT(DBGMCU->CR, Periphs);
+}
+/**
+ * @}
+ */
+
+#if defined(FLASH_ACR_LATENCY)
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+ * @{
+ */
+
+/**
+ * @brief Set FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
+ * @param Latency This parameter can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+ * @brief Get FLASH Latency
+ * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @arg @ref LL_FLASH_LATENCY_2
+ */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+ return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+ * @brief Enable Prefetch
+ * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
+}
+
+/**
+ * @brief Disable Prefetch
+ * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
+}
+
+/**
+ * @brief Check if Prefetch buffer is enabled
+ * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
+{
+ return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
+}
+
+#endif /* FLASH_ACR_LATENCY */
+/**
+ * @brief Enable Flash Half Cycle Access
+ * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
+{
+ SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
+}
+
+/**
+ * @brief Disable Flash Half Cycle Access
+ * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
+{
+ CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
+}
+
+/**
+ * @brief Check if Flash Half Cycle Access is enabled or not
+ * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
+{
+ return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (FLASH) || defined (DBGMCU) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_SYSTEM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_tim.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_tim.h
new file mode 100644
index 0000000..2f93fbd
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_tim.h
@@ -0,0 +1,3837 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_tim.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of TIM LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_TIM_H
+#define __STM32F1xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
+
+/** @defgroup TIM_LL TIM
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+ * @{
+ */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+ 0x00U, /* 0: TIMx_CH1 */
+ 0x00U, /* 1: TIMx_CH1N */
+ 0x00U, /* 2: TIMx_CH2 */
+ 0x00U, /* 3: TIMx_CH2N */
+ 0x04U, /* 4: TIMx_CH3 */
+ 0x04U, /* 5: TIMx_CH3N */
+ 0x04U /* 6: TIMx_CH4 */
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+ 0U, /* 0: OC1M, OC1FE, OC1PE */
+ 0U, /* 1: - NA */
+ 8U, /* 2: OC2M, OC2FE, OC2PE */
+ 0U, /* 3: - NA */
+ 0U, /* 4: OC3M, OC3FE, OC3PE */
+ 0U, /* 5: - NA */
+ 8U /* 6: OC4M, OC4FE, OC4PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+ 0U, /* 0: CC1S, IC1PSC, IC1F */
+ 0U, /* 1: - NA */
+ 8U, /* 2: CC2S, IC2PSC, IC2F */
+ 0U, /* 3: - NA */
+ 0U, /* 4: CC3S, IC3PSC, IC3F */
+ 0U, /* 5: - NA */
+ 8U /* 6: CC4S, IC4PSC, IC4F */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+ 0U, /* 0: CC1P */
+ 2U, /* 1: CC1NP */
+ 4U, /* 2: CC2P */
+ 6U, /* 3: CC2NP */
+ 8U, /* 4: CC3P */
+ 10U, /* 5: CC3NP */
+ 12U /* 6: CC4P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] =
+{
+ 0U, /* 0: OIS1 */
+ 1U, /* 1: OIS1N */
+ 2U, /* 2: OIS2 */
+ 3U, /* 3: OIS2N */
+ 4U, /* 4: OIS3 */
+ 5U, /* 5: OIS3N */
+ 6U /* 6: OIS4 */
+};
+/**
+ * @}
+ */
+
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+ * @{
+ */
+
+
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7F)
+#define DT_DELAY_2 ((uint8_t)0x3F)
+#define DT_DELAY_3 ((uint8_t)0x1F)
+#define DT_DELAY_4 ((uint8_t)0x1F)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+#define DT_RANGE_1 ((uint8_t)0x00)
+#define DT_RANGE_2 ((uint8_t)0x80)
+#define DT_RANGE_3 ((uint8_t)0xC0)
+#define DT_RANGE_4 ((uint8_t)0xE0)
+
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+ * @{
+ */
+/** @brief Convert channel id into channel index.
+ * @param __CHANNEL__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval none
+ */
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
+
+/** @brief Calculate the deadtime sampling period(in ps).
+ * @param __TIMCLK__ timer input clock frequency (in Hz).
+ * @param __CKD__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @retval none
+ */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
+ (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
+ ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+ ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+/**
+ * @}
+ */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+ * @{
+ */
+
+/**
+ * @brief TIM Time Base configuration structure definition.
+ */
+typedef struct
+{
+ uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
+ This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
+
+ uint32_t CounterMode; /*!< Specifies the counter mode.
+ This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
+
+ uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
+ Auto-Reload Register at the next update event.
+ This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+ Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
+
+ uint32_t ClockDivision; /*!< Specifies the clock division.
+ This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
+
+ uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
+ reaches zero, an update event is generated and counting restarts
+ from the RCR value (N).
+ This means in PWM mode that (N+1) corresponds to:
+ - the number of PWM periods in edge-aligned mode
+ - the number of half PWM period in center-aligned mode
+ This parameter must be a number between 0x00 and 0xFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+ * @brief TIM Output Compare configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t OCMode; /*!< Specifies the output mode.
+ This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
+
+ uint32_t OCState; /*!< Specifies the TIM Output Compare state.
+ This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+ uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
+ This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+ uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+ This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+ This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+ uint32_t OCPolarity; /*!< Specifies the output polarity.
+ This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+
+ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
+ This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+
+
+ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+
+ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+ * @brief TIM Input Capture configuration structure definition.
+ */
+
+typedef struct
+{
+
+ uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t ICActiveInput; /*!< Specifies the input.
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t ICFilter; /*!< Specifies the input capture filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+ * @brief TIM Encoder interface configuration structure definition.
+ */
+typedef struct
+{
+ uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
+ This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+ uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
+ This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+
+ uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+ * @brief TIM Hall sensor interface configuration structure definition.
+ */
+typedef struct
+{
+
+ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
+ This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+
+ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
+ Prescaler must be set to get a maximum counter period longer than the
+ time interval between 2 consecutive changes on the Hall inputs.
+ This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+
+ uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
+ This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+
+ uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
+ A positive pulse (TRGO event) is generated with a programmable delay every time
+ a change occurs on the Hall inputs.
+ This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/**
+ * @brief BDTR (Break and Dead Time) structure definition
+ */
+typedef struct
+{
+ uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
+ This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+
+ @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+
+ uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
+ This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+
+ @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+
+ uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
+ This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+ @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
+ has been written, their content is frozen until the next reset.*/
+
+ uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
+ switching-on of the outputs.
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
+
+ @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
+
+ uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+ uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
+ This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+ This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+
+ uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+ This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+ This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+
+ @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+ * @{
+ */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_TIM_ReadReg function.
+ * @{
+ */
+#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
+#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+ * @{
+ */
+#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+ * @{
+ */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
+ * @{
+ */
+#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+ * @{
+ */
+#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+ * @{
+ */
+#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+ * @{
+ */
+#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+ * @{
+ */
+#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+ * @{
+ */
+#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
+ * @{
+ */
+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+ * @{
+ */
+#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+ * @{
+ */
+#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
+#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
+#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
+#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+ * @{
+ */
+#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+ * @{
+ */
+#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+ * @{
+ */
+#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
+#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
+#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
+#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+ * @{
+ */
+#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+ * @{
+ */
+#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
+#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
+ * @{
+ */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
+ * @{
+ */
+#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
+ * @{
+ */
+#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
+ * @{
+ */
+#define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
+ * @{
+ */
+#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
+ * @{
+ */
+#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TRGO Trigger Output
+ * @{
+ */
+#define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
+#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
+#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
+#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
+ * @{
+ */
+#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
+#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
+#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_TS Trigger Selection
+ * @{
+ */
+#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
+ * @{
+ */
+#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
+ * @{
+ */
+#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
+#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
+#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
+ * @{
+ */
+#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
+ * @{
+ */
+#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
+#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
+/**
+ * @}
+ */
+
+
+
+
+/** @defgroup TIM_LL_EC_OSSI OSSI
+ * @{
+ */
+#define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_OSSR OSSR
+ * @{
+ */
+#define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
+ * @{
+ */
+#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
+ * @{
+ */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
+/**
+ * @}
+ */
+
+
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
+ * @{
+ */
+
+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+/**
+ * @brief Write a value in TIM register.
+ * @param __INSTANCE__ TIM Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in TIM register.
+ * @param __INSTANCE__ TIM Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
+ * @{
+ */
+
+/**
+ * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
+ * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CKD__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @param __DT__ deadtime duration (in ns)
+ * @retval DTG[0:7]
+ */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
+ ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
+ (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+ (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+ (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+ 0U)
+
+/**
+ * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+ * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __CNTCLK__ counter clock frequency (in Hz)
+ * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
+ ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+ * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __FREQ__ output signal frequency (in Hz)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+ (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
+
+/**
+ * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
+ * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @retval Compare value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
+((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+ / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+ * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
+ * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+ * @param __TIMCLK__ timer input clock frequency (in Hz)
+ * @param __PSC__ prescaler
+ * @param __DELAY__ timer output compare active/inactive delay (in us)
+ * @param __PULSE__ pulse duration (in us)
+ * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
+ */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
+ ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+ * @brief HELPER macro retrieving the ratio of the input capture prescaler
+ * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+ * @param __ICPSC__ This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+ */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
+ ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+ * @{
+ */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+ * @{
+ */
+/**
+ * @brief Enable timer counter.
+ * @rmtoll CR1 CEN LL_TIM_EnableCounter
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+ * @brief Disable timer counter.
+ * @rmtoll CR1 CEN LL_TIM_DisableCounter
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+ * @brief Indicates whether the timer counter is enabled.
+ * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
+}
+
+/**
+ * @brief Enable update event generation.
+ * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+ * @brief Disable update event generation.
+ * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+ * @brief Indicates whether update event generation is enabled.
+ * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
+}
+
+/**
+ * @brief Set update event source
+ * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+ * generate an update interrupt or DMA request if enabled:
+ * - Counter overflow/underflow
+ * - Setting the UG bit
+ * - Update generation through the slave mode controller
+ * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+ * overflow/underflow generates an update interrupt or DMA request if enabled.
+ * @rmtoll CR1 URS LL_TIM_SetUpdateSource
+ * @param TIMx Timer instance
+ * @param UpdateSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+ * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+ * @brief Get actual event update source
+ * @rmtoll CR1 URS LL_TIM_GetUpdateSource
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+ * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+ * @brief Set one pulse mode (one shot v.s. repetitive).
+ * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
+ * @param TIMx Timer instance
+ * @param OnePulseMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+ * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+ * @brief Get actual one pulse mode.
+ * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+ * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+ * @brief Set the timer counter counting mode.
+ * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * check whether or not the counter mode selection feature is supported
+ * by a timer instance.
+ * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
+ * CR1 CMS LL_TIM_SetCounterMode
+ * @param TIMx Timer instance
+ * @param CounterMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERMODE_UP
+ * @arg @ref LL_TIM_COUNTERMODE_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
+}
+
+/**
+ * @brief Get actual counter mode.
+ * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+ * check whether or not the counter mode selection feature is supported
+ * by a timer instance.
+ * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
+ * CR1 CMS LL_TIM_GetCounterMode
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERMODE_UP
+ * @arg @ref LL_TIM_COUNTERMODE_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+ * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
+}
+
+/**
+ * @brief Enable auto-reload (ARR) preload.
+ * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+ * @brief Disable auto-reload (ARR) preload.
+ * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+ * @brief Indicates whether auto-reload (ARR) preload is enabled.
+ * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
+}
+
+/**
+ * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+ * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * whether or not the clock division feature is supported by the timer
+ * instance.
+ * @rmtoll CR1 CKD LL_TIM_SetClockDivision
+ * @param TIMx Timer instance
+ * @param ClockDivision This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+ MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+ * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+ * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+ * whether or not the clock division feature is supported by the timer
+ * instance.
+ * @rmtoll CR1 CKD LL_TIM_GetClockDivision
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+ * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+ * @brief Set the counter value.
+ * @rmtoll CNT CNT LL_TIM_SetCounter
+ * @param TIMx Timer instance
+ * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+ WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+ * @brief Get the counter value.
+ * @rmtoll CNT CNT LL_TIM_GetCounter
+ * @param TIMx Timer instance
+ * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+ * @brief Get the current direction of the counter
+ * @rmtoll CR1 DIR LL_TIM_GetDirection
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_COUNTERDIRECTION_UP
+ * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+ * @brief Set the prescaler value.
+ * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+ * @note The prescaler can be changed on the fly as this control register is buffered. The new
+ * prescaler ratio is taken into account at the next update event.
+ * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+ * @rmtoll PSC PSC LL_TIM_SetPrescaler
+ * @param TIMx Timer instance
+ * @param Prescaler between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+ WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+ * @brief Get the prescaler value.
+ * @rmtoll PSC PSC LL_TIM_GetPrescaler
+ * @param TIMx Timer instance
+ * @retval Prescaler value between Min_Data=0 and Max_Data=65535
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+ * @brief Set the auto-reload value.
+ * @note The counter is blocked while the auto-reload value is null.
+ * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+ * @rmtoll ARR ARR LL_TIM_SetAutoReload
+ * @param TIMx Timer instance
+ * @param AutoReload between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+ WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+ * @brief Get the auto-reload value.
+ * @rmtoll ARR ARR LL_TIM_GetAutoReload
+ * @param TIMx Timer instance
+ * @retval Auto-reload value
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+ * @brief Set the repetition counter value.
+ * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a repetition counter.
+ * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
+ * @param TIMx Timer instance
+ * @param RepetitionCounter between Min_Data=0 and Max_Data=255
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+{
+ WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+ * @brief Get the repetition counter value.
+ * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports a repetition counter.
+ * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
+ * @param TIMx Timer instance
+ * @retval Repetition counter value
+ */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+ * @{
+ */
+/**
+ * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+ * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+ * they are updated only when a commutation event (COM) occurs.
+ * @note Only on channels that have a complementary output.
+ * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+ * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+ * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+ * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+ * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance is able to generate a commutation event.
+ * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
+ * @param TIMx Timer instance
+ * @param CCUpdateSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+ * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+ * @brief Set the trigger of the capture/compare DMA request.
+ * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
+ * @param TIMx Timer instance
+ * @param DMAReqTrigger This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CCDMAREQUEST_CC
+ * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+ * @brief Get actual trigger of the capture/compare DMA request.
+ * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
+ * @param TIMx Timer instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_CCDMAREQUEST_CC
+ * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+ * @brief Set the lock level to freeze the
+ * configuration of several capture/compare parameters.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * the lock mechanism is supported by a timer instance.
+ * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
+ * @param TIMx Timer instance
+ * @param LockLevel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_LOCKLEVEL_OFF
+ * @arg @ref LL_TIM_LOCKLEVEL_1
+ * @arg @ref LL_TIM_LOCKLEVEL_2
+ * @arg @ref LL_TIM_LOCKLEVEL_3
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+ * @brief Enable capture/compare channels.
+ * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
+ * CCER CC1NE LL_TIM_CC_EnableChannel\n
+ * CCER CC2E LL_TIM_CC_EnableChannel\n
+ * CCER CC2NE LL_TIM_CC_EnableChannel\n
+ * CCER CC3E LL_TIM_CC_EnableChannel\n
+ * CCER CC3NE LL_TIM_CC_EnableChannel\n
+ * CCER CC4E LL_TIM_CC_EnableChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+ * @brief Disable capture/compare channels.
+ * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
+ * CCER CC1NE LL_TIM_CC_DisableChannel\n
+ * CCER CC2E LL_TIM_CC_DisableChannel\n
+ * CCER CC2NE LL_TIM_CC_DisableChannel\n
+ * CCER CC3E LL_TIM_CC_DisableChannel\n
+ * CCER CC3NE LL_TIM_CC_DisableChannel\n
+ * CCER CC4E LL_TIM_CC_DisableChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+ * @brief Indicate whether channel(s) is(are) enabled.
+ * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
+ * CCER CC4E LL_TIM_CC_IsEnabledChannel
+ * @param TIMx Timer instance
+ * @param Channels This parameter can be a combination of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+ return (READ_BIT(TIMx->CCER, Channels) == (Channels));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+ * @{
+ */
+/**
+ * @brief Configure an output channel.
+ * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
+ * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
+ * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
+ * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
+ * CCER CC1P LL_TIM_OC_ConfigOutput\n
+ * CCER CC2P LL_TIM_OC_ConfigOutput\n
+ * CCER CC3P LL_TIM_OC_ConfigOutput\n
+ * CCER CC4P LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
+ * CR2 OIS4 LL_TIM_OC_ConfigOutput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+ (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+ MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+ (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Define the behavior of the output reference signal OCxREF from which
+ * OCx and OCxN (when relevant) are derived.
+ * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
+ * CCMR1 OC2M LL_TIM_OC_SetMode\n
+ * CCMR2 OC3M LL_TIM_OC_SetMode\n
+ * CCMR2 OC4M LL_TIM_OC_SetMode
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param Mode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCMODE_FROZEN
+ * @arg @ref LL_TIM_OCMODE_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_TOGGLE
+ * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_PWM1
+ * @arg @ref LL_TIM_OCMODE_PWM2
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+ * @brief Get the output compare mode of an output channel.
+ * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
+ * CCMR1 OC2M LL_TIM_OC_GetMode\n
+ * CCMR2 OC3M LL_TIM_OC_GetMode\n
+ * CCMR2 OC4M LL_TIM_OC_GetMode
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCMODE_FROZEN
+ * @arg @ref LL_TIM_OCMODE_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_TOGGLE
+ * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+ * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+ * @arg @ref LL_TIM_OCMODE_PWM1
+ * @arg @ref LL_TIM_OCMODE_PWM2
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+ * @brief Set the polarity of an output channel.
+ * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
+ * CCER CC1NP LL_TIM_OC_SetPolarity\n
+ * CCER CC2P LL_TIM_OC_SetPolarity\n
+ * CCER CC2NP LL_TIM_OC_SetPolarity\n
+ * CCER CC3P LL_TIM_OC_SetPolarity\n
+ * CCER CC3NP LL_TIM_OC_SetPolarity\n
+ * CCER CC4P LL_TIM_OC_SetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH
+ * @arg @ref LL_TIM_OCPOLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Get the polarity of an output channel.
+ * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
+ * CCER CC1NP LL_TIM_OC_GetPolarity\n
+ * CCER CC2P LL_TIM_OC_GetPolarity\n
+ * CCER CC2NP LL_TIM_OC_GetPolarity\n
+ * CCER CC3P LL_TIM_OC_GetPolarity\n
+ * CCER CC3NP LL_TIM_OC_GetPolarity\n
+ * CCER CC4P LL_TIM_OC_GetPolarity
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCPOLARITY_HIGH
+ * @arg @ref LL_TIM_OCPOLARITY_LOW
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Set the IDLE state of an output channel
+ * @note This function is significant only for the timer instances
+ * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
+ * can be used to check whether or not a timer instance provides
+ * a break input.
+ * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS1N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS3 LL_TIM_OC_SetIdleState\n
+ * CR2 OIS3N LL_TIM_OC_SetIdleState\n
+ * CR2 OIS4 LL_TIM_OC_SetIdleState
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param IdleState This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Get the IDLE state of an output channel
+ * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS1N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS2N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS3 LL_TIM_OC_GetIdleState\n
+ * CR2 OIS3N LL_TIM_OC_GetIdleState\n
+ * CR2 OIS4 LL_TIM_OC_GetIdleState
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH1N
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH2N
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH3N
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_OCIDLESTATE_LOW
+ * @arg @ref LL_TIM_OCIDLESTATE_HIGH
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+ * @brief Enable fast mode for the output channel.
+ * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
+ * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
+ * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
+ * CCMR2 OC4FE LL_TIM_OC_EnableFast
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+ * @brief Disable fast mode for the output channel.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
+ * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
+ * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
+ * CCMR2 OC4FE LL_TIM_OC_DisableFast
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+ * @brief Indicates whether fast mode is enabled for the output channel.
+ * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
+ * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+ return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+ * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
+ * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
+ * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
+ * CCMR2 OC4PE LL_TIM_OC_EnablePreload
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
+ * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
+ * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
+ * CCMR2 OC4PE LL_TIM_OC_DisablePreload
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+ * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
+ * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+ return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+ * @brief Enable clearing the output channel on an external event.
+ * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+ * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
+ * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
+ * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
+ * CCMR2 OC4CE LL_TIM_OC_EnableClear
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Disable clearing the output channel on an external event.
+ * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
+ * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
+ * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
+ * CCMR2 OC4CE LL_TIM_OC_DisableClear
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+ * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
+ * @note This function enables clearing the output channel on an external event.
+ * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+ * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+ * or not a timer instance can clear the OCxREF signal on an external event.
+ * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
+ * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+ return (READ_BIT(*pReg, bitfield) == bitfield);
+}
+
+/**
+ * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * dead-time insertion feature is supported by a timer instance.
+ * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+ * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
+ * @param TIMx Timer instance
+ * @param DeadTime between Min_Data=0 and Max_Data=255
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+ * @brief Set compare value for output channel 1 (TIMx_CCR1).
+ * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 1 is supported by a timer instance.
+ * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 2 (TIMx_CCR2).
+ * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 2 is supported by a timer instance.
+ * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 3 (TIMx_CCR3).
+ * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * output channel is supported by a timer instance.
+ * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+ * @brief Set compare value for output channel 4 (TIMx_CCR4).
+ * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 4 is supported by a timer instance.
+ * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
+ * @param TIMx Timer instance
+ * @param CompareValue between Min_Data=0 and Max_Data=65535
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+ WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR1) set for output channel 1.
+ * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 1 is supported by a timer instance.
+ * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR2) set for output channel 2.
+ * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 2 is supported by a timer instance.
+ * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR3) set for output channel 3.
+ * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 3 is supported by a timer instance.
+ * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+ * @brief Get compare value (TIMx_CCR4) set for output channel 4.
+ * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * output channel 4 is supported by a timer instance.
+ * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
+ * @param TIMx Timer instance
+ * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+ * @{
+ */
+/**
+ * @brief Configure input channel.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
+ * CCMR1 IC1PSC LL_TIM_IC_Config\n
+ * CCMR1 IC1F LL_TIM_IC_Config\n
+ * CCMR1 CC2S LL_TIM_IC_Config\n
+ * CCMR1 IC2PSC LL_TIM_IC_Config\n
+ * CCMR1 IC2F LL_TIM_IC_Config\n
+ * CCMR2 CC3S LL_TIM_IC_Config\n
+ * CCMR2 IC3PSC LL_TIM_IC_Config\n
+ * CCMR2 IC3F LL_TIM_IC_Config\n
+ * CCMR2 CC4S LL_TIM_IC_Config\n
+ * CCMR2 IC4PSC LL_TIM_IC_Config\n
+ * CCMR2 IC4F LL_TIM_IC_Config\n
+ * CCER CC1P LL_TIM_IC_Config\n
+ * CCER CC1NP LL_TIM_IC_Config\n
+ * CCER CC2P LL_TIM_IC_Config\n
+ * CCER CC2NP LL_TIM_IC_Config\n
+ * CCER CC3P LL_TIM_IC_Config\n
+ * CCER CC3NP LL_TIM_IC_Config\n
+ * CCER CC4P LL_TIM_IC_Config\n
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param Configuration This parameter must be a combination of all the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+ * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+ * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+ ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
+ MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+ (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Set the active input.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
+ * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
+ * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
+ * CCMR2 CC4S LL_TIM_IC_SetActiveInput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICActiveInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_TRC
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the current active input.
+ * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
+ * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
+ * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
+ * CCMR2 CC4S LL_TIM_IC_GetActiveInput
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+ * @arg @ref LL_TIM_ACTIVEINPUT_TRC
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the prescaler of input channel.
+ * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
+ * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the current prescaler value acting on an input channel.
+ * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
+ * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_ICPSC_DIV1
+ * @arg @ref LL_TIM_ICPSC_DIV2
+ * @arg @ref LL_TIM_ICPSC_DIV4
+ * @arg @ref LL_TIM_ICPSC_DIV8
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the input filter duration.
+ * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
+ * CCMR1 IC2F LL_TIM_IC_SetFilter\n
+ * CCMR2 IC3F LL_TIM_IC_SetFilter\n
+ * CCMR2 IC4F LL_TIM_IC_SetFilter
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+ * @brief Get the input filter duration.
+ * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
+ * CCMR1 IC2F LL_TIM_IC_GetFilter\n
+ * CCMR2 IC3F LL_TIM_IC_GetFilter\n
+ * CCMR2 IC4F LL_TIM_IC_GetFilter
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+ * @brief Set the input channel polarity.
+ * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
+ * CCER CC1NP LL_TIM_IC_SetPolarity\n
+ * CCER CC2P LL_TIM_IC_SetPolarity\n
+ * CCER CC2NP LL_TIM_IC_SetPolarity\n
+ * CCER CC3P LL_TIM_IC_SetPolarity\n
+ * CCER CC3NP LL_TIM_IC_SetPolarity\n
+ * CCER CC4P LL_TIM_IC_SetPolarity\n
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param ICPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_IC_POLARITY_RISING
+ * @arg @ref LL_TIM_IC_POLARITY_FALLING
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+ ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Get the current input channel polarity.
+ * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
+ * CCER CC1NP LL_TIM_IC_GetPolarity\n
+ * CCER CC2P LL_TIM_IC_GetPolarity\n
+ * CCER CC2NP LL_TIM_IC_GetPolarity\n
+ * CCER CC3P LL_TIM_IC_GetPolarity\n
+ * CCER CC3NP LL_TIM_IC_GetPolarity\n
+ * CCER CC4P LL_TIM_IC_GetPolarity\n
+ * @param TIMx Timer instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_TIM_IC_POLARITY_RISING
+ * @arg @ref LL_TIM_IC_POLARITY_FALLING
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+ register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+ SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+ * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
+ * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+ * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
+ * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+ * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+ * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an XOR input.
+ * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
+}
+
+/**
+ * @brief Get captured value for input channel 1.
+ * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 1 is supported by a timer instance.
+ * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+ * @brief Get captured value for input channel 2.
+ * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 2 is supported by a timer instance.
+ * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+ * @brief Get captured value for input channel 3.
+ * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 3 is supported by a timer instance.
+ * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+ * @brief Get captured value for input channel 4.
+ * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+ * input channel 4 is supported by a timer instance.
+ * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
+ * @param TIMx Timer instance
+ * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+ */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
+{
+ return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+ * @{
+ */
+/**
+ * @brief Enable external clock mode 2.
+ * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+ * @brief Disable external clock mode 2.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+ * @brief Indicate whether external clock mode 2 is enabled.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
+}
+
+/**
+ * @brief Set the clock source of the counter clock.
+ * @note when selected clock source is external clock mode 1, the timer input
+ * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+ * function. This timer input must be configured by calling
+ * the @ref LL_TIM_IC_Config() function.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode1.
+ * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports external clock mode2.
+ * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
+ * SMCR ECE LL_TIM_SetClockSource
+ * @param TIMx Timer instance
+ * @param ClockSource This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+ * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+ * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+ * @brief Set the encoder interface mode.
+ * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance supports the encoder mode.
+ * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
+ * @param TIMx Timer instance
+ * @param EncoderMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+ * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+ * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+ * @{
+ */
+/**
+ * @brief Set the trigger output (TRGO) used for timer synchronization .
+ * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+ * whether or not a timer instance can operate as a master timer.
+ * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
+ * @param TIMx Timer instance
+ * @param TimerSynchronization This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TRGO_RESET
+ * @arg @ref LL_TIM_TRGO_ENABLE
+ * @arg @ref LL_TIM_TRGO_UPDATE
+ * @arg @ref LL_TIM_TRGO_CC1IF
+ * @arg @ref LL_TIM_TRGO_OC1REF
+ * @arg @ref LL_TIM_TRGO_OC2REF
+ * @arg @ref LL_TIM_TRGO_OC3REF
+ * @arg @ref LL_TIM_TRGO_OC4REF
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+ MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+ * @brief Set the synchronization mode of a slave timer.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
+ * @param TIMx Timer instance
+ * @param SlaveMode This parameter can be one of the following values:
+ * @arg @ref LL_TIM_SLAVEMODE_DISABLED
+ * @arg @ref LL_TIM_SLAVEMODE_RESET
+ * @arg @ref LL_TIM_SLAVEMODE_GATED
+ * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+ * @brief Set the selects the trigger input to be used to synchronize the counter.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR TS LL_TIM_SetTriggerInput
+ * @param TIMx Timer instance
+ * @param TriggerInput This parameter can be one of the following values:
+ * @arg @ref LL_TIM_TS_ITR0
+ * @arg @ref LL_TIM_TS_ITR1
+ * @arg @ref LL_TIM_TS_ITR2
+ * @arg @ref LL_TIM_TS_ITR3
+ * @arg @ref LL_TIM_TS_TI1F_ED
+ * @arg @ref LL_TIM_TS_TI1FP1
+ * @arg @ref LL_TIM_TS_TI2FP2
+ * @arg @ref LL_TIM_TS_ETRF
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+ * @brief Enable the Master/Slave mode.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+ * @brief Disable the Master/Slave mode.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+ * @brief Indicates whether the Master/Slave mode is enabled.
+ * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance can operate as a slave timer.
+ * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
+}
+
+/**
+ * @brief Configure the external trigger (ETR) input.
+ * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides an external trigger input.
+ * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
+ * SMCR ETPS LL_TIM_ConfigETR\n
+ * SMCR ETF LL_TIM_ConfigETR
+ * @param TIMx Timer instance
+ * @param ETRPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+ * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+ * @param ETRPrescaler This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+ * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+ * @param ETRFilter This parameter can be one of the following values:
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+ * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+ uint32_t ETRFilter)
+{
+ MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+ * @{
+ */
+/**
+ * @brief Enable the break function.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR BKE LL_TIM_EnableBRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+ * @brief Disable the break function.
+ * @rmtoll BDTR BKE LL_TIM_DisableBRK
+ * @param TIMx Timer instance
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+ * @brief Configure the break input.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR BKP LL_TIM_ConfigBRK
+ * @param TIMx Timer instance
+ * @param BreakPolarity This parameter can be one of the following values:
+ * @arg @ref LL_TIM_BREAK_POLARITY_LOW
+ * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
+}
+
+/**
+ * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
+ * BDTR OSSR LL_TIM_SetOffStates
+ * @param TIMx Timer instance
+ * @param OffStateIdle This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OSSI_DISABLE
+ * @arg @ref LL_TIM_OSSI_ENABLE
+ * @param OffStateRun This parameter can be one of the following values:
+ * @arg @ref LL_TIM_OSSR_DISABLE
+ * @arg @ref LL_TIM_OSSR_ENABLE
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
+{
+ MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+}
+
+/**
+ * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+ * @brief Disable automatic output (MOE can be set only by software).
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+ * @brief Indicate whether automatic output is enabled.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
+}
+
+/**
+ * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
+ * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+ * software and is reset in case of break or break2 event
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+ * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+ * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+ * software and is reset in case of break or break2 event.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+ * @brief Indicates whether outputs are enabled.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+ * @{
+ */
+/**
+ * @brief Configures the timer DMA burst feature.
+ * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+ * not a timer instance supports the DMA burst mode.
+ * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
+ * DCR DBA LL_TIM_ConfigDMABurst
+ * @param TIMx Timer instance
+ * @param DMABurstBaseAddress This parameter can be one of the following values:
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+ * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+ * @param DMABurstLength This parameter can be one of the following values:
+ * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+ * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+ * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
+{
+ MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
+}
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+ * @{
+ */
+/**
+ * @brief Clear the update interrupt flag (UIF).
+ * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+ * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+ * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
+ * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+ * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
+ * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+ * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
+ * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+ * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
+ * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+ * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
+}
+
+/**
+ * @brief Clear the commutation interrupt flag (COMIF).
+ * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+ * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
+ * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
+}
+
+/**
+ * @brief Clear the trigger interrupt flag (TIF).
+ * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+ * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+ * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
+}
+
+/**
+ * @brief Clear the break interrupt flag (BIF).
+ * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+ * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+ * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+ * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
+ * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+ * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
+ * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+ * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
+ * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
+}
+
+/**
+ * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+ * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+ WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+ * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
+ * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+ * @{
+ */
+/**
+ * @brief Enable update interrupt (UIE).
+ * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+ * @brief Disable update interrupt (UIE).
+ * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+ * @brief Indicates whether the update interrupt (UIE) is enabled.
+ * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
+}
+
+/**
+ * @brief Enable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Disable capture/compare 1 interrupt (CC1IE).
+ * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+ * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
+}
+
+/**
+ * @brief Enable capture/compare 2 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Disable capture/compare 2 interrupt (CC2IE).
+ * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+ * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
+}
+
+/**
+ * @brief Enable capture/compare 3 interrupt (CC3IE).
+ * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+ * @brief Disable capture/compare 3 interrupt (CC3IE).
+ * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+ * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
+}
+
+/**
+ * @brief Enable capture/compare 4 interrupt (CC4IE).
+ * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+ * @brief Disable capture/compare 4 interrupt (CC4IE).
+ * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+ * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
+}
+
+/**
+ * @brief Enable commutation interrupt (COMIE).
+ * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+ * @brief Disable commutation interrupt (COMIE).
+ * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+ * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
+ * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
+}
+
+/**
+ * @brief Enable trigger interrupt (TIE).
+ * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+ * @brief Disable trigger interrupt (TIE).
+ * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+ * @brief Indicates whether the trigger interrupt (TIE) is enabled.
+ * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
+}
+
+/**
+ * @brief Enable break interrupt (BIE).
+ * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+ * @brief Disable break interrupt (BIE).
+ * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+ * @brief Indicates whether the break interrupt (BIE) is enabled.
+ * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
+ * @{
+ */
+/**
+ * @brief Enable update DMA request (UDE).
+ * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+ * @brief Disable update DMA request (UDE).
+ * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+ * @brief Indicates whether the update DMA request (UDE) is enabled.
+ * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
+}
+
+/**
+ * @brief Enable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Disable capture/compare 1 DMA request (CC1DE).
+ * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+ * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
+}
+
+/**
+ * @brief Enable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Disable capture/compare 2 DMA request (CC2DE).
+ * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+ * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
+}
+
+/**
+ * @brief Enable capture/compare 3 DMA request (CC3DE).
+ * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+ * @brief Disable capture/compare 3 DMA request (CC3DE).
+ * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+ * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
+}
+
+/**
+ * @brief Enable capture/compare 4 DMA request (CC4DE).
+ * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+ * @brief Disable capture/compare 4 DMA request (CC4DE).
+ * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+ * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+ * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
+}
+
+/**
+ * @brief Enable commutation DMA request (COMDE).
+ * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+ * @brief Disable commutation DMA request (COMDE).
+ * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+ * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
+ * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
+}
+
+/**
+ * @brief Enable trigger interrupt (TDE).
+ * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+ * @brief Disable trigger interrupt (TDE).
+ * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+ * @brief Indicates whether the trigger interrupt (TDE) is enabled.
+ * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
+ * @param TIMx Timer instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+ return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+ * @{
+ */
+/**
+ * @brief Generate an update event.
+ * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+ * @brief Generate Capture/Compare 1 event.
+ * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+ * @brief Generate Capture/Compare 2 event.
+ * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+ * @brief Generate Capture/Compare 3 event.
+ * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+ * @brief Generate Capture/Compare 4 event.
+ * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+ * @brief Generate commutation event.
+ * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+ * @brief Generate trigger event.
+ * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+ * @brief Generate break event.
+ * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
+ * @param TIMx Timer instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
+{
+ SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+ * @{
+ */
+
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_TIM_H */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usart.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usart.h
new file mode 100644
index 0000000..0098328
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usart.h
@@ -0,0 +1,2589 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_usart.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of USART LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_USART_H
+#define __STM32F1xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
+
+/** @defgroup USART_LL USART
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+ * @{
+ */
+
+/* Defines used for the bit position in the register and perform offsets*/
+#define USART_POSITION_GTPR_GT USART_GTPR_GT_Pos
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+ * @{
+ */
+
+/**
+ * @brief LL USART Init Structure definition
+ */
+typedef struct
+{
+ uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
+
+ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
+ This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
+
+ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
+ This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
+
+ uint32_t Parity; /*!< Specifies the parity mode.
+ This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
+
+ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
+
+ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
+
+#if defined(USART_CR1_OVER8)
+ uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
+ This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+ This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
+
+#endif /* USART_OverSampling_Feature */
+} LL_USART_InitTypeDef;
+
+/**
+ * @brief LL USART Clock Init Structure definition
+ */
+typedef struct
+{
+ uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled.
+ This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+ USART HW configuration can be modified afterwards using unitary functions
+ @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+ For more details, refer to description of this function. */
+
+ uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
+ This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+ USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
+ For more details, refer to description of this function. */
+
+ uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
+ This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+ USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
+ For more details, refer to description of this function. */
+
+ uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+ This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+ USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
+ For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+ * @{
+ */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+ * @brief Flags defines which can be used with LL_USART_ReadReg function
+ * @{
+ */
+#define LL_USART_SR_PE USART_SR_PE /*!< Parity error flag */
+#define LL_USART_SR_FE USART_SR_FE /*!< Framing error flag */
+#define LL_USART_SR_NE USART_SR_NE /*!< Noise detected flag */
+#define LL_USART_SR_ORE USART_SR_ORE /*!< Overrun error flag */
+#define LL_USART_SR_IDLE USART_SR_IDLE /*!< Idle line detected flag */
+#define LL_USART_SR_RXNE USART_SR_RXNE /*!< Read data register not empty flag */
+#define LL_USART_SR_TC USART_SR_TC /*!< Transmission complete flag */
+#define LL_USART_SR_TXE USART_SR_TXE /*!< Transmit data register empty flag */
+#define LL_USART_SR_LBD USART_SR_LBD /*!< LIN break detection flag */
+#define LL_USART_SR_CTS USART_SR_CTS /*!< CTS flag */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions
+ * @{
+ */
+#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */
+#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */
+#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
+#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+ * @{
+ */
+#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+ * @{
+ */
+#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+ * @{
+ */
+#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+ * @{
+ */
+#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+ * @}
+ */
+
+#if defined(USART_CR1_OVER8)
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+ * @{
+ */
+#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
+/**
+ * @}
+ */
+
+#endif /* USART_OverSampling_Feature */
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+ * @{
+ */
+
+#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
+/**
+ * @}
+ */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+ * @{
+ */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+ * @{
+ */
+#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+ * @{
+ */
+#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+ * @{
+ */
+#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+ * @{
+ */
+#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+ * @{
+ */
+#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+ * @{
+ */
+#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+ * @{
+ */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+ * @{
+ */
+
+/**
+ * @brief Write a value in USART register
+ * @param __INSTANCE__ USART Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in USART register
+ * @param __INSTANCE__ USART Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+ * @{
+ */
+
+/**
+ * @brief Compute USARTDIV value according to Peripheral Clock and
+ * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ * @param __BAUDRATE__ Baud rate value to achieve
+ * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+ */
+#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__)))
+#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
+#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100)
+/* UART BRR = mantissa + overflow + fraction
+ = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
+ ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \
+ (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07))
+
+/**
+ * @brief Compute USARTDIV value according to Peripheral Clock and
+ * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+ * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+ * @param __BAUDRATE__ Baud rate value to achieve
+ * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+ */
+#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))
+#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
+#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100)
+/* USART BRR = mantissa + overflow + fraction
+ = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
+ (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \
+ (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+ * @{
+ */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+ * @{
+ */
+
+/**
+ * @brief USART Enable
+ * @rmtoll CR1 UE LL_USART_Enable
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief USART Disable (all USART prescalers and outputs are disabled)
+ * @note When USART is disabled, USART prescalers and outputs are stopped immediately,
+ * and current operations are discarded. The configuration of the USART is kept, but all the status
+ * flags, in the USARTx_SR are set to their default values.
+ * @rmtoll CR1 UE LL_USART_Disable
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+ * @brief Indicate if USART is enabled
+ * @rmtoll CR1 UE LL_USART_IsEnabled
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
+}
+
+/**
+ * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
+ * @rmtoll CR1 RE LL_USART_EnableDirectionRx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Receiver Disable
+ * @rmtoll CR1 RE LL_USART_DisableDirectionRx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+ * @brief Transmitter Enable
+ * @rmtoll CR1 TE LL_USART_EnableDirectionTx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Transmitter Disable
+ * @rmtoll CR1 TE LL_USART_DisableDirectionTx
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+ * @brief Configure simultaneously enabled/disabled states
+ * of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_USART_SetTransferDirection\n
+ * CR1 TE LL_USART_SetTransferDirection
+ * @param USARTx USART Instance
+ * @param TransferDirection This parameter can be one of the following values:
+ * @arg @ref LL_USART_DIRECTION_NONE
+ * @arg @ref LL_USART_DIRECTION_RX
+ * @arg @ref LL_USART_DIRECTION_TX
+ * @arg @ref LL_USART_DIRECTION_TX_RX
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+ * @brief Return enabled/disabled states of Transmitter and Receiver
+ * @rmtoll CR1 RE LL_USART_GetTransferDirection\n
+ * CR1 TE LL_USART_GetTransferDirection
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DIRECTION_NONE
+ * @arg @ref LL_USART_DIRECTION_RX
+ * @arg @ref LL_USART_DIRECTION_TX
+ * @arg @ref LL_USART_DIRECTION_TX_RX
+ */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+ * @brief Configure Parity (enabled/disabled and parity mode if enabled).
+ * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
+ * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+ * (9th or 8th bit depending on data width) and parity is checked on the received data.
+ * @rmtoll CR1 PS LL_USART_SetParity\n
+ * CR1 PCE LL_USART_SetParity
+ * @param USARTx USART Instance
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+ * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
+ * @rmtoll CR1 PS LL_USART_GetParity\n
+ * CR1 PCE LL_USART_GetParity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ */
+__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+ * @brief Set Receiver Wake Up method from Mute mode.
+ * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod
+ * @param USARTx USART Instance
+ * @param Method This parameter can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_IDLELINE
+ * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+ * @brief Return Receiver Wake Up method from Mute mode
+ * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_WAKEUP_IDLELINE
+ * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+ */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+ * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M LL_USART_SetDataWidth
+ * @param USARTx USART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+ * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
+ * @rmtoll CR1 M LL_USART_GetDataWidth
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+#if defined(USART_CR1_OVER8)
+/**
+ * @brief Set Oversampling to 8-bit or 16-bit mode
+ * @rmtoll CR1 OVER8 LL_USART_SetOverSampling
+ * @param USARTx USART Instance
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+ * @brief Return Oversampling mode
+ * @rmtoll CR1 OVER8 LL_USART_GetOverSampling
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+#endif /* USART_OverSampling_Feature */
+/**
+ * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
+ * @param USARTx USART Instance
+ * @param LastBitClockPulse This parameter can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+ * @brief Retrieve Clock pulse of the last data bit output configuration
+ * (Last bit Clock pulse output to the SCLK pin or not)
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+ * @brief Select the phase of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPHA LL_USART_SetClockPhase
+ * @param USARTx USART Instance
+ * @param ClockPhase This parameter can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+ * @brief Return phase of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPHA LL_USART_GetClockPhase
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+ * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPOL LL_USART_SetClockPolarity
+ * @param USARTx USART Instance
+ * @param ClockPolarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+ * @brief Return polarity of the clock output on the SCLK pin in synchronous mode
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CPOL LL_USART_GetClockPolarity
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+ * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+ * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+ * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+ * @rmtoll CR2 CPHA LL_USART_ConfigClock\n
+ * CR2 CPOL LL_USART_ConfigClock\n
+ * CR2 LBCL LL_USART_ConfigClock
+ * @param USARTx USART Instance
+ * @param Phase This parameter can be one of the following values:
+ * @arg @ref LL_USART_PHASE_1EDGE
+ * @arg @ref LL_USART_PHASE_2EDGE
+ * @param Polarity This parameter can be one of the following values:
+ * @arg @ref LL_USART_POLARITY_LOW
+ * @arg @ref LL_USART_POLARITY_HIGH
+ * @param LBCPOutput This parameter can be one of the following values:
+ * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+ * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+ * @brief Enable Clock output on SCLK pin
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Disable Clock output on SCLK pin
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Indicate if Clock output on SCLK pin is enabled
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
+}
+
+/**
+ * @brief Set the length of the stop bits
+ * @rmtoll CR2 STOP LL_USART_SetStopBitsLength
+ * @param USARTx USART Instance
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Retrieve the length of the stop bits
+ * @rmtoll CR2 STOP LL_USART_GetStopBitsLength
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+ * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Data Width configuration using @ref LL_USART_SetDataWidth() function
+ * - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+ * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+ * @rmtoll CR1 PS LL_USART_ConfigCharacter\n
+ * CR1 PCE LL_USART_ConfigCharacter\n
+ * CR1 M LL_USART_ConfigCharacter\n
+ * CR2 STOP LL_USART_ConfigCharacter
+ * @param USARTx USART Instance
+ * @param DataWidth This parameter can be one of the following values:
+ * @arg @ref LL_USART_DATAWIDTH_8B
+ * @arg @ref LL_USART_DATAWIDTH_9B
+ * @param Parity This parameter can be one of the following values:
+ * @arg @ref LL_USART_PARITY_NONE
+ * @arg @ref LL_USART_PARITY_EVEN
+ * @arg @ref LL_USART_PARITY_ODD
+ * @param StopBits This parameter can be one of the following values:
+ * @arg @ref LL_USART_STOPBITS_0_5
+ * @arg @ref LL_USART_STOPBITS_1
+ * @arg @ref LL_USART_STOPBITS_1_5
+ * @arg @ref LL_USART_STOPBITS_2
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+ uint32_t StopBits)
+{
+ MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+ MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+ * @brief Set Address of the USART node.
+ * @note This is used in multiprocessor communication during Mute mode or Stop mode,
+ * for wake up with address mark detection.
+ * @rmtoll CR2 ADD LL_USART_SetNodeAddress
+ * @param USARTx USART Instance
+ * @param NodeAddress 4 bit Address of the USART node.
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD));
+}
+
+/**
+ * @brief Return 4 bit Address of the USART node as set in ADD field of CR2.
+ * @note only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+ * @rmtoll CR2 ADD LL_USART_GetNodeAddress
+ * @param USARTx USART Instance
+ * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD));
+}
+
+/**
+ * @brief Enable RTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Disable RTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+ * @brief Enable CTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Disable CTS HW Flow Control
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+ * @brief Configure HW Flow Control mode (both CTS and RTS)
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
+ * CR3 CTSE LL_USART_SetHWFlowCtrl
+ * @param USARTx USART Instance
+ * @param HardwareFlowControl This parameter can be one of the following values:
+ * @arg @ref LL_USART_HWCONTROL_NONE
+ * @arg @ref LL_USART_HWCONTROL_RTS
+ * @arg @ref LL_USART_HWCONTROL_CTS
+ * @arg @ref LL_USART_HWCONTROL_RTS_CTS
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+ * @brief Return HW Flow Control configuration (both CTS and RTS)
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
+ * CR3 CTSE LL_USART_GetHWFlowCtrl
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_HWCONTROL_NONE
+ * @arg @ref LL_USART_HWCONTROL_RTS
+ * @arg @ref LL_USART_HWCONTROL_CTS
+ * @arg @ref LL_USART_HWCONTROL_RTS_CTS
+ */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+#if defined(USART_CR3_ONEBIT)
+/**
+ * @brief Enable One bit sampling method
+ * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+ * @brief Disable One bit sampling method
+ * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+ * @brief Indicate if One bit sampling method is enabled
+ * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
+}
+#endif /* USART_OneBitSampling_Feature */
+
+#if defined(USART_CR1_OVER8)
+/**
+ * @brief Configure USART BRR register for achieving expected Baud Rate value.
+ * @note Compute and set USARTDIV value in BRR Register (full BRR content)
+ * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+ * @note Peripheral clock and Baud rate values provided as function parameters should be valid
+ * (Baud rate value != 0)
+ * @rmtoll BRR BRR LL_USART_SetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @param BaudRate Baud Rate
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
+ uint32_t BaudRate)
+{
+ if (OverSampling == LL_USART_OVERSAMPLING_8)
+ {
+ USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
+ }
+ else
+ {
+ USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
+ }
+}
+
+/**
+ * @brief Return current Baud Rate value, according to USARTDIV present in BRR register
+ * (full BRR content), and to used Peripheral Clock and Oversampling mode values
+ * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+ * @rmtoll BRR BRR LL_USART_GetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param OverSampling This parameter can be one of the following values:
+ * @arg @ref LL_USART_OVERSAMPLING_16
+ * @arg @ref LL_USART_OVERSAMPLING_8
+ * @retval Baud Rate
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
+{
+ register uint32_t usartdiv = 0x0U;
+ register uint32_t brrresult = 0x0U;
+
+ usartdiv = USARTx->BRR;
+
+ if (OverSampling == LL_USART_OVERSAMPLING_8)
+ {
+ if ((usartdiv & 0xFFF7U) != 0U)
+ {
+ usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+ brrresult = (PeriphClk * 2U) / usartdiv;
+ }
+ }
+ else
+ {
+ if ((usartdiv & 0xFFFFU) != 0U)
+ {
+ brrresult = PeriphClk / usartdiv;
+ }
+ }
+ return (brrresult);
+}
+#else
+/**
+ * @brief Configure USART BRR register for achieving expected Baud Rate value.
+ * @note Compute and set USARTDIV value in BRR Register (full BRR content)
+ * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+ * @note Peripheral clock and Baud rate values provided as function parameters should be valid
+ * (Baud rate value != 0)
+ * @rmtoll BRR BRR LL_USART_SetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ * @param BaudRate Baud Rate
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t BaudRate)
+{
+ USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
+}
+
+/**
+ * @brief Return current Baud Rate value, according to USARTDIV present in BRR register
+ * (full BRR content), and to used Peripheral Clock and Oversampling mode values
+ * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+ * @rmtoll BRR BRR LL_USART_GetBaudRate
+ * @param USARTx USART Instance
+ * @param PeriphClk Peripheral Clock
+ * @retval Baud Rate
+ */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk)
+{
+ register uint32_t usartdiv = 0x0U;
+ register uint32_t brrresult = 0x0U;
+
+ usartdiv = USARTx->BRR;
+
+ if ((usartdiv & 0xFFFFU) != 0U)
+ {
+ brrresult = PeriphClk / usartdiv;
+ }
+ return (brrresult);
+}
+#endif /* USART_OverSampling_Feature */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+ * @{
+ */
+
+/**
+ * @brief Enable IrDA mode
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_EnableIrda
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Disable IrDA mode
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_DisableIrda
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Indicate if IrDA mode is enabled
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IREN LL_USART_IsEnabledIrda
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
+}
+
+/**
+ * @brief Configure IrDA Power Mode (Normal or Low Power)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
+ * @param USARTx USART Instance
+ * @param PowerMode This parameter can be one of the following values:
+ * @arg @ref LL_USART_IRDA_POWER_NORMAL
+ * @arg @ref LL_USART_IRDA_POWER_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+ MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+ * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_IRDA_POWER_NORMAL
+ * @arg @ref LL_USART_PHASE_2EDGE
+ */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+ * @brief Set Irda prescaler value, used for dividing the USART clock source
+ * to achieve the Irda Low Power frequency (8 bits value)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+ * @brief Return Irda prescaler value, used for dividing the USART clock source
+ * to achieve the Irda Low Power frequency (8 bits value)
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
+ * @param USARTx USART Instance
+ * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+ * @{
+ */
+
+/**
+ * @brief Enable Smartcard NACK transmission
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+ * @brief Disable Smartcard NACK transmission
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+ * @brief Indicate if Smartcard NACK transmission is enabled
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
+}
+
+/**
+ * @brief Enable Smartcard mode
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_EnableSmartcard
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Disable Smartcard mode
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_DisableSmartcard
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Indicate if Smartcard mode is enabled
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
+}
+
+/**
+ * @brief Set Smartcard prescaler value, used for dividing the USART clock
+ * source to provide the SMARTCARD Clock (5 bits value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
+ * @param USARTx USART Instance
+ * @param PrescalerValue Value between Min_Data=0 and Max_Data=31
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+ * @brief Return Smartcard prescaler value, used for dividing the USART clock
+ * source to provide the SMARTCARD Clock (5 bits value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
+ * @param USARTx USART Instance
+ * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+ * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
+ * (GT[7:0] bits : Guard time value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
+ * @param USARTx USART Instance
+ * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+ MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);
+}
+
+/**
+ * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
+ * (GT[7:0] bits : Guard time value)
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
+ * @param USARTx USART Instance
+ * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+ */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+ * @{
+ */
+
+/**
+ * @brief Enable Single Wire Half-Duplex mode
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Disable Single Wire Half-Duplex mode
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Indicate if Single Wire Half-Duplex mode is enabled
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+ * @{
+ */
+
+/**
+ * @brief Set LIN Break Detection Length
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
+ * @param USARTx USART Instance
+ * @param LINBDLength This parameter can be one of the following values:
+ * @arg @ref LL_USART_LINBREAK_DETECT_10B
+ * @arg @ref LL_USART_LINBREAK_DETECT_11B
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+ MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+ * @brief Return LIN Break Detection Length
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
+ * @param USARTx USART Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_USART_LINBREAK_DETECT_10B
+ * @arg @ref LL_USART_LINBREAK_DETECT_11B
+ */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+{
+ return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+ * @brief Enable LIN mode
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_EnableLIN
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Disable LIN mode
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_DisableLIN
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Indicate if LIN mode is enabled
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+ * @{
+ */
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+ * @note In UART mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * @note Other remaining configurations items related to Asynchronous Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n
+ * CR2 CLKEN LL_USART_ConfigAsyncMode\n
+ * CR3 SCEN LL_USART_ConfigAsyncMode\n
+ * CR3 IREN LL_USART_ConfigAsyncMode\n
+ * CR3 HDSEL LL_USART_ConfigAsyncMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+ /* In Asynchronous mode, the following bits must be kept cleared:
+ - LINEN, CLKEN bits in the USART_CR2 register,
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Synchronous Mode
+ * @note In Synchronous mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also sets the USART in Synchronous mode.
+ * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * Synchronous mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+ * @note Other remaining configurations items related to Synchronous Mode
+ * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n
+ * CR2 CLKEN LL_USART_ConfigSyncMode\n
+ * CR3 SCEN LL_USART_ConfigSyncMode\n
+ * CR3 IREN LL_USART_ConfigSyncMode\n
+ * CR3 HDSEL LL_USART_ConfigSyncMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+ /* In Synchronous mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register,
+ - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+ /* set the UART/USART in Synchronous mode */
+ SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in LIN Mode
+ * @note In LIN mode, the following bits must be kept cleared:
+ * - STOP and CLKEN bits in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also set the UART/USART in LIN mode.
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+ * @note Other remaining configurations items related to LIN Mode
+ * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n
+ * CR2 STOP LL_USART_ConfigLINMode\n
+ * CR2 LINEN LL_USART_ConfigLINMode\n
+ * CR3 IREN LL_USART_ConfigLINMode\n
+ * CR3 SCEN LL_USART_ConfigLINMode\n
+ * CR3 HDSEL LL_USART_ConfigLINMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+ /* In LIN mode, the following bits must be kept cleared:
+ - STOP and CLKEN bits in the USART_CR2 register,
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+ /* Set the UART/USART in LIN mode */
+ SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode
+ * @note In Half Duplex mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * This function also sets the UART/USART in Half Duplex mode.
+ * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * Half-Duplex mode is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+ * @note Other remaining configurations items related to Half Duplex Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n
+ * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n
+ * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n
+ * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n
+ * CR3 IREN LL_USART_ConfigHalfDuplexMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+ /* In Half Duplex mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - SCEN and IREN bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+ /* set the UART/USART in Half Duplex mode */
+ SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Smartcard Mode
+ * @note In Smartcard mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also configures Stop bits to 1.5 bits and
+ * sets the USART in Smartcard mode (SCEN bit).
+ * Clock Output is also enabled (CLKEN).
+ * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * Smartcard feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+ * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+ * @note Other remaining configurations items related to Smartcard Mode
+ * (as Baud Rate, Word length, Parity, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n
+ * CR2 STOP LL_USART_ConfigSmartcardMode\n
+ * CR2 CLKEN LL_USART_ConfigSmartcardMode\n
+ * CR3 HDSEL LL_USART_ConfigSmartcardMode\n
+ * CR3 SCEN LL_USART_ConfigSmartcardMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+ /* In Smartcard mode, the following bits must be kept cleared:
+ - LINEN bit in the USART_CR2 register,
+ - IREN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+ /* Configure Stop bits to 1.5 bits */
+ /* Synchronous mode is activated by default */
+ SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+ /* set the UART/USART in Smartcard mode */
+ SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Irda Mode
+ * @note In IRDA mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - STOP and CLKEN bits in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * This function also sets the UART/USART in IRDA mode (IREN bit).
+ * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * IrDA feature is supported by the USARTx instance.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+ * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+ * @note Other remaining configurations items related to Irda Mode
+ * (as Baud Rate, Word length, Power mode, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n
+ * CR2 CLKEN LL_USART_ConfigIrdaMode\n
+ * CR2 STOP LL_USART_ConfigIrdaMode\n
+ * CR3 SCEN LL_USART_ConfigIrdaMode\n
+ * CR3 HDSEL LL_USART_ConfigIrdaMode\n
+ * CR3 IREN LL_USART_ConfigIrdaMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+ /* In IRDA mode, the following bits must be kept cleared:
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+ /* set the UART/USART in IRDA mode */
+ SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+ * @brief Perform basic configuration of USART for enabling use in Multi processor Mode
+ * (several USARTs connected in a network, one of the USARTs can be the master,
+ * its TX output connected to the RX inputs of the other slaves USARTs).
+ * @note In MultiProcessor mode, the following bits must be kept cleared:
+ * - LINEN bit in the USART_CR2 register,
+ * - CLKEN bit in the USART_CR2 register,
+ * - SCEN bit in the USART_CR3 register,
+ * - IREN bit in the USART_CR3 register,
+ * - HDSEL bit in the USART_CR3 register.
+ * @note Call of this function is equivalent to following function call sequence :
+ * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+ * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+ * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+ * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+ * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+ * @note Other remaining configurations items related to Multi processor Mode
+ * (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+ * dedicated functions
+ * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n
+ * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n
+ * CR3 SCEN LL_USART_ConfigMultiProcessMode\n
+ * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n
+ * CR3 IREN LL_USART_ConfigMultiProcessMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+ /* In Multi Processor mode, the following bits must be kept cleared:
+ - LINEN and CLKEN bits in the USART_CR2 register,
+ - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+
+/**
+ * @brief Check if the USART Parity Error Flag is set or not
+ * @rmtoll SR PE LL_USART_IsActiveFlag_PE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE));
+}
+
+/**
+ * @brief Check if the USART Framing Error Flag is set or not
+ * @rmtoll SR FE LL_USART_IsActiveFlag_FE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE));
+}
+
+/**
+ * @brief Check if the USART Noise error detected Flag is set or not
+ * @rmtoll SR NF LL_USART_IsActiveFlag_NE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE));
+}
+
+/**
+ * @brief Check if the USART OverRun Error Flag is set or not
+ * @rmtoll SR ORE LL_USART_IsActiveFlag_ORE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE));
+}
+
+/**
+ * @brief Check if the USART IDLE line detected Flag is set or not
+ * @rmtoll SR IDLE LL_USART_IsActiveFlag_IDLE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE));
+}
+
+/**
+ * @brief Check if the USART Read Data Register Not Empty Flag is set or not
+ * @rmtoll SR RXNE LL_USART_IsActiveFlag_RXNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE));
+}
+
+/**
+ * @brief Check if the USART Transmission Complete Flag is set or not
+ * @rmtoll SR TC LL_USART_IsActiveFlag_TC
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC));
+}
+
+/**
+ * @brief Check if the USART Transmit Data Register Empty Flag is set or not
+ * @rmtoll SR TXE LL_USART_IsActiveFlag_TXE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE));
+}
+
+/**
+ * @brief Check if the USART LIN Break Detection Flag is set or not
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll SR LBD LL_USART_IsActiveFlag_LBD
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD));
+}
+
+/**
+ * @brief Check if the USART CTS Flag is set or not
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS));
+}
+
+/**
+ * @brief Check if the USART Send Break Flag is set or not
+ * @rmtoll CR1 SBK LL_USART_IsActiveFlag_SBK
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK));
+}
+
+/**
+ * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not
+ * @rmtoll CR1 RWU LL_USART_IsActiveFlag_RWU
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU));
+}
+
+/**
+ * @brief Clear Parity Error Flag
+ * @note Clearing this flag is done by a read access to the USARTx_SR
+ * register followed by a read access to the USARTx_DR register.
+ * @note Please also consider that when clearing this flag, other flags as
+ * NE, FE, ORE, IDLE would also be cleared.
+ * @rmtoll SR PE LL_USART_ClearFlag_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = USARTx->SR;
+ (void) tmpreg;
+ tmpreg = USARTx->DR;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear Framing Error Flag
+ * @note Clearing this flag is done by a read access to the USARTx_SR
+ * register followed by a read access to the USARTx_DR register.
+ * @note Please also consider that when clearing this flag, other flags as
+ * PE, NE, ORE, IDLE would also be cleared.
+ * @rmtoll SR FE LL_USART_ClearFlag_FE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = USARTx->SR;
+ (void) tmpreg;
+ tmpreg = USARTx->DR;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear Noise detected Flag
+ * @note Clearing this flag is done by a read access to the USARTx_SR
+ * register followed by a read access to the USARTx_DR register.
+ * @note Please also consider that when clearing this flag, other flags as
+ * PE, FE, ORE, IDLE would also be cleared.
+ * @rmtoll SR NF LL_USART_ClearFlag_NE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = USARTx->SR;
+ (void) tmpreg;
+ tmpreg = USARTx->DR;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear OverRun Error Flag
+ * @note Clearing this flag is done by a read access to the USARTx_SR
+ * register followed by a read access to the USARTx_DR register.
+ * @note Please also consider that when clearing this flag, other flags as
+ * PE, NE, FE, IDLE would also be cleared.
+ * @rmtoll SR ORE LL_USART_ClearFlag_ORE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = USARTx->SR;
+ (void) tmpreg;
+ tmpreg = USARTx->DR;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear IDLE line detected Flag
+ * @note Clearing this flag is done by a read access to the USARTx_SR
+ * register followed by a read access to the USARTx_DR register.
+ * @note Please also consider that when clearing this flag, other flags as
+ * PE, NE, FE, ORE would also be cleared.
+ * @rmtoll SR IDLE LL_USART_ClearFlag_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+ __IO uint32_t tmpreg;
+ tmpreg = USARTx->SR;
+ (void) tmpreg;
+ tmpreg = USARTx->DR;
+ (void) tmpreg;
+}
+
+/**
+ * @brief Clear Transmission Complete Flag
+ * @rmtoll SR TC LL_USART_ClearFlag_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->SR , ~(USART_SR_TC));
+}
+
+/**
+ * @brief Clear RX Not Empty Flag
+ * @rmtoll SR RXNE LL_USART_ClearFlag_RXNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->SR , ~(USART_SR_RXNE));
+}
+
+/**
+ * @brief Clear LIN Break Detection Flag
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll SR LBD LL_USART_ClearFlag_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->SR , ~(USART_SR_LBD));
+}
+
+/**
+ * @brief Clear CTS Interrupt Flag
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll SR CTS LL_USART_ClearFlag_nCTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+ WRITE_REG(USARTx->SR , ~(USART_SR_CTS));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+ * @{
+ */
+
+/**
+ * @brief Enable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+ * @brief Enable RX Not Empty Interrupt
+ * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+ * @brief Enable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_USART_EnableIT_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+ * @brief Enable TX Empty Interrupt
+ * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+ * @brief Enable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_USART_EnableIT_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Enable LIN Break Detection Interrupt
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+ * @brief Enable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+ * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
+ * 0: Interrupt is inhibited
+ * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
+ * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Enable CTS Interrupt
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Disable IDLE Interrupt
+ * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+ * @brief Disable RX Not Empty Interrupt
+ * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+ * @brief Disable Transmission Complete Interrupt
+ * @rmtoll CR1 TCIE LL_USART_DisableIT_TC
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+ * @brief Disable TX Empty Interrupt
+ * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+ * @brief Disable Parity Error Interrupt
+ * @rmtoll CR1 PEIE LL_USART_DisableIT_PE
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+ * @brief Disable LIN Break Detection Interrupt
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+ * @brief Disable Error Interrupt
+ * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+ * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
+ * 0: Interrupt is inhibited
+ * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
+ * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+ * @brief Disable CTS Interrupt
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+ * @brief Check if the USART IDLE Interrupt source is enabled or disabled.
+ * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
+}
+
+/**
+ * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled.
+ * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
+}
+
+/**
+ * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled.
+ * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
+}
+
+/**
+ * @brief Check if the USART TX Empty Interrupt is enabled or disabled.
+ * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
+}
+
+/**
+ * @brief Check if the USART Parity Error Interrupt is enabled or disabled.
+ * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
+}
+
+/**
+ * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+ * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * LIN feature is supported by the USARTx instance.
+ * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
+}
+
+/**
+ * @brief Check if the USART Error Interrupt is enabled or disabled.
+ * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
+}
+
+/**
+ * @brief Check if the USART CTS Interrupt is enabled or disabled.
+ * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * Hardware Flow control feature is supported by the USARTx instance.
+ * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+ * @{
+ */
+
+/**
+ * @brief Enable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Disable DMA Mode for reception
+ * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for reception
+ * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
+}
+
+/**
+ * @brief Enable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Disable DMA Mode for transmission
+ * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+ * @brief Check if DMA Mode is enabled for transmission
+ * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX
+ * @param USARTx USART Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+{
+ return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
+}
+
+/**
+ * @brief Get the data register address used for DMA transfer
+ * @rmtoll DR DR LL_USART_DMA_GetRegAddr
+ * @note Address of Data Register is valid for both Transmit and Receive transfers.
+ * @param USARTx USART Instance
+ * @retval Address of data register
+ */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
+{
+ /* return address of DR register */
+ return ((uint32_t) &(USARTx->DR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+ * @{
+ */
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 8 bits)
+ * @rmtoll DR DR LL_USART_ReceiveData8
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+ */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+{
+ return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR));
+}
+
+/**
+ * @brief Read Receiver Data register (Receive Data value, 9 bits)
+ * @rmtoll DR DR LL_USART_ReceiveData9
+ * @param USARTx USART Instance
+ * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+ */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+{
+ return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR));
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
+ * @rmtoll DR DR LL_USART_TransmitData8
+ * @param USARTx USART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+ USARTx->DR = Value;
+}
+
+/**
+ * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
+ * @rmtoll DR DR LL_USART_TransmitData9
+ * @param USARTx USART Instance
+ * @param Value between Min_Data=0x00 and Max_Data=0x1FF
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+ USARTx->DR = Value & 0x1FFU;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_LL_EF_Execution Execution
+ * @{
+ */
+
+/**
+ * @brief Request Break sending
+ * @rmtoll CR1 SBK LL_USART_RequestBreakSending
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_SBK);
+}
+
+/**
+ * @brief Put USART in Mute mode
+ * @rmtoll CR1 RWU LL_USART_RequestEnterMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+ SET_BIT(USARTx->CR1, USART_CR1_RWU);
+}
+
+/**
+ * @brief Put USART in Active mode
+ * @rmtoll CR1 RWU LL_USART_RequestExitMuteMode
+ * @param USARTx USART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx)
+{
+ CLEAR_BIT(USARTx->CR1, USART_CR1_RWU);
+}
+
+/**
+ * @}
+ */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+ * @{
+ */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+ * @}
+ */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_USART_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usb.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usb.h
index 5d5c175..67025ca 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usb.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_usb.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_ll_usb.h
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of USB Low Layer HAL module.
******************************************************************************
* @attention
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_utils.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_utils.h
new file mode 100644
index 0000000..1ac615c
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_utils.h
@@ -0,0 +1,284 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_utils.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of UTILS LL module.
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ The LL UTILS driver contains a set of generic APIs that can be
+ used by user:
+ (+) Device electronic signature
+ (+) Timing functions
+ (+) PLL configuration functions
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_UTILS_H
+#define __STM32F1xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+/** @defgroup UTILS_LL UTILS
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+ * @{
+ */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY 0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+ * @{
+ */
+/**
+ * @}
+ */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+ * @{
+ */
+/**
+ * @brief UTILS PLL structure definition
+ */
+typedef struct
+{
+ uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
+ This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+ uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
+ This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+ * @brief UTILS System, AHB and APB buses clock configuration structure definition
+ */
+typedef struct
+{
+ uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAHBPrescaler(). */
+
+ uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAPB1Prescaler(). */
+
+ uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+ This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+ This feature can be modified afterwards using unitary function
+ @ref LL_RCC_SetAPB2Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+ * @{
+ */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+ * @{
+ */
+#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
+#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+ * @{
+ */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+ * @{
+ */
+
+/**
+ * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[31:0]
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+ * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[63:32]
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+ * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
+ * @retval UID[95:64]
+ */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+ return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+ * @brief Get Flash memory size
+ * @note This bitfield indicates the size of the device Flash memory expressed in
+ * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+ * @retval FLASH_SIZE[15:0]: Flash memory size
+ */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+ return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source of the time base.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ * @note When a RTOS is used, it is recommended to avoid changing the SysTick
+ * configuration by calling this function, for a delay use rather osDelay RTOS service.
+ * @param Ticks Number of ticks
+ * @retval None
+ */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+ /* Configure the SysTick to have interrupt in 1ms time base */
+ SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
+}
+
+void LL_Init1msTick(uint32_t HCLKFrequency);
+void LL_mDelay(uint32_t Delay);
+
+/**
+ * @}
+ */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+ * @{
+ */
+
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_UTILS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_wwdg.h b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_wwdg.h
new file mode 100644
index 0000000..7330ac8
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/include/stm32f1xx_ll_wwdg.h
@@ -0,0 +1,342 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_wwdg.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief Header file of WWDG LL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F1xx_LL_WWDG_H
+#define __STM32F1xx_LL_WWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (WWDG)
+
+/** @defgroup WWDG_LL WWDG
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
+ * @{
+ */
+
+
+/** @defgroup WWDG_LL_EC_IT IT Defines
+ * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
+ * @{
+ */
+#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
+* @{
+*/
+#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
+#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
+#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
+ * @{
+ */
+/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
+ * @{
+ */
+/**
+ * @brief Write a value in WWDG register
+ * @param __INSTANCE__ WWDG Instance
+ * @param __REG__ Register to be written
+ * @param __VALUE__ Value to be written in the register
+ * @retval None
+ */
+#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+ * @brief Read a value in WWDG register
+ * @param __INSTANCE__ WWDG Instance
+ * @param __REG__ Register to be read
+ * @retval Register value
+ */
+#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
+ * @{
+ */
+
+/** @defgroup WWDG_LL_EF_Configuration Configuration
+ * @{
+ */
+/**
+ * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
+ * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
+ * then it cannot be disabled again except by a reset.
+ * This bit is set by software and only cleared by hardware after a reset.
+ * When WDGA = 1, the watchdog can generate a reset.
+ * @rmtoll CR WDGA LL_WWDG_Enable
+ * @param WWDGx WWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
+{
+ SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
+}
+
+/**
+ * @brief Checks if Window Watchdog is enabled
+ * @rmtoll CR WDGA LL_WWDG_IsEnabled
+ * @param WWDGx WWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
+{
+ return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
+}
+
+/**
+ * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
+ * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
+ * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
+ * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
+ * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
+ * @rmtoll CR T LL_WWDG_SetCounter
+ * @param WWDGx WWDG Instance
+ * @param Counter 0..0x7F (7 bit counter value)
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
+{
+ MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
+}
+
+/**
+ * @brief Return current Watchdog Counter Value (7 bits counter value)
+ * @rmtoll CR T LL_WWDG_GetCounter
+ * @param WWDGx WWDG Instance
+ * @retval 7 bit Watchdog Counter value
+ */
+__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
+{
+ return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
+}
+
+/**
+ * @brief Set the time base of the prescaler (WDGTB).
+ * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
+ * is decremented every (4096 x 2expWDGTB) PCLK cycles
+ * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
+ * @param WWDGx WWDG Instance
+ * @param Prescaler This parameter can be one of the following values:
+ * @arg @ref LL_WWDG_PRESCALER_1
+ * @arg @ref LL_WWDG_PRESCALER_2
+ * @arg @ref LL_WWDG_PRESCALER_4
+ * @arg @ref LL_WWDG_PRESCALER_8
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
+{
+ MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
+}
+
+/**
+ * @brief Return current Watchdog Prescaler Value
+ * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
+ * @param WWDGx WWDG Instance
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_WWDG_PRESCALER_1
+ * @arg @ref LL_WWDG_PRESCALER_2
+ * @arg @ref LL_WWDG_PRESCALER_4
+ * @arg @ref LL_WWDG_PRESCALER_8
+ */
+__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
+{
+ return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
+}
+
+/**
+ * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
+ * @note This window value defines when write in the WWDG_CR register
+ * to program Watchdog counter is allowed.
+ * Watchdog counter value update must occur only when the counter value
+ * is lower than the Watchdog window register value.
+ * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
+ * (in the control register) is refreshed before the downcounter has reached
+ * the watchdog window register value.
+ * Physically is possible to set the Window lower then 0x40 but it is not recommended.
+ * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
+ * @rmtoll CFR W LL_WWDG_SetWindow
+ * @param WWDGx WWDG Instance
+ * @param Window 0x00..0x7F (7 bit Window value)
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
+{
+ MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
+}
+
+/**
+ * @brief Return current Watchdog Window Value (7 bits value)
+ * @rmtoll CFR W LL_WWDG_GetWindow
+ * @param WWDGx WWDG Instance
+ * @retval 7 bit Watchdog Window value
+ */
+__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
+{
+ return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
+ * @{
+ */
+/**
+ * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
+ * @note This bit is set by hardware when the counter has reached the value 0x40.
+ * It must be cleared by software by writing 0.
+ * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
+ * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
+}
+
+/**
+ * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
+ * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDG_LL_EF_IT_Management IT_Management
+ * @{
+ */
+/**
+ * @brief Enable the Early Wakeup Interrupt.
+ * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
+ * This interrupt is only cleared by hardware after a reset
+ * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
+}
+
+/**
+ * @brief Check if Early Wakeup Interrupt is enabled
+ * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
+ * @param WWDGx WWDG Instance
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
+{
+ return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* WWDG */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F1xx_LL_WWDG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal.c
index 3e5f1d1..3229c11 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@@ -70,20 +70,19 @@
/** @defgroup HAL_Private_Constants HAL Private Constants
* @{
*/
-
/**
- * @brief STM32F1xx HAL Driver version number
+ * @brief STM32F1xx HAL Driver version number V1.1.0
*/
-#define __STM32F1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F1xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
-#define __STM32F1xx_HAL_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
-#define __STM32F1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
+#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
+#define __STM32F1xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
+#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\
|(__STM32F1xx_HAL_VERSION_SUB1 << 16)\
|(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\
|(__STM32F1xx_HAL_VERSION_RC))
-#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+#define IDCODE_DEVID_MASK 0x00000FFFU
/**
* @}
@@ -95,13 +94,10 @@
/** @defgroup HAL_Private_Variables HAL Private Variables
* @{
*/
-
-static __IO uint32_t uwTick;
-
+__IO uint32_t uwTick;
/**
* @}
*/
-
/* Private function prototypes -----------------------------------------------*/
/* Exported functions ---------------------------------------------------------*/
@@ -136,22 +132,27 @@
peripheral ISR process, the Tick interrupt line must have higher priority
(numerically lower) than the peripheral interrupt. Otherwise the caller
ISR process will be blocked.
- (++) functions affecting time base configurations are declared as __Weak
+ (++) functions affecting time base configurations are declared as __weak
to make override possible in case of other implementations in user file.
-
@endverbatim
* @{
*/
/**
- * @brief This function configures the Flash prefetch,
- * Configures time base source, NVIC and Low level hardware
- * @note This function is called at the beginning of program after reset and before
- * the clock configuration
- * @note The time base configuration is based on MSI clock when exiting from Reset.
- * Once done, time base tick start incrementing.
- * In the default implementation,Systick is used as source of time base.
- * The tick variable is incremented each 1ms in its ISR.
+ * @brief This function is used to initialize the HAL Library; it must be the first
+ * instruction to be executed in the main program (before to call any other
+ * HAL function), it performs the following:
+ * Configure the Flash prefetch.
+ * Configures the SysTick to generate an interrupt each 1 millisecond,
+ * which is clocked by the HSI (at this stage, the clock is not yet
+ * configured and thus the system is running from the internal HSI at 16 MHz).
+ * Set NVIC Group Priority to 4.
+ * Calls the HAL_MspInit() callback function defined in user file
+ * "stm32f1xx_hal_msp.c" to do the global low level hardware initialization
+ *
+ * @note SysTick is used as time base for the HAL_Delay() function, the application
+ * need to ensure that the SysTick time base is always set to 1 millisecond
+ * to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
@@ -241,7 +242,7 @@
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
* The the SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
- * The function is declared as __Weak to be overwritten in case of other
+ * The function is declared as __weak to be overwritten in case of other
* implementation in user file.
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
@@ -249,12 +250,12 @@
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
- HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+ HAL_SYSTICK_Config(SystemCoreClock/1000U);
/*Configure the SysTick IRQ priority */
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
- /* Return function status */
+ /* Return function status */
return HAL_OK;
}
@@ -263,8 +264,8 @@
*/
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
- * @brief HAL Control functions
- *
+ * @brief HAL Control functions
+ *
@verbatim
===============================================================================
##### HAL Control functions #####
@@ -277,10 +278,10 @@
(+) Get the HAL API driver version
(+) Get the device identifier
(+) Get the device revision identifier
- (+) Enable/Disable Debug module during Sleep mode
+ (+) Enable/Disable Debug module during SLEEP mode
(+) Enable/Disable Debug module during STOP mode
(+) Enable/Disable Debug module during STANDBY mode
-
+
@endverbatim
* @{
*/
@@ -301,7 +302,7 @@
/**
* @brief Provides a tick value in millisecond.
- * @note This function is declared as __weak to be overwritten in case of other
+ * @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
@@ -311,21 +312,28 @@
}
/**
- * @brief This function provides accurate delay (in milliseconds) based
+ * @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
- * @note ThiS function is declared as __weak to be overwritten in case of other
+ * @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param Delay: specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(__IO uint32_t Delay)
{
- uint32_t tickstart = 0;
- tickstart = HAL_GetTick();
- while((HAL_GetTick() - tickstart) < Delay)
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t wait = Delay;
+
+ /* Add a period to guarantee minimum wait */
+ if (wait < HAL_MAX_DELAY)
+ {
+ wait++;
+ }
+
+ while((HAL_GetTick() - tickstart) < wait)
{
}
}
@@ -334,7 +342,7 @@
* @brief Suspend Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
- * is called, the the SysTick interrupt will be disabled and so Tick increment
+ * is called, the SysTick interrupt will be disabled and so Tick increment
* is suspended.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
@@ -350,9 +358,9 @@
* @brief Resume Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
- * is called, the the SysTick interrupt will be enabled and so Tick increment
+ * is called, the SysTick interrupt will be enabled and so Tick increment
* is resumed.
- * @note This function is declared as __weak to be overwritten in case of other
+ * @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
@@ -363,8 +371,8 @@
}
/**
- * @brief This method returns the HAL revision
- * @retval version: 0xXYZR (8bits for each decimal, R for RC)
+ * @brief Returns the HAL revision
+ * @retval version : 0xXYZR (8bits for each decimal, R for RC)
*/
uint32_t HAL_GetHalVersion(void)
{
@@ -384,7 +392,7 @@
*/
uint32_t HAL_GetREVID(void)
{
- return((DBGMCU->IDCODE) >> POSITION_VAL(DBGMCU_IDCODE_REV_ID));
+ return((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos);
}
/**
@@ -507,6 +515,18 @@
}
/**
+ * @brief Return the unique device identifier (UID based on 96 bits)
+ * @param UID: pointer to 3 words array.
+ * @retval Device identifier
+ */
+void HAL_GetUID(uint32_t *UID)
+{
+ UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));
+ UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+ UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_adc.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_adc.c
index 5b0fce6..71f5599 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_adc.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_adc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_adc.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
@@ -300,18 +300,18 @@
/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
/* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
/* Unit: ms */
- #define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
- #define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
+ #define ADC_ENABLE_TIMEOUT 2U
+ #define ADC_DISABLE_TIMEOUT 2U
/* Delay for ADC stabilization time. */
/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
/* Unit: us */
- #define ADC_STAB_DELAY_US ((uint32_t) 1)
+ #define ADC_STAB_DELAY_US 1U
/* Delay for temperature sensor stabilization time. */
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
/* Unit: us */
- #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
+ #define ADC_TEMPSENSOR_DELAY_US 10U
/**
* @}
@@ -374,9 +374,9 @@
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- uint32_t tmp_cr1 = 0;
- uint32_t tmp_cr2 = 0;
- uint32_t tmp_sqr1 = 0;
+ uint32_t tmp_cr1 = 0U;
+ uint32_t tmp_cr2 = 0U;
+ uint32_t tmp_sqr1 = 0U;
/* Check ADC handle */
if(hadc == NULL)
@@ -924,12 +924,12 @@
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Variables for polling in case of scan mode enabled and polling for each */
/* conversion. */
- __IO uint32_t Conversion_Timeout_CPU_cycles = 0;
- uint32_t Conversion_Timeout_CPU_cycles_max = 0;
+ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U;
+ uint32_t Conversion_Timeout_CPU_cycles_max = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -974,7 +974,7 @@
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -1002,7 +1002,7 @@
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -1055,7 +1055,7 @@
*/
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -1070,7 +1070,7 @@
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -1702,7 +1702,7 @@
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- __IO uint32_t wait_loop_index = 0;
+ __IO uint32_t wait_loop_index = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -1716,14 +1716,14 @@
/* Regular sequence configuration */
/* For Rank 1 to 6 */
- if (sConfig->Rank < 7)
+ if (sConfig->Rank < 7U)
{
MODIFY_REG(hadc->Instance->SQR3 ,
ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) ,
ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
}
/* For Rank 7 to 12 */
- else if (sConfig->Rank < 13)
+ else if (sConfig->Rank < 13U)
{
MODIFY_REG(hadc->Instance->SQR2 ,
ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) ,
@@ -1771,8 +1771,8 @@
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
- while(wait_loop_index != 0)
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
+ while(wait_loop_index != 0U)
{
wait_loop_index--;
}
@@ -1933,8 +1933,8 @@
*/
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
{
- uint32_t tickstart = 0;
- __IO uint32_t wait_loop_index = 0;
+ uint32_t tickstart = 0U;
+ __IO uint32_t wait_loop_index = 0U;
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
@@ -1947,8 +1947,8 @@
/* Delay for ADC stabilization time */
/* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
- while(wait_loop_index != 0)
+ wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
+ while(wait_loop_index != 0U)
{
wait_loop_index--;
}
@@ -1988,7 +1988,7 @@
*/
HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Verification if ADC is not already disabled */
if (ADC_IS_ENABLE(hadc) != RESET)
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_adc_ex.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_adc_ex.c
index ddd1f6f..1742df5 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_adc_ex.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_adc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_adc_ex.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
@@ -77,7 +77,7 @@
/* Hardware prerequisite before starting a calibration: the ADC must have */
/* been in power-on state for at least two ADC clock cycles. */
/* Unit: ADC clock cycles */
- #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ((uint32_t) 2)
+ #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES 2U
/* Timeout value for ADC calibration */
/* Value defined to be higher than worst cases: low clocks freq, */
@@ -85,12 +85,12 @@
/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
/* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
/* Unit: ms */
- #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10)
+ #define ADC_CALIBRATION_TIMEOUT 10U
/* Delay for temperature sensor stabilization time. */
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
/* Unit: us */
- #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
+ #define ADC_TEMPSENSOR_DELAY_US 10U
/**
* @}
@@ -145,7 +145,7 @@
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tickstart;
- __IO uint32_t wait_loop_index = 0;
+ __IO uint32_t wait_loop_index = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -175,7 +175,7 @@
/ HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
* ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES );
- while(wait_loop_index != 0)
+ while(wait_loop_index != 0U)
{
wait_loop_index--;
}
@@ -405,8 +405,8 @@
/* Variables for polling in case of scan mode enabled and polling for each */
/* conversion. */
- __IO uint32_t Conversion_Timeout_CPU_cycles = 0;
- uint32_t Conversion_Timeout_CPU_cycles_max = 0;
+ __IO uint32_t Conversion_Timeout_CPU_cycles = 0U;
+ uint32_t Conversion_Timeout_CPU_cycles_max = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -438,7 +438,7 @@
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@@ -666,7 +666,7 @@
return tmp_hal_status;
}
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
/**
* @brief Enables ADC, starts conversion of regular group and transfers result
* through DMA.
@@ -704,8 +704,7 @@
/* conversion trigger ADC_SOFTWARE_START. */
/* Note: External trigger of ADC slave must be enabled, it is already done */
/* into function "HAL_ADC_Init()". */
- if ((tmphadcSlave.Instance == NULL) ||
- (! ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave)) )
+ if(!ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave))
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
@@ -829,39 +828,26 @@
tmp_hal_status = ADC_ConversionStop_Disable(hadc);
/* Check if ADC is effectively disabled */
- if (tmp_hal_status == HAL_OK)
+ if(tmp_hal_status == HAL_OK)
{
/* Set a temporary handle of the ADC slave associated to the ADC master */
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
- if (tmphadcSlave.Instance == NULL)
+ /* Disable ADC slave peripheral */
+ tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave);
+
+ /* Check if ADC is effectively disabled */
+ if(tmp_hal_status != HAL_OK)
{
/* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
-
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
/* Process unlocked */
__HAL_UNLOCK(hadc);
-
+
return HAL_ERROR;
}
- else
- {
- /* Disable ADC slave peripheral */
- tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave);
-
- /* Check if ADC is effectively disabled */
- if (tmp_hal_status != HAL_OK)
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
-
- /* Process unlocked */
- __HAL_UNLOCK(hadc);
-
- return HAL_ERROR;
- }
- }
-
+
/* Disable ADC DMA mode */
CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
@@ -871,21 +857,11 @@
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
/* while DMA transfer is on going) */
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
-
-
- /* Check if DMA channel effectively disabled */
- if (tmp_hal_status == HAL_OK)
- {
- /* Change ADC state (ADC master) */
- ADC_STATE_CLR_SET(hadc->State,
- HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
- HAL_ADC_STATE_READY);
- }
- else
- {
- /* Update ADC state machine to error */
- SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
- }
+
+ /* Change ADC state (ADC master) */
+ ADC_STATE_CLR_SET(hadc->State,
+ HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+ HAL_ADC_STATE_READY);
}
/* Process unlocked */
@@ -894,7 +870,7 @@
/* Return function status */
return tmp_hal_status;
}
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
* @brief Get ADC injected group conversion result.
@@ -926,7 +902,7 @@
*/
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
{
- uint32_t tmp_jdr = 0;
+ uint32_t tmp_jdr = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -954,7 +930,7 @@
return tmp_jdr;
}
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
/**
* @brief Returns the last ADC Master&Slave regular conversions results data
* in the selected multi mode.
@@ -963,7 +939,7 @@
*/
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
{
- uint32_t tmpDR = 0;
+ uint32_t tmpDR = 0U;
/* Check the parameters */
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
@@ -980,13 +956,13 @@
if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA))
{
- tmpDR |= (ADC2->DR << 16);
+ tmpDR |= (ADC2->DR << 16U);
}
/* Return ADC converted value */
return tmpDR;
}
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
* @brief Injected conversion complete callback in non blocking mode
@@ -1038,7 +1014,7 @@
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
- __IO uint32_t wait_loop_index = 0;
+ __IO uint32_t wait_loop_index = 0U;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -1080,7 +1056,7 @@
ADC_JSQR_JSQ1 ,
ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
ADC_INJECTED_RANK_1,
- 0x01) );
+ 0x01U));
}
/* If another injected rank than rank1 was intended to be set, and could */
/* not due to ScanConvMode disabled, error is reported. */
@@ -1123,7 +1099,7 @@
sConfigInjected->InjectedRank,
sConfigInjected->InjectedNbrOfConversion) ,
- 0x00000000 );
+ 0x00000000U);
}
}
@@ -1255,8 +1231,8 @@
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
- wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
- while(wait_loop_index != 0)
+ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
+ while(wait_loop_index != 0U)
{
wait_loop_index--;
}
@@ -1279,7 +1255,7 @@
return tmp_hal_status;
}
-#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
/**
* @brief Enable ADC multimode and configure multimode parameters
* @note Possibility to update parameters on the fly:
@@ -1344,7 +1320,7 @@
/* Return function status */
return tmp_hal_status;
}
-#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
+#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_can.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_can.c
index 19afb04..f539af9 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_can.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_can.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_can.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
@@ -27,12 +27,16 @@
(++) Connect and configure the involved CAN pins using the
following function HAL_GPIO_Init();
- (#) Initialise and configure the CAN using HAL_CAN_Init() function.
+ (#) Initialize and configure the CAN using HAL_CAN_Init() function.
(#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
+
+ (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
(#) Receive a CAN frame using HAL_CAN_Receive() function.
+ (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
+
*** Polling mode IO operation ***
=================================
[..]
@@ -73,7 +77,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -102,12 +106,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
-
-#ifdef HAL_CAN_MODULE_ENABLED
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
- defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-
+
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
@@ -117,31 +116,34 @@
* @{
*/
+#ifdef HAL_CAN_MODULE_ENABLED
+
+#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
+ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
+
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
-#define CAN_TIMEOUT_VALUE 10
-
-#define CAN_TI0R_STID_BIT_POSITION ((uint32_t)21) /* Position of LSB bits STID in register CAN_TI0R */
-#define CAN_TI0R_EXID_BIT_POSITION ((uint32_t) 3) /* Position of LSB bits EXID in register CAN_TI0R */
-#define CAN_TDL0R_DATA0_BIT_POSITION ((uint32_t) 0) /* Position of LSB bits DATA0 in register CAN_TDL0R */
-#define CAN_TDL0R_DATA1_BIT_POSITION ((uint32_t) 8) /* Position of LSB bits DATA1 in register CAN_TDL0R */
-#define CAN_TDL0R_DATA2_BIT_POSITION ((uint32_t)16) /* Position of LSB bits DATA2 in register CAN_TDL0R */
-#define CAN_TDL0R_DATA3_BIT_POSITION ((uint32_t)24) /* Position of LSB bits DATA3 in register CAN_TDL0R */
-
+#define CAN_TIMEOUT_VALUE 10U
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup CAN_Private_Functions CAN Private Functions
+ * @{
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
/**
* @}
*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
-/* Exported functions ---------------------------------------------------------*/
-
+/* Exported functions --------------------------------------------------------*/
/** @defgroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
@@ -171,8 +173,8 @@
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
{
uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
- uint32_t tickstart = 0;
- uint32_t tmp_mcr = 0;
+ uint32_t tickstart = 0U;
+ uint32_t tmp_mcr = 0U;
/* Check CAN handle */
if(hcan == NULL)
@@ -220,10 +222,8 @@
if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
-
/* Process unlocked */
__HAL_UNLOCK(hcan);
-
return HAL_TIMEOUT;
}
}
@@ -236,36 +236,58 @@
{
SET_BIT(tmp_mcr, CAN_MCR_TTCM);
}
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_TTCM);
+ }
/* Set the automatic bus-off management */
if (hcan->Init.ABOM == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_ABOM);
}
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_ABOM);
+ }
/* Set the automatic wake-up mode */
if (hcan->Init.AWUM == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_AWUM);
}
-
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_AWUM);
+ }
/* Set the no automatic retransmission */
if (hcan->Init.NART == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_NART);
}
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_NART);
+ }
/* Set the receive FIFO locked mode */
if (hcan->Init.RFLM == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_RFLM);
}
-
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_RFLM);
+ }
/* Set the transmit FIFO priority */
if (hcan->Init.TXFP == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_TXFP);
}
+ else
+ {
+ CLEAR_BIT(tmp_mcr, CAN_MCR_TXFP);
+ }
/* Update register MCR */
MODIFY_REG(hcan->Instance->MCR,
@@ -282,7 +304,7 @@
hcan->Init.SJW |
hcan->Init.BS1 |
hcan->Init.BS2 |
- (hcan->Init.Prescaler - 1) ));
+ (hcan->Init.Prescaler - 1U)));
/* Request leave initialisation */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
@@ -291,7 +313,7 @@
tickstart = HAL_GetTick();
/* Wait the acknowledge */
- while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
+ while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
{
if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
{
@@ -305,7 +327,7 @@
}
/* Check acknowledged */
- if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
+ if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
{
status = CAN_INITSTATUS_SUCCESS;
}
@@ -326,7 +348,7 @@
{
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
-
+
/* Return function status */
return HAL_ERROR;
}
@@ -343,8 +365,11 @@
*/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
{
- uint32_t filternbrbitpos = 0;
+ uint32_t filternbrbitpos = 0U;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
/* Check the parameters */
assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
@@ -353,18 +378,18 @@
assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
- filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
+ filternbrbitpos = (1U) << sFilterConfig->FilterNumber;
/* Initialisation mode for the filter */
/* Select the start slave bank */
MODIFY_REG(hcan->Instance->FMR ,
CAN_FMR_CAN2SB ,
CAN_FMR_FINIT |
- (uint32_t)(sFilterConfig->BankNumber << 8) );
-
+ (uint32_t)(sFilterConfig->BankNumber << 8U) );
+
/* Filter Deactivation */
CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos);
-
+
/* Filter Scale */
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
{
@@ -374,14 +399,14 @@
/* First 16-bit identifier and First 16-bit mask */
/* Or First 16-bit identifier and Second 16-bit identifier */
hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
/* Second 16-bit identifier and Second 16-bit mask */
/* Or Third 16-bit identifier and Fourth 16-bit identifier */
hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
}
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
@@ -390,12 +415,12 @@
SET_BIT(hcan->Instance->FS1R, filternbrbitpos);
/* 32-bit identifier or First 32-bit identifier */
hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
/* 32-bit mask or Second 32-bit identifier */
hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
}
/* Filter Mode */
@@ -503,8 +528,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions
- * @brief I/O operation functions
- *
+ * @brief I/O operation functions
+ *
@verbatim
==============================================================================
##### IO operation functions #####
@@ -529,127 +554,133 @@
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
{
uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- if(hcan->State == HAL_CAN_STATE_BUSY_RX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
- }
- else
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- }
-
- /* Select one empty transmit mailbox */
- if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
- {
- transmitmailbox = 0;
- }
- else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
- {
- transmitmailbox = 1;
- }
- else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME2))
- {
- transmitmailbox = 2;
- }
- else
- {
- transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
- }
- if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
{
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ }
+
+ /* Select one empty transmit mailbox */
+ if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
+ {
+ transmitmailbox = CAN_TXMAILBOX_0;
+ }
+ else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
+ {
+ transmitmailbox = CAN_TXMAILBOX_1;
+ }
+ else
+ {
+ transmitmailbox = CAN_TXMAILBOX_2;
+ }
+
/* Set up the Id */
hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
if (hcan->pTxMsg->IDE == CAN_ID_STD)
{
assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_BIT_POSITION) |
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) |
hcan->pTxMsg->RTR);
}
else
{
assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_BIT_POSITION) |
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) |
hcan->pTxMsg->IDE |
hcan->pTxMsg->RTR);
}
-
+
/* Set up the DLC */
hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
/* Set up the data field */
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_BIT_POSITION) );
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_BIT_POSITION) );
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos));
/* Request transmission */
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
-
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Check End of transmission flag */
while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
{
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
hcan->State = HAL_CAN_STATE_TIMEOUT;
-
+
+ /* Cancel transmission */
+ __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
+
/* Process unlocked */
__HAL_UNLOCK(hcan);
-
return HAL_TIMEOUT;
}
}
}
- if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+ /* Change CAN state */
+ switch(hcan->State)
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_RX;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
}
- else
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
- }
-
+
/* Process unlocked */
__HAL_UNLOCK(hcan);
-
+
/* Return function status */
return HAL_OK;
}
else
{
/* Change CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
+ hcan->State = HAL_CAN_STATE_ERROR;
/* Return function status */
return HAL_ERROR;
@@ -671,7 +702,9 @@
assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
- if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX))
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
{
/* Process Locked */
__HAL_LOCK(hcan);
@@ -679,236 +712,74 @@
/* Select one empty transmit mailbox */
if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0))
{
- transmitmailbox = 0;
+ transmitmailbox = CAN_TXMAILBOX_0;
}
else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1))
{
- transmitmailbox = 1;
- }
- else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME2))
- {
- transmitmailbox = 2;
+ transmitmailbox = CAN_TXMAILBOX_1;
}
else
{
- transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+ transmitmailbox = CAN_TXMAILBOX_2;
}
- if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if(hcan->pTxMsg->IDE == CAN_ID_STD)
{
- /* Set up the Id */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
- if (hcan->pTxMsg->IDE == CAN_ID_STD)
- {
- assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_BIT_POSITION) |
- hcan->pTxMsg->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_BIT_POSITION) |
- hcan->pTxMsg->IDE |
- hcan->pTxMsg->RTR);
- }
-
- /* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
- /* Set up the data field */
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_BIT_POSITION) );
- WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_BIT_POSITION) |
- ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_BIT_POSITION) );
-
- if(hcan->State == HAL_CAN_STATE_BUSY_RX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
- }
- else
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- }
-
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Enable interrupts: */
- /* - Enable Error warning Interrupt */
- /* - Enable Error passive Interrupt */
- /* - Enable Bus-off Interrupt */
- /* - Enable Last error code Interrupt */
- /* - Enable Error Interrupt */
- /* - Enable Transmit mailbox empty Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_TME );
-
- /* Request transmission */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Receives a correct CAN frame.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber: FIFO Number value
- * @param Timeout: Specify Timeout value
- * @retval HAL status
- * @retval None
- */
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Check the parameters */
- assert_param(IS_CAN_FIFO(FIFONumber));
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
- }
- else
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_RX;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check pending message */
- while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hcan->State = HAL_CAN_STATE_TIMEOUT;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- /* Get the Id */
- hcan->pRxMsg->IDE = (uint8_t)CAN_ID_EXT & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (hcan->pRxMsg->IDE == CAN_ID_STD)
- {
- hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
- }
- else
- {
- hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
- }
-
- hcan->pRxMsg->RTR = (uint8_t)CAN_RTR_REMOTE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FMI */
- hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
- /* Get the data field */
- hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
- hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
- hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
- hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
- hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
- hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
-
- /* Release the FIFO */
- if(FIFONumber == CAN_FIFO0)
- {
- /* Release FIFO0 */
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- /* Release FIFO1 */
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
- }
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- }
- else
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
- }
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Receives a correct CAN frame.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber: Specify the FIFO number
- * @retval HAL status
- * @retval None
- */
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_FIFO(FIFONumber));
-
- if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX))
- {
- /* Process locked */
- __HAL_LOCK(hcan);
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX)
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \
+ hcan->pTxMsg->RTR);
}
else
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_RX;
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \
+ hcan->pTxMsg->IDE |
+ hcan->pTxMsg->RTR);
}
-
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3U] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[2U] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[1U] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[0U] << CAN_TDL0R_DATA0_Pos));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7U] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[6U] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[5U] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)hcan->pTxMsg->Data[4U] << CAN_TDL0R_DATA0_Pos));
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ }
+
/* Set CAN error code to none */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
/* Enable interrupts: */
/* - Enable Error warning Interrupt */
/* - Enable Error passive Interrupt */
@@ -922,27 +793,309 @@
CAN_IT_LEC |
CAN_IT_ERR |
CAN_IT_TME );
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- if(FIFONumber == CAN_FIFO0)
- {
- /* Enable FIFO 0 message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0);
- }
- else
- {
- /* Enable FIFO 1 message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1);
- }
-
}
else
{
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber: FIFO Number value
+ * @param Timeout: Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
return HAL_BUSY;
}
+
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ }
+ }
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Check pending message */
+ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
+ /* Get the Id */
+ pRxMsg->IDE = (uint8_t)CAN_ID_EXT & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
+ {
+ pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+ }
+ else
+ {
+ pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
+ }
+
+ pRxMsg->RTR = (uint8_t)CAN_RTR_REMOTE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
+ /* Get the data field */
+ pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
+ pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
+ pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
+ pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
+ pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
+ pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
+
+ /* Release the FIFO */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Release FIFO0 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ /* Release FIFO1 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+ }
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber: Specify the FIFO number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ }
+ }
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+
+ /* Enable interrupts: */
+ /* - Enable Error warning Interrupt */
+ /* - Enable Error passive Interrupt */
+ /* - Enable Bus-off Interrupt */
+ /* - Enable Last error code Interrupt */
+ /* - Enable Error Interrupt */
+ /* - Enable Transmit mailbox empty Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME );
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Enable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
+ }
+ else
+ {
+ /* Enable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
+ }
+
/* Return function status */
return HAL_OK;
}
@@ -955,7 +1108,7 @@
*/
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Process locked */
__HAL_LOCK(hcan);
@@ -967,7 +1120,7 @@
MODIFY_REG(hcan->Instance->MCR,
CAN_MCR_INRQ ,
CAN_MCR_SLEEP );
-
+
/* Sleep mode status */
if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
@@ -979,20 +1132,20 @@
return HAL_ERROR;
}
- /* Get tick */
+ /* Get tick */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) ||
- HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) )
+ HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
{
if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State = HAL_CAN_STATE_TIMEOUT;
-
+
/* Process unlocked */
__HAL_UNLOCK(hcan);
-
+
return HAL_TIMEOUT;
}
}
@@ -1016,7 +1169,7 @@
*/
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Process locked */
__HAL_LOCK(hcan);
@@ -1036,10 +1189,8 @@
if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
-
/* Process unlocked */
__HAL_UNLOCK(hcan);
-
return HAL_TIMEOUT;
}
}
@@ -1070,70 +1221,125 @@
*/
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
{
+ uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
+ uint32_t errorcode = HAL_CAN_ERROR_NONE;
+
+ /* Check Overrun flag for FIFO0 */
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
+ if((tmp1 != 0U) && tmp2)
+ {
+ /* Set CAN error code to FOV0 error */
+ errorcode |= HAL_CAN_ERROR_FOV0;
+
+ /* Clear FIFO0 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+ }
+
+ /* Check Overrun flag for FIFO1 */
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
+ if((tmp1 != 0U) && tmp2)
+ {
+ /* Set CAN error code to FOV1 error */
+ errorcode |= HAL_CAN_ERROR_FOV1;
+
+ /* Clear FIFO1 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+ }
+
/* Check End of transmission flag */
if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
{
- if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) ||
- (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) ||
- (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2)))
+ /* Check Transmit request completion status */
+ tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
+ tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
+ tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
+ if(tmp1 || tmp2 || tmp3)
{
- /* Call transmit function */
- CAN_Transmit_IT(hcan);
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0);
+ tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1);
+ tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2);
+ /* Check Transmit success */
+ if((tmp1) || (tmp2) || (tmp3))
+ {
+ /* Call transmit function */
+ CAN_Transmit_IT(hcan);
+ }
+ else /* Transmit failure */
+ {
+ /* Set CAN error code to TXFAIL error */
+ errorcode |= HAL_CAN_ERROR_TXFAIL;
+ }
+
+ /* Clear transmission status flags (RQCPx and TXOKx) */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
+ CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
}
}
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
/* Check End of reception flag for FIFO0 */
- if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) &&
- (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0))
+ if((tmp1 != 0U) && tmp2)
{
/* Call receive function */
CAN_Receive_IT(hcan, CAN_FIFO0);
}
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
/* Check End of reception flag for FIFO1 */
- if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) &&
- (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0))
+ if((tmp1 != 0U) && tmp2)
{
/* Call receive function */
CAN_Receive_IT(hcan, CAN_FIFO1);
}
-
+
+ /* Set error code in handle */
+ hcan->ErrorCode |= errorcode;
+
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
/* Check Error Warning Flag */
- if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ if(tmp1 && tmp2 && tmp3)
{
/* Set CAN error code to EWG error */
hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
/* No need for clear of Error Warning Flag as read-only */
}
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
/* Check Error Passive Flag */
- if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ if(tmp1 && tmp2 && tmp3)
{
/* Set CAN error code to EPV error */
hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
/* No need for clear of Error Passive Flag as read-only */
}
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
/* Check Bus-Off Flag */
- if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ if(tmp1 && tmp2 && tmp3)
{
/* Set CAN error code to BOF error */
hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
/* No need for clear of Bus-Off Flag as read-only */
}
+ tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
/* Check Last error code Flag */
- if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) &&
- (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR)))
+ if((!tmp1) && tmp2 && tmp3)
{
- switch(hcan->Instance->ESR & CAN_ESR_LEC)
+ tmp1 = (hcan->Instance->ESR & CAN_ESR_LEC);
+ switch(tmp1)
{
case(CAN_ESR_LEC_0):
/* Set CAN error code to STF error */
@@ -1166,15 +1372,37 @@
/* Clear Last error code Flag */
CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
}
-
+
/* Call the Error call Back in case of Errors */
if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
{
/* Clear ERRI Flag */
- hcan->Instance->MSR |= CAN_MSR_ERRI;
+ hcan->Instance->MSR = CAN_MSR_ERRI;
/* Set the CAN state ready to be able to start again the process */
hcan->State = HAL_CAN_STATE_READY;
-
+
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ /* - Disable FIFO 0 message pending Interrupt */
+ /* - Disable FIFO 0 Overrun Interrupt */
+ /* - Disable FIFO 1 message pending Interrupt */
+ /* - Disable FIFO 1 Overrun Interrupt */
+ /* - Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_FMP0|
+ CAN_IT_FOV0|
+ CAN_IT_FMP1|
+ CAN_IT_FOV1|
+ CAN_IT_TME );
+
/* Call Error callback function */
HAL_CAN_ErrorCallback(hcan);
}
@@ -1230,8 +1458,8 @@
*/
/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
- * @brief CAN Peripheral State functions
- *
+ * @brief CAN Peripheral State functions
+ *
@verbatim
==============================================================================
##### Peripheral State and Error functions #####
@@ -1276,9 +1504,9 @@
* @}
*/
-/** @defgroup CAN_Private_Functions CAN Private Functions
- * @{
- */
+/** @addtogroup CAN_Private_Functions
+ * @{
+ */
/**
* @brief Initiates and transmits a CAN frame message.
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
@@ -1302,20 +1530,26 @@
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
- CAN_IT_ERR );
+ CAN_IT_ERR);
}
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+
+ /* Change CAN state */
+ switch(hcan->State)
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_RX;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
}
- else
- {
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
- }
-
+
/* Transmission complete callback */
HAL_CAN_TxCpltCallback(hcan);
@@ -1332,50 +1566,66 @@
*/
static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
{
- /* Get the Id */
- hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (hcan->pRxMsg->IDE == CAN_ID_STD)
+ uint32_t tmp1 = 0U;
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
{
- hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21);
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
+ /* Get the Id */
+ pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
+ {
+ pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
}
else
{
- hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3);
+ pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
}
- hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
/* Get the DLC */
- hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
/* Get the FMI */
- hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8);
+ pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
/* Get the data field */
- hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8);
- hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16);
- hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24);
- hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8);
- hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16);
- hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24);
+ pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
+ pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
+ pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
+ pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
+ pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
+ pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
/* Release the FIFO */
/* Release FIFO0 */
if (FIFONumber == CAN_FIFO0)
{
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
- /* Disable FIFO 0 message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0);
+ /* Disable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
}
/* Release FIFO1 */
else /* FIFONumber == CAN_FIFO1 */
{
__HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
- /* Disable FIFO 1 message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1);
+ /* Disable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
}
-
- if(hcan->State == HAL_CAN_STATE_BUSY_RX)
+
+ tmp1 = hcan->State;
+ if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1))
{
/* Disable interrupts: */
/* - Disable Error warning Interrupt */
@@ -1387,18 +1637,45 @@
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
- CAN_IT_ERR );
+ CAN_IT_ERR);
}
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
{
- /* Disable CAN state */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
}
- else
+ else /* FIFONumber == CAN_FIFO1 */
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
}
/* Receive complete callback */
@@ -1409,18 +1686,15 @@
}
/**
- * @}
- */
+ * @}
+ */
+#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
+#endif /* HAL_CAN_MODULE_ENABLED */
/**
* @}
*/
-#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || */
- /* STM32F103xG) || STM32F105xC || STM32F107xC */
-
-#endif /* HAL_CAN_MODULE_ENABLED */
-
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cec.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cec.c
index 8092fa4..1e172bb 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cec.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cec.c
@@ -2,39 +2,46 @@
******************************************************************************
* @file stm32f1xx_hal_cec.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief CEC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface
* Consumer Electronics Control Peripheral (CEC).
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
- *
- * @verbatim
- ==============================================================================
+ * + Initialization and de-initialization function
+ * + IO operation function
+ * + Peripheral Control function
+ *
+ *
+ @verbatim
+ ===============================================================================
##### How to use this driver #####
- ==============================================================================
- [..]
- The CEC HAL driver can be used as follows:
+ ===============================================================================
+ [..]
+ The CEC HAL driver can be used as follow:
+
(#) Declare a CEC_HandleTypeDef handle structure.
(#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
(##) Enable the CEC interface clock.
- (##) Enable the clock for the CEC GPIOs.
- (##) Configure these CEC pins as alternate function pull-up.
+ (##) CEC pins configuration:
+ (+++) Enable the clock for the CEC GPIOs.
+ (+++) Configure these CEC pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
and HAL_CEC_Receive_IT() APIs):
- (##) Configure the CEC interrupt priority.
- (##) Enable the NVIC CEC IRQ handle.
- (##) The CEC interrupt is activated/deactivated by the HAL driver
+ (+++) Configure the CEC interrupt priority.
+ (+++) Enable the NVIC CEC IRQ handle.
+ (+++) The specific CEC interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
+ and receive process.
(#) Program the Bit Timing Error Mode and the Bit Period Error Mode in the hcec Init structure.
(#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
-
- (#) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customized HAL_CEC_MspInit() API.
+
+ [..]
+ (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
+ by calling the customed HAL_CEC_MspInit() API.
@endverbatim
******************************************************************************
@@ -82,7 +89,7 @@
* @brief HAL CEC module driver
* @{
*/
-
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup CEC_Private_Constants CEC Private Constants
@@ -94,8 +101,8 @@
#define CEC_ESR_ALL_ERROR (CEC_ESR_BTE|CEC_ESR_BPE|CEC_ESR_RBTFE|CEC_ESR_SBE|CEC_ESR_ACKE|CEC_ESR_LINE|CEC_ESR_TBTFE)
#define CEC_RXXFERSIZE_INITIALIZE 0xFFFF /*!< Value used to initialise the RxXferSize of the handle */
/**
- * @}
- */
+ * @}
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
@@ -106,9 +113,9 @@
static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec);
static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec);
/**
- * @}
- */
-
+ * @}
+ */
+
/* Exported functions ---------------------------------------------------------*/
/** @defgroup CEC_Exported_Functions CEC Exported Functions
@@ -118,7 +125,7 @@
/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
@@ -142,7 +149,7 @@
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
{
/* Check the CEC handle allocation */
- if(hcec == NULL)
+ if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
{
return HAL_ERROR;
}
@@ -151,40 +158,42 @@
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(hcec->Init.TimingErrorFree));
assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(hcec->Init.PeriodErrorFree));
- assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress));
+ assert_param(IS_CEC_ADDRESS(hcec->Init.OwnAddress));
- if(hcec->State == HAL_CEC_STATE_RESET)
+ if(hcec->gState == HAL_CEC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcec->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK */
HAL_CEC_MspInit(hcec);
}
-
- hcec->State = HAL_CEC_STATE_BUSY;
+ hcec->gState = HAL_CEC_STATE_BUSY;
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
/* Write to CEC Control Register */
- MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, hcec->Init.TimingErrorFree|hcec->Init.PeriodErrorFree);
+ MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, hcec->Init.TimingErrorFree | hcec->Init.PeriodErrorFree);
/* Write to CEC Own Address Register */
- MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.InitiatorAddress);
+ MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.OwnAddress);
/* Configure the prescaler to generate the required 50 microseconds time base.*/
- MODIFY_REG(hcec->Instance->PRES, CEC_PRES_PRES, 50*(HAL_RCC_GetPCLK1Freq()/1000000)-1);
+ MODIFY_REG(hcec->Instance->PRES, CEC_PRES_PRES, 50U * (HAL_RCC_GetPCLK1Freq()/1000000U) - 1U);
- /* Enable the Peripheral */
- __HAL_CEC_ENABLE(hcec);
+ /* Enable the following CEC Interrupt */
+ __HAL_CEC_ENABLE_IT(hcec, CEC_IT_IE);
- hcec->State = HAL_CEC_STATE_READY;
+ /* Enable the CEC Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+ hcec->gState = HAL_CEC_STATE_READY;
+ hcec->RxState = HAL_CEC_STATE_READY;
return HAL_OK;
}
-
-
/**
* @brief DeInitializes the CEC peripheral
* @param hcec: CEC handle
@@ -201,26 +210,17 @@
/* Check the parameters */
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
- hcec->State = HAL_CEC_STATE_BUSY;
-
- /* Set peripheral to reset state */
- hcec->Instance->CFGR = 0x0;
- hcec->Instance->OAR = 0x0;
- hcec->Instance->PRES = 0x0;
- hcec->Instance->CFGR = 0x0;
- hcec->Instance->ESR = 0x0;
- hcec->Instance->CSR = 0x0;
- hcec->Instance->TXD = 0x0;
- hcec->Instance->RXD = 0x0;
-
- /* Disable the Peripheral */
- __HAL_CEC_DISABLE(hcec);
-
+ hcec->gState = HAL_CEC_STATE_BUSY;
+
/* DeInit the low level hardware */
HAL_CEC_MspDeInit(hcec);
+ __HAL_RCC_CEC_FORCE_RESET();
+ __HAL_RCC_CEC_RELEASE_RESET();
+
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
- hcec->State = HAL_CEC_STATE_RESET;
+ hcec->gState = HAL_CEC_STATE_RESET;
+ hcec->RxState = HAL_CEC_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(hcec);
@@ -229,6 +229,53 @@
}
/**
+ * @brief Initializes the Own Address of the CEC device
+ * @param hcec: CEC handle
+ * @param CEC_OwnAddress: The CEC own address.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
+{
+ /* Check the parameters */
+ assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
+
+ if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcec);
+
+ hcec->gState = HAL_CEC_STATE_BUSY;
+
+ /* Disable the Peripheral */
+ __HAL_CEC_DISABLE(hcec);
+
+ if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
+ {
+ MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.OwnAddress);
+ }
+ else
+ {
+ CLEAR_BIT(hcec->Instance->OAR, CEC_OAR_OA);
+ }
+
+ hcec->gState = HAL_CEC_STATE_READY;
+ hcec->ErrorCode = HAL_CEC_ERROR_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcec);
+
+ /* Enable the Peripheral */
+ __HAL_CEC_ENABLE(hcec);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
* @brief CEC MSP Init
* @param hcec: CEC handle
* @retval None
@@ -269,318 +316,36 @@
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the CEC data transfers.
-
- (#) There are two modes of transfer:
- (##) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (##) No-Blocking mode: The communication is performed using Interrupts.
+
+ (#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
+ logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
+
+ (#) The communication is performed using Interrupts.
These API's return the HAL status.
The end of the data processing will be indicated through the
dedicated CEC IRQ when using Interrupt mode.
The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
- will be executed respectivelly at the end of the Transmit or Receive process.
- The HAL_CEC_ErrorCallback()user callback will be executed when a communication
+ will be executed respectively at the end of the transmit or Receive process
+ The HAL_CEC_ErrorCallback() user callback will be executed when a communication
error is detected
- (#) Blocking mode API's are :
- (##) HAL_CEC_Transmit()
- (##) HAL_CEC_Receive()
- (#) Non-Blocking mode API's with Interrupt are :
- (##) HAL_CEC_Transmit_IT()
- (##) HAL_CEC_Receive_IT()
- (##) HAL_CEC_IRQHandler()
- (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
- (##) HAL_CEC_TxCpltCallback()
- (##) HAL_CEC_RxCpltCallback()
- (##) HAL_CEC_ErrorCallback()
+
+ (#) API's with Interrupt are :
+ (+) HAL_CEC_Transmit_IT()
+ (+) HAL_CEC_IRQHandler()
+
+ (#) A set of User Callbacks are provided:
+ (+) HAL_CEC_TxCpltCallback()
+ (+) HAL_CEC_RxCpltCallback()
+ (+) HAL_CEC_ErrorCallback()
@endverbatim
* @{
*/
/**
- * @brief Send data in blocking mode
- * @param hcec: CEC handle
- * @param DestinationAddress: destination logical address
- * @param pData: pointer to input byte data buffer
- * @param Size: amount of data to be sent in bytes (without counting the header).
- * 0 means only the header is sent (ping operation).
- * Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
- * @param Timeout: Timeout duration.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout)
-{
- uint8_t temp = 0;
- uint32_t tickstart = 0;
-
- /* If the IP is ready */
- if((hcec->State == HAL_CEC_STATE_READY)
- && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
- {
- /* Basic check on pData pointer */
- if(((pData == NULL) && (Size > 0)) || (! IS_CEC_MSGSIZE(Size)))
- {
- return HAL_ERROR;
- }
-
- assert_param(IS_CEC_ADDRESS(DestinationAddress));
-
- /* Process Locked */
- __HAL_LOCK(hcec);
-
- /* Enter the transmit mode */
- hcec->State = HAL_CEC_STATE_BUSY_TX;
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-
- /* Initialize the number of bytes to send,
- * 0 means only one header is sent (ping operation) */
- hcec->TxXferCount = Size;
-
- /* Send header block */
- temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress;
- hcec->Instance->TXD = temp;
-
- /* In case no data to be sent, sender is only pinging the system */
- if (Size != 0)
- {
- /* Set TX Start of Message (TXSOM) bit */
- hcec->Instance->CSR = CEC_FLAG_TSOM;
- }
- else
- {
- /* Send a ping command */
- hcec->Instance->CSR = CEC_FLAG_TEOM|CEC_FLAG_TSOM;
- }
-
- /* Polling TBTRF bit with timeout handling*/
- while (hcec->TxXferCount > 0)
- {
- /* Decreasing of the number of remaining data to receive */
- hcec->TxXferCount--;
-
- /* Timeout handling */
- tickstart = HAL_GetTick();
-
- /* Waiting for the next data transmission */
- while(HAL_IS_BIT_CLR(hcec->Instance->CSR, CEC_FLAG_TBTRF))
- {
- /* Timeout handling */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hcec->State = HAL_CEC_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hcec);
- return HAL_TIMEOUT;
- }
- }
-
- /* Check if an error occured */
- if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_TERR) || HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR))
- {
- /* Copy ESR for error handling purposes */
- hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR);
-
- /* Acknowledgement of the error */
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR);
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR);
-
- hcec->State = HAL_CEC_STATE_READY;
- __HAL_UNLOCK(hcec);
- return HAL_ERROR;
- }
- }
-
- /* Write the next data to TX buffer */
- hcec->Instance->TXD = *pData++;
-
- /* If this is the last byte of the ongoing transmission */
- if (hcec->TxXferCount == 0)
- {
- /* Acknowledge byte request and signal end of message */
- MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM);
- }
- else
- {
- /* Acknowledge byte request by writing 0x00 */
- MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00);
- }
- }
-
- /* Timeout handling */
- tickstart = HAL_GetTick();
-
- /* Wait for message transmission completion (TBTRF is set) */
- while (HAL_IS_BIT_CLR(hcec->Instance->CSR, CEC_FLAG_TBTRF))
- {
- /* Timeout handling */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hcec->State = HAL_CEC_STATE_READY;
- __HAL_UNLOCK(hcec);
- return HAL_TIMEOUT;
- }
- }
-
- /* Check of error during transmission of the last byte */
- if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_TERR) || HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR))
- {
- /* Copy ESR for error handling purposes */
- hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR);
-
- /* Acknowledgement of the error */
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR);
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR);
-
- hcec->State = HAL_CEC_STATE_READY;
- __HAL_UNLOCK(hcec);
- return HAL_ERROR;
- }
- }
-
- /* Check of error after the last byte transmission */
- if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_TERR) || HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR))
- {
- /* Copy ESR for error handling purposes */
- hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR);
-
- /* Acknowledgement of the error */
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR);
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR);
-
- hcec->State = HAL_CEC_STATE_READY;
- __HAL_UNLOCK(hcec);
- return HAL_ERROR;
- }
-
- /* Acknowledge successful completion by writing 0x00 */
- MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00);
-
- hcec->State = HAL_CEC_STATE_READY;
- __HAL_UNLOCK(hcec);
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-/**
- * @brief Receive data in blocking mode.
- * @param hcec: CEC handle
- * @param pData: pointer to received data buffer.
- * @param Timeout: Timeout duration.
- * @note The received data size is not known beforehand, the latter is known
- * when the reception is complete and is stored in hcec->RxXferSize.
- * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
- * If only a header is received, hcec->RxXferSize = 0
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout)
-{
- uint32_t temp = 0;
- uint32_t tickstart = 0;
-
- if(hcec->State == HAL_CEC_STATE_READY)
- {
- if(pData == NULL)
- {
- return HAL_ERROR;
- }
-
- /* When a ping is received, RxXferSize is 0*/
- /* When a message is received, RxXferSize contains the number of received bytes */
- hcec->RxXferSize = CEC_RXXFERSIZE_INITIALIZE;
-
- /* Process Locked */
- __HAL_LOCK(hcec);
-
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-
- /* Continue the reception until the End Of Message is received (CEC_FLAG_REOM) */
- do
- {
- /* Timeout handling */
- tickstart = HAL_GetTick();
-
- /* Wait for next byte to be received */
- while (HAL_IS_BIT_CLR(hcec->Instance->CSR, CEC_FLAG_RBTF))
- {
- /* Timeout handling */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
- {
- hcec->State = HAL_CEC_STATE_READY;
- __HAL_UNLOCK(hcec);
- return HAL_TIMEOUT;
- }
- }
-
- /* Check if an error occured during the reception */
- if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR))
- {
- /* Copy ESR for error handling purposes */
- hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR);
-
- /* Acknowledgement of the error */
- __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR);
-
- hcec->State = HAL_CEC_STATE_READY;
- __HAL_UNLOCK(hcec);
- return HAL_ERROR;
- }
- }
-
- /* Keep the value of CSR register as the register is cleared during reception process */
- temp = hcec->Instance->CSR;
-
- /* Read received data */
- *pData++ = hcec->Instance->RXD;
-
- /* Acknowledge received byte by writing 0x00 */
- CLEAR_BIT(hcec->Instance->CSR, CEC_FLAG_RECEIVE_MASK);
-
- /* Increment the number of received data */
- if(hcec->RxXferSize == CEC_RXXFERSIZE_INITIALIZE)
- {
- hcec->RxXferSize = 0;
- }
- else
- {
- hcec->RxXferSize++;
- }
-
- }while (HAL_IS_BIT_CLR(temp, CEC_FLAG_REOM));
-
- hcec->State = HAL_CEC_STATE_READY;
- __HAL_UNLOCK(hcec);
-
- if(IS_CEC_MSGSIZE(hcec->RxXferSize))
- {
- return HAL_OK;
- }
- else
- {
- return HAL_ERROR;
- }
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
-
-/**
* @brief Send data in interrupt mode
* @param hcec: CEC handle
+ * @param InitiatorAddress: Initiator address
* @param DestinationAddress: destination logical address
* @param pData: pointer to input byte data buffer
* @param Size: amount of data to be sent in bytes (without counting the header).
@@ -588,52 +353,33 @@
* Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
{
- uint8_t temp = 0;
- uint32_t tmp_state = 0;
-
- tmp_state = hcec->State;
- if(((tmp_state == HAL_CEC_STATE_READY) || (tmp_state == HAL_CEC_STATE_BUSY_RX))
- && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET))
- {
-
- /* Basic check on pData pointer */
- if(((pData == NULL) && (Size > 0)) || (! IS_CEC_MSGSIZE(Size)))
+ /* if the IP isn't already busy and if there is no previous transmission
+ already pending due to arbitration lost */
+ if(hcec->gState == HAL_CEC_STATE_READY)
+ {
+ if((pData == NULL ) && (Size > 0U))
{
return HAL_ERROR;
}
assert_param(IS_CEC_ADDRESS(DestinationAddress));
+ assert_param(IS_CEC_ADDRESS(InitiatorAddress));
+ assert_param(IS_CEC_MSGSIZE(Size));
/* Process Locked */
__HAL_LOCK(hcec);
hcec->pTxBuffPtr = pData;
-
- /* Check if a receive process is ongoing or not */
- if(hcec->State == HAL_CEC_STATE_BUSY_RX)
- {
- hcec->State = HAL_CEC_STATE_BUSY_TX_RX;
-
- /* Interrupt are not enabled here because they are already enabled in the Reception process */
- }
- else
- {
- hcec->State = HAL_CEC_STATE_BUSY_TX;
-
- /* Enable the CEC interrupt */
- __HAL_CEC_ENABLE_IT(hcec, CEC_IT_IE);
- }
-
+ hcec->gState = HAL_CEC_STATE_BUSY_TX;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-
+
/* initialize the number of bytes to send,
* 0 means only one header is sent (ping operation) */
hcec->TxXferCount = Size;
/* send header block */
- temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress;
- hcec->Instance->TXD = temp;
+ hcec->Instance->TXD = (uint8_t)((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress;
/* Process Unlocked */
__HAL_UNLOCK(hcec);
@@ -650,6 +396,7 @@
MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM|CEC_FLAG_TSOM);
}
return HAL_OK;
+
}
else
{
@@ -657,71 +404,27 @@
}
}
-
-/**
- * @brief Receive data in interrupt mode.
- * @param hcec: CEC handle
- * @param pData: pointer to received data buffer.
- * @note The received data size is not known beforehand, the latter is known
- * when the reception is complete and is stored in hcec->RxXferSize.
- * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max).
- * If only a header is received, hcec->RxXferSize = 0
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData)
-{
- uint32_t tmp_state = 0;
- tmp_state = hcec->State;
- if((tmp_state == HAL_CEC_STATE_READY) || (tmp_state == HAL_CEC_STATE_BUSY_TX))
- {
- if(pData == NULL)
- {
- return HAL_ERROR;
- }
-
- /* When a ping is received, RxXferSize is 0 */
- /* When a message is received, RxXferSize contains the number of received bytes */
- hcec->RxXferSize = CEC_RXXFERSIZE_INITIALIZE;
-
- /* Process Locked */
- __HAL_LOCK(hcec);
-
- hcec->pRxBuffPtr = pData;
- hcec->ErrorCode = HAL_CEC_ERROR_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcec);
-
- /* Check if a transmit process is ongoing or not */
- if(hcec->State == HAL_CEC_STATE_BUSY_TX)
- {
- hcec->State = HAL_CEC_STATE_BUSY_TX_RX;
- }
- else
- {
- hcec->State = HAL_CEC_STATE_BUSY_RX;
-
- /* Enable CEC interrupt */
- __HAL_CEC_ENABLE_IT(hcec, CEC_IT_IE);
- }
-
- return HAL_OK;
- }
- else
- {
- return HAL_BUSY;
- }
-}
-
/**
* @brief Get size of the received frame.
* @param hcec: CEC handle
* @retval Frame size
*/
-uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec)
+uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
{
return hcec->RxXferSize;
}
+
+/**
+ * @brief Change Rx Buffer.
+ * @param hcec: CEC handle
+ * @param Rxbuffer: Rx Buffer
+ * @note This function can be called only inside the HAL_CEC_RxCpltCallback()
+ * @retval Frame size
+ */
+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
+{
+ hcec->Init.RxBuffer = Rxbuffer;
+}
/**
* @brief This function handles CEC interrupt requests.
@@ -734,63 +437,44 @@
hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR);
/* Transmit error */
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TERR) != RESET))
+ if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TERR) != RESET)
{
/* Acknowledgement of the error */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR);
- /* Check if a receive process is ongoing or not */
- if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX)
- {
- /* Interrupts are not disabled due to reception still ongoing */
-
- hcec->State = HAL_CEC_STATE_BUSY_RX;
- }
- else
- {
- /* Disable the CEC Transmission Interrupts */
- __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE);
-
- hcec->State = HAL_CEC_STATE_READY;
- }
+ hcec->gState = HAL_CEC_STATE_READY;
}
/* Receive error */
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RERR) != RESET))
+ if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RERR) != RESET)
{
/* Acknowledgement of the error */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR);
-
- /* Check if a transmit process is ongoing or not */
- if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX)
- {
- /* Interrupts are not disabled due to reception still ongoing */
-
- hcec->State = HAL_CEC_STATE_BUSY_TX;
- }
- else
- {
- /* Disable the CEC Transmission Interrupts */
- __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE);
-
- hcec->State = HAL_CEC_STATE_READY;
- }
- }
+ hcec->Init.RxBuffer-=hcec->RxXferSize;
+ hcec->RxXferSize = 0U;
+ hcec->RxState = HAL_CEC_STATE_READY;
+ }
- if ((hcec->ErrorCode & CEC_ESR_ALL_ERROR) != 0)
+ if((hcec->ErrorCode & CEC_ESR_ALL_ERROR) != 0U)
{
+ /* Error Call Back */
HAL_CEC_ErrorCallback(hcec);
}
/* Transmit byte request or block transfer finished */
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TBTRF) != RESET))
+ if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TBTRF) != RESET)
{
CEC_Transmit_IT(hcec);
- }
+ }
/* Receive byte or block transfer finished */
- if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RBTF) != RESET))
+ if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RBTF) != RESET)
{
+ if(hcec->RxXferSize == 0U)
+ {
+ /* reception is starting */
+ hcec->RxState = HAL_CEC_STATE_BUSY_RX;
+ }
CEC_Receive_IT(hcec);
}
}
@@ -813,12 +497,14 @@
/**
* @brief Rx Transfer completed callback
* @param hcec: CEC handle
+ * @param RxFrameSize: Size of frame
* @retval None
*/
-__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec)
+__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
+ UNUSED(RxFrameSize);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_RxCpltCallback can be implemented in the user file
*/
@@ -837,7 +523,6 @@
the HAL_CEC_ErrorCallback can be implemented in the user file
*/
}
-
/**
* @}
*/
@@ -847,24 +532,28 @@
*
@verbatim
===============================================================================
- ##### Peripheral Control functions #####
+ ##### Peripheral Control function #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the CEC.
(+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
- (+) HAL_CEC_GetError() API can be helpful to get the error code of a failed transmission or reception.
+ (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
@endverbatim
* @{
*/
-
/**
* @brief return the CEC state
- * @param hcec: CEC handle
+ * @param hcec: pointer to a CEC_HandleTypeDef structure that contains
+ * the configuration information for the specified CEC module.
* @retval HAL state
*/
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
{
- return hcec->State;
+ uint32_t temp1= 0x00U, temp2 = 0x00U;
+ temp1 = hcec->gState;
+ temp2 = hcec->RxState;
+
+ return (HAL_CEC_StateTypeDef)(temp1 | temp2);
}
/**
@@ -899,34 +588,17 @@
*/
static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec)
{
- uint32_t tmp_state = 0;
-
- tmp_state = hcec->State;
/* if the IP is already busy or if there is a previous transmission
already pending due to arbitration loss */
- if(((tmp_state == HAL_CEC_STATE_BUSY_TX) || (tmp_state == HAL_CEC_STATE_BUSY_TX_RX))
- || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
+ if((hcec->gState == HAL_CEC_STATE_BUSY_TX) || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET))
{
/* if all data have been sent */
- if(hcec->TxXferCount == 0)
+ if(hcec->TxXferCount == 0U)
{
/* Acknowledge successful completion by writing 0x00 */
- MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00);
+ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00U);
- /* Check if a receive process is ongoing or not */
- if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX)
- {
- /* Interrupts are not disabled due to reception still ongoing */
-
- hcec->State = HAL_CEC_STATE_BUSY_RX;
- }
- else
- {
- /* Disable the CEC Transmission Interrupts */
- __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE);
-
- hcec->State = HAL_CEC_STATE_READY;
- }
+ hcec->gState = HAL_CEC_STATE_READY;
HAL_CEC_TxCpltCallback(hcec);
@@ -941,7 +613,7 @@
hcec->Instance->TXD = *hcec->pTxBuffPtr++;
/* If this is the last byte of the ongoing transmission */
- if (hcec->TxXferCount == 0)
+ if(hcec->TxXferCount == 0U)
{
/* Acknowledge byte request and signal end of message */
MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM);
@@ -949,7 +621,7 @@
else
{
/* Acknowledge byte request by writing 0x00 */
- MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00);
+ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00U);
}
return HAL_OK;
@@ -971,50 +643,28 @@
static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec)
{
static uint32_t temp;
- uint32_t tmp_state = 0;
-
- tmp_state = hcec->State;
- if((tmp_state == HAL_CEC_STATE_BUSY_RX) || (tmp_state == HAL_CEC_STATE_BUSY_TX_RX))
+
+ if(hcec->RxState == HAL_CEC_STATE_BUSY_RX)
{
temp = hcec->Instance->CSR;
/* Store received data */
- *hcec->pRxBuffPtr++ = hcec->Instance->RXD;
+ hcec->RxXferSize++;
+ *hcec->Init.RxBuffer++ = hcec->Instance->RXD;
/* Acknowledge received byte by writing 0x00 */
- MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_RECEIVE_MASK, 0x00);
-
- /* Increment the number of received data */
- if(hcec->RxXferSize == CEC_RXXFERSIZE_INITIALIZE)
- {
- hcec->RxXferSize = 0;
- }
- else
- {
- hcec->RxXferSize++;
- }
+ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_RECEIVE_MASK, 0x00U);
/* If the End Of Message is reached */
if(HAL_IS_BIT_SET(temp, CEC_FLAG_REOM))
{
- if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX)
- {
- /* Interrupts are not disabled due to transmission still ongoing */
-
- hcec->State = HAL_CEC_STATE_BUSY_TX;
- }
- else
- {
- /* Disable the CEC Transmission Interrupts */
- __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE);
-
- hcec->State = HAL_CEC_STATE_READY;
- }
-
- HAL_CEC_RxCpltCallback(hcec);
-
+ /* Interrupts are not disabled due to transmission still ongoing */
+ hcec->RxState = HAL_CEC_STATE_READY;
+
+ HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
+
return HAL_OK;
- }
+ }
else
{
return HAL_BUSY;
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cortex.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cortex.c
index 8f0ddcf..ed6d1b4 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cortex.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_cortex.c
@@ -2,81 +2,59 @@
******************************************************************************
* @file stm32f1xx_hal_cortex.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief CORTEX HAL module driver.
- *
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the CORTEX:
* + Initialization and de-initialization functions
- * + Peripheral Control functions
- *
- * @verbatim
+ * + Peripheral Control functions
+ *
+ @verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
- *** How to configure Interrupts using Cortex HAL driver ***
+ *** How to configure Interrupts using CORTEX HAL driver ***
===========================================================
[..]
- This section provide functions allowing to configure the NVIC interrupts (IRQ).
+ This section provides functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M3 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
function according to the following table.
-
- The table below gives the allowed values of the pre-emption priority and subpriority according
- to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
- ==========================================================================================================================
- NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
- ==========================================================================================================================
- NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
- | | | 4 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
- | | | 3 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
- | | | 2 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
- | | | 1 bits for subpriority
- --------------------------------------------------------------------------------------------------------------------------
- NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
- | | | 0 bits for subpriority
- ==========================================================================================================================
- (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
-
- (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
+ (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+ (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+ (#) please refer to programming manual for details in how to configure priority.
-
- -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
+ -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority):
- (+@) Lowest pre-emption priority
+ (+@) Lowest preemption priority
(+@) Lowest sub priority
(+@) Lowest hardware priority (IRQ number)
[..]
- *** How to configure Systick using Cortex HAL driver ***
+ *** How to configure Systick using CORTEX HAL driver ***
========================================================
[..]
- Setup SysTick Timer for 1 msec interrupts.
+ Setup SysTick Timer for time base.
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
- (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+ (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
(++) Starts the SysTick Counter.
- (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function
- HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
- HAL_SYSTICK_Config() function call.
+ (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+ __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+ HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+ inside the stm32f1xx_hal_cortex.h file.
(+) You can change the SysTick IRQ priority by calling the
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
@@ -92,7 +70,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -133,12 +111,12 @@
#ifdef HAL_CORTEX_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
@@ -146,14 +124,14 @@
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..]
- This section provide the Cortex HAL driver functions allowing to configure Interrupts
+ This section provides the CORTEX HAL driver functions allowing to configure Interrupts
Systick functionalities
@endverbatim
@@ -162,21 +140,21 @@
/**
- * @brief Sets the priority grouping field (pre-emption priority and subpriority)
+ * @brief Sets the priority grouping field (preemption priority and subpriority)
* using the required unlock sequence.
* @param PriorityGroup: The priority grouping bits length.
* This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority
- * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
+ * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
@@ -191,10 +169,10 @@
/**
* @brief Sets the priority of an interrupt.
- * @param IRQn: External interrupt number
+ * @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
- * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
- * @param PreemptPriority: The pre-emption priority for the IRQn channel.
+ * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h))
+ * @param PreemptPriority: The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority
* @param SubPriority: the subpriority level for the IRQ channel.
@@ -203,8 +181,8 @@
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t prioritygroup = 0x00;
+{
+ uint32_t prioritygroup = 0x00U;
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
@@ -219,7 +197,7 @@
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
- * @param IRQn External interrupt number
+ * @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
@@ -235,7 +213,7 @@
/**
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
- * @param IRQn External interrupt number
+ * @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
@@ -245,7 +223,6 @@
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
@@ -276,8 +253,8 @@
*/
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
- * @brief Cortex control functions
- *
+ * @brief Cortex control functions
+ *
@verbatim
==============================================================================
##### Peripheral Control functions #####
@@ -291,7 +268,47 @@
* @{
*/
-#if (__MPU_PRESENT == 1)
+#if (__MPU_PRESENT == 1U)
+/**
+ * @brief Disables the MPU
+ * @retval None
+ */
+void HAL_MPU_Disable(void)
+{
+ /* Make sure outstanding transfers are done */
+ __DMB();
+
+ /* Disable fault exceptions */
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Disable the MPU and clear the control register*/
+ MPU->CTRL = 0U;
+}
+
+/**
+ * @brief Enable the MPU.
+ * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
+ * NMI, FAULTMASK and privileged access to the default memory
+ * This parameter can be one of the following values:
+ * @arg MPU_HFNMI_PRIVDEF_NONE
+ * @arg MPU_HARDFAULT_NMI
+ * @arg MPU_PRIVILEGED_DEFAULT
+ * @arg MPU_HFNMI_PRIVDEF
+ * @retval None
+ */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+ /* Enable the MPU */
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+
+ /* Enable fault exceptions */
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+
+ /* Ensure MPU setting take effects */
+ __DSB();
+ __ISB();
+}
+
/**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
@@ -332,8 +349,8 @@
}
else
{
- MPU->RBAR = 0x00;
- MPU->RASR = 0x00;
+ MPU->RBAR = 0x00U;
+ MPU->RASR = 0x00U;
}
}
#endif /* __MPU_PRESENT */
@@ -350,26 +367,26 @@
/**
* @brief Gets the priority of an interrupt.
- * @param IRQn: External interrupt number
+ * @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @param PriorityGroup: the priority grouping bits length.
* This parameter can be one of the following values:
- * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority
- * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
+ * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority
* @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
* @param pSubPriority: Pointer on the Subpriority value (starting from 0).
* @retval None
*/
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
@@ -385,35 +402,44 @@
* @retval None
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
/**
- * @brief Gets Pending Interrupt (reads the pending register in the NVIC
+ * @brief Gets Pending Interrupt (reads the pending register in the NVIC
* and returns the pending bit for the specified interrupt).
- * @param IRQn External interrupt number
+ * @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
/**
- * @brief Clears the pending bit of an external interrupt.
- * @param IRQn External interrupt number
+ * @brief Clears the pending bit of an external interrupt.
+ * @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
@@ -427,7 +453,10 @@
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
-{
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_crc.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_crc.c
index f543335..b69e9ee 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_crc.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_crc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_crc.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@@ -162,6 +162,9 @@
/* Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF */
__HAL_CRC_DR_RESET(hcrc);
+ /* Reset IDR register content */
+ CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
+
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_RESET;
@@ -234,7 +237,7 @@
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
- uint32_t index = 0;
+ uint32_t index = 0U;
/* Process Locked */
__HAL_LOCK(hcrc);
@@ -243,7 +246,7 @@
hcrc->State = HAL_CRC_STATE_BUSY;
/* Enter Data to the CRC calculator */
- for(index = 0; index < BufferLength; index++)
+ for(index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
@@ -269,7 +272,7 @@
*/
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
- uint32_t index = 0;
+ uint32_t index = 0U;
/* Process Locked */
__HAL_LOCK(hcrc);
@@ -281,7 +284,7 @@
__HAL_CRC_DR_RESET(hcrc);
/* Enter Data to the CRC calculator */
- for(index = 0; index < BufferLength; index++)
+ for(index = 0U; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac.c
index 74759e9..24e66a0 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_dac.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@@ -471,7 +471,7 @@
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
- * @param pData: The destination peripheral Buffer address.
+ * @param pData: The Source memory Buffer address.
* @param Length: The length of data to be transferred from memory to DAC peripheral
* @param Alignment: Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
@@ -482,7 +482,7 @@
*/
__weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -740,7 +740,7 @@
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
{
- uint32_t tmpreg1 = 0;
+ uint32_t tmpreg1 = 0U;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
@@ -795,7 +795,7 @@
*/
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
{
- __IO uint32_t tmp = 0;
+ __IO uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac_ex.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac_ex.c
index 1ff1f82..0fc7781 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac_ex.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dac_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_dac_ex.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:
@@ -106,11 +106,11 @@
*/
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
{
- uint32_t tmp = 0;
+ uint32_t tmp = 0U;
tmp |= hdac->Instance->DOR1;
- tmp |= hdac->Instance->DOR2 << 16;
+ tmp |= hdac->Instance->DOR2 << 16U;
/* Returns the DAC channel data output register value */
return tmp;
@@ -229,7 +229,7 @@
*/
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
{
- uint32_t data = 0, tmp = 0;
+ uint32_t data = 0U, tmp = 0U;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(Alignment));
@@ -239,11 +239,11 @@
/* Calculate and set dual DAC data holding register value */
if (Alignment == DAC_ALIGN_8B_R)
{
- data = ((uint32_t)Data2 << 8) | Data1;
+ data = ((uint32_t)Data2 << 8U) | Data1;
}
else
{
- data = ((uint32_t)Data2 << 16) | Data1;
+ data = ((uint32_t)Data2 << 16U) | Data1;
}
tmp = (uint32_t)hdac->Instance;
@@ -366,7 +366,7 @@
*/
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dma.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dma.c
index 8906c5d..74c8945 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dma.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_dma.c
@@ -2,28 +2,27 @@
******************************************************************************
* @file stm32f1xx_hal_dma.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief DMA HAL module driver.
- *
- * This file provides firmware functions to manage the following
- * functionalities of the Direct Memory Access (DMA) peripheral:
+ * This file provides firmware functions to manage the following
+ * functionalities of the Direct Memory Access (DMA) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and errors functions
- @verbatim
- ==============================================================================
+ @verbatim
+ ==============================================================================
##### How to use this driver #####
- ==============================================================================
+ ==============================================================================
[..]
(#) Enable and configure the peripheral to be connected to the DMA Channel
(except for internal SRAM / FLASH memories: no initialization is
- necessary) please refer to Reference manual for connection between peripherals
+ necessary). Please refer to the Reference manual for connection between peripherals
and DMA requests.
- (#) For a given Channel, program the required configuration through the following parameters:
- Transfer Direction, Source and Destination data formats,
- Circular or Normal mode, Channel Priority level, Source and Destination Increment mode,
+ (#) For a given Channel, program the required configuration through the following parameters:
+ Channel request, Transfer Direction, Source and Destination data formats,
+ Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
using HAL_DMA_Init() function.
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
@@ -33,29 +32,29 @@
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
*** Polling mode IO operation ***
- =================================
- [..]
- (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
- address and destination address and the Length of data to be transferred
- (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
- case a fixed Timeout can be configured by User depending from his application.
-
- *** Interrupt mode IO operation ***
- ===================================
+ =================================
[..]
- (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
- (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
- (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
- Source address and destination address and the Length of data to be transferred.
- In this case the DMA interrupt is configured
- (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
- (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
- add his own function by customization of function pointer XferCpltCallback and
- XferErrorCallback (i.e a member of DMA handle structure).
+ (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+ address and destination address and the Length of data to be transferred
+ (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+ case a fixed Timeout can be configured by User depending from his application.
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+ Source address and destination address and the Length of data to be transferred.
+ In this case the DMA interrupt is configured
+ (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+ (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+ add his own function by customization of function pointer XferCpltCallback and
+ XferErrorCallback (i.e. a member of DMA handle structure).
*** DMA HAL driver macros list ***
=============================================
- [..]
+ [..]
Below the list of most used macros in DMA HAL driver.
(+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
@@ -73,7 +72,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -98,7 +97,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
@@ -116,14 +115,6 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Constants DMA Private Constants
- * @{
- */
-#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */
-/**
- * @}
- */
-
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -142,12 +133,12 @@
*/
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and de-initialization functions
- *
-@verbatim
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
- ===============================================================================
+ ===============================================================================
[..]
This section provides functions allowing to initialize the DMA Channel source
and destination addresses, incrementation and data sizes, transfer direction,
@@ -159,24 +150,24 @@
@endverbatim
* @{
*/
-
+
/**
- * @brief Initializes the DMA according to the specified
- * parameters in the DMA_InitTypeDef and create the associated handle.
+ * @brief Initialize the DMA according to the specified
+ * parameters in the DMA_InitTypeDef and initialize the associated handle.
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
- uint32_t tmp = 0;
-
+{
+ uint32_t tmp = 0U;
+
/* Check the DMA handle allocation */
if(hdma == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
@@ -186,24 +177,38 @@
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
assert_param(IS_DMA_MODE(hdma->Init.Mode));
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-
- if(hdma->State == HAL_DMA_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hdma->Lock = HAL_UNLOCKED;
+
+#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
+ /* calculation of the channel index */
+ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
+ {
+ /* DMA1 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
+ hdma->DmaBaseAddress = DMA1;
}
-
+ else
+ {
+ /* DMA2 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
+ hdma->DmaBaseAddress = DMA2;
+ }
+#else
+ /* DMA1 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
+ hdma->DmaBaseAddress = DMA1;
+#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */
+
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Get the CR register value */
tmp = hdma->Instance->CCR;
-
- /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
+
+ /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
DMA_CCR_DIR));
-
+
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction |
hdma->Init.PeriphInc | hdma->Init.MemInc |
@@ -211,21 +216,30 @@
hdma->Init.Mode | hdma->Init.Priority;
/* Write to DMA Channel CR register */
- hdma->Instance->CCR = tmp;
-
+ hdma->Instance->CCR = tmp;
+
+
+ /* Clean callbacks */
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+
/* Initialise the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
+ /* Allocate lock resource and initialize it */
+ hdma->Lock = HAL_UNLOCKED;
return HAL_OK;
}
/**
- * @brief DeInitializes the DMA peripheral
+ * @brief DeInitialize the DMA peripheral.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
@@ -235,36 +249,48 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
- /* Check the DMA peripheral state */
- if(hdma->State == HAL_DMA_STATE_BUSY)
- {
- return HAL_ERROR;
- }
-
/* Disable the selected DMA Channelx */
__HAL_DMA_DISABLE(hdma);
-
+
/* Reset DMA Channel control register */
- hdma->Instance->CCR = 0;
-
+ hdma->Instance->CCR = 0U;
+
/* Reset DMA Channel Number of Data to Transfer register */
- hdma->Instance->CNDTR = 0;
-
+ hdma->Instance->CNDTR = 0U;
+
/* Reset DMA Channel peripheral address register */
- hdma->Instance->CPAR = 0;
-
+ hdma->Instance->CPAR = 0U;
+
/* Reset DMA Channel memory address register */
- hdma->Instance->CMAR = 0;
+ hdma->Instance->CMAR = 0U;
+
+#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
+ /* calculation of the channel index */
+ if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
+ {
+ /* DMA1 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
+ hdma->DmaBaseAddress = DMA1;
+ }
+ else
+ {
+ /* DMA2 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
+ hdma->DmaBaseAddress = DMA2;
+ }
+#else
+ /* DMA1 */
+ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
+ hdma->DmaBaseAddress = DMA1;
+#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */
/* Clear all flags */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex));
+
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
@@ -281,29 +307,29 @@
* @}
*/
-/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
- * @brief I/O operation functions
- *
-@verbatim
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ * @brief Input and Output operation functions
+ *
+@verbatim
===============================================================================
##### IO operation functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
(+) Configure the source, destination address and data length and Start DMA transfer
- (+) Configure the source, destination address and data length and
+ (+) Configure the source, destination address and data length and
Start DMA transfer with interrupt
(+) Abort DMA transfer
(+) Poll for transfer complete
- (+) Handle DMA interrupt request
+ (+) Handle DMA interrupt request
@endverbatim
* @{
*/
/**
- * @brief Starts the DMA Transfer.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * @brief Start the DMA Transfer.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
@@ -311,31 +337,42 @@
*/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
/* Process locked */
__HAL_LOCK(hdma);
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
-
- /* Configure the source, destination address and the data length */
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
-
- return HAL_OK;
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length & clear flags*/
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+ status = HAL_BUSY;
+ }
+ return status;
}
/**
* @brief Start the DMA Transfer with interrupt enabled.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
@@ -343,97 +380,150 @@
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
/* Process locked */
__HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ /* Change DMA peripheral state */
+ hdma->State = HAL_DMA_STATE_BUSY;
+ hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Disable the peripheral */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Configure the source, destination address and the data length & clear flags*/
+ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+ /* Enable the transfer complete interrupt */
+ /* Enable the transfer Error interrupt */
+ if(NULL != hdma->XferHalfCpltCallback)
+ {
+ /* Enable the Half transfer complete interrupt as well */
+ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ }
+ else
+ {
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
+ }
+ /* Enable the Peripheral */
+ __HAL_DMA_ENABLE(hdma);
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_BUSY;
-
- /* Check the parameters */
- assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
- /* Disable the peripheral */
- __HAL_DMA_DISABLE(hdma);
-
- /* Configure the source, destination address and the data length */
- DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
- /* Enable the transfer complete interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
-
- /* Enable the Half transfer complete interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
-
- /* Enable the transfer Error interrupt */
- __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
-
- /* Enable the Peripheral */
- __HAL_DMA_ENABLE(hdma);
-
- return HAL_OK;
-}
+ /* Remain BUSY */
+ status = HAL_BUSY;
+ }
+ return status;
+}
/**
- * @brief Aborts the DMA Transfer.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- *
- * @note After disabling a DMA Channel, a check for wait until the DMA Channel is
- * effectively disabled is added. If a Channel is disabled
- * while a data transfer is ongoing, the current data will be transferred
- * and the Channel will be effectively disabled only after the transfer of
- * this single data is finished.
+ * @brief Abort the DMA Transfer.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
- uint32_t tickstart = 0x00;
-
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Disable DMA IT */
+ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
/* Disable the channel */
__HAL_DMA_DISABLE(hdma);
+
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check if the DMA Channel is effectively disabled */
- while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
- {
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
- {
- /* Update error code */
- SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_TIMEOUT;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- return HAL_TIMEOUT;
- }
- }
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
-
+
/* Process Unlocked */
- __HAL_UNLOCK(hdma);
+ __HAL_UNLOCK(hdma);
- return HAL_OK;
+ return status;
+}
+
+/**
+ * @brief Aborts the DMA Transfer in Interrupt mode.
+ * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(HAL_DMA_STATE_BUSY != hdma->State)
+ {
+ /* no transfer ongoing */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Disable DMA IT */
+ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+ /* Disable the channel */
+ __HAL_DMA_DISABLE(hdma);
+
+ /* Clear all flags */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ /* Call User Abort callback */
+ if(hdma->XferAbortCallback != NULL)
+ {
+ hdma->XferAbortCallback(hdma);
+ }
+ }
+ return status;
}
/**
* @brief Polling for transfer complete.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
- * @param CompleteLevel: Specifies the DMA level complete.
+ * @param CompleteLevel: Specifies the DMA level complete.
* @param Timeout: Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
{
uint32_t temp;
- uint32_t tickstart = 0x00;
+ uint32_t tickstart = 0U;
+
+ if(HAL_DMA_STATE_BUSY != hdma->State)
+ {
+ /* no transfer ongoing */
+ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ __HAL_UNLOCK(hdma);
+ return HAL_ERROR;
+ }
+
+ /* Polling mode not supported in circular mode */
+ if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
+ {
+ hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+ return HAL_ERROR;
+ }
/* Get the level transfer complete flag */
if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
@@ -453,36 +543,38 @@
while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
{
if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
- {
- /* Clear the transfer error flags */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
-
+ {
+ /* When a DMA transfer error occurs */
+ /* A hardware clear of its EN bits is performed */
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+
/* Update error code */
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
/* Change the DMA state */
- hdma->State= HAL_DMA_STATE_ERROR;
-
+ hdma->State= HAL_DMA_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hdma);
-
+
return HAL_ERROR;
}
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Update error code */
SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
-
+
/* Change the DMA state */
- hdma->State = HAL_DMA_STATE_TIMEOUT;
+ hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
-
- return HAL_TIMEOUT;
+
+ return HAL_ERROR;
}
}
}
@@ -492,19 +584,14 @@
/* Clear the transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
- /* The selected Channelx EN bit is cleared (DMA is disabled and
+ /* The selected Channelx EN bit is cleared (DMA is disabled and
all transfers are complete) */
hdma->State = HAL_DMA_STATE_READY;
-
}
else
- {
+ {
/* Clear the half transfer complete flag */
__HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
- /* The selected Channelx EN bit is cleared (DMA is disabled and
- all transfers of half buffer are complete) */
- hdma->State = HAL_DMA_STATE_READY_HALF;
}
/* Process unlocked */
@@ -521,101 +608,206 @@
*/
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
- /* Transfer Error Interrupt management ***************************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
- {
- if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
- {
- /* Disable the transfer error interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
-
- /* Clear the transfer error flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
-
- /* Update error code */
- SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
-
- /* Change the DMA state */
- hdma->State = HAL_DMA_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if (hdma->XferErrorCallback != NULL)
- {
- /* Transfer error callback */
- hdma->XferErrorCallback(hdma);
- }
- }
- }
-
- /* Half Transfer Complete Interrupt management ******************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
- {
- if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
- {
- /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
- {
- /* Disable the half transfer interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
- }
- /* Clear the half transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
- /* Change DMA peripheral state */
- hdma->State = HAL_DMA_STATE_READY_HALF;
-
- if(hdma->XferHalfCpltCallback != NULL)
- {
- /* Half transfer callback */
- hdma->XferHalfCpltCallback(hdma);
- }
- }
- }
+ uint32_t flag_it = hdma->DmaBaseAddress->ISR;
+ uint32_t source_it = hdma->Instance->CCR;
- /* Transfer Complete Interrupt management ***********************************/
- if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
+ /* Half Transfer Complete Interrupt management ******************************/
+ if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET))
{
- if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
+ /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
- if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
- {
- /* Disable the transfer complete interrupt */
- __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
- }
- /* Clear the transfer complete flag */
- __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-
- /* Update error code */
- SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE);
+ /* Disable the half transfer interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ }
+ /* Clear the half transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+ /* DMA peripheral state is not updated in Half Transfer */
+ /* but in Transfer Complete case */
+
+ if(hdma->XferHalfCpltCallback != NULL)
+ {
+ /* Half transfer callback */
+ hdma->XferHalfCpltCallback(hdma);
+ }
+ }
+
+ /* Transfer Complete Interrupt management ***********************************/
+ else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET))
+ {
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ {
+ /* Disable the transfer complete and error interrupt */
+ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hdma);
-
- if(hdma->XferCpltCallback != NULL)
- {
- /* Transfer complete callback */
- hdma->XferCpltCallback(hdma);
- }
+ }
+ /* Clear the transfer complete flag */
+ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if(hdma->XferCpltCallback != NULL)
+ {
+ /* Transfer complete callback */
+ hdma->XferCpltCallback(hdma);
}
}
+
+ /* Transfer Error Interrupt management **************************************/
+ else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
+ {
+ /* When a DMA transfer error occurs */
+ /* A hardware clear of its EN bits is performed */
+ /* Disable ALL DMA IT */
+ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+
+ /* Update error code */
+ hdma->ErrorCode = HAL_DMA_ERROR_TE;
+
+ /* Change the DMA state */
+ hdma->State = HAL_DMA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdma);
+
+ if (hdma->XferErrorCallback != NULL)
+ {
+ /* Transfer error callback */
+ hdma->XferErrorCallback(hdma);
+ }
+ }
+ return;
}
/**
+ * @brief Register callbacks
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param CallbackID: User Callback identifer
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ * @param pCallback: pointer to private callbacsk function which has pointer to
+ * a DMA_HandleTypeDef structure as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = pCallback;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = pCallback;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister callbacks
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @param CallbackID: User Callback identifer
+ * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hdma);
+
+ if(HAL_DMA_STATE_READY == hdma->State)
+ {
+ switch (CallbackID)
+ {
+ case HAL_DMA_XFER_CPLT_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_HALFCPLT_CB_ID:
+ hdma->XferHalfCpltCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ERROR_CB_ID:
+ hdma->XferErrorCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ABORT_CB_ID:
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ case HAL_DMA_XFER_ALL_CB_ID:
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
+ break;
+
+ default:
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hdma);
+
+ return status;
+}
+
+/**
* @}
*/
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
+ *
+@verbatim
===============================================================================
- ##### State and Errors functions #####
- ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
[..]
This subsection provides functions allowing to
(+) Check the DMA state
@@ -626,18 +818,19 @@
*/
/**
- * @brief Returns the DMA state.
+ * @brief Return the DMA hande state.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @retval HAL state
*/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
{
+ /* Return DMA handle state */
return hdma->State;
}
/**
- * @brief Return the DMA error code
+ * @brief Return the DMA error code.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval DMA Error Code
@@ -655,14 +848,14 @@
* @}
*/
-/** @addtogroup DMA_Private_Functions DMA Private Functions
+/** @addtogroup DMA_Private_Functions
* @{
*/
/**
* @brief Sets the DMA Transfer parameter.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
+ * the configuration information for the specified DMA Channel.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
@@ -670,15 +863,18 @@
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
+ /* Clear all flags */
+ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
+
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
-
+
/* Peripheral to Memory */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
-
+
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
}
@@ -687,7 +883,7 @@
{
/* Configure DMA Channel source address */
hdma->Instance->CPAR = SrcAddress;
-
+
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_eth.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_eth.c
index b1b7953..2e94314 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_eth.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_eth.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_eth.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief ETH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Ethernet (ETH) peripheral:
@@ -118,13 +118,13 @@
/** @defgroup ETH_Private_Constants ETH Private Constants
* @{
*/
-#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
-#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
+#define ETH_TIMEOUT_SWRESET 500U
+#define ETH_TIMEOUT_LINKED_STATE 5000U
+#define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U
/**
* @}
*/
-
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -142,6 +142,7 @@
static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
+static void ETH_Delay(uint32_t mdelay);
/**
* @}
@@ -176,9 +177,9 @@
*/
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
{
- uint32_t tmpreg = 0, phyreg = 0;
- uint32_t hclk = 60000000;
- uint32_t tickstart = 0;
+ uint32_t tmpreg1 = 0U, phyreg = 0U;
+ uint32_t hclk = 60000000U;
+ uint32_t tickstart = 0U;
uint32_t err = ETH_SUCCESS;
/* Check the ETH peripheral state */
@@ -197,7 +198,6 @@
{
/* Allocate lock resource and initialize it */
heth->Lock = HAL_UNLOCKED;
-
/* Init the low level hardware : GPIO, CLOCK, NVIC. */
HAL_ETH_MspInit(heth);
}
@@ -211,39 +211,54 @@
/* After reset all the registers holds their respective reset values */
(heth->Instance)->DMABMR |= ETH_DMABMR_SR;
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Wait for software reset */
while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
{
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
+ {
+ heth->State= HAL_ETH_STATE_TIMEOUT;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(heth);
+
+ /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
+ not available, please check your external PHY or the IO configuration */
+ return HAL_TIMEOUT;
+ }
}
/*-------------------------------- MAC Initialization ----------------------*/
/* Get the ETHERNET MACMIIAR value */
- tmpreg = (heth->Instance)->MACMIIAR;
+ tmpreg1 = (heth->Instance)->MACMIIAR;
/* Clear CSR Clock Range CR[2:0] bits */
- tmpreg &= ETH_MACMIIAR_CR_MASK;
+ tmpreg1 &= ETH_MACMIIAR_CR_MASK;
/* Get hclk frequency value */
hclk = HAL_RCC_GetHCLKFreq();
/* Set CR bits depending on hclk value */
- if((hclk >= 20000000)&&(hclk < 35000000))
+ if((hclk >= 20000000U)&&(hclk < 35000000U))
{
/* CSR Clock Range between 20-35 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_DIV16;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV16;
}
- else if((hclk >= 35000000)&&(hclk < 60000000))
+ else if((hclk >= 35000000U)&&(hclk < 60000000U))
{
/* CSR Clock Range between 35-60 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_DIV26;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV26;
}
else
{
/* CSR Clock Range between 60-72 MHz */
- tmpreg |= (uint32_t)ETH_MACMIIAR_CR_DIV42;
+ tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV42;
}
/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
- (heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
+ (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
/*-------------------- PHY initialization and configuration ----------------*/
/* Put the PHY in reset mode */
@@ -276,7 +291,7 @@
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
+ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
{
/* In case of write timeout */
err = ETH_ERROR;
@@ -319,7 +334,7 @@
HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
/* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
+ if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
{
/* In case of write timeout */
err = ETH_ERROR;
@@ -383,8 +398,8 @@
assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
/* Set MAC Speed and Duplex Mode */
- if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
- (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
+ if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) |
+ (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK)
{
/* In case of write timeout */
err = ETH_ERROR;
@@ -448,7 +463,7 @@
*/
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
{
- uint32_t i = 0;
+ uint32_t i = 0U;
ETH_DMADescTypeDef *dmatxdesc;
/* Process Locked */
@@ -461,7 +476,7 @@
heth->TxDesc = DMATxDescTab;
/* Fill each DMATxDesc descriptor with the right values */
- for(i=0; i < TxBuffCount; i++)
+ for(i=0U; i < TxBuffCount; i++)
{
/* Get the pointer on the ith member of the Tx Desc list */
dmatxdesc = DMATxDescTab + i;
@@ -479,10 +494,10 @@
}
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
- if(i < (TxBuffCount-1))
+ if(i < (TxBuffCount-1U))
{
/* Set next descriptor address register with next descriptor base address */
- dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
+ dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U);
}
else
{
@@ -515,7 +530,7 @@
*/
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
{
- uint32_t i = 0;
+ uint32_t i = 0U;
ETH_DMADescTypeDef *DMARxDesc;
/* Process Locked */
@@ -528,7 +543,7 @@
heth->RxDesc = DMARxDescTab;
/* Fill each DMARxDesc descriptor with the right values */
- for(i=0; i < RxBuffCount; i++)
+ for(i=0U; i < RxBuffCount; i++)
{
/* Get the pointer on the ith member of the Rx Desc list */
DMARxDesc = DMARxDescTab+i;
@@ -549,10 +564,10 @@
}
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
- if(i < (RxBuffCount-1))
+ if(i < (RxBuffCount-1U))
{
/* Set next descriptor address register with next descriptor base address */
- DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U);
}
else
{
@@ -640,7 +655,7 @@
*/
HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
{
- uint32_t bufcount = 0, size = 0, i = 0;
+ uint32_t bufcount = 0U, size = 0U, i = 0U;
/* Process Locked */
__HAL_LOCK(heth);
@@ -648,7 +663,7 @@
/* Set the ETH peripheral state to BUSY */
heth->State = HAL_ETH_STATE_BUSY;
- if (FrameLength == 0)
+ if (FrameLength == 0U)
{
/* Set ETH HAL state to READY */
heth->State = HAL_ETH_STATE_READY;
@@ -682,9 +697,9 @@
}
else
{
- bufcount = 1;
+ bufcount = 1U;
}
- if (bufcount == 1)
+ if (bufcount == 1U)
{
/* Set LAST and FIRST segment */
heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
@@ -697,12 +712,12 @@
}
else
{
- for (i=0; i< bufcount; i++)
+ for (i=0U; i< bufcount; i++)
{
/* Clear FIRST and LAST segment bits */
heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
- if (i == 0)
+ if (i == 0U)
{
/* Setting the first segment bit */
heth->TxDesc->Status |= ETH_DMATXDESC_FS;
@@ -711,11 +726,11 @@
/* Program size */
heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
- if (i == (bufcount-1))
+ if (i == (bufcount-1U))
{
/* Setting the last segment bit */
heth->TxDesc->Status |= ETH_DMATXDESC_LS;
- size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
+ size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE;
heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
}
@@ -732,7 +747,7 @@
/* Clear TBUS ETHERNET DMA flag */
(heth->Instance)->DMASR = ETH_DMASR_TBUS;
/* Resume DMA transmission*/
- (heth->Instance)->DMATPDR = 0;
+ (heth->Instance)->DMATPDR = 0U;
}
/* Set ETH HAL State to Ready */
@@ -753,7 +768,7 @@
*/
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
{
- uint32_t framelength = 0;
+ uint32_t framelength = 0U;
/* Process Locked */
__HAL_LOCK(heth);
@@ -772,7 +787,7 @@
(heth->RxFrameInfos).SegCount++;
/* Check if last segment is first segment: one segment contains the frame */
- if ((heth->RxFrameInfos).SegCount == 1)
+ if ((heth->RxFrameInfos).SegCount == 1U)
{
(heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
}
@@ -780,7 +795,7 @@
heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
- framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
+ framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
heth->RxFrameInfos.length = framelength;
/* Get the address of the buffer start address */
@@ -802,7 +817,7 @@
{
(heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
(heth->RxFrameInfos).LSRxDesc = NULL;
- (heth->RxFrameInfos).SegCount = 1;
+ (heth->RxFrameInfos).SegCount = 1U;
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
}
@@ -833,7 +848,7 @@
*/
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
{
- uint32_t descriptorscancounter = 0;
+ uint32_t descriptorscancounter = 0U;
/* Process Locked */
__HAL_LOCK(heth);
@@ -852,7 +867,7 @@
if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
{
heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
- heth->RxFrameInfos.SegCount = 1;
+ heth->RxFrameInfos.SegCount = 1U;
/* Point to next descriptor */
heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
}
@@ -875,13 +890,13 @@
(heth->RxFrameInfos.SegCount)++;
/* Check if last segment is first segment: one segment contains the frame */
- if ((heth->RxFrameInfos.SegCount) == 1)
+ if ((heth->RxFrameInfos.SegCount) == 1U)
{
heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
}
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
- heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
+ heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U;
/* Get the address of the buffer start address */
heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
@@ -1029,8 +1044,8 @@
*/
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
{
- uint32_t tmpreg = 0;
- uint32_t tickstart = 0;
+ uint32_t tmpreg1 = 0U;
+ uint32_t tickstart = 0U;
/* Check parameters */
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
@@ -1044,25 +1059,25 @@
heth->State = HAL_ETH_STATE_BUSY_RD;
/* Get the ETHERNET MACMIIAR value */
- tmpreg = heth->Instance->MACMIIAR;
+ tmpreg1 = heth->Instance->MACMIIAR;
/* Keep only the CSR Clock Range CR[2:0] bits value */
- tmpreg &= ~ETH_MACMIIAR_CR_MASK;
+ tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
/* Prepare the MII address register value */
- tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
- tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
- tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
- tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
+ tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+ tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
+ tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
+ tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
/* Write the result value into the MII Address register */
- heth->Instance->MACMIIAR = tmpreg;
+ heth->Instance->MACMIIAR = tmpreg1;
/* Get tick */
tickstart = HAL_GetTick();
/* Check for the Busy flag */
- while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
+ while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
@@ -1075,7 +1090,7 @@
return HAL_TIMEOUT;
}
- tmpreg = heth->Instance->MACMIIAR;
+ tmpreg1 = heth->Instance->MACMIIAR;
}
/* Get MACMIIDR value */
@@ -1101,8 +1116,8 @@
*/
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
{
- uint32_t tmpreg = 0;
- uint32_t tickstart = 0;
+ uint32_t tmpreg1 = 0U;
+ uint32_t tickstart = 0U;
/* Check parameters */
assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
@@ -1116,28 +1131,28 @@
heth->State = HAL_ETH_STATE_BUSY_WR;
/* Get the ETHERNET MACMIIAR value */
- tmpreg = heth->Instance->MACMIIAR;
+ tmpreg1 = heth->Instance->MACMIIAR;
/* Keep only the CSR Clock Range CR[2:0] bits value */
- tmpreg &= ~ETH_MACMIIAR_CR_MASK;
+ tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
/* Prepare the MII register address value */
- tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
- tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
- tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
- tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
+ tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */
+ tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */
+ tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
+ tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
/* Give the value to the MII data register */
heth->Instance->MACMIIDR = (uint16_t)RegValue;
/* Write the result value into the MII Address register */
- heth->Instance->MACMIIAR = tmpreg;
+ heth->Instance->MACMIIAR = tmpreg1;
/* Get tick */
tickstart = HAL_GetTick();
/* Check for the Busy flag */
- while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
+ while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
@@ -1150,7 +1165,7 @@
return HAL_TIMEOUT;
}
- tmpreg = heth->Instance->MACMIIAR;
+ tmpreg1 = heth->Instance->MACMIIAR;
}
/* Set ETH HAL State to READY */
@@ -1272,7 +1287,7 @@
*/
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0U;
/* Process Locked */
__HAL_LOCK(heth);
@@ -1316,11 +1331,11 @@
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
/* Clear WD, PCE, PS, TE and RE bits */
- tmpreg &= ETH_MACCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACCR_CLEAR_MASK;
- tmpreg |= (uint32_t)(macconf->Watchdog |
+ tmpreg1 |= (uint32_t)(macconf->Watchdog |
macconf->Jabber |
macconf->InterFrameGap |
macconf->CarrierSense |
@@ -1335,13 +1350,13 @@
macconf->DeferralCheck);
/* Write to ETHERNET MACCR */
- (heth->Instance)->MACCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
/* Write to ETHERNET MACFFR */
@@ -1356,9 +1371,9 @@
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFFR;
+ tmpreg1 = (heth->Instance)->MACFFR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFFR = tmpreg;
+ (heth->Instance)->MACFFR = tmpreg1;
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
/* Write to ETHERNET MACHTHR */
@@ -1369,11 +1384,11 @@
/*----------------------- ETHERNET MACFCR Configuration --------------------*/
/* Get the ETHERNET MACFCR value */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
/* Clear xx bits */
- tmpreg &= ETH_MACFCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
- tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
+ tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) |
macconf->ZeroQuantaPause |
macconf->PauseLowThreshold |
macconf->UnicastPauseFrameDetect |
@@ -1381,13 +1396,13 @@
macconf->TransmitFlowControl);
/* Write to ETHERNET MACFCR */
- (heth->Instance)->MACFCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFCR = tmpreg;
+ (heth->Instance)->MACFCR = tmpreg1;
/*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
(heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
@@ -1395,29 +1410,29 @@
/* Wait until the write operation will be taken into account :
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACVLANTR;
+ tmpreg1 = (heth->Instance)->MACVLANTR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACVLANTR = tmpreg;
+ (heth->Instance)->MACVLANTR = tmpreg1;
}
else /* macconf == NULL : here we just configure Speed and Duplex mode */
{
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
/* Clear FES and DM bits */
- tmpreg &= ~((uint32_t)0x00004800);
+ tmpreg1 &= ~(0x00004800U);
- tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
+ tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
/* Write to ETHERNET MACCR */
- (heth->Instance)->MACCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
}
/* Set the ETH state to Ready */
@@ -1439,7 +1454,7 @@
*/
HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0U;
/* Process Locked */
__HAL_LOCK(heth);
@@ -1466,11 +1481,11 @@
/*----------------------- ETHERNET DMAOMR Configuration --------------------*/
/* Get the ETHERNET DMAOMR value */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
/* Clear xx bits */
- tmpreg &= ETH_DMAOMR_CLEAR_MASK;
+ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
- tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
+ tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
dmaconf->ReceiveStoreForward |
dmaconf->FlushReceivedFrame |
dmaconf->TransmitStoreForward |
@@ -1481,28 +1496,28 @@
dmaconf->SecondFrameOperate);
/* Write to ETHERNET DMAOMR */
- (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMAOMR = tmpreg;
+ (heth->Instance)->DMAOMR = tmpreg1;
/*----------------------- ETHERNET DMABMR Configuration --------------------*/
(heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
dmaconf->FixedBurst |
dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
dmaconf->TxDMABurstLength |
- (dmaconf->DescriptorSkipLength << 2) |
+ (dmaconf->DescriptorSkipLength << 2U) |
dmaconf->DMAArbitration |
ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMABMR;
+ tmpreg1 = (heth->Instance)->DMABMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMABMR = tmpreg;
+ (heth->Instance)->DMABMR = tmpreg1;
/* Set the ETH state to Ready */
heth->State= HAL_ETH_STATE_READY;
@@ -1571,7 +1586,7 @@
{
ETH_MACInitTypeDef macinit;
ETH_DMAInitTypeDef dmainit;
- uint32_t tmpreg = 0;
+ uint32_t tmpreg1 = 0U;
if (err != ETH_SUCCESS) /* Auto-negotiation failed */
{
@@ -1609,22 +1624,22 @@
macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
- macinit.HashTableHigh = 0x0;
- macinit.HashTableLow = 0x0;
- macinit.PauseTime = 0x0;
+ macinit.HashTableHigh = 0x0U;
+ macinit.HashTableLow = 0x0U;
+ macinit.PauseTime = 0x0U;
macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
- macinit.VLANTagIdentifier = 0x0;
+ macinit.VLANTagIdentifier = 0x0U;
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
/* Clear WD, PCE, PS, TE and RE bits */
- tmpreg &= ETH_MACCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACCR_CLEAR_MASK;
/* Set the WD bit according to ETH Watchdog value */
/* Set the JD: bit according to ETH Jabber value */
/* Set the IFG bit according to ETH InterFrameGap value */
@@ -1638,7 +1653,7 @@
/* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
/* Set the BL bit according to ETH BackOffLimit value */
/* Set the DC bit according to ETH DeferralCheck value */
- tmpreg |= (uint32_t)(macinit.Watchdog |
+ tmpreg1 |= (uint32_t)(macinit.Watchdog |
macinit.Jabber |
macinit.InterFrameGap |
macinit.CarrierSense |
@@ -1653,13 +1668,13 @@
macinit.DeferralCheck);
/* Write to ETHERNET MACCR */
- (heth->Instance)->MACCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
+ tmpreg1 = (heth->Instance)->MACCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ (heth->Instance)->MACCR = tmpreg1;
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
/* Set the RA bit according to ETH ReceiveAll value */
@@ -1682,9 +1697,9 @@
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFFR;
+ tmpreg1 = (heth->Instance)->MACFFR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFFR = tmpreg;
+ (heth->Instance)->MACFFR = tmpreg1;
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
/* Write to ETHERNET MACHTHR */
@@ -1695,9 +1710,9 @@
/*----------------------- ETHERNET MACFCR Configuration -------------------*/
/* Get the ETHERNET MACFCR value */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
/* Clear xx bits */
- tmpreg &= ETH_MACFCR_CLEAR_MASK;
+ tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
/* Set the PT bit according to ETH PauseTime value */
/* Set the DZPQ bit according to ETH ZeroQuantaPause value */
@@ -1705,7 +1720,7 @@
/* Set the UP bit according to ETH UnicastPauseFrameDetect value */
/* Set the RFE bit according to ETH ReceiveFlowControl value */
/* Set the TFE bit according to ETH TransmitFlowControl value */
- tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
+ tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) |
macinit.ZeroQuantaPause |
macinit.PauseLowThreshold |
macinit.UnicastPauseFrameDetect |
@@ -1713,13 +1728,13 @@
macinit.TransmitFlowControl);
/* Write to ETHERNET MACFCR */
- (heth->Instance)->MACFCR = (uint32_t)tmpreg;
+ (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACFCR;
+ tmpreg1 = (heth->Instance)->MACFCR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACFCR = tmpreg;
+ (heth->Instance)->MACFCR = tmpreg1;
/*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
/* Set the ETV bit according to ETH VLANTagComparison value */
@@ -1729,9 +1744,9 @@
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACVLANTR;
+ tmpreg1 = (heth->Instance)->MACVLANTR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACVLANTR = tmpreg;
+ (heth->Instance)->MACVLANTR = tmpreg1;
/* Ethernet DMA default initialization ************************************/
dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
@@ -1747,13 +1762,13 @@
dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
- dmainit.DescriptorSkipLength = 0x0;
+ dmainit.DescriptorSkipLength = 0x0U;
dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
/* Get the ETHERNET DMAOMR value */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
/* Clear xx bits */
- tmpreg &= ETH_DMAOMR_CLEAR_MASK;
+ tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
/* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
/* Set the RSF bit according to ETH ReceiveStoreForward value */
@@ -1764,7 +1779,7 @@
/* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
/* Set the RTC bit according to ETH ReceiveThresholdControl value */
/* Set the OSF bit according to ETH SecondFrameOperate value */
- tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
+ tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
dmainit.ReceiveStoreForward |
dmainit.FlushReceivedFrame |
dmainit.TransmitStoreForward |
@@ -1775,13 +1790,13 @@
dmainit.SecondFrameOperate);
/* Write to ETHERNET DMAOMR */
- (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
+ (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMAOMR;
+ tmpreg1 = (heth->Instance)->DMAOMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMAOMR = tmpreg;
+ (heth->Instance)->DMAOMR = tmpreg1;
/*----------------------- ETHERNET DMABMR Configuration ------------------*/
/* Set the AAL bit according to ETH AddressAlignedBeats value */
@@ -1794,15 +1809,15 @@
dmainit.FixedBurst |
dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
dmainit.TxDMABurstLength |
- (dmainit.DescriptorSkipLength << 2) |
+ (dmainit.DescriptorSkipLength << 2U) |
dmainit.DMAArbitration |
ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMABMR;
+ tmpreg1 = (heth->Instance)->DMABMR;
HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMABMR = tmpreg;
+ (heth->Instance)->DMABMR = tmpreg1;
if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
{
@@ -1829,20 +1844,23 @@
*/
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
{
- uint32_t tmpreg;
+ uint32_t tmpreg1;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(heth);
+
/* Check the parameters */
assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
/* Calculate the selected MAC address high register */
- tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
+ tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U];
/* Load the selected MAC address high register */
- (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
/* Calculate the selected MAC address low register */
- tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
+ tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U];
/* Load the selected MAC address low register */
- (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
+ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
}
/**
@@ -1853,16 +1871,16 @@
*/
static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0U;
/* Enable the MAC transmission */
(heth->Instance)->MACCR |= ETH_MACCR_TE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ tmpreg1 = (heth->Instance)->MACCR;
+ ETH_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
@@ -1873,16 +1891,16 @@
*/
static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0U;
/* Disable the MAC transmission */
(heth->Instance)->MACCR &= ~ETH_MACCR_TE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ tmpreg1 = (heth->Instance)->MACCR;
+ ETH_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
@@ -1893,16 +1911,16 @@
*/
static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0U;
/* Enable the MAC reception */
(heth->Instance)->MACCR |= ETH_MACCR_RE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ tmpreg1 = (heth->Instance)->MACCR;
+ ETH_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
@@ -1913,16 +1931,16 @@
*/
static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0U;
/* Disable the MAC reception */
(heth->Instance)->MACCR &= ~ETH_MACCR_RE;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->MACCR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->MACCR = tmpreg;
+ tmpreg1 = (heth->Instance)->MACCR;
+ ETH_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->MACCR = tmpreg1;
}
/**
@@ -1981,16 +1999,31 @@
*/
static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
{
- __IO uint32_t tmpreg = 0;
+ __IO uint32_t tmpreg1 = 0U;
/* Set the Flush Transmit FIFO bit */
(heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
/* Wait until the write operation will be taken into account:
at least four TX_CLK/RX_CLK clock cycles */
- tmpreg = (heth->Instance)->DMAOMR;
- HAL_Delay(ETH_REG_WRITE_DELAY);
- (heth->Instance)->DMAOMR = tmpreg;
+ tmpreg1 = (heth->Instance)->DMAOMR;
+ ETH_Delay(ETH_REG_WRITE_DELAY);
+ (heth->Instance)->DMAOMR = tmpreg1;
+}
+
+/**
+ * @brief This function provides delay (in milliseconds) based on CPU cycles method.
+ * @param mdelay: specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+static void ETH_Delay(uint32_t mdelay)
+{
+ __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
+ do
+ {
+ __NOP();
+ }
+ while (Delay --);
}
/**
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash.c
index 4b8504c..45d8901 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_flash.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -41,7 +41,6 @@
(++) Lock and Unlock the FLASH interface
(++) Erase function: Erase page, erase all pages
(++) Program functions: half word, word and doubleword
-
(#) FLASH Option Bytes Programming functions: this group includes all needed
functions to manage the Option Bytes:
(++) Lock and Unlock the Option Bytes
@@ -58,7 +57,7 @@
includes all needed functions to:
(++) Handle FLASH interrupts
(++) Wait for last FLASH operation according to its status
- (++) Get error flag status
+ (++) Get error flag status
[..] In addition to these function, this driver includes a set of macros allowing
to handle the following operations:
@@ -148,6 +147,7 @@
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
static void FLASH_SetErrorCode(void);
+extern void FLASH_PageErase(uint32_t PageAddress);
/**
* @}
*/
@@ -201,13 +201,13 @@
{
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
#if defined(FLASH_BANK2_END)
}
else
{
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
}
#endif /* FLASH_BANK2_END */
@@ -216,29 +216,29 @@
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
{
/* Program halfword (16-bit) at a specified address. */
- nbiterations = 1;
+ nbiterations = 1U;
}
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
/* Program word (32-bit = 2*16-bit) at a specified address. */
- nbiterations = 2;
+ nbiterations = 2U;
}
else
{
/* Program double word (64-bit = 4*16-bit) at a specified address. */
- nbiterations = 4;
+ nbiterations = 4U;
}
- for (index = 0; index < nbiterations; index++)
+ for (index = 0U; index < nbiterations; index++)
{
- FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index)));
+ FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index)));
#if defined(FLASH_BANK2_END)
if(Address <= FLASH_BANK1_END)
{
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
@@ -247,7 +247,7 @@
else
{
/* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE);
+ status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
@@ -321,23 +321,23 @@
if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD;
- /*Program halfword (16-bit) at a specified address.*/
- pFlash.DataRemaining = 1;
+ /* Program halfword (16-bit) at a specified address. */
+ pFlash.DataRemaining = 1U;
}
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD;
- /*Program word (32-bit : 2*16-bit) at a specified address.*/
- pFlash.DataRemaining = 2;
+ /* Program word (32-bit : 2*16-bit) at a specified address. */
+ pFlash.DataRemaining = 2U;
}
else
{
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD;
- /*Program double word (64-bit : 4*16-bit) at a specified address.*/
- pFlash.DataRemaining = 4;
+ /* Program double word (64-bit : 4*16-bit) at a specified address. */
+ pFlash.DataRemaining = 4U;
}
- /*Program halfword (16-bit) at a specified address.*/
+ /* Program halfword (16-bit) at a specified address. */
FLASH_Program_HalfWord(Address, (uint16_t)Data);
return status;
@@ -349,7 +349,7 @@
*/
void HAL_FLASH_IRQHandler(void)
{
- uint32_t addresstmp = 0;
+ uint32_t addresstmp = 0U;
/* Check FLASH operation error flags */
#if defined(FLASH_BANK2_END)
@@ -359,18 +359,18 @@
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
#endif /* FLASH_BANK2_END */
{
- /*return the faulty address*/
+ /* Return the faulty address */
addresstmp = pFlash.Address;
/* Reset address */
- pFlash.Address = 0xFFFFFFFF;
+ pFlash.Address = 0xFFFFFFFFU;
- /*Save the Error code*/
+ /* Save the Error code */
FLASH_SetErrorCode();
/* FLASH error interrupt user callback */
HAL_FLASH_OperationErrorCallback(addresstmp);
- /* Stop the procedure ongoing*/
+ /* Stop the procedure ongoing */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
@@ -395,11 +395,11 @@
/* Nb of pages to erased can be decreased */
pFlash.DataRemaining--;
- /* Check if there are still pages to erase*/
- if(pFlash.DataRemaining != 0)
+ /* Check if there are still pages to erase */
+ if(pFlash.DataRemaining != 0U)
{
addresstmp = pFlash.Address;
- /*Indicate user which sector has been erased*/
+ /*Indicate user which sector has been erased */
HAL_FLASH_EndOfOperationCallback(addresstmp);
/*Increment sector number*/
@@ -413,9 +413,9 @@
}
else
{
- /*No more pages to Erase, user callback can be called.*/
- /*Reset Sector and stop Erase pages procedure*/
- pFlash.Address = addresstmp = 0xFFFFFFFF;
+ /* No more pages to Erase, user callback can be called. */
+ /* Reset Sector and stop Erase pages procedure */
+ pFlash.Address = addresstmp = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(addresstmp);
@@ -431,9 +431,9 @@
if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER))
{
#endif /* FLASH_BANK2_END */
- /* MassErase ended. Return the selected bank*/
+ /* MassErase ended. Return the selected bank */
/* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(0);
+ HAL_FLASH_EndOfOperationCallback(0U);
/* Stop Mass Erase procedure*/
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
@@ -447,14 +447,14 @@
pFlash.DataRemaining--;
/* Check if there are still 16-bit data to program */
- if(pFlash.DataRemaining != 0)
+ if(pFlash.DataRemaining != 0U)
{
/* Increment address to 16-bit */
- pFlash.Address += 2;
+ pFlash.Address += 2U;
addresstmp = pFlash.Address;
/* Shift to have next 16-bit data */
- pFlash.Data = (pFlash.Data >> 16);
+ pFlash.Data = (pFlash.Data >> 16U);
/* Operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
@@ -464,7 +464,7 @@
}
else
{
- /*Program ended. Return the selected address*/
+ /* Program ended. Return the selected address */
/* FLASH EOP interrupt user callback */
if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD)
{
@@ -472,15 +472,15 @@
}
else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
{
- HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2);
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U);
}
else
{
- HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6);
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U);
}
- /* Reset Address and stop Program procedure*/
- pFlash.Address = 0xFFFFFFFF;
+ /* Reset Address and stop Program procedure */
+ pFlash.Address = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
}
@@ -503,7 +503,7 @@
pFlash.DataRemaining--;
/* Check if there are still pages to erase*/
- if(pFlash.DataRemaining != 0)
+ if(pFlash.DataRemaining != 0U)
{
/* Indicate user which page address has been erased*/
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
@@ -522,7 +522,7 @@
/*No more pages to Erase*/
/*Reset Address and stop Erase pages procedure*/
- pFlash.Address = 0xFFFFFFFF;
+ pFlash.Address = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
/* FLASH EOP interrupt user callback */
@@ -538,7 +538,7 @@
{
/* MassErase ended. Return the selected bank*/
/* FLASH EOP interrupt user callback */
- HAL_FLASH_EndOfOperationCallback(0);
+ HAL_FLASH_EndOfOperationCallback(0U);
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
@@ -549,14 +549,14 @@
pFlash.DataRemaining--;
/* Check if there are still 16-bit data to program */
- if(pFlash.DataRemaining != 0)
+ if(pFlash.DataRemaining != 0U)
{
/* Increment address to 16-bit */
- pFlash.Address += 2;
+ pFlash.Address += 2U;
addresstmp = pFlash.Address;
/* Shift to have next 16-bit data */
- pFlash.Data = (pFlash.Data >> 16);
+ pFlash.Data = (pFlash.Data >> 16U);
/* Operation is completed, disable the PG Bit */
CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG);
@@ -574,15 +574,15 @@
}
else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD)
{
- HAL_FLASH_EndOfOperationCallback(pFlash.Address-2);
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address-2U);
}
else
{
- HAL_FLASH_EndOfOperationCallback(pFlash.Address-6);
+ HAL_FLASH_EndOfOperationCallback(pFlash.Address-6U);
}
/* Reset Address and stop Program procedure*/
- pFlash.Address = 0xFFFFFFFF;
+ pFlash.Address = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
}
@@ -612,7 +612,6 @@
}
}
-
/**
* @brief FLASH end of operation interrupt callback
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
@@ -626,6 +625,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
*/
@@ -643,6 +643,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
*/
@@ -712,12 +713,11 @@
#if defined(FLASH_BANK2_END)
/* Set the LOCK Bit to lock the FLASH BANK2 Registers access */
SET_BIT(FLASH->CR2, FLASH_CR2_LOCK);
-#endif /* FLASH_BANK2_END */
+#endif /* FLASH_BANK2_END */
return HAL_OK;
}
-
/**
* @brief Unlock the FLASH Option Control Registers access.
* @retval HAL Status
@@ -753,29 +753,27 @@
/**
* @brief Launch the option byte loading.
* @note This function will reset automatically the MCU.
- * @retval HAL_StatusTypeDef HAL Status
+ * @retval None
*/
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+void HAL_FLASH_OB_Launch(void)
{
/* Initiates a system reset request to launch the option byte loading */
HAL_NVIC_SystemReset();
-
- return HAL_OK;
}
/**
* @}
*/
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
+ * @brief Peripheral errors functions
*
@verbatim
===============================================================================
- ##### Peripheral State functions #####
+ ##### Peripheral Errors functions #####
===============================================================================
[..]
- This subsection permit to get in run-time the status of the FLASH peripheral.
+ This subsection permit to get in run-time errors of the FLASH peripheral.
@endverbatim
* @{
@@ -783,13 +781,14 @@
/**
* @brief Get the specific FLASH error flag.
- * @retval FLASH_ErrorCode: The returned value can be:
+ * @retval FLASH_ErrorCode The returned value can be:
* @ref FLASH_Error_Codes
*/
uint32_t HAL_FLASH_GetError(void)
-{
+{
return pFlash.ErrorCode;
-}
+}
+
/**
* @}
*/
@@ -804,8 +803,8 @@
/**
* @brief Program a half-word (16-bit) at a specified address.
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
+ * @param Address specify the address to be programmed.
+ * @param Data specify the data to be programmed.
* @retval None
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
@@ -834,8 +833,8 @@
/**
* @brief Wait for a FLASH operation to complete.
- * @param Timeout: maximum flash operation timeout
- * @retval HAL_StatusTypeDef HAL Status
+ * @param Timeout maximum flash operation timeout
+ * @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
@@ -849,7 +848,7 @@
{
if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
return HAL_TIMEOUT;
}
@@ -872,14 +871,14 @@
return HAL_ERROR;
}
- /* If there is no error flag set */
+ /* There is no error flag set */
return HAL_OK;
}
#if defined(FLASH_BANK2_END)
/**
* @brief Wait for a FLASH BANK2 operation to complete.
- * @param Timeout: maximum flash operation timeout
+ * @param Timeout maximum flash operation timeout
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout)
@@ -894,7 +893,7 @@
{
if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
{
return HAL_TIMEOUT;
}
@@ -926,7 +925,9 @@
* @retval None
*/
static void FLASH_SetErrorCode(void)
-{
+{
+ uint32_t flags = 0U;
+
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2))
#else
@@ -934,6 +935,11 @@
#endif /* FLASH_BANK2_END */
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+#if defined(FLASH_BANK2_END)
+ flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2;
+#else
+ flags |= FLASH_FLAG_WRPERR;
+#endif /* FLASH_BANK2_END */
}
#if defined(FLASH_BANK2_END)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2))
@@ -941,21 +947,21 @@
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR))
#endif /* FLASH_BANK2_END */
{
- pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
+#if defined(FLASH_BANK2_END)
+ flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2;
+#else
+ flags |= FLASH_FLAG_PGERR;
+#endif /* FLASH_BANK2_END */
}
-
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
{
- pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
+ pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
+ __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
}
/* Clear FLASH error pending bits */
-#if defined(FLASH_BANK2_END)
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2);
-#else
- __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);
-#endif /* FLASH_BANK2_END */
+ __HAL_FLASH_CLEAR_FLAG(flags);
}
/**
* @}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash_ex.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash_ex.c
index dc970ee..ce38dcf 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash_ex.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_flash_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_flash_ex.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Extended FLASH HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -91,9 +91,9 @@
/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
* @{
*/
-#define FLASH_POSITION_IWDGSW_BIT (uint32_t)POSITION_VAL(FLASH_OBR_IWDG_SW)
-#define FLASH_POSITION_OB_USERDATA0_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA0)
-#define FLASH_POSITION_OB_USERDATA1_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA1)
+#define FLASH_POSITION_IWDGSW_BIT FLASH_OBR_IWDG_SW_Pos
+#define FLASH_POSITION_OB_USERDATA0_BIT FLASH_OBR_DATA0_Pos
+#define FLASH_POSITION_OB_USERDATA1_BIT FLASH_OBR_DATA1_Pos
/**
* @}
*/
@@ -113,6 +113,7 @@
*/
/* Erase operations */
static void FLASH_MassErase(uint32_t Banks);
+void FLASH_PageErase(uint32_t PageAddress);
/* Option bytes control */
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage);
@@ -176,7 +177,7 @@
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
{
HAL_StatusTypeDef status = HAL_ERROR;
- uint32_t address = 0;
+ uint32_t address = 0U;
/* Process Locked */
__HAL_LOCK(&pFlash);
@@ -258,7 +259,7 @@
if (FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
{
/*Initialization of PageError variable*/
- *PageError = 0xFFFFFFFF;
+ *PageError = 0xFFFFFFFFU;
/* Erase by page by page to be done*/
for(address = pEraseInit->PageAddress;
@@ -290,7 +291,7 @@
if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK)
{
/*Initialization of PageError variable*/
- *PageError = 0xFFFFFFFF;
+ *PageError = 0xFFFFFFFFU;
/* Erase page by page to be done*/
for(address = pEraseInit->PageAddress;
@@ -635,6 +636,10 @@
else
{
#endif /* FLASH_BANK2_END */
+#if !defined(FLASH_BANK2_END)
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Banks);
+#endif /* FLASH_BANK2_END */
/* Only bank1 will be erased*/
SET_BIT(FLASH->CR, FLASH_CR_MER);
SET_BIT(FLASH->CR, FLASH_CR_STRT);
@@ -681,26 +686,26 @@
#endif /* OB_WRP_PAGES0TO31MASK */
#if defined(OB_WRP_PAGES16TO31MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
#elif defined(OB_WRP_PAGES32TO63MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8);
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
#endif /* OB_WRP_PAGES32TO63MASK */
#if defined(OB_WRP_PAGES64TO95MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16);
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U);
#endif /* OB_WRP_PAGES64TO95MASK */
#if defined(OB_WRP_PAGES32TO47MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
#endif /* OB_WRP_PAGES32TO47MASK */
#if defined(OB_WRP_PAGES96TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24);
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO255MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24);
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO511MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24);
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
#endif /* OB_WRP_PAGES96TO127MASK */
/* Wait for last operation to be completed */
@@ -719,7 +724,7 @@
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
#if defined(FLASH_WRP0_WRP0)
- if(WRP0_Data != 0xFF)
+ if(WRP0_Data != 0xFFU)
{
OB->WRP0 &= WRP0_Data;
@@ -729,7 +734,7 @@
#endif /* FLASH_WRP0_WRP0 */
#if defined(FLASH_WRP1_WRP1)
- if((status == HAL_OK) && (WRP1_Data != 0xFF))
+ if((status == HAL_OK) && (WRP1_Data != 0xFFU))
{
OB->WRP1 &= WRP1_Data;
@@ -739,7 +744,7 @@
#endif /* FLASH_WRP1_WRP1 */
#if defined(FLASH_WRP2_WRP2)
- if((status == HAL_OK) && (WRP2_Data != 0xFF))
+ if((status == HAL_OK) && (WRP2_Data != 0xFFU))
{
OB->WRP2 &= WRP2_Data;
@@ -749,7 +754,7 @@
#endif /* FLASH_WRP2_WRP2 */
#if defined(FLASH_WRP3_WRP3)
- if((status == HAL_OK) && (WRP3_Data != 0xFF))
+ if((status == HAL_OK) && (WRP3_Data != 0xFFU))
{
OB->WRP3 &= WRP3_Data;
@@ -804,26 +809,26 @@
#endif /* OB_WRP_PAGES0TO31MASK */
#if defined(OB_WRP_PAGES16TO31MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8);
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U);
#elif defined(OB_WRP_PAGES32TO63MASK)
- WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8);
+ WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U);
#endif /* OB_WRP_PAGES32TO63MASK */
#if defined(OB_WRP_PAGES64TO95MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16);
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U);
#endif /* OB_WRP_PAGES64TO95MASK */
#if defined(OB_WRP_PAGES32TO47MASK)
- WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16);
+ WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U);
#endif /* OB_WRP_PAGES32TO47MASK */
#if defined(OB_WRP_PAGES96TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24);
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO255MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24);
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO511MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24);
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U);
#elif defined(OB_WRP_PAGES48TO127MASK)
- WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24);
+ WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U);
#endif /* OB_WRP_PAGES96TO127MASK */
@@ -842,7 +847,7 @@
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
#if defined(FLASH_WRP0_WRP0)
- if(WRP0_Data != 0xFF)
+ if(WRP0_Data != 0xFFU)
{
OB->WRP0 |= WRP0_Data;
@@ -852,7 +857,7 @@
#endif /* FLASH_WRP0_WRP0 */
#if defined(FLASH_WRP1_WRP1)
- if((status == HAL_OK) && (WRP1_Data != 0xFF))
+ if((status == HAL_OK) && (WRP1_Data != 0xFFU))
{
OB->WRP1 |= WRP1_Data;
@@ -862,7 +867,7 @@
#endif /* FLASH_WRP1_WRP1 */
#if defined(FLASH_WRP2_WRP2)
- if((status == HAL_OK) && (WRP2_Data != 0xFF))
+ if((status == HAL_OK) && (WRP2_Data != 0xFFU))
{
OB->WRP2 |= WRP2_Data;
@@ -872,7 +877,7 @@
#endif /* FLASH_WRP2_WRP2 */
#if defined(FLASH_WRP3_WRP3)
- if((status == HAL_OK) && (WRP3_Data != 0xFF))
+ if((status == HAL_OK) && (WRP3_Data != 0xFFU))
{
OB->WRP3 |= WRP3_Data;
@@ -971,9 +976,9 @@
SET_BIT(FLASH->CR, FLASH_CR_OPTPG);
#if defined(FLASH_BANK2_END)
- OB->USER = (UserConfig | 0xF0);
+ OB->USER = (UserConfig | 0xF0U);
#else
- OB->USER = (UserConfig | 0x88);
+ OB->USER = (UserConfig | 0x88U);
#endif /* FLASH_BANK2_END */
/* Wait for last operation to be completed */
@@ -1039,7 +1044,7 @@
/**
* @brief Returns the FLASH Read Protection level.
- * @retval FLASH ReadOut Protection Status:
+ * @retval FLASH RDP level
* This parameter can be one of the following values:
* @arg @ref OB_RDP_LEVEL_0 No protection
* @arg @ref OB_RDP_LEVEL_1 Read protection of the memory
@@ -1047,7 +1052,7 @@
static uint32_t FLASH_OB_GetRDP(void)
{
uint32_t readstatus = OB_RDP_LEVEL_0;
- uint32_t tmp_reg = 0;
+ uint32_t tmp_reg = 0U;
/* Read RDP level bits */
tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT);
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_gpio.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_gpio.c
index 600b4ef..b70fb1c 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_gpio.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_gpio.c
@@ -2,18 +2,18 @@
******************************************************************************
* @file stm32f1xx_hal_gpio.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief GPIO HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- *
+ *
@verbatim
==============================================================================
##### GPIO Peripheral features #####
- ==============================================================================
+ ==============================================================================
[..]
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
@@ -50,7 +50,7 @@
##### How to use this driver #####
==============================================================================
- [..]
+ [..]
(#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
@@ -135,48 +135,47 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup GPIO_Private_Constants GPIO Private Constants
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
-
-#define GPIO_MODE ((uint32_t)0x00000003)
-#define EXTI_MODE ((uint32_t)0x10000000)
-#define GPIO_MODE_IT ((uint32_t)0x00010000)
-#define GPIO_MODE_EVT ((uint32_t)0x00020000)
-#define RISING_EDGE ((uint32_t)0x00100000)
-#define FALLING_EDGE ((uint32_t)0x00200000)
-#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
-#define GPIO_NUMBER ((uint32_t)16)
+#define GPIO_MODE 0x00000003U
+#define EXTI_MODE 0x10000000U
+#define GPIO_MODE_IT 0x00010000U
+#define GPIO_MODE_EVT 0x00020000U
+#define RISING_EDGE 0x00100000U
+#define FALLING_EDGE 0x00200000U
+#define GPIO_OUTPUT_TYPE 0x00000010U
+
+#define GPIO_NUMBER 16U
/* Definitions for bit manipulation of CRL and CRH register */
-#define GPIO_CR_MODE_INPUT ((uint32_t)0x00000000) /*!< 00: Input mode (reset state) */
-#define GPIO_CR_CNF_ANALOG ((uint32_t)0x00000000) /*!< 00: Analog mode */
-#define GPIO_CR_CNF_INPUT_FLOATING ((uint32_t)0x00000004) /*!< 01: Floating input (reset state) */
-#define GPIO_CR_CNF_INPUT_PU_PD ((uint32_t)0x00000008) /*!< 10: Input with pull-up / pull-down */
-#define GPIO_CR_CNF_GP_OUTPUT_PP ((uint32_t)0x00000000) /*!< 00: General purpose output push-pull */
-#define GPIO_CR_CNF_GP_OUTPUT_OD ((uint32_t)0x00000004) /*!< 01: General purpose output Open-drain */
-#define GPIO_CR_CNF_AF_OUTPUT_PP ((uint32_t)0x00000008) /*!< 10: Alternate function output Push-pull */
-#define GPIO_CR_CNF_AF_OUTPUT_OD ((uint32_t)0x0000000C) /*!< 11: Alternate function output Open-drain */
+#define GPIO_CR_MODE_INPUT 0x00000000U /*!< 00: Input mode (reset state) */
+#define GPIO_CR_CNF_ANALOG 0x00000000U /*!< 00: Analog mode */
+#define GPIO_CR_CNF_INPUT_FLOATING 0x00000004U /*!< 01: Floating input (reset state) */
+#define GPIO_CR_CNF_INPUT_PU_PD 0x00000008U /*!< 10: Input with pull-up / pull-down */
+#define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000U /*!< 00: General purpose output push-pull */
+#define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004U /*!< 01: General purpose output Open-drain */
+#define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008U /*!< 10: Alternate function output Push-pull */
+#define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000CU /*!< 11: Alternate function output Open-drain */
/**
* @}
*/
-
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
+/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @{
*/
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization and deinitialization functions
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
- ##### Initialization and deinitialization functions #####
+ ##### Initialization and de-initialization functions #####
===============================================================================
[..]
This section provides functions allowing to initialize and de-initialize the GPIOs
@@ -186,6 +185,7 @@
* @{
*/
+
/**
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
@@ -196,12 +196,12 @@
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
uint32_t position;
- uint32_t ioposition = 0x00;
- uint32_t iocurrent = 0x00;
- uint32_t temp = 0x00;
- uint32_t config = 0x00;
+ uint32_t ioposition = 0x00U;
+ uint32_t iocurrent = 0x00U;
+ uint32_t temp = 0x00U;
+ uint32_t config = 0x00U;
__IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
- uint32_t registeroffset = 0; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */
+ uint32_t registeroffset = 0U; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
@@ -209,10 +209,10 @@
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
- for (position = 0; position < GPIO_NUMBER; position++)
+ for (position = 0U; position < GPIO_NUMBER; position++)
{
/* Get the IO position */
- ioposition = ((uint32_t)0x01) << position;
+ ioposition = (0x01U << position);
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
@@ -296,7 +296,7 @@
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register*/
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
- registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2);
+ registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);
/* Apply the new configuration of the pin to the register */
MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), (config << registeroffset));
@@ -307,10 +307,10 @@
{
/* Enable AFIO Clock */
__HAL_RCC_AFIO_CLK_ENABLE();
- temp = AFIO->EXTICR[position >> 2];
- CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03)));
- SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
- AFIO->EXTICR[position >> 2] = temp;
+ temp = AFIO->EXTICR[position >> 2U];
+ CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
+ SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
+ AFIO->EXTICR[position >> 2U] = temp;
/* Configure the interrupt mask */
@@ -366,21 +366,21 @@
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
- uint32_t position = 0x00;
- uint32_t iocurrent = 0x00;
- uint32_t tmp = 0x00;
+ uint32_t position = 0x00U;
+ uint32_t iocurrent = 0x00U;
+ uint32_t tmp = 0x00U;
__IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
- uint32_t registeroffset = 0;
+ uint32_t registeroffset = 0U;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Configure the port pins */
- while ((GPIO_Pin >> position) != 0)
+ while ((GPIO_Pin >> position) != 0U)
{
/* Get current io position */
- iocurrent = (GPIO_Pin) & ((uint32_t)1 << position);
+ iocurrent = (GPIO_Pin) & (1U << position);
if (iocurrent)
{
@@ -388,7 +388,7 @@
/* Check if the current bit belongs to first half or last half of the pin count number
in order to address CRH or CRL register */
configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
- registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2);
+ registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);
/* CRL/CRH default value is floating input(0x04) shifted to correct position */
MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), GPIO_CRL_CNF0_0 << registeroffset);
@@ -399,12 +399,12 @@
/*------------------------- EXTI Mode Configuration --------------------*/
/* Clear the External Interrupt or Event for the current IO */
- tmp = AFIO->EXTICR[position >> 2];
- tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
- if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
+ tmp = AFIO->EXTICR[position >> 2U];
+ tmp &= 0x0FU << (4U * (position & 0x03U));
+ if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
{
- tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
- CLEAR_BIT(AFIO->EXTICR[position >> 2], tmp);
+ tmp = 0x0FU << (4U * (position & 0x03U));
+ CLEAR_BIT(AFIO->EXTICR[position >> 2U], tmp);
/* Clear EXTI line configuration */
CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
@@ -425,9 +425,9 @@
*/
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
- * @brief GPIO Read and Write
+ * @brief GPIO Read and Write
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@@ -437,6 +437,7 @@
@endverbatim
* @{
*/
+
/**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
@@ -490,7 +491,7 @@
}
else
{
- GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
+ GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
@@ -548,39 +549,38 @@
}
/**
- * @brief This function handles EXTI interrupt request.
- * @param GPIO_Pin: Specifies the pins connected EXTI line
+ * @brief This function handles EXTI interrupt request.
+ * @param GPIO_Pin: Specifies the pins connected EXTI line
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
/* EXTI line interrupt detected */
- if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
- {
+ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+ {
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);
}
}
/**
- * @brief EXTI line detection callback
- * @param GPIO_Pin: Specifies the pins connected EXTI line
+ * @brief EXTI line detection callbacks.
+ * @param GPIO_Pin: Specifies the pins connected EXTI line
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_GPIO_EXTI_Callback could be implemented in the user file
- */
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_GPIO_EXTI_Callback could be implemented in the user file
+ */
}
/**
* @}
*/
-
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_gpio_ex.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_gpio_ex.c
index 092a0ea..6bf77c5 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_gpio_ex.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_gpio_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_gpio_ex.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief GPIO Extension HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) extension peripheral.
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_hcd.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_hcd.c
index adc3386..ad1dfea 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_hcd.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_hcd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_hcd.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -149,7 +149,7 @@
/* Disable the Interrupts */
__HAL_HCD_DISABLE(hhcd);
- /*Init the Core (common init.) */
+ /* Init the Core (common init.) */
USB_CoreInit(hhcd->Instance, hhcd->Init);
/* Force Host Mode*/
@@ -202,8 +202,8 @@
hhcd->hc[ch_num].max_packet = mps;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].ep_type = ep_type;
- hhcd->hc[ch_num].ep_num = epnum & 0x7F;
- hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
+ hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
+ hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80U) == 0x80U);
hhcd->hc[ch_num].speed = speed;
status = USB_HC_Init(hhcd->Instance,
@@ -253,7 +253,7 @@
/* DeInit the low level hardware */
HAL_HCD_MspDeInit(hhcd);
- __HAL_HCD_DISABLE(hhcd);
+ __HAL_HCD_DISABLE(hhcd);
hhcd->State = HAL_HCD_STATE_RESET;
@@ -292,7 +292,7 @@
* @}
*/
-/** @defgroup HCD_Exported_Functions_Group2 IO operation functions
+/** @defgroup HCD_Exported_Functions_Group2 IO operation functions
* @brief HCD IO operation functions
*
@verbatim
@@ -332,7 +332,7 @@
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
uint8_t ch_num,
- uint8_t direction ,
+ uint8_t direction,
uint8_t ep_type,
uint8_t token,
uint8_t* pbuff,
@@ -342,7 +342,7 @@
hhcd->hc[ch_num].ep_is_in = direction;
hhcd->hc[ch_num].ep_type = ep_type;
- if(token == 0)
+ if(token == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
}
@@ -355,21 +355,21 @@
switch(ep_type)
{
case EP_TYPE_CTRL:
- if((token == 1) && (direction == 0)) /*send data */
+ if((token == 1U) && (direction == 0U)) /*send data */
{
- if ( length == 0 )
+ if (length == 0U)
{ /* For Status OUT stage, Length==0, Status Out PID = 1 */
- hhcd->hc[ch_num].toggle_out = 1;
+ hhcd->hc[ch_num].toggle_out = 1U;
}
/* Set the Data Toggle bit as per the Flag */
- if ( hhcd->hc[ch_num].toggle_out == 0)
+ if ( hhcd->hc[ch_num].toggle_out == 0U)
{ /* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{ /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
{
@@ -379,16 +379,16 @@
break;
case EP_TYPE_BULK:
- if(direction == 0)
+ if(direction == 0U)
{
/* Set the Data Toggle bit as per the Flag */
- if ( hhcd->hc[ch_num].toggle_out == 0)
+ if ( hhcd->hc[ch_num].toggle_out == 0U)
{ /* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{ /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
{
@@ -397,7 +397,7 @@
}
else
{
- if( hhcd->hc[ch_num].toggle_in == 0)
+ if( hhcd->hc[ch_num].toggle_in == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
@@ -409,21 +409,21 @@
break;
case EP_TYPE_INTR:
- if(direction == 0)
+ if(direction == 0U)
{
/* Set the Data Toggle bit as per the Flag */
- if ( hhcd->hc[ch_num].toggle_out == 0)
+ if ( hhcd->hc[ch_num].toggle_out == 0U)
{ /* Put the PID 0 */
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{ /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
else
{
- if( hhcd->hc[ch_num].toggle_in == 0)
+ if( hhcd->hc[ch_num].toggle_in == 0U)
{
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
@@ -441,8 +441,8 @@
hhcd->hc[ch_num].xfer_buff = pbuff;
hhcd->hc[ch_num].xfer_len = length;
- hhcd->hc[ch_num].urb_state = URB_IDLE;
- hhcd->hc[ch_num].xfer_count = 0 ;
+ hhcd->hc[ch_num].urb_state = URB_IDLE;
+ hhcd->hc[ch_num].xfer_count = 0U;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].state = HC_IDLE;
@@ -450,7 +450,7 @@
}
/**
- * @brief This function handles HCD interrupt request.
+ * @brief handle HCD interrupt request.
* @param hhcd: HCD handle
* @retval None
*/
@@ -458,12 +458,12 @@
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint32_t index = 0 , interrupt = 0;
-
+ uint32_t index = 0U, interrupt = 0U;
+
/* ensure that we are in device mode */
if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
{
- /* avoid spurious interrupt */
+ /* Avoid spurious interrupt */
if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
{
return;
@@ -471,25 +471,25 @@
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
- /* incorrect mode, acknowledge the interrupt */
+ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
}
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
{
- /* incorrect mode, acknowledge the interrupt */
+ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
}
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
{
- /* incorrect mode, acknowledge the interrupt */
+ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
}
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
{
- /* incorrect mode, acknowledge the interrupt */
+ /* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
}
@@ -503,7 +503,7 @@
/* Handle Host Port Interrupts */
HAL_HCD_Disconnect_Callback(hhcd);
- USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
+ USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ);
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
}
@@ -524,7 +524,7 @@
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
{
interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
- for (index = 0; index < hhcd->Init.Host_channels ; index++)
+ for (index = 0U; index < hhcd->Init.Host_channels ; index++)
{
if (interrupt & (1 << index))
{
@@ -550,7 +550,6 @@
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
-
}
}
@@ -583,7 +582,7 @@
}
/**
- * @brief Disonnexion Event callback.
+ * @brief Disonnection Event callback.
* @param hhcd: HCD handle
* @retval None
*/
@@ -608,7 +607,7 @@
* URB_NOTREADY/
* URB_NYET/
* URB_ERROR/
- * URB_STALL/
+ * URB_STALL/
* @retval None
*/
__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
@@ -650,7 +649,7 @@
{
__HAL_LOCK(hhcd);
__HAL_HCD_ENABLE(hhcd);
- USB_DriveVbus(hhcd->Instance, 1);
+ USB_DriveVbus(hhcd->Instance, 1U);
__HAL_UNLOCK(hhcd);
return HAL_OK;
}
@@ -699,7 +698,7 @@
*/
/**
- * @brief Return the HCD state
+ * @brief Return the HCD handle state
* @param hhcd: HCD handle
* @retval HAL state
*/
@@ -802,7 +801,7 @@
static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
{
@@ -841,7 +840,7 @@
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
{
hhcd->hc[chnum].state = HC_XFRC;
- hhcd->hc[chnum].ErrCnt = 0;
+ hhcd->hc[chnum].ErrCnt = 0U;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
@@ -858,7 +857,7 @@
hhcd->hc[chnum].urb_state = URB_DONE;
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
}
- hhcd->hc[chnum].toggle_in ^= 1;
+ hhcd->hc[chnum].toggle_in ^= 1U;
}
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)
@@ -876,9 +875,9 @@
else if((hhcd->hc[chnum].state == HC_XACTERR) ||
(hhcd->hc[chnum].state == HC_DATATGLERR))
{
- if(hhcd->hc[chnum].ErrCnt++ > 3)
+ if(hhcd->hc[chnum].ErrCnt++ > 3U)
{
- hhcd->hc[chnum].ErrCnt = 0;
+ hhcd->hc[chnum].ErrCnt = 0U;
hhcd->hc[chnum].urb_state = URB_ERROR;
}
else
@@ -935,7 +934,7 @@
static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
{
@@ -946,7 +945,7 @@
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
- if( hhcd->hc[chnum].do_ping == 1)
+ if( hhcd->hc[chnum].do_ping == 1U)
{
hhcd->hc[chnum].state = HC_NYET;
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
@@ -958,7 +957,7 @@
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET)
{
hhcd->hc[chnum].state = HC_NYET;
- hhcd->hc[chnum].ErrCnt= 0;
+ hhcd->hc[chnum].ErrCnt= 0U;
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
@@ -974,7 +973,7 @@
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
{
- hhcd->hc[chnum].ErrCnt = 0;
+ hhcd->hc[chnum].ErrCnt = 0U;
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
@@ -989,7 +988,7 @@
}
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
{
- hhcd->hc[chnum].ErrCnt = 0;
+ hhcd->hc[chnum].ErrCnt = 0U;
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
USB_HC_Halt(hhcd->Instance, chnum);
hhcd->hc[chnum].state = HC_NAK;
@@ -1019,7 +1018,7 @@
hhcd->hc[chnum].urb_state = URB_DONE;
if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)
{
- hhcd->hc[chnum].toggle_out ^= 1;
+ hhcd->hc[chnum].toggle_out ^= 1U;
}
}
else if (hhcd->hc[chnum].state == HC_NAK)
@@ -1029,7 +1028,7 @@
else if (hhcd->hc[chnum].state == HC_NYET)
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
- hhcd->hc[chnum].do_ping = 0;
+ hhcd->hc[chnum].do_ping = 0U;
}
else if (hhcd->hc[chnum].state == HC_STALL)
{
@@ -1038,9 +1037,9 @@
else if((hhcd->hc[chnum].state == HC_XACTERR) ||
(hhcd->hc[chnum].state == HC_DATATGLERR))
{
- if(hhcd->hc[chnum].ErrCnt++ > 3)
+ if(hhcd->hc[chnum].ErrCnt++ > 3U)
{
- hhcd->hc[chnum].ErrCnt = 0;
+ hhcd->hc[chnum].ErrCnt = 0U;
hhcd->hc[chnum].urb_state = URB_ERROR;
}
else
@@ -1068,22 +1067,22 @@
static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint8_t channelnum =0;
+ uint8_t channelnum =0U;
uint32_t pktsts;
uint32_t pktcnt;
- uint32_t temp = 0;
- uint32_t tmpreg = 0;
+ uint32_t temp = 0U;
+ uint32_t tmpreg = 0U;
temp = hhcd->Instance->GRXSTSP;
channelnum = temp & USB_OTG_GRXSTSP_EPNUM;
- pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;
- pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U;
+ pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
switch (pktsts)
{
case GRXSTS_PKTSTS_IN:
/* Read the data into the host buffer. */
- if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void *)0))
+ if ((pktcnt > 0U) && (hhcd->hc[channelnum].xfer_buff != (void *)0U))
{
USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
@@ -1091,14 +1090,14 @@
hhcd->hc[channelnum].xfer_buff += pktcnt;
hhcd->hc[channelnum].xfer_count += pktcnt;
- if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
+ if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U)
{
/* re-activate the channel when more packets are expected */
tmpreg = USBx_HC(channelnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(channelnum)->HCCHAR = tmpreg;
- hhcd->hc[channelnum].toggle_in ^= 1;
+ hhcd->hc[channelnum].toggle_in ^= 1U;
}
}
break;
@@ -1121,7 +1120,7 @@
static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- __IO uint32_t hprt0 = 0, hprt0_dup = 0;
+ __IO uint32_t hprt0 = 0, hprt0_dup = 0U;
/* Handle Host Port Interrupts */
hprt0 = USBx_HPRT0;
@@ -1148,7 +1147,7 @@
if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
{
- if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
+ if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17U))
{
USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ );
}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2c.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2c.c
index 2d20b53..6e4781d 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2c.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2c.c
@@ -2,16 +2,15 @@
******************************************************************************
* @file stm32f1xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State functions
- *
+ * + Peripheral State, Mode and Error functions
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -67,74 +66,118 @@
*** Interrupt mode IO operation ***
===================================
[..]
- (+) The I2C interrupts should have the highest priority in the application in order
- to make them uninterruptible.
- (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
- (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
- (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
- (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
- (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
+ (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
+ (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
+ (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+
+ *** Interrupt mode IO sequential operation ***
+ ==============================================
+ [..]
+ (@) These interfaces allow to manage a sequential transfer with a repeated start condition
+ when a direction change during transfer
+ [..]
+ (+) A specific option field manage the different steps of a sequential transfer
+ (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+ (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
+ and data to transfer without a final stop condition
+ (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to transfer
+ if no direction change and without a final stop condition in both cases
+ (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
+ and with new data to transfer if the direction change or manage only the new data to transfer
+ if no direction change and with a final stop condition in both cases
+
+ (+) Differents sequential I2C interfaces are listed below:
+ (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
+ (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+ (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
+ (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+ (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+ (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
+ (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
+ add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
+ (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
+ (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
+ (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+ (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
+ (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2C_ErrorCallback()
*** Interrupt mode IO MEM operation ***
=======================================
[..]
- (+) The I2C interrupts should have the highest priority in the application in order
- to make them uninterruptible.
- (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
+ (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
HAL_I2C_Mem_Write_IT()
- (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
- (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
+ (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
HAL_I2C_Mem_Read_IT()
- (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
*** DMA mode IO operation ***
==============================
[..]
- (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
+ (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
HAL_I2C_Master_Transmit_DMA()
- (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
- (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
+ (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
+ (+) Receive in master mode an amount of data in non blocking mode (DMA) using
HAL_I2C_Master_Receive_DMA()
- (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
- (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
+ (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
+ (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
HAL_I2C_Slave_Transmit_DMA()
- (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
- (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
+ (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
+ (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
HAL_I2C_Slave_Receive_DMA()
- (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+ (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
+ (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+ (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
*** DMA mode IO MEM operation ***
=================================
[..]
- (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
+ (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
HAL_I2C_Mem_Write_DMA()
- (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
- (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
+ (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
+ (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
HAL_I2C_Mem_Read_DMA()
- (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+ (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_I2C_ErrorCallback()
+ add his own code by customization of function pointer HAL_I2C_ErrorCallback
*** I2C HAL driver macros list ***
@@ -144,12 +187,13 @@
(+) __HAL_I2C_ENABLE: Enable the I2C peripheral
(+) __HAL_I2C_DISABLE: Disable the I2C peripheral
- (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+ (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
(+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
(+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
(+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
- (@) You can refer to the I2C HAL driver header file for more useful macros
+ [..]
+ (@) You can refer to the I2C HAL driver header file for more useful macros
*** I2C Workarounds linked to Silicon Limitation ***
====================================================
@@ -216,47 +260,59 @@
#ifdef HAL_I2C_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup I2C_Private_Constants I2C Private Constants
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup I2C_Private_Define
* @{
- */
-#define I2C_TIMEOUT_FLAG ((uint32_t)35) /*!< Timeout 35 ms */
-#define I2C_TIMEOUT_ADDR_SLAVE ((uint32_t)10000) /*!< Timeout 10 s */
-#define I2C_TIMEOUT_BUSY_FLAG ((uint32_t)10000) /*!< Timeout 10 s */
+ */
+#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
+#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
+#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
+
+/* Private define for @ref PreviousState usage */
+#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */
+#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
+#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
+
/**
* @}
- */
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup I2C_Private_Functions I2C Private Functions
+/** @addtogroup I2C_Private_Functions
* @{
*/
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
+/* Private functions to handle DMA transfer */
+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
static void I2C_DMAError(DMA_HandleTypeDef *hdma);
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout);
+static void I2C_ITError(I2C_HandleTypeDef *hi2c);
+
+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
+/* Private functions for I2C transfer IRQ handler */
static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
+static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
@@ -265,14 +321,11 @@
static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
-
-static uint32_t I2C_Configure_Speed(I2C_HandleTypeDef *hi2c, uint32_t I2CClkSrcFreq);
/**
* @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
+ */
+/* Exported functions --------------------------------------------------------*/
/** @defgroup I2C_Exported_Functions I2C Exported Functions
* @{
*/
@@ -285,7 +338,7 @@
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the I2Cx peripheral:
+ de-initialize the I2Cx peripheral:
(+) User must Implement HAL_I2C_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
@@ -302,7 +355,7 @@
(++) Nostretch mode
(+) Call the function HAL_I2C_DeInit() to restore the default configuration
- of the selected I2Cx periperal.
+ of the selected I2Cx peripheral.
@endverbatim
* @{
@@ -310,15 +363,15 @@
/**
* @brief Initializes the I2C according to the specified parameters
- * in the I2C_InitTypeDef and initialize the associated handle.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * in the I2C_InitTypeDef and create the associated handle.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
- uint32_t freqrange = 0;
- uint32_t pclk1 = 0;
+ uint32_t freqrange = 0U;
+ uint32_t pclk1 = 0U;
/* Check the I2C handle allocation */
if(hi2c == NULL)
@@ -341,7 +394,6 @@
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
-
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_I2C_MspInit(hi2c);
}
@@ -355,7 +407,7 @@
pclk1 = HAL_RCC_GetPCLK1Freq();
/* Calculate frequency range */
- freqrange = I2C_FREQ_RANGE(pclk1);
+ freqrange = I2C_FREQRANGE(pclk1);
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Frequency range */
@@ -367,7 +419,7 @@
/*---------------------------- I2Cx CCR Configuration ----------------------*/
/* Configure I2Cx: Speed */
- hi2c->Instance->CCR = I2C_Configure_Speed(hi2c, pclk1);
+ hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
@@ -386,15 +438,16 @@
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
return HAL_OK;
}
/**
- * @brief DeInitialize the I2C peripheral.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief DeInitializes the I2C peripheral.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
@@ -416,9 +469,10 @@
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_I2C_MspDeInit(hi2c);
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State = HAL_I2C_STATE_RESET;
- hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_RESET;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
/* Release Lock */
__HAL_UNLOCK(hi2c);
@@ -427,31 +481,31 @@
}
/**
- * @brief Initialize the I2C MSP.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief I2C MSP Init.
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
- /* NOTE : This function should not be modified, when the callback is needed,
+ /* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2C_MspInit could be implemented in the user file
*/
}
/**
- * @brief DeInitialize the I2C MSP.
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * @brief I2C MSP DeInit
+ * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval None
*/
__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
- /* NOTE : This function should not be modified, when the callback is needed,
+ /* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2C_MspDeInit could be implemented in the user file
*/
}
@@ -460,7 +514,7 @@
* @}
*/
-/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
+/** @defgroup I2C_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
@@ -475,7 +529,7 @@
(++) Blocking mode : The communication is performed in the polling mode.
The status of all data processing is returned by the same function
after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
+ (++) No-Blocking mode : The communication is performed using Interrupts
or DMA. These functions return the status of the transfer startup.
The end of the data processing will be indicated through the
dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
@@ -495,6 +549,10 @@
(++) HAL_I2C_Master_Receive_IT()
(++) HAL_I2C_Slave_Transmit_IT()
(++) HAL_I2C_Slave_Receive_IT()
+ (++) HAL_I2C_Master_Sequential_Transmit_IT()
+ (++) HAL_I2C_Master_Sequential_Receive_IT()
+ (++) HAL_I2C_Slave_Sequential_Transmit_IT()
+ (++) HAL_I2C_Slave_Sequential_Receive_IT()
(++) HAL_I2C_Mem_Write_IT()
(++) HAL_I2C_Mem_Read_IT()
@@ -514,6 +572,7 @@
(++) HAL_I2C_SlaveTxCpltCallback()
(++) HAL_I2C_SlaveRxCpltCallback()
(++) HAL_I2C_ErrorCallback()
+ (++) HAL_I2C_AbortCpltCallback()
@endverbatim
* @{
@@ -523,7 +582,8 @@
* @brief Transmits in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@@ -531,15 +591,15 @@
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
+ uint32_t tickstart = 0x00U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
{
return HAL_BUSY;
}
@@ -547,15 +607,28 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+
/* Send Slave Address */
- if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout) != HAL_OK)
+ if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -574,15 +647,15 @@
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- while(Size > 0)
+ while(hi2c->XferSize > 0U)
{
/* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
return HAL_ERROR;
}
else
@@ -592,37 +665,40 @@
}
/* Write data to DR */
- hi2c->Instance->DR = (*pData++);
- Size--;
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
{
/* Write data to DR */
- hi2c->Instance->DR = (*pData++);
- Size--;
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
}
- }
-
- /* Wait until BTF flag is set */
- if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- /* Generate Stop */
- SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
- return HAL_ERROR;
- }
- else
- {
- return HAL_TIMEOUT;
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_TIMEOUT;
+ }
}
}
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
hi2c->State = HAL_I2C_STATE_READY;
-
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -638,7 +714,8 @@
* @brief Receives in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@@ -646,15 +723,15 @@
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
+ uint32_t tickstart = 0x00U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
{
return HAL_BUSY;
}
@@ -662,15 +739,28 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
/* Send Slave Address */
- if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout) != HAL_OK)
+ if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -686,60 +776,68 @@
}
}
- if(Size == 1)
+ if(hi2c->XferSize == 0U)
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ }
+ else if(hi2c->XferSize == 1U)
{
/* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
- software sequence must complete before the current byte end of transfer */
+ software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
/* Re-enable IRQs */
__enable_irq();
}
- else if(Size == 2)
+ else if(hi2c->XferSize == 2U)
{
/* Enable Pos */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ hi2c->Instance->CR1 |= I2C_CR1_POS;
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
- software sequence must complete before the current byte end of transfer */
+ software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- /* Re-enable IRQs */
- __enable_irq();
+ /* Re-enable IRQs */
+ __enable_irq();
}
else
{
/* Enable Acknowledge */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
}
- while(Size > 0)
+ while(hi2c->XferSize > 0U)
{
- if(Size <= 3)
+ if(hi2c->XferSize <= 3U)
{
/* One byte */
- if(Size == 1)
+ if(hi2c->XferSize == 1U)
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
{
@@ -752,14 +850,15 @@
}
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
/* Two bytes */
- else if(Size == 2)
+ else if(hi2c->XferSize == 2U)
{
/* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -769,64 +868,69 @@
__disable_irq();
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
/* Re-enable IRQs */
__enable_irq();
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
/* 3 Last bytes */
else
{
/* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
/* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
-
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
+
/* Re-enable IRQs */
__enable_irq();
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
}
else
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
{
@@ -839,14 +943,16 @@
}
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
{
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
}
}
@@ -876,34 +982,46 @@
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
+ uint32_t tickstart = 0x00U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
- {
- return HAL_BUSY;
- }
-
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
/* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
/* Enable Address Acknowledge */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
/* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -915,7 +1033,7 @@
if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
/* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -924,13 +1042,14 @@
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
}
- while(Size > 0)
+ while(hi2c->XferSize > 0U)
{
/* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
@@ -942,19 +1061,21 @@
}
/* Write data to DR */
- hi2c->Instance->DR = (*pData++);
- Size--;
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
{
/* Write data to DR */
- hi2c->Instance->DR = (*pData++);
- Size--;
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ hi2c->XferSize--;
}
}
/* Wait until AF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -963,7 +1084,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Disable Address Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -982,7 +1103,7 @@
/**
* @brief Receive in slave mode an amount of data in blocking mode
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@@ -990,34 +1111,46 @@
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
+ uint32_t tickstart = 0x00U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
- {
- return HAL_BUSY;
- }
-
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
/* Enable Address Acknowledge */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
/* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -1025,13 +1158,14 @@
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- while(Size > 0)
+ while(hi2c->XferSize > 0U)
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
{
return HAL_TIMEOUT;
@@ -1043,19 +1177,21 @@
}
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
{
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
}
/* Wait until STOP flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_FLAG) != HAL_OK)
+ if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
@@ -1074,7 +1210,7 @@
__HAL_I2C_CLEAR_STOPFLAG(hi2c);
/* Disable Address Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
@@ -1094,59 +1230,61 @@
* @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
+ __IO uint32_t count = 0U;
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
{
- return HAL_BUSY;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2c);
-
- /* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
-
- /* Send Slave Address */
- if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if(count-- == 0U)
{
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+
return HAL_TIMEOUT;
}
}
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1154,7 +1292,6 @@
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
-
/* Enable EVT, BUF and ERR interrupt */
__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -1170,94 +1307,71 @@
* @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
+ __IO uint32_t count = 0U;
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
{
- return HAL_BUSY;
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
}
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
/* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
- /* Send Slave Address */
- if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
- if(hi2c->XferCount == 1)
- {
- /* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
- }
- else if(hi2c->XferCount == 2)
- {
- /* Enable Pos */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- }
- else
- {
- /* Enable Acknowledge */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- }
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
/* Enable EVT, BUF and ERR interrupt */
__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -1271,44 +1385,274 @@
}
/**
- * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+ * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shift at right before call interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ __IO uint32_t Prev_State = 0x00U;
+ __IO uint32_t count = 0x00U;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Check Busy Flag only if FIRST call of Master interface */
+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
+
+ Prev_State = hi2c->PreviousState;
+
+ /* Generate Start */
+ if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE))
+ {
+ /* Generate Start condition if first transfer */
+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+ {
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+ else if(Prev_State == I2C_STATE_MASTER_BUSY_RX)
+ {
+ /* Generate ReStart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shift at right before call interface
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ __IO uint32_t count = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ /* Check Busy Flag only if FIRST call of Master interface */
+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
+ {
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
+ {
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
+
+ if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE))
+ {
+ /* Generate Start condition if first transfer */
+ if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME))
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate ReStart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+ }
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
+ __IO uint32_t count = 0U;
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
{
- return HAL_BUSY;
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
}
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
/* Enable Address Acknowledge */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1338,34 +1682,57 @@
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
+ __IO uint32_t count = 0U;
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ /* Wait until BUSY flag is reset */
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
{
- return HAL_BUSY;
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
}
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferSize = Size;
hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
/* Enable Address Acknowledge */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1385,79 +1752,313 @@
}
}
-
+/**
+ * @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hi2c->State == HAL_I2C_STATE_LISTEN)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * @note This interface allow to manage repeated start condition when a direction change during transfer
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
+
+ if(hi2c->State == HAL_I2C_STATE_LISTEN)
+ {
+ if((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = XferOptions;
+ hi2c->XferSize = hi2c->XferCount;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Enable the Address listen mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+ if(hi2c->State == HAL_I2C_STATE_READY)
+ {
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
+ /* Enable Address Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Disable the Address listen mode with Interrupt.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of tmp to prevent undefined behavior of volatile usage */
+ uint32_t tmp;
+
+ /* Disable Address listen mode only if a transfer is not ongoing */
+ if(hi2c->State == HAL_I2C_STATE_LISTEN)
+ {
+ tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
+ hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Disable EVT and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
/**
* @brief Transmit in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
+ __IO uint32_t count = 0U;
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
{
- return HAL_BUSY;
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
}
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
-
- /* Set the I2C DMA transfert complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
-
- /* Send Slave Address */
- if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
}
- /* Enable DMA Request */
- SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
+
+ if(hi2c->XferSize > 0U)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ }
return HAL_OK;
}
@@ -1468,89 +2069,115 @@
}
/**
- * @brief Receive in master mode an amount of data in non-blocking mode with DMA
+ * @brief Receive in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
{
+ __IO uint32_t count = 0U;
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
{
- return HAL_BUSY;
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
}
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
-
- /* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
-
- /* Set the I2C DMA transfert complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
-
- /* Send Slave Address */
- if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
}
- if(Size == 1)
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+ hi2c->Devaddress = DevAddress;
+
+ if(hi2c->XferSize > 0U)
{
- /* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
}
else
{
- /* Enable Last DMA bit */
- SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
}
-
- /* Enable DMA Request */
- SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
+
return HAL_OK;
}
else
@@ -1560,7 +2187,57 @@
}
/**
- * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
+ * @brief Abort a master I2C process communication with Interrupt.
+ * @note This abort can be called only if state is ready
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shift at right before call interface
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(DevAddress);
+
+ /* Abort Master transfer during Receive or Transmit process */
+ if(hi2c->Mode == HAL_I2C_MODE_MASTER)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hi2c);
+
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_ABORT;
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ hi2c->XferCount = 0U;
+
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c);
+
+ return HAL_OK;
+ }
+ else
+ {
+ /* Wrong usage of abort function */
+ /* This function should be used only in case of abort monitored by master device */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
@@ -1569,78 +2246,83 @@
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
+ __IO uint32_t count = 0U;
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
{
- return HAL_BUSY;
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
}
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
- /* Set the I2C DMA transfert complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
-
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
+
/* Set the DMA error callback */
hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable DMA Request */
- SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
/* Enable Address Acknowledge */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* If 7bit addressing mode is selected */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- }
- else
- {
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- }
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+
return HAL_OK;
}
else
@@ -1650,7 +2332,7 @@
}
/**
- * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
+ * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
@@ -1659,60 +2341,83 @@
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
+ __IO uint32_t count = 0U;
+
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
{
- return HAL_BUSY;
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
}
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_SLAVE;
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
- hi2c->XferCount = Size;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
/* Set the I2C DMA transfer complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
/* Set the DMA error callback */
hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferHalfCpltCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable DMA Request */
- SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
/* Enable Address Acknowledge */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
- /* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
+
return HAL_OK;
}
else
@@ -1720,7 +2425,6 @@
return HAL_BUSY;
}
}
-
/**
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -1735,34 +2439,47 @@
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
+ uint32_t tickstart = 0x00U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
/* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -1778,15 +2495,15 @@
}
}
- while(Size > 0)
+ while(hi2c->XferSize > 0U)
{
/* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
return HAL_ERROR;
}
else
@@ -1796,24 +2513,26 @@
}
/* Write data to DR */
- hi2c->Instance->DR = (*pData++);
- Size--;
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferSize--;
+ hi2c->XferCount--;
- if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
+ if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
{
/* Write data to DR */
- hi2c->Instance->DR = (*pData++);
- Size--;
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
}
-
- /* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+
+ /* Wait until BTF flag is set */
+ if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
return HAL_ERROR;
}
else
@@ -1823,11 +2542,11 @@
}
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1853,34 +2572,47 @@
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
+ uint32_t tickstart = 0x00U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
/* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
+ hi2c->pBuffPtr = pData;
+ hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
+
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -1896,10 +2628,18 @@
}
}
- if(Size == 1)
+ if(hi2c->XferSize == 0U)
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ }
+ else if(hi2c->XferSize == 1U)
{
/* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
@@ -1909,15 +2649,15 @@
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Re-enable IRQs */
- __enable_irq();
+ __enable_irq();
}
- else if(Size == 2)
+ else if(hi2c->XferSize == 2U)
{
/* Enable Pos */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ hi2c->Instance->CR1 |= I2C_CR1_POS;
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
@@ -1925,10 +2665,10 @@
/* Clear ADDR flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
+
/* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
/* Re-enable IRQs */
__enable_irq();
}
@@ -1941,15 +2681,15 @@
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
}
- while(Size > 0)
+ while(hi2c->XferSize > 0U)
{
- if(Size <= 3)
+ if(hi2c->XferSize <= 3U)
{
/* One byte */
- if(Size== 1)
+ if(hi2c->XferSize== 1U)
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
{
@@ -1962,14 +2702,15 @@
}
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
/* Two bytes */
- else if(Size == 2)
+ else if(hi2c->XferSize == 2U)
{
/* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -1979,64 +2720,69 @@
__disable_irq();
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
/* Re-enable IRQs */
__enable_irq();
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
/* 3 Last bytes */
else
{
/* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
software sequence must complete before the current byte end of transfer */
__disable_irq();
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
/* Wait until BTF flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
/* Re-enable IRQs */
- __enable_irq();
+ __enable_irq();
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
}
else
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
{
@@ -2049,21 +2795,23 @@
}
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
{
/* Read data from DR */
- (*pData++) = hi2c->Instance->DR;
- Size--;
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferSize--;
+ hi2c->XferCount--;
}
}
}
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2088,59 +2836,66 @@
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
+ __IO uint32_t count = 0U;
+
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
{
- return HAL_BUSY;
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
}
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferSize = Size;
hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->Devaddress = DevAddress;
+ hi2c->Memaddress = MemAddress;
+ hi2c->MemaddSize = MemAddSize;
+ hi2c->EventCount = 0U;
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
/* Enable EVT, BUF and ERR interrupt */
__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -2166,94 +2921,75 @@
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
+ __IO uint32_t count = 0U;
+
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
{
- return HAL_BUSY;
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
}
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
+
/* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferSize = Size;
hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->Devaddress = DevAddress;
+ hi2c->Memaddress = MemAddress;
+ hi2c->MemaddSize = MemAddSize;
+ hi2c->EventCount = 0U;
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
- }
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
- if(hi2c->XferCount == 1)
- {
- /* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
- }
- else if(hi2c->XferCount == 2)
- {
- /* Enable Pos */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
- }
- else
- {
- /* Enable Acknowledge */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
- }
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
- to avoid the risk of I2C interrupt handle execution before current
- process unlock */
-
- /* Enable EVT, BUF and ERR interrupt */
- __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
+ if(hi2c->XferSize > 0U)
+ {
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+
+ /* Enable EVT, BUF and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ }
return HAL_OK;
}
else
@@ -2262,7 +2998,6 @@
}
}
-
/**
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -2276,68 +3011,105 @@
*/
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
+ __IO uint32_t count = 0U;
+
+ uint32_t tickstart = 0x00U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
{
- return HAL_BUSY;
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
}
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
- hi2c->State = HAL_I2C_STATE_BUSY_TX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferSize = Size;
hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- /* Set the I2C DMA transfert complete callback */
- hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
+ if(hi2c->XferSize > 0U)
+ {
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
- /* Set the DMA error callback */
- hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+ /* Set the DMA error callback */
+ hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hi2c->hdmatx->XferAbortCallback = NULL;
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
}
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
- }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
}
-
- /* Enable DMA Request */
- SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
return HAL_OK;
}
else
@@ -2359,82 +3131,146 @@
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
+ uint32_t tickstart = 0x00U;
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ __IO uint32_t count = 0U;
+
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if(hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
+ do
{
- return HAL_BUSY;
+ if(count-- == 0U)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
+ }
}
+ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
/* Process Locked */
__HAL_LOCK(hi2c);
- /* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
- hi2c->State = HAL_I2C_STATE_BUSY_RX;
- hi2c->Mode = HAL_I2C_MODE_MEM;
+ /* Disable Pos */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ hi2c->State = HAL_I2C_STATE_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_MEM;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
- hi2c->XferSize = Size;
hi2c->XferCount = Size;
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->XferSize = hi2c->XferCount;
- /* Set the I2C DMA transfert complete callback */
- hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
-
- /* Set the DMA error callback */
- hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
-
- /* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
+ if(hi2c->XferSize > 0U)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ /* Set the I2C DMA transfer complete callback */
+ hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
+
+ /* Set the DMA error callback */
+ hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
+
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_ERROR;
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ if(Size == 1U)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
}
else
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
- return HAL_TIMEOUT;
+ /* Enable Last DMA bit */
+ hi2c->Instance->CR2 |= I2C_CR2_LAST;
}
- }
- if(Size == 1)
- {
- /* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
+ to avoid the risk of I2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
+
+ /* Enable DMA Request */
+ hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
}
else
{
- /* Enable Last DMA bit */
- SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
+ /* Send Slave Address and Memory Address */
+ if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ {
+ if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
}
- /* Enable DMA Request */
- SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
return HAL_OK;
}
else
@@ -2443,7 +3279,6 @@
}
}
-
/**
* @brief Checks if target device is ready for communication.
* @note This function is used with Memory devices
@@ -2456,39 +3291,50 @@
*/
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
{
- uint32_t tickstart = 0, tmp1 = 0, tmp2 = 0, tmp3 = 0, I2C_Trials = 1;
+ uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
if(hi2c->State == HAL_I2C_STATE_READY)
{
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
+
+ /* Check if the I2C is already enabled */
+ if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
+ {
+ /* Enable I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
+ }
/* Disable Pos */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
hi2c->State = HAL_I2C_STATE_BUSY;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+
do
{
/* Generate Start */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+ hi2c->Instance->CR1 |= I2C_CR1_START;
/* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Send slave address */
hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-
+
/* Wait until ADDR or AF flag are set */
/* Get tick */
tickstart = HAL_GetTick();
@@ -2498,7 +3344,7 @@
tmp3 = hi2c->State;
while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hi2c->State = HAL_I2C_STATE_TIMEOUT;
}
@@ -2513,13 +3359,13 @@
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
{
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Clear ADDR Flag */
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2534,13 +3380,13 @@
else
{
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Clear AF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2559,13 +3405,6 @@
return HAL_BUSY;
}
}
-/**
- * @}
- */
-
-/** @defgroup I2C_Exported_Functions_Group4 IRQ Handler and Callbacks
- * @{
- */
/**
* @brief This function handles I2C event interrupt request.
@@ -2575,25 +3414,41 @@
*/
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
{
- uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0, tmp4 = 0;
+ uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2);
+ uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
+ uint32_t itsources = READ_REG(hi2c->Instance->CR2);
+
+ uint32_t CurrentMode = hi2c->Mode;
+
/* Master or Memory mode selected */
- if((hi2c->Mode == HAL_I2C_MODE_MASTER) || \
- (hi2c->Mode == HAL_I2C_MODE_MEM))
+ if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
{
- /* I2C in mode Transmitter -----------------------------------------------*/
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == SET)
+ /* SB Set ----------------------------------------------------------------*/
+ if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
{
- tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE);
- tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
- tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
- tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
+ I2C_Master_SB(hi2c);
+ }
+ /* ADD10 Set -------------------------------------------------------------*/
+ else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ {
+ I2C_Master_ADD10(hi2c);
+ }
+ /* ADDR Set --------------------------------------------------------------*/
+ else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
+ {
+ I2C_Master_ADDR(hi2c);
+ }
+
+ /* I2C in mode Transmitter -----------------------------------------------*/
+ if((sr2itflags & I2C_FLAG_TRA) != RESET)
+ {
/* TXE set and BTF reset -----------------------------------------------*/
- if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+ if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
{
I2C_MasterTransmit_TXE(hi2c);
}
/* BTF set -------------------------------------------------------------*/
- else if((tmp3 == SET) && (tmp4 == SET))
+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
{
I2C_MasterTransmit_BTF(hi2c);
}
@@ -2601,17 +3456,13 @@
/* I2C in mode Receiver --------------------------------------------------*/
else
{
- tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE);
- tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
- tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
- tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
/* RXNE set and BTF reset -----------------------------------------------*/
- if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+ if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
{
I2C_MasterReceive_RXNE(hi2c);
}
/* BTF set -------------------------------------------------------------*/
- else if((tmp3 == SET) && (tmp4 == SET))
+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
{
I2C_MasterReceive_BTF(hi2c);
}
@@ -2620,34 +3471,26 @@
/* Slave mode selected */
else
{
- tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
- tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_EVT));
- tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
- tmp4 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA);
/* ADDR set --------------------------------------------------------------*/
- if((tmp1 == SET) && (tmp2 == SET))
+ if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
{
I2C_Slave_ADDR(hi2c);
}
/* STOPF set --------------------------------------------------------------*/
- else if((tmp3 == SET) && (tmp2 == SET))
+ else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
{
I2C_Slave_STOPF(hi2c);
}
/* I2C in mode Transmitter -----------------------------------------------*/
- else if(tmp4 == SET)
+ else if((sr2itflags & I2C_FLAG_TRA) != RESET)
{
- tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE);
- tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
- tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
- tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
/* TXE set and BTF reset -----------------------------------------------*/
- if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+ if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
{
I2C_SlaveTransmit_TXE(hi2c);
}
/* BTF set -------------------------------------------------------------*/
- else if((tmp3 == SET) && (tmp4 == SET))
+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
{
I2C_SlaveTransmit_BTF(hi2c);
}
@@ -2655,17 +3498,13 @@
/* I2C in mode Receiver --------------------------------------------------*/
else
{
- tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE);
- tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF);
- tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF);
- tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT);
/* RXNE set and BTF reset ----------------------------------------------*/
- if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET))
+ if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
{
I2C_SlaveReceive_RXNE(hi2c);
}
/* BTF set -------------------------------------------------------------*/
- else if((tmp3 == SET) && (tmp4 == SET))
+ else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
{
I2C_SlaveReceive_BTF(hi2c);
}
@@ -2675,32 +3514,30 @@
/**
* @brief This function handles I2C error interrupt request.
- * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for I2C module
- * @retval HAL status
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
*/
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
{
- uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
+ uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
+ uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
+ uint32_t itsources = READ_REG(hi2c->Instance->CR2);
- tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR);
- tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
/* I2C Bus error interrupt occurred ----------------------------------------*/
- if((tmp1 == SET) && (tmp2 == SET))
+ if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
/* Clear BERR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
-
+
/* Workaround: Start cannot be generated after a misplaced Stop */
SET_BIT(hi2c->Instance->CR1, I2C_CR1_SWRST);
}
- tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO);
- tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
/* I2C Arbitration Loss error interrupt occurred ---------------------------*/
- if((tmp1 == SET) && (tmp2 == SET))
+ if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
@@ -2708,49 +3545,47 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
}
- tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
- tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
/* I2C Acknowledge failure error interrupt occurred ------------------------*/
- if((tmp1 == SET) && (tmp2 == SET))
+ if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
{
tmp1 = hi2c->Mode;
tmp2 = hi2c->XferCount;
tmp3 = hi2c->State;
- if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0) && \
- (tmp3 == HAL_I2C_STATE_BUSY_TX))
+ tmp4 = hi2c->PreviousState;
+ if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
+ ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
+ ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
{
I2C_Slave_AF(hi2c);
}
else
{
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
- /* Generate Stop */
- SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
+
+ /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
+ if(hi2c->Mode == HAL_I2C_MODE_MASTER)
+ {
+ /* Generate Stop */
+ SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
+ }
+
/* Clear AF flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
}
}
- tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR);
- tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR);
/* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
- if((tmp1 == SET) && (tmp2 == SET))
+ if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
/* Clear OVR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
}
+ /* Call the Error Callback in case of Error detected -----------------------*/
if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
{
- hi2c->State = HAL_I2C_STATE_READY;
-
- /* Disable Pos bit in I2C CR1 when error occured in Master/Mem Receive IT Process */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
- HAL_I2C_ErrorCallback(hi2c);
+ I2C_ITError(hi2c);
}
}
@@ -2760,12 +3595,13 @@
* the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
+
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_TxCpltCallback could be implemented in the user file
+ the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
*/
}
@@ -2779,8 +3615,9 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
+
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_TxCpltCallback could be implemented in the user file
+ the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
*/
}
@@ -2789,12 +3626,13 @@
* the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
+
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_TxCpltCallback could be implemented in the user file
+ the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
*/
}
@@ -2808,8 +3646,45 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
+
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_TxCpltCallback could be implemented in the user file
+ the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Slave Address Match callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition
+ * @param AddrMatchCode Address Match Code
+ * @retval None
+ */
+__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+ UNUSED(TransferDirection);
+ UNUSED(AddrMatchCode);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_AddrCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Listen Complete callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_ListenCpltCallback can be implemented in the user file
*/
}
@@ -2819,12 +3694,13 @@
* the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
+
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_TxCpltCallback could be implemented in the user file
+ the HAL_I2C_MemTxCpltCallback can be implemented in the user file
*/
}
@@ -2838,8 +3714,9 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
+
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_TxCpltCallback could be implemented in the user file
+ the HAL_I2C_MemRxCpltCallback can be implemented in the user file
*/
}
@@ -2849,12 +3726,29 @@
* the configuration information for the specified I2C.
* @retval None
*/
- __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
+__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hi2c);
+
/* NOTE : This function should not be modified, when the callback is needed,
- the HAL_I2C_ErrorCallback could be implemented in the user file
+ the HAL_I2C_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief I2C abort callback.
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval None
+ */
+__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2c);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_I2C_AbortCpltCallback could be implemented in the user file
*/
}
@@ -2862,13 +3756,12 @@
* @}
*/
-
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
+/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+ * @brief Peripheral State and Errors functions
+ *
@verbatim
===============================================================================
- ##### Peripheral State and Errors functions #####
+ ##### Peripheral State, Mode and Error functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
@@ -2891,11 +3784,22 @@
}
/**
- * @brief Return the I2C error code.
+ * @brief Return the I2C Master, Slave, Memory or no mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
-* @retval I2C Error Code
-*/
+ * the configuration information for I2C module
+ * @retval HAL mode
+ */
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+{
+ return hi2c->Mode;
+}
+
+/**
+ * @brief Return the I2C error code
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval I2C Error Code
+ */
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
{
return hi2c->ErrorCode;
@@ -2906,146 +3810,306 @@
*/
/**
- * @}
- */
-
-/** @addtogroup I2C_Private_Functions
- * @{
- */
-
-/**
- * @brief Handle TXE flag for Master Transmit Mode
+ * @brief Handle TXE flag for Master
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
{
- if(hi2c->XferCount == 0)
- {
- /* Disable BUF interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
- }
- else
- {
- /* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- }
-
- return HAL_OK;
-}
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hi2c->State;
+ uint32_t CurrentMode = hi2c->Mode;
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
-/**
- * @brief Handle BTF flag for Master Transmit Mode
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @retval HAL status
- */
-static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
-{
- if(hi2c->XferCount != 0)
+ if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
{
- /* Write data to DR */
- hi2c->Instance->DR = (*hi2c->pBuffPtr++);
- hi2c->XferCount--;
- }
- else
- {
- /* Disable EVT, BUF and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- /* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ /* Call TxCpltCallback() directly if no stop mode is set */
+ if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
{
- hi2c->State = HAL_I2C_STATE_READY;
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
- HAL_I2C_MemTxCpltCallback(hi2c);
- }
- else
- {
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->State = HAL_I2C_STATE_READY;
HAL_I2C_MasterTxCpltCallback(hi2c);
}
+ else /* Generate Stop condition then Call TxCpltCallback() */
+ {
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ HAL_I2C_MemTxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+ }
+ }
+ else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
+ ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
+ {
+ if(hi2c->XferCount == 0U)
+ {
+ /* Disable BUF interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+ }
+ else
+ {
+ if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ if(hi2c->EventCount == 0)
+ {
+ /* If Memory address size is 8Bit */
+ if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
+ {
+ /* Send Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
+
+ hi2c->EventCount += 2;
+ }
+ /* If Memory address size is 16Bit */
+ else
+ {
+ /* Send MSB of Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
+
+ hi2c->EventCount++;
+ }
+ }
+ else if(hi2c->EventCount == 1)
+ {
+ /* Send LSB of Memory Address */
+ hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
+
+ hi2c->EventCount++;
+ }
+ else if(hi2c->EventCount == 2)
+ {
+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ /* Generate Restart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+ else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ }
+ }
+ }
+ else
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ }
+ }
}
return HAL_OK;
}
/**
- * @brief Handle RXNE flag for Master Receive Mode
+ * @brief Handle BTF flag for Master transmitter
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+ if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ if(hi2c->XferCount != 0U)
+ {
+ /* Write data to DR */
+ hi2c->Instance->DR = (*hi2c->pBuffPtr++);
+ hi2c->XferCount--;
+ }
+ else
+ {
+ /* Call TxCpltCallback() directly if no stop mode is set */
+ if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
+ {
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+ else /* Generate Stop condition then Call TxCpltCallback() */
+ {
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ HAL_I2C_MemTxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ HAL_I2C_MasterTxCpltCallback(hi2c);
+ }
+ }
+ }
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle RXNE flag for Master
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
{
- uint32_t tmp = 0;
-
- tmp = hi2c->XferCount;
- if(tmp > 3)
+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferCount--;
- }
- else if((tmp == 2) || (tmp == 3))
- {
- /* Disable BUF interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
- }
- else
- {
- /* Disable EVT, BUF and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
- /* Read data from DR */
- (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
- hi2c->XferCount--;
-
- if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ uint32_t tmp = 0U;
+
+ tmp = hi2c->XferCount;
+ if(tmp > 3U)
{
- hi2c->State = HAL_I2C_STATE_READY;
-
- HAL_I2C_MemRxCpltCallback(hi2c);
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+ }
+ else if((tmp == 2U) || (tmp == 3U))
+ {
+ if(hi2c->XferOptions != I2C_NEXT_FRAME)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Enable Pos */
+ hi2c->Instance->CR1 |= I2C_CR1_POS;
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ }
+
+ /* Disable BUF interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
}
else
{
+ if(hi2c->XferOptions != I2C_NEXT_FRAME)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ }
+
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+
hi2c->State = HAL_I2C_STATE_READY;
- HAL_I2C_MasterRxCpltCallback(hi2c);
+ if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ HAL_I2C_MemRxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+ }
}
}
return HAL_OK;
}
/**
- * @brief Handle BTF flag for Master Receive Mode
+ * @brief Handle BTF flag for Master receiver
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
{
- if(hi2c->XferCount == 3)
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+ if(hi2c->XferCount == 3U)
{
- /* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ }
/* Read data from DR */
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
hi2c->XferCount--;
}
- else if(hi2c->XferCount == 2)
+ else if(hi2c->XferCount == 2U)
{
- /* Disable EVT and ERR interrupt */
- /* Workaround - Wong data read into data register */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+ /* Prepare next transfer or stop current transfer */
+ if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
+ {
+ if(CurrentXferOptions != I2C_NEXT_FRAME)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ }
- /* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ /* Disable EVT and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+ }
+ else
+ {
+ /* Disable EVT and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ }
/* Read data from DR */
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
@@ -3055,15 +4119,19 @@
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
hi2c->XferCount--;
+ hi2c->State = HAL_I2C_STATE_READY;
+
if(hi2c->Mode == HAL_I2C_MODE_MEM)
{
- hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
HAL_I2C_MemRxCpltCallback(hi2c);
}
else
{
- hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
HAL_I2C_MasterRxCpltCallback(hi2c);
}
@@ -3078,31 +4146,263 @@
}
/**
- * @brief Handle TXE flag for Slave Transmit Mode
+ * @brief Handle SB flag for Master
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
+{
+ if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ if(hi2c->EventCount == 0U)
+ {
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
+ }
+ else
+ {
+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
+ }
+ }
+ else
+ {
+ if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ {
+ /* Send slave 7 Bits address */
+ if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ {
+ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
+ }
+ else
+ {
+ hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
+ }
+ }
+ else
+ {
+ if(hi2c->EventCount == 0U)
+ {
+ /* Send header of slave address */
+ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
+ }
+ else if(hi2c->EventCount == 1U)
+ {
+ /* Send header of slave address */
+ hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle ADD10 flag for Master
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
+{
+ /* Send slave address */
+ hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle ADDR flag for Master
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ uint32_t CurrentMode = hi2c->Mode;
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
+ uint32_t Prev_State = hi2c->PreviousState;
+
+ if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ {
+ if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+ else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Restart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+
+ hi2c->EventCount++;
+ }
+ else
+ {
+ if(hi2c->XferCount == 0U)
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ }
+ else if(hi2c->XferCount == 1U)
+ {
+ if(CurrentXferOptions == I2C_NO_OPTION_FRAME)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+ else
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ }
+ }
+ /* Prepare next transfer or stop current transfer */
+ else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
+ && (Prev_State != I2C_STATE_MASTER_BUSY_RX))
+ {
+ if(hi2c->XferOptions != I2C_NEXT_FRAME)
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+ else
+ {
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+ }
+ }
+ else if(hi2c->XferCount == 2U)
+ {
+ if(hi2c->XferOptions != I2C_NEXT_FRAME)
+ {
+ /* Enable Pos */
+ hi2c->Instance->CR1 |= I2C_CR1_POS;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+
+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ {
+ /* Enable Last DMA bit */
+ hi2c->Instance->CR2 |= I2C_CR2_LAST;
+ }
+ }
+ else
+ {
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ {
+ /* Enable Last DMA bit */
+ hi2c->Instance->CR2 |= I2C_CR2_LAST;
+ }
+
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+
+ /* Reset Event counter */
+ hi2c->EventCount = 0U;
+ }
+ }
+ else
+ {
+ /* Clear ADDR flag */
+ __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle TXE flag for Slave
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
{
- if(hi2c->XferCount != 0)
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hi2c->State;
+
+ if(hi2c->XferCount != 0U)
{
/* Write data to DR */
hi2c->Instance->DR = (*hi2c->pBuffPtr++);
hi2c->XferCount--;
+
+ if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ /* Last Byte is received, disable Interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+
+ /* Set state at HAL_I2C_STATE_LISTEN */
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+
+ /* Call the Tx complete callback to inform upper layer of the end of receive process */
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+ }
}
return HAL_OK;
}
/**
- * @brief Handle BTF flag for Slave Transmit Mode
+ * @brief Handle BTF flag for Slave transmitter
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
{
- if(hi2c->XferCount != 0)
+ if(hi2c->XferCount != 0U)
{
/* Write data to DR */
hi2c->Instance->DR = (*hi2c->pBuffPtr++);
@@ -3112,31 +4412,47 @@
}
/**
- * @brief Handle RXNE flag for Slave Receive Mode
+ * @brief Handle RXNE flag for Slave
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
{
- if(hi2c->XferCount != 0)
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hi2c->State;
+
+ if(hi2c->XferCount != 0U)
{
/* Read data from DR */
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
hi2c->XferCount--;
+
+ if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ /* Last Byte is received, disable Interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
+
+ /* Set state at HAL_I2C_STATE_LISTEN */
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+
+ /* Call the Rx complete callback to inform upper layer of the end of receive process */
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+ }
}
return HAL_OK;
}
/**
- * @brief Handle BTF flag for Slave Receive Mode
+ * @brief Handle BTF flag for Slave receiver
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
{
- if(hi2c->XferCount != 0)
+ if(hi2c->XferCount != 0U)
{
/* Read data from DR */
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
@@ -3148,25 +4464,46 @@
/**
* @brief Handle ADD flag for Slave
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
{
- /* Clear ADDR flag */
- __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
+ uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
+ uint16_t SlaveAddrCode = 0U;
+
+ /* Transfer Direction requested by Master */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET)
+ {
+ TransferDirection = I2C_DIRECTION_TRANSMIT;
+ }
+
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET)
+ {
+ SlaveAddrCode = hi2c->Init.OwnAddress1;
+ }
+ else
+ {
+ SlaveAddrCode = hi2c->Init.OwnAddress2;
+ }
+
+ /* Call Slave Addr callback */
+ HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
return HAL_OK;
}
/**
- * @brief Handle STOPF flag for Slave Mode
+ * @brief Handle STOPF flag for Slave
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
{
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hi2c->State;
+
/* Disable EVT, BUF and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -3174,54 +4511,288 @@
__HAL_I2C_CLEAR_STOPFLAG(hi2c);
/* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- hi2c->State = HAL_I2C_STATE_READY;
+ /* If a DMA is ongoing, Update handle size context */
+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ {
+ if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+ }
+ else
+ {
+ hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+ }
+ }
- HAL_I2C_SlaveRxCpltCallback(hi2c);
+ /* All data are not transferred, so set error code accordingly */
+ if(hi2c->XferCount != 0U)
+ {
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+ }
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ hi2c->XferCount--;
+ }
+
+ /* Set ErrorCode corresponding to a Non-Acknowledge */
+ hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+ }
+
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ {
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ I2C_ITError(hi2c);
+ }
+ else
+ {
+ if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \
+ (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ {
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ HAL_I2C_ListenCpltCallback(hi2c);
+ }
+ else
+ {
+ if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
+ {
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ HAL_I2C_SlaveRxCpltCallback(hi2c);
+ }
+ }
+ }
return HAL_OK;
}
/**
- * @brief Handle Acknowledge Failed for Slave Mode
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for I2C module
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
{
- /* Disable EVT, BUF and ERR interrupt */
- __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+ /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hi2c->State;
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
- /* Clear AF flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
+ (CurrentState == HAL_I2C_STATE_LISTEN))
+ {
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- /* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
- hi2c->State = HAL_I2C_STATE_READY;
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- HAL_I2C_SlaveTxCpltCallback(hi2c);
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ HAL_I2C_ListenCpltCallback(hi2c);
+ }
+ else if(CurrentState == HAL_I2C_STATE_BUSY_TX)
+ {
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Disable EVT, BUF and ERR interrupt */
+ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
+
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ HAL_I2C_SlaveTxCpltCallback(hi2c);
+ }
+ else
+ {
+ /* Clear AF flag only */
+ /* State Listen, but XferOptions == FIRST or NEXT */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+ }
+
return HAL_OK;
}
/**
- * @brief Master sends target device address followed by internal memory address for write request.
+ * @brief I2C interrupts error process
+ * @param hi2c I2C handle.
+ * @retval None
+ */
+static void I2C_ITError(I2C_HandleTypeDef *hi2c)
+{
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hi2c->State;
+
+ if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ {
+ /* keep HAL_I2C_STATE_LISTEN */
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_LISTEN;
+ }
+ else
+ {
+ /* If state is an abort treatment on going, don't change state */
+ /* This change will be do later */
+ if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN))
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ }
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ }
+
+ /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
+ hi2c->Instance->CR1 &= ~I2C_CR1_POS;
+
+ /* Abort DMA transfer */
+ if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
+ {
+ hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+
+ if(hi2c->hdmatx->State != HAL_DMA_STATE_READY)
+ {
+ /* Set the DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
+
+ if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ {
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Call Directly XferAbortCallback function in case of error */
+ hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
+ }
+ }
+ else
+ {
+ /* Set the DMA Abort callback :
+ will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
+
+ if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ {
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ }
+
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
+
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
+ hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
+ }
+ }
+ }
+ else if(hi2c->State == HAL_I2C_STATE_ABORT)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ }
+
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_AbortCpltCallback(hi2c);
+ }
+ else
+ {
+ /* Store Last receive data if any */
+ if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ {
+ /* Read data from DR */
+ (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
+ }
+
+ /* Call user error callback */
+ HAL_I2C_ErrorCallback(hi2c);
+ }
+ /* STOP Flag is not set after a NACK reception */
+ /* So may inform upper layer that listen phase is stopped */
+ /* during NACK error treatment */
+ if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF))
+ {
+ hi2c->XferOptions = I2C_NO_OPTION_FRAME;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
+ HAL_I2C_ListenCpltCallback(hi2c);
+ }
+}
+
+/**
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address
+ * the configuration information for I2C module
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param Timeout Timeout duration
+ * @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
{
- /* Generate Start */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
+
+ /* Generate Start condition if first transfer */
+ if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
+ {
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
+ {
+ /* Generate ReStart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
/* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -3237,7 +4808,7 @@
hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
/* Wait until ADD10 flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -3254,7 +4825,7 @@
}
/* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -3270,23 +4841,37 @@
}
/**
- * @brief Master sends target device address followed by internal memory address for read request.
+ * @brief Master sends target device address for read request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param DevAddress Target device address
+ * the configuration information for I2C module
+ * @param DevAddress Target device address: The device 7 bits address value
+ * in datasheet must be shift at right before call interface
* @param Timeout Timeout duration
+ * @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
{
- /* Enable Acknowledge */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ uint32_t CurrentXferOptions = hi2c->XferOptions;
- /* Generate Start */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+ /* Enable Acknowledge */
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
+
+ /* Generate Start condition if first transfer */
+ if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
+ {
+ /* Generate Start */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
+ else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+ {
+ /* Generate ReStart */
+ hi2c->Instance->CR1 |= I2C_CR1_START;
+ }
/* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -3302,7 +4887,7 @@
hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
/* Wait until ADD10 flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -3318,7 +4903,7 @@
hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
/* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -3334,10 +4919,10 @@
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Generate Restart */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+ hi2c->Instance->CR1 |= I2C_CR1_START;
/* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -3347,7 +4932,7 @@
}
/* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -3365,20 +4950,21 @@
/**
* @brief Master sends target device address followed by internal memory address for write request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for I2C module
* @param DevAddress Target device address
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
+ * @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
/* Generate Start */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+ hi2c->Instance->CR1 |= I2C_CR1_START;
/* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -3387,7 +4973,7 @@
hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
/* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -3403,12 +4989,12 @@
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
return HAL_ERROR;
}
else
@@ -3430,12 +5016,12 @@
hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
return HAL_ERROR;
}
else
@@ -3454,23 +5040,24 @@
/**
* @brief Master sends target device address followed by internal memory address for read request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
+ * the configuration information for I2C module
* @param DevAddress Target device address
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
+ * @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
/* Enable Acknowledge */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
+ hi2c->Instance->CR1 |= I2C_CR1_ACK;
/* Generate Start */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+ hi2c->Instance->CR1 |= I2C_CR1_START;
/* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -3479,7 +5066,7 @@
hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
/* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -3495,12 +5082,12 @@
__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
/* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
return HAL_ERROR;
}
else
@@ -3522,12 +5109,12 @@
hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
return HAL_ERROR;
}
else
@@ -3541,12 +5128,12 @@
}
/* Wait until TXE flag is set */
- if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK)
+ if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
return HAL_ERROR;
}
else
@@ -3556,10 +5143,10 @@
}
/* Generate Restart */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
+ hi2c->Instance->CR1 |= I2C_CR1_START;
/* Wait until SB flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
+ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -3568,7 +5155,7 @@
hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
/* Wait until ADDR flag is set */
- if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
+ if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
{
if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
@@ -3584,400 +5171,194 @@
}
/**
- * @brief DMA I2C master transmit process complete callback.
- * @param hdma: DMA handle
+ * @brief DMA I2C process complete callback.
+ * @param hdma DMA handle
* @retval None
*/
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
+static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
{
I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Wait until BTF flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
- /* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
- /* Disable DMA Request */
- CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
- hi2c->XferCount = 0;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- HAL_I2C_MasterTxCpltCallback(hi2c);
- }
-}
-
-/**
- * @brief DMA I2C slave transmit process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Wait until AF flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
- /* Clear AF flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Disable Address Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
- /* Disable DMA Request */
- CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
- hi2c->XferCount = 0;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- HAL_I2C_SlaveTxCpltCallback(hi2c);
- }
-}
-
-/**
- * @brief DMA I2C master receive process complete callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
- /* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
- /* Disable Last DMA */
- CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
-
- /* Disable DMA Request */
- CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
- hi2c->XferCount = 0;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- HAL_I2C_MasterRxCpltCallback(hi2c);
- }
-}
-
-/**
- * @brief DMA I2C slave receive process complete callback.
- * @param hdma: DMA handle
- * @retval None
- */
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- }
- else
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
- }
-
- /* Clear STOPF flag */
- __HAL_I2C_CLEAR_STOPFLAG(hi2c);
-
- /* Disable Address Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
- /* Disable DMA Request */
- CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
- hi2c->XferCount = 0;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- HAL_I2C_SlaveRxCpltCallback(hi2c);
- }
-}
-
-/**
- * @brief DMA I2C Memory Write process complete callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Wait until BTF flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
- {
- hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- }
-
- /* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
- /* Disable DMA Request */
- CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
- hi2c->XferCount = 0;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- HAL_I2C_MemTxCpltCallback(hi2c);
- }
-}
-
-/**
- * @brief DMA I2C Memory Read process complete callback
- * @param hdma: DMA handle
- * @retval None
- */
-static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
- /* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-
- /* Disable Last DMA */
- CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
-
- /* Disable DMA Request */
- CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
- hi2c->XferCount = 0;
-
- hi2c->State = HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Check if Errors has been detected during transfer */
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
- {
- HAL_I2C_ErrorCallback(hi2c);
- }
- else
- {
- HAL_I2C_MemRxCpltCallback(hi2c);
- }
-}
-
-/**
- * @brief I2C Configuration Speed function
- * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param I2CClkSrcFreq: PCLK frequency from RCC.
- * @retval CCR Speed: Speed to set in I2C CCR Register
- */
-static uint32_t I2C_Configure_Speed(I2C_HandleTypeDef *hi2c, uint32_t I2CClkSrcFreq)
-{
- uint32_t tmp1 = 0;
- /* Clock Standard Mode */
- if(hi2c->Init.ClockSpeed <= I2C_STANDARD_MODE_MAX_CLK)
+ /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
+ uint32_t CurrentState = hi2c->State;
+ uint32_t CurrentMode = hi2c->Mode;
+
+ if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
{
- /* Calculate Value to be set in CCR register */
- tmp1 = (I2CClkSrcFreq/(hi2c->Init.ClockSpeed << 1));
+ /* Disable DMA Request */
+ hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
- /* The minimum allowed value set in CCR register is 0x04 for Standard Mode */
- if( (tmp1 & I2C_CCR_CCR) < 4 )
- {
- return 4;
- }
- else
- {
- return tmp1;
- }
+ hi2c->XferCount = 0U;
+
+ /* Enable EVT and ERR interrupt */
+ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
}
else
{
- /* Clock Fast Mode */
- tmp1 = I2C_CCR_FS;
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
- /* Duty Cylce tLow/tHigh = 2 */
- if(hi2c->Init.DutyCycle == I2C_DUTYCYCLE_2)
- {
- tmp1 |= (I2CClkSrcFreq/(hi2c->Init.ClockSpeed * 3)) | I2C_DUTYCYCLE_2;
- }
- else /* Duty Cylce tLow/tHigh = 16/9 */
- {
- tmp1 |= (I2CClkSrcFreq/(hi2c->Init.ClockSpeed * 25)) | I2C_DUTYCYCLE_16_9;
- }
+ /* Generate Stop */
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
+
+ /* Disable Last DMA */
+ hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
+
+ /* Disable DMA Request */
+ hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
+
+ hi2c->XferCount = 0U;
- /* The minimum allowed value set in CCR register is 0x01 for Fast Mode */
- if( (tmp1 & I2C_CCR_CCR) < 1 )
+ /* Check if Errors has been detected during transfer */
+ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
{
- return 1;
+ HAL_I2C_ErrorCallback(hi2c);
}
else
{
- return tmp1;
+ hi2c->State = HAL_I2C_STATE_READY;
+
+ if(hi2c->Mode == HAL_I2C_MODE_MEM)
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ HAL_I2C_MemRxCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ HAL_I2C_MasterRxCpltCallback(hi2c);
+ }
}
}
}
/**
* @brief DMA I2C communication error callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void I2C_DMAError(DMA_HandleTypeDef *hdma)
{
I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
+
/* Disable Acknowledge */
- CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
- hi2c->XferCount = 0;
-
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ hi2c->XferCount = 0U;
+
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
-
+
hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+ HAL_I2C_ErrorCallback(hi2c);
+}
- HAL_I2C_ErrorCallback(hi2c);
+/**
+ * @brief DMA I2C communication abort callback
+ * (To be called at end of DMA Abort procedure).
+ * @param hdma: DMA handle.
+ * @retval None
+ */
+static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
+{
+ I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable Acknowledge */
+ hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
+
+ hi2c->XferCount = 0U;
+
+ /* Reset XferAbortCallback */
+ hi2c->hdmatx->XferAbortCallback = NULL;
+ hi2c->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if come from abort from user */
+ if(hi2c->State == HAL_I2C_STATE_ABORT)
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_AbortCpltCallback(hi2c);
+ }
+ else
+ {
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Disable I2C peripheral to prevent dummy data in buffer */
+ __HAL_I2C_DISABLE(hi2c);
+
+ /* Call the corresponding callback to inform upper layer of End of Transfer */
+ HAL_I2C_ErrorCallback(hi2c);
+ }
}
/**
* @brief This function handles I2C Communication Timeout.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Flag: specifies the I2C flag to check.
- * @param Status: The new Flag status (SET or RESET).
+ * the configuration information for I2C module
+ * @param Flag specifies the I2C flag to check.
+ * @param Status The new Flag status (SET or RESET).
* @param Timeout Timeout duration
+ * @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
- uint32_t tickstart = 0;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
/* Wait until flag is set */
- if(Status == RESET)
+ while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)
{
- while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->PreviousState = I2C_STATE_NONE;
+ hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_TIMEOUT;
}
}
}
- else
- {
- while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hi2c->State= HAL_I2C_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
+
return HAL_OK;
}
/**
* @brief This function handles I2C Communication Timeout for Master addressing phase.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
- * the configuration information for the specified I2C.
- * @param Flag: specifies the I2C flag to check.
+ * the configuration information for I2C module
+ * @param Flag specifies the I2C flag to check.
* @param Timeout Timeout duration
+ * @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
{
- uint32_t tickstart = 0;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
{
if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
{
/* Generate Stop */
- SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
+ hi2c->Instance->CR1 |= I2C_CR1_STOP;
/* Clear AF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State= HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -3989,8 +5370,9 @@
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
{
+ hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State= HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -4008,12 +5390,11 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Timeout Timeout duration
+ * @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
-{
- uint32_t tickstart = HAL_GetTick();
-
+static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+{
while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
{
/* Check if a NACK is detected */
@@ -4025,9 +5406,10 @@
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State= HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -4045,12 +5427,11 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Timeout Timeout duration
+ * @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- uint32_t tickstart = HAL_GetTick();
-
while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
{
/* Check if a NACK is detected */
@@ -4058,13 +5439,14 @@
{
return HAL_ERROR;
}
-
+
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State= HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -4074,7 +5456,7 @@
}
}
}
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -4082,13 +5464,11 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Timeout Timeout duration
+ * @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- uint32_t tickstart = 0x00;
- tickstart = HAL_GetTick();
-
while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
{
/* Check if a NACK is detected */
@@ -4096,11 +5476,12 @@
{
return HAL_ERROR;
}
-
+
/* Check for the Timeout */
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+ hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State= HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -4117,13 +5498,12 @@
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Timeout Timeout duration
+ * @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout)
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- uint32_t tickstart = 0x00;
- tickstart = HAL_GetTick();
-
+
while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
{
/* Check if a STOPF is detected */
@@ -4133,6 +5513,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State= HAL_I2C_STATE_READY;
/* Process Unlocked */
@@ -4140,9 +5521,9 @@
return HAL_ERROR;
}
-
+
/* Check for the Timeout */
- if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State= HAL_I2C_STATE_READY;
@@ -4170,6 +5551,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+ hi2c->PreviousState = I2C_STATE_NONE;
hi2c->State= HAL_I2C_STATE_READY;
/* Process Unlocked */
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2s.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2s.c
index 98d824c..57cd581 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2s.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_i2s.c
@@ -2,10 +2,10 @@
******************************************************************************
* @file stm32f1xx_hal_i2s.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief I2S HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
@@ -16,10 +16,10 @@
===============================================================================
[..]
The I2S HAL driver can be used as follow:
-
+
(#) Declare a I2S_HandleTypeDef handle structure.
(#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
- (##) Enable the SPIx interface clock.
+ (##) Enable the SPIx interface clock.
(##) I2S pins configuration:
(+++) Enable the clock for the I2S GPIOs.
(+++) Configure these I2S pins as alternate function.
@@ -33,14 +33,14 @@
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx Channel.
- (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
+ (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
DMA Tx/Rx Channel.
(#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
using HAL_I2S_Init() function.
- -@- The specific I2S interrupts (Transmission complete interrupt,
+ -@- The specific I2S interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
-@- The I2SxCLK source is the system clock (provided by the HSI, the HSE or the PLL, and sourcing the AHB clock).
@@ -50,44 +50,44 @@
(+@) External clock source is configured after setting correctly
the define constant HSE_VALUE in the stm32f1xx_hal_conf.h file.
- (#) Three mode of operations are available within this driver :
+ (#) Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
(+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
-
+
*** Interrupt mode IO operation ***
===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
- (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
- (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
- (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2S_ErrorCallback
*** DMA mode IO operation ***
==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
- (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
- (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
- (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
+ (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxCpltCallback
- (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
+ (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2S_ErrorCallback
(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
@@ -96,9 +96,9 @@
*** I2S HAL driver macros list ***
=============================================
[..]
- Below the list of most used macros in USART HAL driver.
-
- (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
+ Below the list of most used macros in I2S HAL driver.
+
+ (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
(+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
@@ -119,7 +119,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -144,7 +144,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
@@ -152,7 +152,7 @@
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
-
+
#ifdef HAL_I2S_MODULE_ENABLED
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
@@ -170,52 +170,54 @@
* @{
*/
static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
static void I2S_DMAError(DMA_HandleTypeDef *hdma);
static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
+static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State,
+ uint32_t Timeout);
/**
* @}
*/
-
+
/* Exported functions ---------------------------------------------------------*/
/** @defgroup I2S_Exported_Functions I2S Exported Functions
* @{
*/
/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the I2Sx peripheral in simplex mode:
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the I2Sx peripheral in simplex mode:
- (+) User must Implement HAL_I2S_MspInit() function in which he configures
+ (+) User must Implement HAL_I2S_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
- (+) Call the function HAL_I2S_Init() to configure the selected device with
+ (+) Call the function HAL_I2S_Init() to configure the selected device with
the selected configuration:
(++) Mode
- (++) Standard
+ (++) Standard
(++) Data Format
(++) MCLK Output
(++) Audio frequency
(++) Polarity
- (+) Call the function HAL_I2S_DeInit() to restore the default configuration
- of the selected I2Sx periperal.
- @endverbatim
+ (+) Call the function HAL_I2S_DeInit() to restore the default configuration
+ of the selected I2Sx peripheral.
+@endverbatim
* @{
*/
/**
- * @brief Initializes the I2S according to the specified parameters
+ * @brief Initializes the I2S according to the specified parameters
* in the I2S_InitTypeDef and create the associated handle.
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
@@ -223,15 +225,15 @@
*/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
{
- uint32_t i2sdiv = 2, i2sodd = 0, packetlength = 1;
- uint32_t tmp = 0, i2sclk = 0;
-
+ uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 16U;
+ uint32_t tmp = 0U, i2sclk = 0U;
+
/* Check the I2S handle allocation */
if(hi2s == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the I2S parameters */
assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
assert_param(IS_I2S_MODE(hi2s->Init.Mode));
@@ -239,40 +241,50 @@
assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
- assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
-
- if(hi2s->State == HAL_I2S_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hi2s->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
- HAL_I2S_MspInit(hi2s);
- }
-
+ assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
+
hi2s->State = HAL_I2S_STATE_BUSY;
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
- if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
- {
- i2sodd = (uint32_t)0;
- i2sdiv = (uint32_t)2;
- }
+ /* Initialize Default I2S IrqHandler ISR */
+ hi2s->IrqHandlerISR = I2S_IRQHandler;
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_I2S_MspInit(hi2s);
+
+ /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+ CLEAR_BIT(hi2s->Instance->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
+ SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
+ SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
+ hi2s->Instance->I2SPR = 0x0002U;
+
+ /* Get the I2SCFGR register value */
+ tmpreg = hi2s->Instance->I2SCFGR;
+
+ /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
/* If the requested audio frequency is not the default, compute the prescaler */
- else
+ if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
{
/* Check the frame length (For the Prescaler computing) *******************/
- if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
+ /* Set I2S Packet Length value*/
+ if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
{
- /* Packet length is 16 bits */
- packetlength = 1;
+ /* Packet length is 32 bits */
+ packetlength = 32U;
}
else
{
- /* Packet length is 32 bits */
- packetlength = 2;
+ /* Packet length is 16 bits */
+ packetlength = 16U;
}
-
+
+ /* I2S standard */
+ if(hi2s->Init.Standard <= I2S_STANDARD_LSB)
+ {
+ /* In I2S standard packet lenght is multiplied by 2 */
+ packetlength = packetlength * 2U;
+ }
+
if(hi2s->Instance == SPI2)
{
/* Get the source clock value: based on SPI2 Instance */
@@ -286,68 +298,71 @@
else
{
/* Get the source clock value: based on System Clock value */
- i2sclk = HAL_RCC_GetSysClockFreq();
+ i2sclk = HAL_RCC_GetSysClockFreq();
}
- if(i2sclk == 0)
- {
- return HAL_ERROR;
- }
-
+
/* Compute the Real divider depending on the MCLK output state, with a floating point */
if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
{
/* MCLK output is enabled */
- tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
+ if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
+ {
+ tmp = (uint32_t)(((((i2sclk / (packetlength*4)) * 10) / hi2s->Init.AudioFreq)) + 5);
+ }
+ else
+ {
+ tmp = (uint32_t)(((((i2sclk / (packetlength*8)) * 10) / hi2s->Init.AudioFreq)) + 5);
+ }
}
else
{
/* MCLK output is disabled */
- tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
+ tmp = (uint32_t)(((((i2sclk / packetlength) *10 ) / hi2s->Init.AudioFreq)) + 5);
}
/* Remove the flatting point */
- tmp = tmp / 10;
+ tmp = tmp / 10U;
/* Check the parity of the divider */
- i2sodd = (uint32_t)(tmp & (uint32_t)1);
+ i2sodd = (uint16_t)(tmp & (uint16_t)1U);
/* Compute the i2sdiv prescaler */
- i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint32_t) (i2sodd << 8);
+ i2sodd = (uint32_t) (i2sodd << 8U);
}
/* Test if the divider is 1 or 0 or greater than 0xFF */
- if((i2sdiv < 2) || (i2sdiv > 0xFF))
+ if((i2sdiv < 2U) || (i2sdiv > 0xFFU))
{
/* Set the default values */
- i2sdiv = 2;
- i2sodd = 0;
- }
+ i2sdiv = 2U;
+ i2sodd = 0U;
- /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- /* And configure the I2S with the I2S_InitStruct values */
- MODIFY_REG( hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN |\
- SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD |\
- SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG |\
- SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD),\
- (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode |\
- hi2s->Init.Standard | hi2s->Init.DataFormat |\
- hi2s->Init.CPOL));
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
+ HAL_I2S_ErrorCallback(hi2s);
+ return HAL_ERROR;
+ }
/* Write to SPIx I2SPR register the computed value */
hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
+ /* Configure the I2S with the I2S_InitStruct values */
+ tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
+ (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
+ (uint16_t)hi2s->Init.CPOL))));
+ /* Write to SPIx I2SCFGR */
+ WRITE_REG(hi2s->Instance->I2SCFGR,tmpreg);
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State= HAL_I2S_STATE_READY;
+ hi2s->State = HAL_I2S_STATE_READY;
return HAL_OK;
}
/**
- * @brief DeInitializes the I2S peripheral
+ * @brief DeInitializes the I2S peripheral
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
@@ -359,17 +374,14 @@
{
return HAL_ERROR;
}
-
+
hi2s->State = HAL_I2S_STATE_BUSY;
-
- /* Disable the I2S Peripheral Clock */
- __HAL_I2S_DISABLE(hi2s);
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_I2S_MspDeInit(hi2s);
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_RESET;
+ hi2s->State = HAL_I2S_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hi2s);
@@ -389,7 +401,7 @@
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspInit could be implemented in the user file
- */
+ */
}
/**
@@ -404,9 +416,8 @@
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspDeInit could be implemented in the user file
- */
+ */
}
-
/**
* @}
*/
@@ -414,28 +425,28 @@
/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
- This subsection provides a set of functions allowing to manage the I2S data
+ This subsection provides a set of functions allowing to manage the I2S data
transfers.
(#) There are two modes of transfer:
- (++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode : The communication is performed using Interrupts
+ (++) Blocking mode : The communication is performed in the polling mode.
+ The status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode : The communication is performed using Interrupts
or DMA. These functions return the status of the transfer startup.
- The end of the data processing will be indicated through the
- dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
+ The end of the data processing will be indicated through the
+ dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
(#) Blocking mode functions are :
(++) HAL_I2S_Transmit()
(++) HAL_I2S_Receive()
-
+
(#) No-Blocking mode functions with Interrupt are :
(++) HAL_I2S_Transmit_IT()
(++) HAL_I2S_Receive_IT()
@@ -460,195 +471,200 @@
* @param pData: a 16-bit pointer to data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
* @param Timeout: Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
- if((pData == NULL ) || (Size == 0))
+ uint32_t tmp1 = 0U;
+
+ if((pData == NULL ) || (Size == 0U))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
if(hi2s->State == HAL_I2S_STATE_READY)
- {
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
- hi2s->TxXferSize = (Size << 1);
- hi2s->TxXferCount = (Size << 1);
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
}
else
{
- hi2s->TxXferSize = Size;
+ hi2s->TxXferSize = Size;
hi2s->TxXferCount = Size;
}
-
- /* Set state and reset error code */
+
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->pTxBuffPtr = pData;
-
- /* Check if the I2S is already enabled */
- if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
-
- while(hi2s->TxXferCount > 0)
+
+ while(hi2s->TxXferCount > 0U)
{
+ hi2s->Instance->DR = (*pData++);
+ hi2s->TxXferCount--;
+
/* Wait until TXE flag is set */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
{
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
+ HAL_I2S_ErrorCallback(hi2s);
return HAL_TIMEOUT;
}
- hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
- hi2s->TxXferCount--;
/* Check if an underrun occurs */
- if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
{
+ /* Clear underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
/* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
+ hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
/* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ HAL_I2S_ErrorCallback(hi2s);
+
return HAL_ERROR;
}
- }
-
- /* Wait until TXE flag is set, to confirm the end of the transcation */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- /* Check if Slave mode is selected */
- if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
- {
- /* Wait until Busy flag is reset */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
}
- hi2s->State = HAL_I2S_STATE_READY;
-
+ hi2s->State = HAL_I2S_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
-
+
return HAL_OK;
}
else
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
}
/**
- * @brief Receive an amount of data in blocking mode
+ * @brief Receive an amount of data in blocking mode
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData: a 16-bit pointer to data buffer.
+ * @param pData: a 16-bit pointer to data buffer
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
* @param Timeout: Timeout duration
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
- * between Master and Slave(example: audio streaming).
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * between Master and Slave(example: audio streaming)
* @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
- * in continouse way and as the I2S is not disabled at the end of the I2S transaction.
+ * in continuous way and as the I2S is not disabled at the end of the I2S transaction
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
- if((pData == NULL ) || (Size == 0))
+ uint32_t tmp1 = 0U;
+
+ if((pData == NULL ) || (Size == 0U))
{
return HAL_ERROR;
}
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
+
if(hi2s->State == HAL_I2S_STATE_READY)
- {
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ {
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
- hi2s->RxXferSize = (Size << 1);
- hi2s->RxXferCount = (Size << 1);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
}
else
{
- hi2s->RxXferSize = Size;
+ hi2s->RxXferSize = Size;
hi2s->RxXferCount = Size;
}
-
- /* Set state and reset error code */
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
- hi2s->pRxBuffPtr = pData;
-
- /* Check if the I2S is already enabled */
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+
+ /* Check if the I2S is already enabled */
if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
-
- /* Receive data */
- while(hi2s->RxXferCount > 0)
+
+ /* Check if Master Receiver mode is selected */
+ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
{
- /* Wait until RXNE flag is reset */
- if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
+ access to the SPI_SR register. */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+ }
+
+ /* Receive data */
+ while(hi2s->RxXferCount > 0U)
+ {
+ /* Wait until RXNE flag is set */
+ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
{
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT);
+ HAL_I2S_ErrorCallback(hi2s);
return HAL_TIMEOUT;
}
-
- (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
- hi2s->RxXferCount--;
/* Check if an overrun occurs */
- if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
+ if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
{
+ /* Clear overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
/* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
+ hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
/* Set the error code and execute error callback*/
- hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
+ HAL_I2S_ErrorCallback(hi2s);
+
return HAL_ERROR;
}
+
+ (*pData++) = hi2s->Instance->DR;
+ hi2s->RxXferCount--;
}
-
- hi2s->State = HAL_I2S_STATE_READY;
-
+
+ hi2s->State = HAL_I2S_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
-
+
return HAL_OK;
}
else
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
}
@@ -660,45 +676,47 @@
* @param pData: a 16-bit pointer to data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
+ uint32_t tmp1 = 0U;
+
if(hi2s->State == HAL_I2S_STATE_READY)
{
- hi2s->pTxBuffPtr = pData;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ if((pData == NULL) || (Size == 0U))
{
- hi2s->TxXferSize = (Size << 1);
- hi2s->TxXferCount = (Size << 1);
+ return HAL_ERROR;
+ }
+
+ hi2s->pTxBuffPtr = pData;
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
+ {
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
}
else
{
- hi2s->TxXferSize = Size;
+ hi2s->TxXferSize = Size;
hi2s->TxXferCount = Size;
}
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
/* Enable TXE and ERR interrupt */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
- /* Check if the I2S is already enabled */
+ /* Check if the I2S is already enabled */
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
@@ -707,13 +725,11 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
-
+
return HAL_OK;
}
else
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
}
@@ -725,47 +741,48 @@
* @param pData: a 16-bit pointer to the Receive data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
- * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
- * between Master and Slave otherwise the I2S interrupt should be optimized.
+ * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
+ * between Master and Slave otherwise the I2S interrupt should be optimized.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- if((pData == NULL) || (Size == 0))
+ uint32_t tmp1 = 0U;
+
+ if(hi2s->State == HAL_I2S_STATE_READY)
+ {
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
- if(hi2s->State == HAL_I2S_STATE_READY)
- {
hi2s->pRxBuffPtr = pData;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
- hi2s->RxXferSize = (Size << 1);
- hi2s->RxXferCount = (Size << 1);
- }
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
+ }
else
{
- hi2s->RxXferSize = Size;
+ hi2s->RxXferSize = Size;
hi2s->RxXferCount = Size;
}
-
- /* Enable RXNE and ERR interrupt */
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ /* Enable TXE and ERR interrupt */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Check if the I2S is already enabled */
+
+ /* Check if the I2S is already enabled */
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
@@ -777,12 +794,11 @@
return HAL_OK;
}
+
else
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
- return HAL_BUSY;
- }
+ return HAL_BUSY;
+ }
}
/**
@@ -792,155 +808,159 @@
* @param pData: a 16-bit pointer to the Transmit data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- if((pData == NULL) || (Size == 0))
+ uint32_t *tmp = NULL;
+ uint32_t tmp1 = 0U;
+
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if(hi2s->State == HAL_I2S_STATE_READY)
- {
+ {
hi2s->pTxBuffPtr = pData;
- hi2s->State = HAL_I2S_STATE_BUSY_TX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
- hi2s->TxXferSize = (Size << 1);
- hi2s->TxXferCount = (Size << 1);
+ hi2s->TxXferSize = (Size << 1U);
+ hi2s->TxXferCount = (Size << 1U);
}
else
{
- hi2s->TxXferSize = Size;
+ hi2s->TxXferSize = Size;
hi2s->TxXferCount = Size;
}
- /* Set the I2S Tx DMA Half transfert complete callback */
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+ hi2s->State = HAL_I2S_STATE_BUSY_TX;
+
+ /* Set the I2S Tx DMA Half transfer complete callback */
hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
- /* Set the I2S Tx DMA transfert complete callback */
+ /* Set the I2S Tx DMA transfer complete callback */
hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
/* Set the DMA error callback */
hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
- /* Enable the Tx DMA Channel */
- HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
+ /* Enable the Tx DMA Stream */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
- /* Check if the I2S is already enabled */
- if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
- /* Check if the I2S Tx request is already enabled */
- if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
+ /* Check if the I2S Tx request is already enabled */
+ if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
{
- /* Enable Tx DMA Request */
+ /* Enable Tx DMA Request */
SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
-
+
return HAL_OK;
}
else
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
}
/**
- * @brief Receive an amount of data in non-blocking mode with DMA
+ * @brief Receive an amount of data in non-blocking mode with DMA
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @param pData: a 16-bit pointer to the Receive data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
- * configuration phase, the Size parameter means the number of 16-bit data length
- * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
- * the Size parameter means the number of 16-bit data length.
- * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
+ * configuration phase, the Size parameter means the number of 16-bit data length
+ * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
+ * the Size parameter means the number of 16-bit data length.
+ * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
- if((pData == NULL) || (Size == 0))
+ uint32_t *tmp = NULL;
+ uint32_t tmp1 = 0U;
+
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- /* Process Locked */
- __HAL_LOCK(hi2s);
-
if(hi2s->State == HAL_I2S_STATE_READY)
{
hi2s->pRxBuffPtr = pData;
- hi2s->State = HAL_I2S_STATE_BUSY_RX;
- hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
- if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
- ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
+ tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
+ if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B))
{
- hi2s->RxXferSize = (Size << 1);
- hi2s->RxXferCount = (Size << 1);
+ hi2s->RxXferSize = (Size << 1U);
+ hi2s->RxXferCount = (Size << 1U);
}
else
{
- hi2s->RxXferSize = Size;
+ hi2s->RxXferSize = Size;
hi2s->RxXferCount = Size;
}
-
-
- /* Set the I2S Rx DMA Half transfert complete callback */
+ /* Process Locked */
+ __HAL_LOCK(hi2s);
+
+ hi2s->State = HAL_I2S_STATE_BUSY_RX;
+ hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
+
+ /* Set the I2S Rx DMA Half transfer complete callback */
hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
-
- /* Set the I2S Rx DMA transfert complete callback */
+
+ /* Set the I2S Rx DMA transfer complete callback */
hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
-
+
/* Set the DMA error callback */
hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
-
+
/* Check if Master Receiver mode is selected */
if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
{
/* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
- access to the SPI_SR register. */
+ access to the SPI_SR register. */
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
}
-
- /* Enable the Rx DMA Channel */
- HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
-
- /* Check if the I2S is already enabled */
- if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+
+ /* Enable the Rx DMA Stream */
+ tmp = (uint32_t*)&pData;
+ HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
+
+ /* Check if the I2S is already enabled */
+ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
- /* Check if the I2S Rx request is already enabled */
- if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
+ /* Check if the I2S Rx request is already enabled */
+ if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
{
- /* Enable Rx DMA Request */
- SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ /* Enable Rx DMA Request */
+ SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
}
/* Process Unlocked */
@@ -950,14 +970,12 @@
}
else
{
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
return HAL_BUSY;
}
}
/**
- * @brief Pauses the audio stream playing from the Media.
+ * @brief Pauses the audio channel playing from the Media.
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
@@ -966,26 +984,26 @@
{
/* Process Locked */
__HAL_LOCK(hi2s);
-
+
if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
/* Disable the I2S DMA Tx request */
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
}
else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* Disable the I2S DMA Rx request */
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
}
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
- * @brief Resumes the audio stream playing from the Media.
+ * @brief Resumes the audio channel playing from the Media.
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
@@ -994,33 +1012,33 @@
{
/* Process Locked */
__HAL_LOCK(hi2s);
-
+
if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
/* Enable the I2S DMA Tx request */
- SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ SET_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
}
else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* Enable the I2S DMA Rx request */
- SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
+ SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
}
/* If the I2S peripheral is still not enabled, enable it */
- if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
+ if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U)
{
- /* Enable I2S peripheral */
+ /* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
-
+
return HAL_OK;
}
/**
- * @brief Resumes the audio stream playing from the Media.
+ * @brief Resumes the audio channel playing from the Media.
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
@@ -1029,34 +1047,31 @@
{
/* Process Locked */
__HAL_LOCK(hi2s);
-
- /* Disable the I2S Tx/Rx DMA requests */
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Abort the I2S DMA Channel tx */
- if(hi2s->hdmatx != NULL)
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
- /* Disable the I2S DMA channel */
- __HAL_DMA_DISABLE(hi2s->hdmatx);
+ /* Disable the I2S DMA requests */
+ CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
+
+ /* Disable the I2S DMA Channel */
HAL_DMA_Abort(hi2s->hdmatx);
}
- /* Abort the I2S DMA Channel rx */
- if(hi2s->hdmarx != NULL)
+ else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
- /* Disable the I2S DMA channel */
- __HAL_DMA_DISABLE(hi2s->hdmarx);
+ /* Disable the I2S DMA requests */
+ CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
+
+ /* Disable the I2S DMA Channel */
HAL_DMA_Abort(hi2s->hdmarx);
}
-
/* Disable I2S peripheral */
__HAL_I2S_DISABLE(hi2s);
-
+
hi2s->State = HAL_I2S_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
-
+
return HAL_OK;
}
@@ -1067,52 +1082,9 @@
* @retval None
*/
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
-{
- uint32_t i2ssr = hi2s->Instance->SR;
-
- /* I2S in mode Receiver ------------------------------------------------*/
- if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
- ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
- {
- I2S_Receive_IT(hi2s);
- return;
- }
-
- /* I2S in mode Tramitter -----------------------------------------------*/
- if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
- {
- I2S_Transmit_IT(hi2s);
- return;
- }
-
- /* I2S interrupt error -------------------------------------------------*/
- if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)
- {
- /* I2S Overrun error interrupt occured ---------------------------------*/
- if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR)
- {
- /* Disable RXNE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
- }
-
- /* I2S Underrun error interrupt occured --------------------------------*/
- if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR)
- {
- /* Disable TXE and ERR interrupt */
- __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
- }
-
- /* Set the I2S State ready */
- hi2s->State = HAL_I2S_STATE_READY;
- /* Call the Error Callback */
- HAL_I2S_ErrorCallback(hi2s);
- }
+{
+ /* Call the IrqHandler ISR set during HAL_I2S_INIT */
+ hi2s->IrqHandlerISR(hi2s);
}
/**
@@ -1127,7 +1099,7 @@
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
- */
+ */
}
/**
@@ -1142,7 +1114,7 @@
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxCpltCallback could be implemented in the user file
- */
+ */
}
/**
@@ -1187,7 +1159,7 @@
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_ErrorCallback could be implemented in the user file
- */
+ */
}
/**
@@ -1197,12 +1169,12 @@
/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection permits to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1243,28 +1215,27 @@
* @{
*/
/**
- * @brief DMA I2S transmit process complete callback
+ * @brief DMA I2S transmit process complete callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
{
/* Disable Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
+ CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN);
- hi2s->TxXferCount = 0;
- hi2s->State = HAL_I2S_STATE_READY;
+ hi2s->TxXferCount = 0U;
+ hi2s->State = HAL_I2S_STATE_READY;
}
HAL_I2S_TxCpltCallback(hi2s);
}
-
/**
- * @brief DMA I2S transmit process half complete callback
+ * @brief DMA I2S transmit process half complete callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
@@ -1277,27 +1248,27 @@
}
/**
- * @brief DMA I2S receive process complete callback
+ * @brief DMA I2S receive process complete callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
{
- I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
{
/* Disable Rx DMA Request */
- CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
- hi2s->RxXferCount = 0;
- hi2s->State = HAL_I2S_STATE_READY;
+ CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN);
+ hi2s->RxXferCount = 0U;
+ hi2s->State = HAL_I2S_STATE_READY;
}
- HAL_I2S_RxCpltCallback(hi2s);
+ HAL_I2S_RxCpltCallback(hi2s);
}
/**
- * @brief DMA I2S receive process half complete callback
+ * @brief DMA I2S receive process half complete callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
@@ -1306,11 +1277,11 @@
{
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- HAL_I2S_RxHalfCpltCallback(hi2s);
+ HAL_I2S_RxHalfCpltCallback(hi2s);
}
/**
- * @brief DMA I2S communication error callback
+ * @brief DMA I2S communication error callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
@@ -1320,14 +1291,13 @@
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
/* Disable Rx and Tx DMA Request */
- CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
- hi2s->TxXferCount = 0;
- hi2s->RxXferCount = 0;
+ CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
+ hi2s->TxXferCount = 0U;
+ hi2s->RxXferCount = 0U;
hi2s->State= HAL_I2S_STATE_READY;
- /* Set the error code and execute error callback*/
- SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_DMA);
HAL_I2S_ErrorCallback(hi2s);
}
@@ -1335,15 +1305,15 @@
* @brief Transmit an amount of data in non-blocking mode with Interrupt
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @retval None
+ * @retval HAL status
*/
static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
{
/* Transmit data */
hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
hi2s->TxXferCount--;
-
- if(hi2s->TxXferCount == 0)
+
+ if(hi2s->TxXferCount == 0U)
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
@@ -1355,78 +1325,118 @@
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s: I2S handle
- * @retval None
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval HAL status
*/
static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
{
- /* Receive data */
+ /* Receive data */
(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
hi2s->RxXferCount--;
-
- if(hi2s->RxXferCount == 0)
+
+ if(hi2s->RxXferCount == 0U)
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
- hi2s->State = HAL_I2S_STATE_READY;
- HAL_I2S_RxCpltCallback(hi2s);
+ hi2s->State = HAL_I2S_STATE_READY;
+ HAL_I2S_RxCpltCallback(hi2s);
}
}
+/**
+ * @brief This function handles I2S interrupt request.
+ * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * the configuration information for I2S module
+ * @retval None
+ */
+static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+ __IO uint32_t i2ssr = hi2s->Instance->SR;
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
+ {
+ /* I2S in mode Receiver ------------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
+ {
+ I2S_Receive_IT(hi2s);
+ }
+
+ /* I2S Overrun error interrupt occured -------------------------------------*/
+ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable RXNE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
+
+ /* Clear Overrun flag */
+ __HAL_I2S_CLEAR_OVRFLAG(hi2s);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR);
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+ }
+
+ if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
+ {
+ /* I2S in mode Transmitter -----------------------------------------------*/
+ if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
+ {
+ I2S_Transmit_IT(hi2s);
+ }
+
+ /* I2S Underrun error interrupt occurred --------------------------------*/
+ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
+ {
+ /* Disable TXE and ERR interrupt */
+ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
+
+ /* Clear Underrun flag */
+ __HAL_I2S_CLEAR_UDRFLAG(hi2s);
+
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
+
+ /* Set the error code and execute error callback*/
+ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
+ HAL_I2S_ErrorCallback(hi2s);
+ }
+ }
+}
/**
* @brief This function handles I2S Communication Timeout.
* @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @param Flag: Flag checked
- * @param Status: Value of the flag expected
+ * @param State: Value of the flag expected
* @param Timeout: Duration of the timeout
* @retval HAL status
*/
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State,
+ uint32_t Timeout)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = HAL_GetTick();
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until flag is set */
- if(Status == RESET)
+ /* Wait until flag is set to status*/
+ while(((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
{
- while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
+ if(Timeout != HAL_MAX_DELAY)
{
- if(Timeout != HAL_MAX_DELAY)
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
+ /* Set the I2S State ready */
+ hi2s->State = HAL_I2S_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2s);
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Set the I2S State ready */
- hi2s->State= HAL_I2S_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2s);
-
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
}
}
@@ -1443,8 +1453,6 @@
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
#endif /* HAL_I2S_MODULE_ENABLED */
-
-
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_irda.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_irda.c
index 64af1f5..07b761b 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_irda.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_irda.c
@@ -2,16 +2,15 @@
******************************************************************************
* @file stm32f1xx_hal_irda.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA SIR ENDEC block (IrDA):
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral State and Errors functions
- * + Peripheral Control functions
- *
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
@verbatim
==============================================================================
##### How to use this driver #####
@@ -24,7 +23,7 @@
(##) Enable the USARTx interface clock.
(##) IRDA pins configuration:
(+++) Enable the clock for the IRDA GPIOs.
- (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+ (+++) Configure the IRDA pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
and HAL_IRDA_Receive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
@@ -35,23 +34,23 @@
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initilalized DMA handle to the IRDA DMA Tx/Rx handle.
+ (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
- (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
- (used for last byte sending completion detection in DMA non circular mode)
+ (+++) Configure the IRDAx interrupt priority and enable the NVIC USART IRQ handle
+ (used for last byte sending completion detection in DMA non circular mode)
(#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler
and Mode(Receiver/Transmitter) in the hirda Init structure.
(#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_IRDA_MspInit() API.
-
- -@@- The specific IRDA interrupts (Transmission complete interrupt,
+ by calling the customized HAL_IRDA_MspInit() API.
+ [..]
+ (@) The specific IRDA interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
-
- (#) Three operation modes are available within this driver :
+ [..]
+ Three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
@@ -59,7 +58,7 @@
(+) Send an amount of data in blocking mode using HAL_IRDA_Transmit()
(+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
- *** Interrupt mode IO operation ***
+ *** Interrupt mode IO operation ***
===================================
[..]
(+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT()
@@ -71,39 +70,61 @@
(+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_IRDA_ErrorCallback
- *** DMA mode IO operation ***
+ *** DMA mode IO operation ***
==============================
[..]
(+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_IRDA_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback
(+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
(+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA()
+ (+) At reception end of half transfer HAL_IRDA_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback
(+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
+ add his own code by customization of function pointer HAL_IRDA_RxCpltCallback
(+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_IRDA_ErrorCallback
+ (+) Pause the DMA Transfer using HAL_IRDA_DMAPause()
+ (+) Resume the DMA Transfer using HAL_IRDA_DMAResume()
+ (+) Stop the DMA Transfer using HAL_IRDA_DMAStop()
*** IRDA HAL driver macros list ***
====================================
[..]
Below the list of most used macros in IRDA HAL driver.
-
+
(+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral
- (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
+ (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral
(+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
(+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
(+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
(+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
(+) __HAL_IRDA_GET_IT_SOURCE: Check whether the specified IRDA interrupt has occurred or not
-
- [..]
- (@) You can refer to the IRDA HAL driver header file for more useful macros
+ [..]
+ (@) You can refer to the IRDA HAL driver header file for more useful macros
@endverbatim
+ [..]
+ (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ the possible IRDA frame formats are as listed in the following table:
+ +-------------------------------------------------------------+
+ | M bit | PCE bit | IRDA frame |
+ |---------------------|---------------------------------------|
+ | 0 | 0 | | SB | 8 bit data | 1 STB | |
+ |---------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7 bit data | PB | 1 STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9 bit data | 1 STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8 bit data | PB | 1 STB | |
+ +-------------------------------------------------------------+
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -141,99 +162,78 @@
* @brief HAL IRDA module driver
* @{
*/
-
#ifdef HAL_IRDA_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup IRDA_Private_Constants IRDA Private Constants
+/** @addtogroup IRDA_Private_Constants
* @{
*/
-#define IRDA_DR_MASK_U16_8DATABITS (uint16_t)0x00FF
-#define IRDA_DR_MASK_U16_9DATABITS (uint16_t)0x01FF
-
-#define IRDA_DR_MASK_U8_7DATABITS (uint8_t)0x7F
-#define IRDA_DR_MASK_U8_8DATABITS (uint8_t)0xFF
-
-
/**
* @}
*/
-
-/* Private macros --------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup IRDA_Private_Functions IRDA Private Functions
+/** @addtogroup IRDA_Private_Functions
* @{
*/
+static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
-static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart,uint32_t Timeout);
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda);
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
-
/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
+/** @defgroup IRDA_Exported_Functions IrDA Exported Functions
* @{
*/
-/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
- ##### Initialization and Configuration functions #####
+ ##### Initialization and Configuration functions #####
==============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
- in IrDA mode.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate
- (++) Word Length
- (++) Parity
- (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
- not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
- specification specifies a minimum of 10 ms delay between transmission and
- reception (IrDA is a half duplex protocol).
- (++) Mode: Receiver/transmitter modes
- (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
-
- [..]
- The HAL_IRDA_Init() function follows IRDA configuration procedures (details for the procedures
- are available in reference manuals (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)).
+ [..]
+ This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+ in IrDA mode.
+ (+) For the asynchronous mode only these parameters can be configured:
+ (++) BaudRate
+ (++) WordLength
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ please refer to Reference manual for possible IRDA frame formats.
+ (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
+ not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
+ specification specifies a minimum of 10 ms delay between transmission and
+ reception (IrDA is a half duplex protocol).
+ (++) Mode: Receiver/transmitter modes
+ (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
+ [..]
+ The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures
+ are available in reference manual).
@endverbatim
* @{
*/
-
-/*
- Additionnal remark: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible IRDA frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | IRDA frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
-*/
-
/**
* @brief Initializes the IRDA mode according to the specified
* parameters in the IRDA_InitTypeDef and create the associated handle.
@@ -248,22 +248,19 @@
{
return HAL_ERROR;
}
-
- /* Check the IRDA instance parameters */
+
+ /* Check the parameters */
assert_param(IS_IRDA_INSTANCE(hirda->Instance));
- /* Check the IRDA mode parameter in the IRDA handle */
- assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
-
- if(hirda->State == HAL_IRDA_STATE_RESET)
+
+ if(hirda->gState == HAL_IRDA_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hirda->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_IRDA_MspInit(hirda);
}
- hirda->State = HAL_IRDA_STATE_BUSY;
+ hirda->gState = HAL_IRDA_STATE_BUSY;
/* Disable the IRDA peripheral */
__HAL_IRDA_DISABLE(hirda);
@@ -272,8 +269,8 @@
IRDA_SetConfig(hirda);
/* In IrDA mode, the following bits must be kept cleared:
- - LINEN, STOP and CLKEN bits in the USART_CR2 register,
- - SCEN and HDSEL bits in the USART_CR3 register.*/
+ - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+ - SCEN and HDSEL bits in the USART_CR3 register.*/
CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN));
CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
@@ -291,7 +288,8 @@
/* Initialize the IRDA state*/
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->State= HAL_IRDA_STATE_READY;
+ hirda->gState= HAL_IRDA_STATE_READY;
+ hirda->RxState= HAL_IRDA_STATE_READY;
return HAL_OK;
}
@@ -312,9 +310,9 @@
/* Check the parameters */
assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-
- hirda->State = HAL_IRDA_STATE_BUSY;
-
+
+ hirda->gState = HAL_IRDA_STATE_BUSY;
+
/* Disable the Peripheral */
__HAL_IRDA_DISABLE(hirda);
@@ -322,8 +320,9 @@
HAL_IRDA_MspDeInit(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- hirda->State = HAL_IRDA_STATE_RESET;
-
+ hirda->gState = HAL_IRDA_STATE_RESET;
+ hirda->RxState = HAL_IRDA_STATE_RESET;
+
/* Release Lock */
__HAL_UNLOCK(hirda);
@@ -336,13 +335,13 @@
* the configuration information for the specified IRDA module.
* @retval None
*/
- __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_IRDA_MspInit can be implemented in the user file
- */
+ */
}
/**
@@ -351,13 +350,13 @@
* the configuration information for the specified IRDA module.
* @retval None
*/
- __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_IRDA_MspDeInit can be implemented in the user file
- */
+ */
}
/**
@@ -373,8 +372,6 @@
==============================================================================
[..]
This subsection provides a set of functions allowing to manage the IRDA data transfers.
-
- [..]
IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver
is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
@@ -386,7 +383,7 @@
The HAL status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, These API's return the HAL status.
+ or DMA, these APIs return the HAL status.
The end of the data processing will be indicated through the
dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
@@ -395,16 +392,16 @@
The HAL_IRDA_ErrorCallback() user callback will be executed when a communication
error is detected
- (#) Blocking mode APIs are :
+ (#) Blocking mode APIs are:
(++) HAL_IRDA_Transmit()
(++) HAL_IRDA_Receive()
- (#) Non Blocking mode APIs with Interrupt are :
+ (#) Non Blocking mode APIs with Interrupt are:
(++) HAL_IRDA_Transmit_IT()
(++) HAL_IRDA_Receive_IT()
(++) HAL_IRDA_IRQHandler()
- (#) Non Blocking mode functions with DMA are :
+ (#) Non Blocking mode functions with DMA are:
(++) HAL_IRDA_Transmit_DMA()
(++) HAL_IRDA_Receive_DMA()
(++) HAL_IRDA_DMAPause()
@@ -433,13 +430,13 @@
*/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp = 0;
- uint32_t tmp_state = 0;
-
- tmp_state = hirda->State;
- if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_RX))
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
+
+ /* Check that a Tx process is not already ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -448,64 +445,54 @@
__HAL_LOCK(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
- }
- else
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX;
- }
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
- while(hirda->TxXferCount > 0)
+ while(hirda->TxXferCount > 0U)
{
+ hirda->TxXferCount--;
if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
tmp = (uint16_t*) pData;
- WRITE_REG(hirda->Instance->DR,(*tmp & IRDA_DR_MASK_U16_9DATABITS));
+ hirda->Instance->DR = (*tmp & (uint16_t)0x01FF);
if(hirda->Init.Parity == IRDA_PARITY_NONE)
{
- pData +=2;
+ pData +=2U;
}
else
{
- pData +=1;
+ pData +=1U;
}
}
else
{
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- WRITE_REG(hirda->Instance->DR, (*pData++ & IRDA_DR_MASK_U8_8DATABITS));
+ hirda->Instance->DR = (*pData++ & (uint8_t)0xFF);
}
- hirda->TxXferCount--;
}
-
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK)
- {
+
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
}
-
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_RX;
- }
- else
- {
- hirda->State = HAL_IRDA_STATE_READY;
- }
-
+
+ /* At end of Tx process, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hirda);
-
+
return HAL_OK;
}
else
@@ -525,13 +512,13 @@
*/
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp = 0;
- uint32_t tmp_state = 0;
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
- tmp_state = hirda->State;
- if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_TX))
+ /* Check that a Rx process is not already ongoing */
+ if(hirda->RxState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -540,62 +527,55 @@
__HAL_LOCK(hirda);
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
- }
- else
- {
- hirda->State = HAL_IRDA_STATE_BUSY_RX;
- }
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
+
hirda->RxXferSize = Size;
hirda->RxXferCount = Size;
+
/* Check the remain data to be received */
- while(hirda->RxXferCount > 0)
+ while(hirda->RxXferCount > 0U)
{
+ hirda->RxXferCount--;
if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
}
- tmp = (uint16_t*) pData ;
+ tmp = (uint16_t*)pData;
if(hirda->Init.Parity == IRDA_PARITY_NONE)
{
- *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_9DATABITS);
- pData +=2;
+ *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FF);
+ pData +=2U;
}
else
{
- *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_8DATABITS);
- pData +=1;
+ *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FF);
+ pData +=1U;
}
}
else
{
- if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
+ if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
}
if(hirda->Init.Parity == IRDA_PARITY_NONE)
{
- *pData++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_8DATABITS);
+ *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FF);
}
else
{
- *pData++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_7DATABITS);
+ *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007F);
}
}
- hirda->RxXferCount--;
}
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX;
- }
- else
- {
- hirda->State = HAL_IRDA_STATE_READY;
- }
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@@ -604,12 +584,12 @@
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Sends an amount of data in non-blocking mode.
+ * @brief Sends an amount of data in non blocking mode.
* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
@@ -618,12 +598,10 @@
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
- uint32_t tmp_state = 0;
-
- tmp_state = hirda->State;
- if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_RX))
+ /* Check that a Tx process is not already ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -635,19 +613,12 @@
hirda->TxXferCount = Size;
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
- }
- else
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX;
- }
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
/* Process Unlocked */
__HAL_UNLOCK(hirda);
- /* Enable the IRDA Transmit Data Register Empty Interrupt */
+ /* Enable the IRDA Transmit data register empty Interrupt */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
return HAL_OK;
@@ -659,7 +630,7 @@
}
/**
- * @brief Receives an amount of data in non-blocking mode.
+ * @brief Receives an amount of data in non blocking mode.
* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
@@ -668,45 +639,36 @@
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
- uint32_t tmp_state = 0;
-
- tmp_state = hirda->State;
- if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_TX))
+ /* Check that a Rx process is not already ongoing */
+ if(hirda->RxState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
-
+
/* Process Locked */
__HAL_LOCK(hirda);
-
+
hirda->pRxBuffPtr = pData;
hirda->RxXferSize = Size;
hirda->RxXferCount = Size;
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
- }
- else
- {
- hirda->State = HAL_IRDA_STATE_BUSY_RX;
- }
-
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
+
/* Process Unlocked */
__HAL_UNLOCK(hirda);
- /* Enable the IRDA Data Register not empty Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
-
/* Enable the IRDA Parity Error Interrupt */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
/* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
+ /* Enable the IRDA Data Register not empty Interrupt */
+ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE);
+
return HAL_OK;
}
else
@@ -716,7 +678,7 @@
}
/**
- * @brief Sends an amount of data in non-blocking mode.
+ * @brief Sends an amount of data in non blocking mode.
* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
@@ -725,13 +687,12 @@
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
- uint32_t *tmp = 0;
- uint32_t tmp_state = 0;
-
- tmp_state = hirda->State;
- if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_RX))
+ uint32_t *tmp;
+
+ /* Check that a Tx process is not already ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -742,40 +703,36 @@
hirda->pTxBuffPtr = pData;
hirda->TxXferSize = Size;
hirda->TxXferCount = Size;
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
- }
- else
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX;
- }
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->gState = HAL_IRDA_STATE_BUSY_TX;
/* Set the IRDA DMA transfer complete callback */
hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
- /* Set the IRDA DMA half transfert complete callback */
+ /* Set the IRDA DMA half transfer complete callback */
hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
/* Set the DMA error callback */
hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
- /* Enable the IRDA transmit DMA channel */
+ /* Set the DMA abort callback */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the IRDA transmit DMA Channel */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the USART CR3 register */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
return HAL_OK;
}
else
@@ -785,7 +742,7 @@
}
/**
- * @brief Receive an amount of data in non-blocking mode.
+ * @brief Receives an amount of data in non blocking mode.
* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @param pData: Pointer to data buffer
@@ -795,13 +752,12 @@
*/
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
{
- uint32_t *tmp = 0;
- uint32_t tmp_state = 0;
-
- tmp_state = hirda->State;
- if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_TX))
+ uint32_t *tmp;
+
+ /* Check that a Rx process is not already ongoing */
+ if(hirda->RxState == HAL_IRDA_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -811,36 +767,42 @@
hirda->pRxBuffPtr = pData;
hirda->RxXferSize = Size;
- hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
- }
- else
- {
- hirda->State = HAL_IRDA_STATE_BUSY_RX;
- }
+
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
/* Set the IRDA DMA transfer complete callback */
hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
- /* Set the IRDA DMA half transfert complete callback */
+ /* Set the IRDA DMA half transfer complete callback */
hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
/* Set the DMA error callback */
hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
+ /* Set the DMA abort callback */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
/* Enable the DMA channel */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
- SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
+ __HAL_IRDA_CLEAR_OREFLAG(hirda);
/* Process Unlocked */
__HAL_UNLOCK(hirda);
+ /* Enable the IRDA Parity Error Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the USART CR3 register */
+ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
return HAL_OK;
}
else
@@ -857,42 +819,39 @@
*/
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
{
+ uint32_t dmarequest = 0x00U;
+
/* Process Locked */
__HAL_LOCK(hirda);
-
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+
+ dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
+ if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
{
/* Disable the IRDA DMA Tx request */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
}
- else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+
+ dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+ if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
{
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
/* Disable the IRDA DMA Rx request */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
}
- else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
- {
- /* Disable the IRDA DMA Tx & Rx requests */
- CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_ERROR;
- }
/* Process Unlocked */
__HAL_UNLOCK(hirda);
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Resumes the DMA Transfer.
* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
@@ -900,33 +859,25 @@
/* Process Locked */
__HAL_LOCK(hirda);
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
+ if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
/* Enable the IRDA DMA Tx request */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
}
- else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
+
+ if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
- /* Clear the Overrun flag before resumming the Rx transfer*/
+ /* Clear the Overrun flag before resuming the Rx transfer */
__HAL_IRDA_CLEAR_OREFLAG(hirda);
+
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
/* Enable the IRDA DMA Rx request */
SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
}
- else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
- {
- /* Clear the Overrun flag before resumming the Rx transfer*/
- __HAL_IRDA_CLEAR_OREFLAG(hirda);
- /* Enable the IRDA DMA Tx & Rx request */
- SET_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_ERROR;
- }
-
+
/* Process Unlocked */
__HAL_UNLOCK(hirda);
@@ -936,33 +887,447 @@
/**
* @brief Stops the DMA Transfer.
* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
- * the configuration information for the specified UART module.
+ * the configuration information for the specified IRDA module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
{
+ uint32_t dmarequest = 0x00U;
/* The Lock is not implemented on this API to allow the user application
- to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback():
- when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
- and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback()
- */
+ to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback():
+ when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+ and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback()
+ */
- /* Disable the IRDA Tx/Rx DMA requests */
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
- CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+ /* Stop IRDA DMA Tx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
+ if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel */
+ if(hirda->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+ IRDA_EndTxTransfer(hirda);
+ }
+
+ /* Stop IRDA DMA Rx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+ if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel */
+ if(hirda->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+ IRDA_EndRxTransfer(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param hirda IRDA handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
- /* Abort the IRDA DMA tx channel */
+ /* Disable the IRDA DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel: use blocking DMA Abort API (no callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+ }
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel: use blocking DMA Abort API (no callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ hirda->TxXferCount = 0x00U;
+ hirda->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Restore hirda->RxState and hirda->gState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param hirda IRDA handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmatx);
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0x00U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param hirda IRDA handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hirda->hdmarx);
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0x00U;
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param hirda IRDA handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda)
+{
+ uint32_t AbortCplt = 0x01U;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
if(hirda->hdmatx != NULL)
{
- HAL_DMA_Abort(hirda->hdmatx);
+ /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback;
+ }
+ else
+ {
+ hirda->hdmatx->XferAbortCallback = NULL;
+ }
}
- /* Abort the IRDA DMA rx channel */
+ /* DMA Rx Handle is valid */
if(hirda->hdmarx != NULL)
{
- HAL_DMA_Abort(hirda->hdmarx);
+ /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback;
+ }
+ else
+ {
+ hirda->hdmarx->XferAbortCallback = NULL;
+ }
}
-
- hirda->State = HAL_IRDA_STATE_READY;
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at IRDA level */
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* IRDA Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ {
+ hirda->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* IRDA Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ hirda->hdmarx->XferAbortCallback = NULL;
+ AbortCplt = 0x01U;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if(AbortCplt == 0x01U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hirda->TxXferCount = 0x00U;
+ hirda->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param hirda IRDA handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the IRDA DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmatx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+ hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */
+ hirda->hdmatx->XferAbortCallback(hirda->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0x00U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hirda->TxXferCount = 0x00U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param hirda IRDA handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the IRDA DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */
+ hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0x00U;
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hirda->RxXferCount = 0x00U;
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+ }
return HAL_OK;
}
@@ -975,93 +1340,138 @@
*/
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
{
- uint32_t tmp_flag = 0, tmp_it_source = 0;
-
- tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_PE);
- tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE);
- /* IRDA parity error interrupt occurred -----------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ uint32_t isrflags = READ_REG(hirda->Instance->SR);
+ uint32_t cr1its = READ_REG(hirda->Instance->CR1);
+ uint32_t cr3its = READ_REG(hirda->Instance->CR3);
+ uint32_t errorflags = 0x00U;
+ uint32_t dmarequest = 0x00U;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+ if(errorflags == RESET)
{
- hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+ /* IRDA in mode Receiver -----------------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ IRDA_Receive_IT(hirda);
+ return;
+ }
}
- tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_FE);
- tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
- /* IRDA frame error interrupt occurred ------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ /* If some errors occur */
+ if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
{
- hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
- }
+ /* IRDA parity error interrupt occurred -------------------------------*/
+ if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
+ }
- tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_NE);
- /* IRDA noise error interrupt occurred ------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
- }
+ /* IRDA noise error interrupt occurred --------------------------------*/
+ if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
+ }
- tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_ORE);
- /* IRDA Over-Run interrupt occurred ---------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
- }
+ /* IRDA frame error interrupt occurred --------------------------------*/
+ if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
+ }
- /* Call the Error call Back in case of Errors */
- if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
- {
- /* Disable PE and ERR interrupt */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
-
- /* Clear all the error flag at once */
- __HAL_IRDA_CLEAR_PEFLAG(hirda);
+ /* IRDA Over-Run interrupt occurred -----------------------------------*/
+ if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
+ }
+ /* Call IRDA Error Call back function if need be -----------------------*/
+ if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
+ {
+ /* IRDA in mode Receiver ---------------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ IRDA_Receive_IT(hirda);
+ }
- /* Set the IRDA state ready to be able to start again the process */
- hirda->State = HAL_IRDA_STATE_READY;
- HAL_IRDA_ErrorCallback(hirda);
- }
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+ if(((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || dmarequest)
+ {
+ /* Blocking error : transfer is aborted
+ Set the IRDA state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ IRDA_EndRxTransfer(hirda);
- tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_RXNE);
- tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE);
- /* IRDA in mode Receiver --------------------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- IRDA_Receive_IT(hirda);
- }
+ /* Disable the IRDA DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
- tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TXE);
- tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE);
- /* IRDA in mode Transmitter -----------------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ /* Abort the IRDA DMA Rx channel */
+ if(hirda->hdmarx != NULL)
+ {
+ /* Set the IRDA DMA Abort callback :
+ will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */
+ hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError;
+
+ if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hirda->hdmarx->XferAbortCallback(hirda->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_IRDA_ErrorCallback(hirda);
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+ }
+ }
+ return;
+ } /* End if some error occurs */
+
+ /* IRDA in mode Transmitter ------------------------------------------------*/
+ if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
IRDA_Transmit_IT(hirda);
+ return;
}
- tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC);
- tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC);
- /* IRDA in mode Transmitter (transmission end) -----------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ /* IRDA in mode Transmitter end --------------------------------------------*/
+ if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
IRDA_EndTransmit_IT(hirda);
- }
-
+ return;
+ }
}
/**
- * @brief Tx Transfer completed callbacks.
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief Tx Transfer complete callbacks.
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
- __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_IRDA_TxCpltCallback can be implemented in the user file
- */
+ */
}
/**
@@ -1070,17 +1480,17 @@
* the configuration information for the specified USART module.
* @retval None
*/
- __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file
- */
+ */
}
/**
- * @brief Rx Transfer completed callbacks.
+ * @brief Rx Transfer complete callbacks.
* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
@@ -1091,7 +1501,7 @@
UNUSED(hirda);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_IRDA_RxCpltCallback can be implemented in the user file
- */
+ */
}
/**
@@ -1106,22 +1516,67 @@
UNUSED(hirda);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file
- */
+ */
}
/**
- * @brief IRDA error callbacks.
+ * @brief IRDA error callbacks.
* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
- __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
+__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hirda);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_IRDA_ErrorCallback can be implemented in the user file
- */
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_IRDA_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief IRDA Abort Complete callback.
+ * @param hirda IRDA handle.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort Transmit Complete callback.
+ * @param hirda IRDA handle.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief IRDA Abort ReceiveComplete callback.
+ * @param hirda IRDA handle.
+ * @retval None
+ */
+__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hirda);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file.
+ */
}
/**
@@ -1138,11 +1593,9 @@
[..]
This subsection provides a set of functions allowing to return the State of IrDA
communication process and also return Peripheral Errors occurred during communication process
- (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state
- of the IRDA peripheral.
- (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during
- communication.
-
+ (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral.
+ (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication.
+
@endverbatim
* @{
*/
@@ -1155,7 +1608,11 @@
*/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
{
- return hirda->State;
+ uint32_t temp1 = 0x00U, temp2 = 0x00U;
+ temp1 = hirda->gState;
+ temp2 = hirda->RxState;
+
+ return (HAL_IRDA_StateTypeDef)(temp1 | temp2);
}
/**
@@ -1174,14 +1631,6 @@
*/
/**
- * @}
- */
-
-/** @defgroup IRDA_Private_Functions IRDA Private Functions
- * @brief IRDA Private functions
- * @{
- */
-/**
* @brief DMA IRDA transmit process complete callback.
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
@@ -1191,15 +1640,15 @@
{
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
- hirda->TxXferCount = 0;
-
+ hirda->TxXferCount = 0U;
+
/* Disable the DMA transfer for transmit request by setting the DMAT bit
- in the IRDA CR3 register */
+ in the IRDA CR3 register */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
- /* Enable the IRDA Transmit Complete Interrupt */
+
+ /* Enable the IRDA Transmit Complete Interrupt */
__HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
}
/* DMA Circular mode */
@@ -1212,74 +1661,82 @@
/**
* @brief DMA IRDA receive process half complete callback
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+
HAL_IRDA_TxHalfCpltCallback(hirda);
}
/**
* @brief DMA IRDA receive process complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma: DMA handle
* @retval None
*/
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
- hirda->RxXferCount = 0;
+ hirda->RxXferCount = 0U;
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
/* Disable the DMA transfer for the receiver request by setting the DMAR bit
- in the IRDA CR3 register */
+ in the IRDA CR3 register */
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX;
- }
- else
- {
- hirda->State = HAL_IRDA_STATE_READY;
- }
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
}
-
HAL_IRDA_RxCpltCallback(hirda);
}
/**
* @brief DMA IRDA receive process half complete callback
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
{
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
HAL_IRDA_RxHalfCpltCallback(hirda);
}
/**
- * @brief DMA IRDA communication error callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief DMA IRDA communication error callback.
+ * @param hdma: DMA handle
* @retval None
*/
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
+static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
{
+ uint32_t dmarequest = 0x00U;
IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hirda->RxXferCount = 0;
- hirda->TxXferCount = 0;
+ /* Stop IRDA DMA Tx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT);
+ if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest)
+ {
+ hirda->TxXferCount = 0U;
+ IRDA_EndTxTransfer(hirda);
+ }
+
+ /* Stop IRDA DMA Rx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR);
+ if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest)
+ {
+ hirda->RxXferCount = 0U;
+ IRDA_EndRxTransfer(hirda);
+ }
+
hirda->ErrorCode |= HAL_IRDA_ERROR_DMA;
- hirda->State= HAL_IRDA_STATE_READY;
HAL_IRDA_ErrorCallback(hirda);
}
@@ -1290,64 +1747,31 @@
* the configuration information for the specified IRDA module.
* @param Flag: specifies the IRDA flag to check.
* @param Status: The new Flag status (SET or RESET).
+ * @param Tickstart: Tick start value
* @param Timeout: Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
- uint32_t tickstart = 0;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
/* Wait until flag is set */
- if(Status == RESET)
+ while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status)
{
- while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
- hirda->State= HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
- hirda->State= HAL_IRDA_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hirda);
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
- return HAL_TIMEOUT;
- }
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hirda);
+
+ return HAL_TIMEOUT;
}
}
}
@@ -1355,48 +1779,206 @@
}
/**
- * @brief Send an amount of data in non-blocking mode.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_IRDA_Transmit_IT()
- * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+ * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
+ * @param hirda: IRDA handle.
+ * @retval None
+ */
+static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* At end of Tx process, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+}
+
+/**
+ * @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
+ * @param hirda: IRDA handle.
+ * @retval None
+ */
+static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+}
+
+/**
+ * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hirda->RxXferCount = 0x00U;
+ hirda->TxXferCount = 0x00U;
+
+ HAL_IRDA_ErrorCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hirda->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hirda->hdmarx != NULL)
+ {
+ if(hirda->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0x00U;
+ hirda->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hirda->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hirda->hdmatx != NULL)
+ {
+ if(hirda->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hirda->TxXferCount = 0x00U;
+ hirda->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
+
+ /* Restore hirda->gState and hirda->RxState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hirda->TxXferCount = 0x00U;
+
+ /* Restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortTransmitCpltCallback(hirda);
+}
+
+/**
+ * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to
+ * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hirda->RxXferCount = 0x00U;
+
+ /* Restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_IRDA_AbortReceiveCpltCallback(hirda);
+}
+
+/**
+ * @brief Send an amount of data in non blocking mode.
+ * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
{
- uint16_t* tmp = 0;
- uint32_t tmp_state = 0;
-
- tmp_state = hirda->State;
- if((tmp_state == HAL_IRDA_STATE_BUSY_TX) || (tmp_state == HAL_IRDA_STATE_BUSY_TX_RX))
+ uint16_t* tmp;
+
+ /* Check that a Tx process is ongoing */
+ if(hirda->gState == HAL_IRDA_STATE_BUSY_TX)
{
if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
tmp = (uint16_t*) hirda->pTxBuffPtr;
- WRITE_REG(hirda->Instance->DR, (uint16_t)(*tmp & IRDA_DR_MASK_U16_9DATABITS));
+ hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
if(hirda->Init.Parity == IRDA_PARITY_NONE)
{
- hirda->pTxBuffPtr += 2;
+ hirda->pTxBuffPtr += 2U;
}
else
{
- hirda->pTxBuffPtr += 1;
+ hirda->pTxBuffPtr += 1U;
}
}
else
{
- WRITE_REG(hirda->Instance->DR, (uint8_t)(*hirda->pTxBuffPtr++ & IRDA_DR_MASK_U8_8DATABITS));
- }
-
- if(--hirda->TxXferCount == 0)
- {
- /* Disable the IRDA Transmit Data Register Empty Interrupt */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
-
- /* Enable the IRDA Transmit Complete Interrupt */
- __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
+ hirda->Instance->DR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FF);
}
+ if(--hirda->TxXferCount == 0U)
+ {
+ /* Disable the IRDA Transmit Data Register Empty Interrupt */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE);
+
+ /* Enable the IRDA Transmit Complete Interrupt */
+ SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
+ }
return HAL_OK;
}
else
@@ -1414,86 +1996,69 @@
static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
{
/* Disable the IRDA Transmit Complete Interrupt */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE);
- /* Check if a receive process is ongoing or not */
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_RX;
- }
- else
- {
- /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
- hirda->State = HAL_IRDA_STATE_READY;
- }
-
+ /* Tx process is ended, restore hirda->gState to Ready */
+ hirda->gState = HAL_IRDA_STATE_READY;
HAL_IRDA_TxCpltCallback(hirda);
return HAL_OK;
}
-
/**
- * @brief Receive an amount of data in non-blocking mode.
+ * @brief Receives an amount of data in non blocking mode.
* @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
{
- uint16_t* tmp = 0;
- uint32_t tmp_state = 0;
-
- tmp_state = hirda->State;
- if((tmp_state == HAL_IRDA_STATE_BUSY_RX) || (tmp_state == HAL_IRDA_STATE_BUSY_TX_RX))
+ uint16_t* tmp;
+ uint16_t uhdata;
+
+ /* Check that a Rx process is ongoing */
+ if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX)
{
+ uhdata = (uint16_t) READ_REG(hirda->Instance->DR);
if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
{
tmp = (uint16_t*) hirda->pRxBuffPtr;
if(hirda->Init.Parity == IRDA_PARITY_NONE)
{
- *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_9DATABITS);
- hirda->pRxBuffPtr += 2;
+ *tmp = (uint16_t)(uhdata & (uint16_t)0x01FF);
+ hirda->pRxBuffPtr += 2U;
}
else
{
- *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_8DATABITS);
- hirda->pRxBuffPtr += 1;
+ *tmp = (uint16_t)(uhdata & (uint16_t)0x00FF);
+ hirda->pRxBuffPtr += 1U;
}
- }
+ }
else
{
if(hirda->Init.Parity == IRDA_PARITY_NONE)
{
- *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_8DATABITS);
+ *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x00FF);
}
else
{
- *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_7DATABITS);
+ *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x007F);
}
}
- if(--hirda->RxXferCount == 0)
+ if(--hirda->RxXferCount == 0U)
{
+ /* Disable the IRDA Data Register not empty Interrupt */
__HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
+
+ /* Disable the IRDA Parity Error Interrupt */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
- if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
- {
- hirda->State = HAL_IRDA_STATE_BUSY_TX;
- }
- else
- {
- /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
- /* Disable the IRDA Parity Error Interrupt */
- __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-
-
- hirda->State = HAL_IRDA_STATE_READY;
- }
+ /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
+ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
+
+ /* Rx process is completed, restore hirda->RxState to Ready */
+ hirda->RxState = HAL_IRDA_STATE_READY;
HAL_IRDA_RxCpltCallback(hirda);
return HAL_OK;
@@ -1502,7 +2067,7 @@
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
@@ -1515,38 +2080,43 @@
static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
{
/* Check the parameters */
+ assert_param(IS_IRDA_INSTANCE(hirda->Instance));
assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
assert_param(IS_IRDA_MODE(hirda->Init.Mode));
-
- /*------- IRDA-associated USART registers setting : CR2 Configuration ------*/
+ assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode));
+
+ /*-------------------------- USART CR2 Configuration ------------------------*/
/* Clear STOP[13:12] bits */
CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP);
- /*------- IRDA-associated USART registers setting : CR1 Configuration ------*/
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ /* Clear M, PCE, PS, TE and RE bits */
+ CLEAR_BIT(hirda->Instance->CR1, USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE);
+
/* Configure the USART Word Length, Parity and mode:
- Set the M bits according to hirda->Init.WordLength value
- Set PCE and PS bits according to hirda->Init.Parity value
- Set TE and RE bits according to hirda->Init.Mode value */
- MODIFY_REG(hirda->Instance->CR1,
- ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)),
- (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode);
+ Set the M bits according to hirda->Init.WordLength value
+ Set PCE and PS bits according to hirda->Init.Parity value
+ Set TE and RE bits according to hirda->Init.Mode value */
+ /* Write to USART CR1 */
+ SET_BIT(hirda->Instance->CR1, (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode);
- /*------- IRDA-associated USART registers setting : CR3 Configuration ------*/
+ /*-------------------------- USART CR3 Configuration -----------------------*/
/* Clear CTSE and RTSE bits */
- CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
+ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_RTSE | USART_CR3_CTSE);
- /*------- IRDA-associated USART registers setting : BRR Configuration ------*/
+ /*-------------------------- USART BRR Configuration -----------------------*/
if(hirda->Instance == USART1)
{
- hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate);
+ SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate));
}
else
{
- hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate);
+ SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate));
}
}
+
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_iwdg.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_iwdg.c
index 7b85539..639fcfd 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_iwdg.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_iwdg.c
@@ -2,66 +2,73 @@
******************************************************************************
* @file stm32f1xx_hal_iwdg.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief IWDG HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
- * + Initialization and Configuration functions
+ * + Initialization and Start functions
* + IO operation functions
- * + Peripheral State functions
- @verbatim
-================================================================================
- ##### IWDG specific features #####
-================================================================================
- [..]
+ *
+ @verbatim
+ ==============================================================================
+ ##### IWDG Generic features #####
+ ==============================================================================
+ [..]
(+) The IWDG can be started by either software or hardware (configurable
through option byte).
- (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
- thus stays active even if the main clock fails.
- (+) Once the IWDG is started, the LSI is forced ON and cannot be disabled
- (LSI cannot be disabled too), and the counter starts counting down from
- the reset value of 0xFFF. When it reaches the end of count value (0x000)
- a system reset is generated.
- (+) The IWDG counter should be refreshed at regular intervals, otherwise the
- watchdog generates an MCU reset when the counter reaches 0.
+
+ (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
+ if the main clock fails.
+
+ (+) Once the IWDG is started, the LSI is forced ON and both can not be
+ disabled. The counter starts counting down from the reset value (0xFFF).
+ When it reaches the end of count value (0x000) a reset signal is
+ generated (IWDG reset).
+
+ (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
+ the IWDG_RLR value is reloaded in the counter and the watchdog reset is
+ prevented.
+
(+) The IWDG is implemented in the VDD voltage domain that is still functional
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
- (+) IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
+ IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
- (+) Min-max timeout value at 40KHz (LSI): 0.1us / 26.2s .
- The IWDG timeout may vary due to LSI frequency dispersion. STM32F1xx
- devices provide the capability to measure the LSI frequency (LSI clock
- connected internally to TIM5 CH4 input capture). The measured value
- can be used to have an IWDG timeout with an acceptable accuracy.
- For more information, please refer to the STM32F1xx Reference manual.
- Note: LSI Calibration is only available on: High density, XL-density and Connectivity line devices.
+ (+) Debug mode : When the microcontroller enters debug mode (core halted),
+ the IWDG counter either continues to work normally or stops, depending
+ on DBG_IWDG_STOP configuration bit in DBG module, accessible through
+ __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
+
+ [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
+ The IWDG timeout may vary due to LSI frequency dispersion. STM32F1xx
+ devices provide the capability to measure the LSI frequency (LSI clock
+ connected internally to TIM5 CH4 input capture). The measured value
+ can be used to have an IWDG timeout with an acceptable accuracy.
##### How to use this driver #####
==============================================================================
- [..]
- (+) Use IWDG using HAL_IWDG_Init() function to :
- (++) Enable write access to IWDG_PR, IWDG_RLR.
- (++) Configure the IWDG prescaler, counter reload value.
- This reload value will be loaded in the IWDG counter each time the counter
- is reloaded, then the IWDG will start counting down from this value.
- (+) Use IWDG using HAL_IWDG_Start() function to :
- (++) Reload IWDG counter with value defined in the IWDG_RLR register.
- (++) Start the IWDG, when the IWDG is used in software mode (no need
- to enable the LSI, it will be enabled by hardware).
- (+) Then the application program must refresh the IWDG counter at regular
+ [..]
+ (#) Use IWDG using HAL_IWDG_Init() function to :
+ (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
+ clock is forced ON and IWDG counter starts downcounting.
+ (++) Enable write access to configuration register: IWDG_PR & IWDG_RLR.
+ (++) Configure the IWDG prescaler and counter reload value. This reload
+ value will be loaded in the IWDG counter each time the watchdog is
+ reloaded, then the IWDG will start counting down from this value.
+ (++) wait for status flags to be reset"
+
+ (#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
- HAL_IWDG_Refresh() function.
-
+ HAL_IWDG_Refresh() function.
+
*** IWDG HAL driver macros list ***
====================================
[..]
- Below the list of most used macros in IWDG HAL driver.
-
+ Below the list of most used macros in IWDG HAL driver:
(+) __HAL_IWDG_START: Enable the IWDG peripheral
- (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
- (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
+ (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
+ the reload register
@endverbatim
******************************************************************************
@@ -75,7 +82,7 @@
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
+ * and/or other materials provided with the distribution
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
@@ -92,7 +99,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
@@ -101,22 +108,21 @@
* @{
*/
+#ifdef HAL_IWDG_MODULE_ENABLED
/** @defgroup IWDG IWDG
* @brief IWDG HAL module driver.
* @{
*/
-#ifdef HAL_IWDG_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-
-/** @defgroup IWDG_Private_Constants IWDG Private Constants
+/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
-
-#define IWDG_DEFAULT_TIMEOUT (uint32_t)1000
-
+/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
+ higher prescaler (256), and according to HSI variation, we need to wait at
+ least 6 cycles so 48 ms. */
+#define HAL_IWDG_DEFAULT_TIMEOUT 48U
/**
* @}
*/
@@ -124,38 +130,41 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
+/** @addtogroup IWDG_Exported_Functions
* @{
*/
-/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
+/** @addtogroup IWDG_Exported_Functions_Group1
+ * @brief Initialization and Start functions.
+ *
+@verbatim
===============================================================================
- ##### Initialization and de-initialization functions #####
+ ##### Initialization and Start functions #####
===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the IWDG according to the specified parameters
- in the IWDG_InitTypeDef and create the associated handle
- (+) Initialize the IWDG MSP
- (+) DeInitialize IWDG MSP
-
+ [..] This section provides functions allowing to:
+ (+) Initialize the IWDG according to the specified parameters in the
+ IWDG_InitTypeDef of associated handle.
+ (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
+ is reloaded in order to exit function with correct time base.
+
@endverbatim
* @{
*/
/**
- * @brief Initializes the IWDG according to the specified
- * parameters in the IWDG_InitTypeDef and creates the associated handle.
- * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * @brief Initialize the IWDG according to the specified parameters in the
+ * IWDG_InitTypeDef and start watchdog. Before exiting function,
+ * watchdog is refreshed in order to have correct time base.
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
{
+ uint32_t tickstart;
+
/* Check the IWDG handle allocation */
if(hiwdg == NULL)
{
@@ -165,69 +174,49 @@
/* Check the parameters */
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
- assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
-
- /* Check pending flag, if previous update not done, return error */
- if((__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET)
- &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET))
- {
- return HAL_ERROR;
- }
-
- if(hiwdg->State == HAL_IWDG_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hiwdg->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_IWDG_MspInit(hiwdg);
- }
-
- /* Change IWDG peripheral state */
- hiwdg->State = HAL_IWDG_STATE_BUSY;
-
- /* Enable write access to IWDG_PR and IWDG_RLR registers */
+ assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
+
+ /* Enable IWDG. LSI is turned on automaticaly */
+ __HAL_IWDG_START(hiwdg);
+
+ /* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
-
- /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
- MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler);
- MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload);
-
- /* Change IWDG peripheral state */
- hiwdg->State = HAL_IWDG_STATE_READY;
-
+
+ /* Write to IWDG registers the Prescaler & Reload values to work with */
+ hiwdg->Instance->PR = hiwdg->Init.Prescaler;
+ hiwdg->Instance->RLR = hiwdg->Init.Reload;
+
+ /* Check pending flag, if previous update not done, return timeout */
+ tickstart = HAL_GetTick();
+
+ /* Wait for register to be updated */
+ while(hiwdg->Instance->SR != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Reload IWDG counter with value defined in the reload register */
+ __HAL_IWDG_RELOAD_COUNTER(hiwdg);
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Initializes the IWDG MSP.
- * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
- * the configuration information for the specified IWDG module.
- * @retval None
- */
-__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hiwdg);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_IWDG_MspInit could be implemented in the user file
- */
-}
-
-/**
* @}
*/
-/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
- *
-@verbatim
+/** @addtogroup IWDG_Exported_Functions_Group2
+ * @brief IO operation functions
+ *
+@verbatim
===============================================================================
##### IO operation functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Start the IWDG.
+ ===============================================================================
+ [..] This section provides functions allowing to:
(+) Refresh the IWDG.
@endverbatim
@@ -235,77 +224,16 @@
*/
/**
- * @brief Starts the IWDG.
- * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
- * the configuration information for the specified IWDG module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
-{
- /* Process Locked */
- __HAL_LOCK(hiwdg);
-
- /* Change IWDG peripheral state */
- hiwdg->State = HAL_IWDG_STATE_BUSY;
-
- /* Start the IWDG peripheral */
- __HAL_IWDG_START(hiwdg);
-
- /* Reload IWDG counter with value defined in the RLR register */
- __HAL_IWDG_RELOAD_COUNTER(hiwdg);
-
- /* Change IWDG peripheral state */
- hiwdg->State = HAL_IWDG_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hiwdg);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Refreshes the IWDG.
- * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
+ * @brief Refresh the IWDG.
+ * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
{
- uint32_t tickstart = 0;
-
- /* Process Locked */
- __HAL_LOCK(hiwdg);
-
- /* Change IWDG peripheral state */
- hiwdg->State = HAL_IWDG_STATE_BUSY;
-
- tickstart = HAL_GetTick();
-
- /* Wait until RVU flag is RESET */
- while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
- {
- if((HAL_GetTick() - tickstart ) > IWDG_DEFAULT_TIMEOUT)
- {
- /* Set IWDG state */
- hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
-
- /* Process unlocked */
- __HAL_UNLOCK(hiwdg);
-
- return HAL_TIMEOUT;
- }
- }
-
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
-
- /* Change IWDG peripheral state */
- hiwdg->State = HAL_IWDG_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hiwdg);
-
+
/* Return function status */
return HAL_OK;
}
@@ -314,36 +242,6 @@
* @}
*/
-/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ===============================================================================
- ##### Peripheral State functions #####
- ===============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the IWDG state.
- * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
- * the configuration information for the specified IWDG module.
- * @retval HAL state
- */
-HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
-{
- return hiwdg->State;
-}
-
-/**
- * @}
- */
-
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_mmc.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_mmc.c
new file mode 100644
index 0000000..61001b4
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_mmc.c
@@ -0,0 +1,2598 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_mmc.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief MMC card HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Secure Digital (MMC) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + MMC card Control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver implements a high level communication layer for read and write from/to
+ this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by
+ the user in HAL_MMC_MspInit() function (MSP layer).
+ Basically, the MSP layer configuration should be the same as we provide in the
+ examples.
+ You can easily tailor this configuration according to hardware resources.
+
+ [..]
+ This driver is a generic layered driver for SDMMC memories which uses the HAL
+ SDMMC driver functions to interface with MMC and eMMC cards devices.
+ It is used as follows:
+
+ (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API:
+ (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE();
+ (##) SDMMC pins configuration for MMC card
+ (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE();
+ (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init()
+ and according to your pin assignment;
+ (##) DMA Configuration if you need to use DMA process (HAL_MMC_ReadBlocks_DMA()
+ and HAL_MMC_WriteBlocks_DMA() APIs).
+ (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE();
+ (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled.
+ (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
+ (+++) Configure the SDMMC and DMA interrupt priorities using functions
+ HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority
+ (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+ (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
+ and __HAL_MMC_DISABLE_IT() inside the communication process.
+ (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
+ and __HAL_MMC_CLEAR_IT()
+ (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT()
+ and HAL_MMC_WriteBlocks_IT() APIs).
+ (+++) Configure the SDMMC interrupt priorities using function
+ HAL_NVIC_SetPriority();
+ (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ()
+ (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT()
+ and __HAL_MMC_DISABLE_IT() inside the communication process.
+ (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT()
+ and __HAL_MMC_CLEAR_IT()
+ (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization
+
+
+ *** MMC Card Initialization and configuration ***
+ ================================================
+ [..]
+ To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes
+ SDMMC IP (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
+ This function provide the following operations:
+
+ (#) Initialize the SDMMC peripheral interface with defaullt configuration.
+ The initialization process is done at 400KHz. You can change or adapt
+ this frequency by adjusting the "ClockDiv" field.
+ The MMC Card frequency (SDMMC_CK) is computed as follows:
+
+ SDMMC_CK = SDMMCCLK / (ClockDiv + 2)
+
+ In initialization mode and according to the MMC Card standard,
+ make sure that the SDMMC_CK frequency doesn't exceed 400KHz.
+
+ This phase of initialization is done through SDMMC_Init() and
+ SDMMC_PowerState_ON() SDMMC low level APIs.
+
+ (#) Initialize the MMC card. The API used is HAL_MMC_InitCard().
+ This phase allows the card initialization and identification
+ and check the MMC Card type (Standard Capacity or High Capacity)
+ The initialization flow is compatible with MMC standard.
+
+ This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case
+ of plug-off plug-in.
+
+ (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer
+ frequency is set to 24MHz. You can change or adapt this frequency by adjusting
+ the "ClockDiv" field.
+ In transfer mode and according to the MMC Card standard, make sure that the
+ SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
+ To be able to use a frequency higher than 24MHz, you should use the SDMMC
+ peripheral in bypass mode. Refer to the corresponding reference manual
+ for more details.
+
+ (#) Select the corresponding MMC Card according to the address read with the step 2.
+
+ (#) Configure the MMC Card in wide bus mode: 4-bits data.
+
+ *** MMC Card Read operation ***
+ ==============================
+ [..]
+ (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+
+ (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+ You could also check the DMA transfer process through the MMC Rx interrupt event.
+
+ (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+ You could also check the IT transfer process through the MMC Rx interrupt event.
+
+ *** MMC Card Write operation ***
+ ===============================
+ [..]
+ (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+
+ (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+ You could also check the DMA transfer process through the MMC Tx interrupt event.
+
+ (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_MMC_GetCardState() function for MMC card state.
+ You could also check the IT transfer process through the MMC Tx interrupt event.
+
+ *** MMC card status ***
+ ======================
+ [..]
+ (+) The MMC Status contains status bits that are related to the MMC Memory
+ Card proprietary features. To get MMC card status use the HAL_MMC_GetCardStatus().
+
+ *** MMC card information ***
+ ===========================
+ [..]
+ (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo().
+ It returns useful information about the MMC card such as block size, card type,
+ block number ...
+
+ *** MMC card CSD register ***
+ ============================
+ [..]
+ (+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register.
+ Some of the CSD parameters are useful for card initialization and identification.
+
+ *** MMC card CID register ***
+ ============================
+ [..]
+ (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register.
+ Some of the CID parameters are useful for card initialization and identification.
+
+ *** MMC HAL driver macros list ***
+ ==================================
+ [..]
+ Below the list of most used macros in MMC HAL driver.
+
+ (+) __HAL_MMC_ENABLE : Enable the MMC device
+ (+) __HAL_MMC_DISABLE : Disable the MMC device
+ (+) __HAL_MMC_DMA_ENABLE: Enable the SDMMC DMA transfer
+ (+) __HAL_MMC_DMA_DISABLE: Disable the SDMMC DMA transfer
+ (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt
+ (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt
+ (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not
+ (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags
+
+ [..]
+ (@) You can refer to the MMC HAL driver header file for more useful macros
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup MMC
+ * @{
+ */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+
+#if defined(STM32F103xE) || defined(STM32F103xG)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup MMC_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Functions MMC Private Functions
+ * @{
+ */
+static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc);
+static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc);
+static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus);
+static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc);
+static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc);
+static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc);
+static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void MMC_DMAError(DMA_HandleTypeDef *hdma);
+static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma);
+static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup MMC_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup MMC_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize/de-initialize the MMC
+ card device to be ready for use.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the MMC according to the specified parameters in the
+ MMC_HandleTypeDef and create the associated handle.
+ * @param hmmc: Pointer to the MMC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
+{
+ /* Check the MMC handle allocation */
+ if(hmmc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_ALL_INSTANCE(hmmc->Instance));
+ assert_param(IS_SDIO_CLOCK_EDGE(hmmc->Init.ClockEdge));
+ assert_param(IS_SDIO_CLOCK_BYPASS(hmmc->Init.ClockBypass));
+ assert_param(IS_SDIO_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave));
+ assert_param(IS_SDIO_BUS_WIDE(hmmc->Init.BusWide));
+ assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl));
+ assert_param(IS_SDIO_CLKDIV(hmmc->Init.ClockDiv));
+
+ if(hmmc->State == HAL_MMC_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hmmc->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_MMC_MspInit(hmmc);
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize the Card parameters */
+ HAL_MMC_InitCard(hmmc);
+
+ /* Initialize the error code */
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ /* Initialize the MMC operation */
+ hmmc->Context = MMC_CONTEXT_NONE;
+
+ /* Initialize the MMC state */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the MMC Card.
+ * @param hmmc: Pointer to MMC handle
+ * @note This function initializes the MMC card. It could be used when a card
+ re-initialization is needed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ MMC_InitTypeDef Init;
+
+ /* Default SDMMC peripheral configuration for MMC card initialization */
+ Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
+ Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
+ Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
+ Init.BusWide = SDIO_BUS_WIDE_1B;
+ Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+ Init.ClockDiv = SDIO_INIT_CLK_DIV;
+
+ /* Initialize SDMMC peripheral interface with default configuration */
+ SDIO_Init(hmmc->Instance, Init);
+
+ /* Disable SDMMC Clock */
+ __HAL_MMC_DISABLE(hmmc);
+
+ /* Set Power State to ON */
+ SDIO_PowerState_ON(hmmc->Instance);
+
+ /* Enable SDMMC Clock */
+ __HAL_MMC_ENABLE(hmmc);
+
+ /* Required power up waiting time before starting the SD initialization
+ sequence */
+ HAL_Delay(2U);
+
+ /* Identify card operating voltage */
+ errorstate = MMC_PowerON(hmmc);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
+ /* Card initialization */
+ errorstate = MMC_InitCard(hmmc);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode |= errorstate;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief De-Initializes the MMC card.
+ * @param hmmc: Pointer to MMC handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
+{
+ /* Check the MMC handle allocation */
+ if(hmmc == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_ALL_INSTANCE(hmmc->Instance));
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Set SD power state to off */
+ MMC_PowerOFF(hmmc);
+
+ /* De-Initialize the MSP layer */
+ HAL_MMC_MspDeInit(hmmc);
+
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+ hmmc->State = HAL_MMC_STATE_RESET;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Initializes the MMC MSP.
+ * @param hmmc: Pointer to MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MMC_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-Initialize MMC MSP.
+ * @param hmmc: Pointer to MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_MMC_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup MMC_Exported_Functions_Group2
+ * @brief Data transfer functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the data
+ transfer from/to MMC card.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by polling mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of MMC blocks to read
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count = 0U, *tempbuff = (uint32_t *)pData;
+
+ if(NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ /* Check the Card capacity in term of Logical number of blocks */
+ if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hmmc->Instance, &config);
+
+ /* Read block(s) in polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK;
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
+ }
+ else
+ {
+ hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK;
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Poll on SDMMC flags */
+#ifdef SDIO_STA_STBITERR
+ while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_STA_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
+#endif /* SDIO_STA_STBITERR */
+ {
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF))
+ {
+ /* Read data from SDMMC Rx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ *(tempbuff + count) = SDIO_ReadFIFO(hmmc->Instance);
+ }
+ tempbuff += 8U;
+ }
+
+ if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State= HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send stop transmission command in case of multiblock read */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ {
+ /* Send stop transmission command */
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get error state */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Empty FIFO if there is still any data */
+ while ((__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXDAVL)))
+ {
+ *tempbuff = SDIO_ReadFIFO(hmmc->Instance);
+ tempbuff++;
+
+ if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State= HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Allows to write block(s) to a specified address in a card. The Data
+ * transfer is managed by polling mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of MMC blocks to write
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count = 0U;
+ uint32_t *tempbuff = (uint32_t *)pData;
+
+ if(NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ /* Check the Card capacity in term of Logical number of blocks */
+ if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Write Blocks in Polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
+ }
+ else
+ {
+ hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK;
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hmmc->Instance, &config);
+
+ /* Write block(s) in polling mode */
+#ifdef SDIO_STA_STBITERR
+ while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+#else /* SDIO_STA_STBITERR not defined */
+ while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND))
+#endif /* SDIO_STA_STBITERR */
+ {
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXFIFOHE))
+ {
+ /* Write data to SDIO Tx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ SDIO_WriteFIFO(hmmc->Instance, (tempbuff + count));
+ }
+ tempbuff += 8U;
+ }
+
+ if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Send stop transmission command in case of multiblock write */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ {
+ /* Send stop transmission command */
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get error state */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY;
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @note You could also check the IT transfer process through the MMC Rx
+ * interrupt event.
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of blocks to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ if(NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ hmmc->pRxBuffPtr = (uint32_t *)pData;
+ hmmc->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF));
+
+ /* Check the Card capacity in term of Logical number of blocks */
+ if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hmmc->Instance, &config);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Read Blocks in IT mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
+ }
+ else
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @note You could also check the IT transfer process through the MMC Tx
+ * interrupt event.
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ if(NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ hmmc->pTxBuffPtr = (uint32_t *)pData;
+ hmmc->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+ /* Enable transfer interrupts */
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE));
+
+ /* Check the Card capacity in term of Logical number of blocks */
+ if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Write Blocks in Polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
+ }
+ else
+ {
+ hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hmmc->Instance, &config);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed by DMA mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @note You could also check the DMA transfer process through the MMC Rx
+ * interrupt event.
+ * @param hmmc: Pointer MMC handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of blocks to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ if(NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+#ifdef SDIO_STA_STBITER
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND));
+#endif /* SDIO_STA_STBITERR */
+
+ /* Set the DMA transfer complete callback */
+ hmmc->hdmarx->XferCpltCallback = MMC_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hmmc->hdmarx->XferErrorCallback = MMC_DMAError;
+
+ /* Set the DMA Abort callback */
+ hmmc->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
+
+ /* Enable MMC DMA transfer */
+ __HAL_MMC_DMA_ENABLE(hmmc);
+
+ /* Check the Card capacity in term of Logical number of blocks */
+ if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hmmc->Instance, &config);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Read Blocks in DMA mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd);
+ }
+ else
+ {
+ hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed by DMA mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @note You could also check the DMA transfer process through the MMC Tx
+ * interrupt event.
+ * @param hmmc: Pointer to MMC handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ if(NULL == pData)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0U;
+
+ /* Enable MMC Error interrupts */
+#ifdef SDIO_STA_STBITER
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR));
+#endif /* SDIO_STA_STBITERR */
+
+ /* Set the DMA transfer complete callback */
+ hmmc->hdmatx->XferCpltCallback = MMC_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hmmc->hdmatx->XferErrorCallback = MMC_DMAError;
+
+ /* Set the DMA Abort callback */
+ hmmc->hdmatx->XferAbortCallback = NULL;
+
+ /* Check the Card capacity in term of Logical number of blocks */
+ if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Write Blocks in Polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd);
+ }
+ else
+ {
+ hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Enable SDIO DMA transfer */
+ __HAL_MMC_DMA_ENABLE(hmmc);
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hmmc->Instance, &config);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Erases the specified memory area of the given MMC card.
+ * @note This API should be followed by a check on the card state through
+ * HAL_MMC_GetCardState().
+ * @param hmmc: Pointer to MMC handle
+ * @param BlockStartAdd: Start Block address
+ * @param BlockEndAdd: End Block address
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
+{
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if(BlockEndAdd < BlockStartAdd)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(BlockEndAdd > (hmmc->MmcCard.LogBlockNbr))
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Check if the card command class supports erase command */
+ if((hmmc->MmcCard.Class) & SDIO_CCCC_ERASE == 0U)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ if((SDIO_GetResponse(hmmc->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Check the Card capacity in term of Logical number of blocks */
+ if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY)
+ {
+ BlockStartAdd *= 512U;
+ BlockEndAdd *= 512U;
+ }
+
+ /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */
+ errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, BlockStartAdd);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Send CMD36 MMC_ERASE_GRP_END with argument as addr */
+ errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, BlockEndAdd);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Send CMD38 ERASE */
+ errorstate = SDMMC_CmdErase(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief This function handles MMC card interrupt request.
+ * @param hmmc: Pointer to MMC handle
+ * @retval None
+ */
+void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ /* Check for SDIO interrupt flags */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DATAEND) != RESET)
+ {
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_DATAEND);
+
+#ifdef SDIO_STA_STBITERR
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
+#else /* SDIO_STA_STBITERR not defined */
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR);
+#endif
+
+ if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
+ {
+ if(((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
+ {
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ HAL_MMC_ErrorCallback(hmmc);
+ }
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+ if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
+ {
+ HAL_MMC_RxCpltCallback(hmmc);
+ }
+ else
+ {
+ HAL_MMC_TxCpltCallback(hmmc);
+ }
+ }
+ else if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
+ {
+ if((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
+ {
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ HAL_MMC_ErrorCallback(hmmc);
+ }
+ }
+ if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
+ {
+ /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+ in the MMC DCTRL register */
+ hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ HAL_MMC_TxCpltCallback(hmmc);
+ }
+ }
+ }
+
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_TXFIFOHE) != RESET)
+ {
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_TXFIFOHE);
+
+ MMC_Write_IT(hmmc);
+ }
+
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_RXFIFOHF) != RESET)
+ {
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_RXFIFOHF);
+
+ MMC_Read_IT(hmmc);
+ }
+
+#ifdef SDIO_STA_STBITERR
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR) != RESET)
+ {
+ /* Set Error code */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ }
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DTIMEOUT) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ }
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_RXOVERR) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ }
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_TXUNDERR) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+ }
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_STBITERR) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ }
+
+ /* Clear All flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS | SDIO_FLAG_STBITERR);
+
+ /* Disable all interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR |SDIO_IT_STBITERR);
+
+ if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
+ {
+ /* Abort the MMC DMA Streams */
+ if(hmmc->hdmatx != NULL)
+ {
+ /* Set the DMA Tx abort callback */
+ hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort;
+ /* Abort DMA in IT mode */
+ if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK)
+ {
+ MMC_DMATxAbort(hmmc->hdmatx);
+ }
+ }
+ else if(hmmc->hdmarx != NULL)
+ {
+ /* Set the DMA Rx abort callback */
+ hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort;
+ /* Abort DMA in IT mode */
+ if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK)
+ {
+ MMC_DMARxAbort(hmmc->hdmarx);
+ }
+ }
+ else
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+ hmmc->State = HAL_MMC_STATE_READY;
+ HAL_MMC_AbortCallback(hmmc);
+ }
+ }
+ else if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
+ {
+ /* Set the MMC state to ready to be able to start again the process */
+ hmmc->State = HAL_MMC_STATE_READY;
+ HAL_MMC_ErrorCallback(hmmc);
+ }
+ }
+#else /* SDIO_STA_STBITERR not defined */
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR) != RESET)
+ {
+ /* Set Error code */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ }
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DTIMEOUT) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ }
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_RXOVERR) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ }
+ if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_TXUNDERR) != RESET)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
+ }
+
+ /* Clear All flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ /* Disable all interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ if((hmmc->Context & MMC_CONTEXT_DMA) != RESET)
+ {
+ /* Abort the MMC DMA Streams */
+ if(hmmc->hdmatx != NULL)
+ {
+ /* Set the DMA Tx abort callback */
+ hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort;
+ /* Abort DMA in IT mode */
+ if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK)
+ {
+ MMC_DMATxAbort(hmmc->hdmatx);
+ }
+ }
+ else if(hmmc->hdmarx != NULL)
+ {
+ /* Set the DMA Rx abort callback */
+ hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort;
+ /* Abort DMA in IT mode */
+ if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK)
+ {
+ MMC_DMARxAbort(hmmc->hdmarx);
+ }
+ }
+ else
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+ hmmc->State = HAL_MMC_STATE_READY;
+ HAL_MMC_AbortCallback(hmmc);
+ }
+ }
+ else if((hmmc->Context & MMC_CONTEXT_IT) != RESET)
+ {
+ /* Set the MMC state to ready to be able to start again the process */
+ hmmc->State = HAL_MMC_STATE_READY;
+ HAL_MMC_ErrorCallback(hmmc);
+ }
+ }
+#endif /* SDIO_STA_STBITERR */
+}
+
+/**
+ * @brief return the MMC state
+ * @param hmmc: Pointer to mmc handle
+ * @retval HAL state
+ */
+HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
+{
+ return hmmc->State;
+}
+
+/**
+* @brief Return the MMC error code
+* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains
+ * the configuration information.
+* @retval MMC Error Code
+*/
+uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc)
+{
+ return hmmc->ErrorCode;
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hmmc: Pointer to MMC handle
+ * @retval None
+ */
+ __weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MMC_TxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief Rx Transfer completed callbacks
+ * @param hmmc: Pointer MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MMC_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief MMC error callbacks
+ * @param hmmc: Pointer MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MMC_ErrorCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief MMC Abort callbacks
+ * @param hmmc: Pointer MMC handle
+ * @retval None
+ */
+__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hmmc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_MMC_ErrorCallback can be implemented in the user file
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup MMC_Exported_Functions_Group3
+ * @brief management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral Control functions #####
+ ==============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the MMC card
+ operations and get the related information
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns information the information of the card which are stored on
+ * the CID register.
+ * @param hmmc: Pointer to MMC handle
+ * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that
+ * contains all CID register parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID)
+{
+ uint32_t tmp = 0U;
+
+ /* Byte 0 */
+ tmp = (uint8_t)((hmmc->CID[0U] & 0xFF000000U) >> 24U);
+ pCID->ManufacturerID = tmp;
+
+ /* Byte 1 */
+ tmp = (uint8_t)((hmmc->CID[0U] & 0x00FF0000U) >> 16U);
+ pCID->OEM_AppliID = tmp << 8U;
+
+ /* Byte 2 */
+ tmp = (uint8_t)((hmmc->CID[0U] & 0x000000FF00U) >> 8U);
+ pCID->OEM_AppliID |= tmp;
+
+ /* Byte 3 */
+ tmp = (uint8_t)(hmmc->CID[0U] & 0x000000FFU);
+ pCID->ProdName1 = tmp << 24U;
+
+ /* Byte 4 */
+ tmp = (uint8_t)((hmmc->CID[1U] & 0xFF000000U) >> 24U);
+ pCID->ProdName1 |= tmp << 16U;
+
+ /* Byte 5 */
+ tmp = (uint8_t)((hmmc->CID[1U] & 0x00FF0000U) >> 16U);
+ pCID->ProdName1 |= tmp << 8U;
+
+ /* Byte 6 */
+ tmp = (uint8_t)((hmmc->CID[1U] & 0x0000FF00U) >> 8U);
+ pCID->ProdName1 |= tmp;
+
+ /* Byte 7 */
+ tmp = (uint8_t)(hmmc->CID[1U] & 0x000000FFU);
+ pCID->ProdName2 = tmp;
+
+ /* Byte 8 */
+ tmp = (uint8_t)((hmmc->CID[2U] & 0xFF000000U) >> 24U);
+ pCID->ProdRev = tmp;
+
+ /* Byte 9 */
+ tmp = (uint8_t)((hmmc->CID[2U] & 0x00FF0000U) >> 16U);
+ pCID->ProdSN = tmp << 24U;
+
+ /* Byte 10 */
+ tmp = (uint8_t)((hmmc->CID[2U] & 0x0000FF00U) >> 8U);
+ pCID->ProdSN |= tmp << 16U;
+
+ /* Byte 11 */
+ tmp = (uint8_t)(hmmc->CID[2U] & 0x000000FFU);
+ pCID->ProdSN |= tmp << 8U;
+
+ /* Byte 12 */
+ tmp = (uint8_t)((hmmc->CID[3U] & 0xFF000000U) >> 24U);
+ pCID->ProdSN |= tmp;
+
+ /* Byte 13 */
+ tmp = (uint8_t)((hmmc->CID[3U] & 0x00FF0000U) >> 16U);
+ pCID->Reserved1 |= (tmp & 0xF0U) >> 4U;
+ pCID->ManufactDate = (tmp & 0x0FU) << 8U;
+
+ /* Byte 14 */
+ tmp = (uint8_t)((hmmc->CID[3U] & 0x0000FF00U) >> 8U);
+ pCID->ManufactDate |= tmp;
+
+ /* Byte 15 */
+ tmp = (uint8_t)(hmmc->CID[3U] & 0x000000FFU);
+ pCID->CID_CRC = (tmp & 0xFEU) >> 1U;
+ pCID->Reserved2 = 1U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns information the information of the card which are stored on
+ * the CSD register.
+ * @param hmmc: Pointer to MMC handle
+ * @param pCSD: Pointer to a HAL_MMC_CardInfoTypeDef structure that
+ * contains all CSD register parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD)
+{
+ uint32_t tmp = 0U;
+
+ /* Byte 0 */
+ tmp = (hmmc->CSD[0U] & 0xFF000000U) >> 24U;
+ pCSD->CSDStruct = (uint8_t)((tmp & 0xC0U) >> 6U);
+ pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3CU) >> 2U);
+ pCSD->Reserved1 = tmp & 0x03U;
+
+ /* Byte 1 */
+ tmp = (hmmc->CSD[0U] & 0x00FF0000U) >> 16U;
+ pCSD->TAAC = (uint8_t)tmp;
+
+ /* Byte 2 */
+ tmp = (hmmc->CSD[0U] & 0x0000FF00U) >> 8U;
+ pCSD->NSAC = (uint8_t)tmp;
+
+ /* Byte 3 */
+ tmp = hmmc->CSD[0U] & 0x000000FFU;
+ pCSD->MaxBusClkFrec = (uint8_t)tmp;
+
+ /* Byte 4 */
+ tmp = (hmmc->CSD[1U] & 0xFF000000U) >> 24U;
+ pCSD->CardComdClasses = (uint16_t)(tmp << 4U);
+
+ /* Byte 5 */
+ tmp = (hmmc->CSD[1U] & 0x00FF0000U) >> 16U;
+ pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0U) >> 4U);
+ pCSD->RdBlockLen = (uint8_t)(tmp & 0x0FU);
+
+ /* Byte 6 */
+ tmp = (hmmc->CSD[1U] & 0x0000FF00U) >> 8U;
+ pCSD->PartBlockRead = (uint8_t)((tmp & 0x80U) >> 7U);
+ pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40U) >> 6U);
+ pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20U) >> 5U);
+ pCSD->DSRImpl = (uint8_t)((tmp & 0x10U) >> 4U);
+ pCSD->Reserved2 = 0; /*!< Reserved */
+
+ pCSD->DeviceSize = (tmp & 0x03U) << 10U;
+
+ /* Byte 7 */
+ tmp = (uint8_t)(hmmc->CSD[1U] & 0x000000FFU);
+ pCSD->DeviceSize |= (tmp) << 2U;
+
+ /* Byte 8 */
+ tmp = (uint8_t)((hmmc->CSD[2U] & 0xFF000000U) >> 24U);
+ pCSD->DeviceSize |= (tmp & 0xC0U) >> 6U;
+
+ pCSD->MaxRdCurrentVDDMin = (tmp & 0x38U) >> 3U;
+ pCSD->MaxRdCurrentVDDMax = (tmp & 0x07U);
+
+ /* Byte 9 */
+ tmp = (uint8_t)((hmmc->CSD[2U] & 0x00FF0000U) >> 16U);
+ pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0U) >> 5U;
+ pCSD->MaxWrCurrentVDDMax = (tmp & 0x1CU) >> 2U;
+ pCSD->DeviceSizeMul = (tmp & 0x03U) << 1U;
+ /* Byte 10 */
+ tmp = (uint8_t)((hmmc->CSD[2] & 0x0000FF00U) >> 8U);
+ pCSD->DeviceSizeMul |= (tmp & 0x80U) >> 7U;
+
+ hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
+ hmmc->MmcCard.BlockNbr *= (1U << (pCSD->DeviceSizeMul + 2U));
+ hmmc->MmcCard.BlockSize = 1U << (pCSD->RdBlockLen);
+
+ hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U);
+ hmmc->MmcCard.LogBlockSize = 512U;
+
+ pCSD->EraseGrSize = (tmp & 0x40U) >> 6U;
+ pCSD->EraseGrMul = (tmp & 0x3FU) << 1U;
+
+ /* Byte 11 */
+ tmp = (uint8_t)(hmmc->CSD[2U] & 0x000000FFU);
+ pCSD->EraseGrMul |= (tmp & 0x80U) >> 7U;
+ pCSD->WrProtectGrSize = (tmp & 0x7FU);
+
+ /* Byte 12 */
+ tmp = (uint8_t)((hmmc->CSD[3U] & 0xFF000000U) >> 24U);
+ pCSD->WrProtectGrEnable = (tmp & 0x80U) >> 7U;
+ pCSD->ManDeflECC = (tmp & 0x60U) >> 5U;
+ pCSD->WrSpeedFact = (tmp & 0x1CU) >> 2U;
+ pCSD->MaxWrBlockLen = (tmp & 0x03U) << 2U;
+
+ /* Byte 13 */
+ tmp = (uint8_t)((hmmc->CSD[3U] & 0x00FF0000U) >> 16U);
+ pCSD->MaxWrBlockLen |= (tmp & 0xC0U) >> 6U;
+ pCSD->WriteBlockPaPartial = (tmp & 0x20U) >> 5U;
+ pCSD->Reserved3 = 0U;
+ pCSD->ContentProtectAppli = (tmp & 0x01U);
+
+ /* Byte 14 */
+ tmp = (uint8_t)((hmmc->CSD[3U] & 0x0000FF00U) >> 8U);
+ pCSD->FileFormatGrouop = (tmp & 0x80U) >> 7U;
+ pCSD->CopyFlag = (tmp & 0x40U) >> 6U;
+ pCSD->PermWrProtect = (tmp & 0x20U) >> 5U;
+ pCSD->TempWrProtect = (tmp & 0x10U) >> 4U;
+ pCSD->FileFormat = (tmp & 0x0CU) >> 2U;
+ pCSD->ECC = (tmp & 0x03U);
+
+ /* Byte 15 */
+ tmp = (uint8_t)(hmmc->CSD[3U] & 0x000000FFU);
+ pCSD->CSD_CRC = (tmp & 0xFEU) >> 1U;
+ pCSD->Reserved4 = 1U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets the MMC card info.
+ * @param hmmc: Pointer to MMC handle
+ * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that
+ * will contain the MMC card status information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo)
+{
+ pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType);
+ pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class);
+ pCardInfo->RelCardAdd = (uint32_t)(hmmc->MmcCard.RelCardAdd);
+ pCardInfo->BlockNbr = (uint32_t)(hmmc->MmcCard.BlockNbr);
+ pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize);
+ pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr);
+ pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enables wide bus operation for the requested card if supported by
+ * card.
+ * @param hmmc: Pointer to MMC handle
+ * @param WideMode: Specifies the MMC card wide bus mode
+ * This parameter can be one of the following values:
+ * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
+ * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
+ * @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode)
+{
+ __IO uint32_t count = 0U;
+ SDIO_InitTypeDef Init;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t response = 0U, busy = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_BUS_WIDE(WideMode));
+
+ /* Chnage Satte */
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Update Clock for Bus mode update */
+ Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
+ Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
+ Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
+ Init.BusWide = WideMode;
+ Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+ Init.ClockDiv = SDIO_INIT_CLK_DIV;
+ /* Initialize SDIO*/
+ SDIO_Init(hmmc->Instance, Init);
+
+ if(WideMode == SDIO_BUS_WIDE_8B)
+ {
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+ }
+ else if(WideMode == SDIO_BUS_WIDE_4B)
+ {
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+ }
+ else if(WideMode == SDIO_BUS_WIDE_1B)
+ {
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+ }
+ else
+ {
+ /* WideMode is not a valid argument*/
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ }
+
+ /* Check for switch error and violation of the trial number of sending CMD 13 */
+ while(busy == 0U)
+ {
+ if(count++ == SDMMC_MAX_TRIAL)
+ {
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
+ return HAL_ERROR;
+ }
+
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+
+ /* Get command response */
+ response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
+
+ /* Get operating voltage*/
+ busy = (((response >> 7U) == 1U) ? 0U : 1U);
+ }
+
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_DATATIMEOUT;
+ while((response & 0x00000100U) == 0U)
+ {
+ if(count-- == 0U)
+ {
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
+ return HAL_ERROR;
+ }
+
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+
+ /* Get command response */
+ response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
+ }
+
+ if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Configure the SDIO peripheral */
+ Init.ClockEdge = hmmc->Init.ClockEdge;
+ Init.ClockBypass = hmmc->Init.ClockBypass;
+ Init.ClockPowerSave = hmmc->Init.ClockPowerSave;
+ Init.BusWide = WideMode;
+ Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
+ Init.ClockDiv = hmmc->Init.ClockDiv;
+ SDIO_Init(hmmc->Instance, Init);
+ }
+
+ /* Change State */
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Gets the current mmc card data state.
+ * @param hmmc: pointer to MMC handle
+ * @retval Card state
+ */
+HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
+{
+ HAL_MMC_CardStateTypeDef cardstate = HAL_MMC_CARD_TRANSFER;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t resp1 = 0U;
+
+ errorstate = MMC_SendStatus(hmmc, &resp1);
+ if(errorstate != HAL_OK)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+
+ cardstate = (HAL_MMC_CardStateTypeDef)((resp1 >> 9U) & 0x0FU);
+
+ return cardstate;
+}
+
+/**
+ * @brief Abort the current transfer and disable the MMC.
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * the configuration information for MMC module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
+{
+ HAL_MMC_CardStateTypeDef CardState;
+
+ /* DIsable All interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ /* Clear All flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL))
+ {
+ /* Disable the MMC DMA request */
+ hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+ /* Abort the MMC DMA Tx Stream */
+ if(hmmc->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(hmmc->hdmatx);
+ }
+ /* Abort the MMC DMA Rx Stream */
+ if(hmmc->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hmmc->hdmarx);
+ }
+ }
+
+ hmmc->State = HAL_MMC_STATE_READY;
+ CardState = HAL_MMC_GetCardState(hmmc);
+ if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ {
+ hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
+ }
+ if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort the current transfer and disable the MMC (IT mode).
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * the configuration information for MMC module.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc)
+{
+ HAL_MMC_CardStateTypeDef CardState;
+
+ /* DIsable All interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ /* Clear All flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL))
+ {
+ /* Disable the MMC DMA request */
+ hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+ /* Abort the MMC DMA Tx Stream */
+ if(hmmc->hdmatx != NULL)
+ {
+ hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort;
+ if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK)
+ {
+ hmmc->hdmatx = NULL;
+ }
+ }
+ /* Abort the MMC DMA Rx Stream */
+ if(hmmc->hdmarx != NULL)
+ {
+ hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort;
+ if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK)
+ {
+ hmmc->hdmarx = NULL;
+ }
+ }
+ }
+
+ /* No transfer ongoing on both DMA channels*/
+ if((hmmc->hdmatx == NULL) && (hmmc->hdmarx == NULL))
+ {
+ CardState = HAL_MMC_GetCardState(hmmc);
+ hmmc->State = HAL_MMC_STATE_READY;
+ if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ {
+ hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
+ }
+ if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ HAL_MMC_AbortCallback(hmmc);
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup MMC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief DMA MMC transmit process complete callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
+
+ /* Enable DATAEND Interrupt */
+ __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DATAEND));
+}
+
+/**
+ * @brief DMA MMC receive process complete callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ /* Send stop command in multiblock write */
+ if(hmmc->Context == (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA))
+ {
+ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ HAL_MMC_ErrorCallback(hmmc);
+ }
+ }
+
+ /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+ in the MMC DCTRL register */
+ hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ hmmc->State = HAL_MMC_STATE_READY;
+
+ HAL_MMC_RxCpltCallback(hmmc);
+}
+
+/**
+ * @brief DMA MMC communication error callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void MMC_DMAError(DMA_HandleTypeDef *hdma)
+{
+ MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
+ HAL_MMC_CardStateTypeDef CardState;
+
+ if((hmmc->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hmmc->hdmatx->ErrorCode == HAL_DMA_ERROR_TE))
+ {
+ /* Clear All flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+
+ /* Disable All interrupts */
+ __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DMA;
+ CardState = HAL_MMC_GetCardState(hmmc);
+ if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ {
+ hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
+ }
+
+ hmmc->State= HAL_MMC_STATE_READY;
+ }
+
+ HAL_MMC_ErrorCallback(hmmc);
+}
+
+/**
+ * @brief DMA MMC Tx Abort callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma)
+{
+ MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
+ HAL_MMC_CardStateTypeDef CardState;
+
+ if(hmmc->hdmatx != NULL)
+ {
+ hmmc->hdmatx = NULL;
+ }
+
+ /* All DMA channels are aborted */
+ if(hmmc->hdmarx == NULL)
+ {
+ CardState = HAL_MMC_GetCardState(hmmc);
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+ hmmc->State = HAL_MMC_STATE_READY;
+ if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ {
+ hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
+
+ if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ {
+ HAL_MMC_AbortCallback(hmmc);
+ }
+ else
+ {
+ HAL_MMC_ErrorCallback(hmmc);
+ }
+ }
+ }
+}
+
+/**
+ * @brief DMA MMC Rx Abort callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma)
+{
+ MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
+ HAL_MMC_CardStateTypeDef CardState;
+
+ if(hmmc->hdmarx != NULL)
+ {
+ hmmc->hdmarx = NULL;
+ }
+
+ /* All DMA channels are aborted */
+ if(hmmc->hdmatx == NULL)
+ {
+ CardState = HAL_MMC_GetCardState(hmmc);
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+ hmmc->State = HAL_MMC_STATE_READY;
+ if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+ {
+ hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
+
+ if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
+ {
+ HAL_MMC_AbortCallback(hmmc);
+ }
+ else
+ {
+ HAL_MMC_ErrorCallback(hmmc);
+ }
+ }
+ }
+}
+
+
+/**
+ * @brief Initializes the mmc card.
+ * @param hmmc: Pointer to MMC handle
+ * @retval MMC Card error state
+ */
+static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
+{
+ HAL_MMC_CardCSDTypeDef CSD;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint16_t mmc_rca = 1;
+
+ /* Check the power State */
+ if(SDIO_GetPowerState(hmmc->Instance) == 0U)
+ {
+ /* Power off */
+ return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE;
+ }
+
+ /* Send CMD2 ALL_SEND_CID */
+ errorstate = SDMMC_CmdSendCID(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+ else
+ {
+ /* Get Card identification number data */
+ hmmc->CID[0U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
+ hmmc->CID[1U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP2);
+ hmmc->CID[2U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP3);
+ hmmc->CID[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4);
+ }
+
+ /* Send CMD3 SET_REL_ADDR with argument 0 */
+ /* MMC Card publishes its RCA. */
+ errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Get the MMC card RCA */
+ hmmc->MmcCard.RelCardAdd = mmc_rca;
+
+ /* Send CMD9 SEND_CSD with argument as card's RCA */
+ errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+ else
+ {
+ /* Get Card Specific Data */
+ hmmc->CSD[0U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
+ hmmc->CSD[1U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP2);
+ hmmc->CSD[2U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP3);
+ hmmc->CSD[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4);
+ }
+
+ /* Get the Card Class */
+ hmmc->MmcCard.Class = (SDIO_GetResponse(hmmc->Instance, SDIO_RESP2) >> 20U);
+
+ /* Get CSD parameters */
+ HAL_MMC_GetCardCSD(hmmc, &CSD);
+
+ /* Select the Card */
+ errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Configure SDIO peripheral interface */
+ SDIO_Init(hmmc->Instance, hmmc->Init);
+
+ /* All cards are initialized */
+ return HAL_MMC_ERROR_NONE;
+}
+
+/**
+ * @brief Enquires cards about their operating voltage and configures clock
+ * controls and stores MMC information that will be needed in future
+ * in the MMC handle.
+ * @param hmmc: Pointer to MMC handle
+ * @retval error state
+ */
+static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
+{
+ __IO uint32_t count = 0U;
+ uint32_t response = 0U, validvoltage = 0U;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ /* CMD0: GO_IDLE_STATE */
+ errorstate = SDMMC_CmdGoIdleState(hmmc->Instance);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ while(validvoltage == 0U)
+ {
+ if(count++ == SDMMC_MAX_VOLT_TRIAL)
+ {
+ return HAL_MMC_ERROR_INVALID_VOLTRANGE;
+ }
+
+ /* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */
+ errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ return HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+
+ /* Get command response */
+ response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
+
+ /* Get operating voltage*/
+ validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+ }
+
+ /* When power routine is finished and command returns valid voltage */
+ if ((response & eMMC_HIGH_VOLTAGE_RANGE) == MMC_HIGH_VOLTAGE_RANGE)
+ {
+ /* When voltage range of the card is within 2.7V and 3.6V */
+ hmmc->MmcCard.CardType = MMC_HIGH_VOLTAGE_CARD;
+ }
+ else
+ {
+ /* When voltage range of the card is within 1.65V and 1.95V or 2.7V and 3.6V */
+ hmmc->MmcCard.CardType = MMC_DUAL_VOLTAGE_CARD;
+ }
+
+ return HAL_MMC_ERROR_NONE;
+}
+
+/**
+ * @brief Turns the SDIO output signals off.
+ * @param hmmc: Pointer to MMC handle
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
+{
+ /* Set Power State to OFF */
+ SDIO_PowerState_OFF(hmmc->Instance);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns the current card's status.
+ * @param hmmc: Pointer to MMC handle
+ * @param pCardStatus: pointer to the buffer that will contain the MMC card
+ * status (Card Status register)
+ * @retval error state
+ */
+static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus)
+{
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+
+ if(pCardStatus == NULL)
+ {
+ return HAL_MMC_ERROR_PARAM;
+ }
+
+ /* Send Status command */
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U));
+ if(errorstate != HAL_OK)
+ {
+ return errorstate;
+ }
+
+ /* Get MMC card status */
+ *pCardStatus = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1);
+
+ return HAL_MMC_ERROR_NONE;
+}
+
+/**
+ * @brief Wrap up reading in non-blocking mode.
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * the configuration information.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t count = 0U;
+ uint32_t* tmp;
+
+ tmp = (uint32_t*)hmmc->pRxBuffPtr;
+
+ /* Read data from SDMMC Rx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ *(tmp + count) = SDIO_ReadFIFO(hmmc->Instance);
+ }
+
+ hmmc->pRxBuffPtr += 8U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Wrap up writing in non-blocking mode.
+ * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * the configuration information.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc)
+{
+ uint32_t count = 0U;
+ uint32_t* tmp;
+
+ tmp = (uint32_t*)hmmc->pTxBuffPtr;
+
+ /* Write data to SDMMC Tx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ SDIO_WriteFIFO(hmmc->Instance, (tmp + count));
+ }
+
+ hmmc->pTxBuffPtr += 8U;
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#endif /* STM32F103xE || STM32F103xG */
+
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_msp_template.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_msp_template.c
index d003d36..03fafd5 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_msp_template.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_msp_template.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_msp_template.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief HAL BSP module.
* This file template is located in the HAL folder and should be copied
* to the user folder.
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_nand.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_nand.c
index 097cd15..3663bf2 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_nand.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_nand.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_nand.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
@@ -14,7 +14,7 @@
==============================================================================
[..]
This driver is a generic layered driver which contains a set of APIs used to
- control NAND flash memories. It uses the FSMC/FSMC layer functions to interface
+ control NAND flash memories. It uses the FSMC layer functions to interface
with NAND devices. This driver is used as follows:
(+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
@@ -25,9 +25,12 @@
structure declared by the function caller.
(+) Access NAND flash memory by read/write operations using the functions
- HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
+ HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
+ HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
+ HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
+ HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
to read/write page(s)/spare area(s). These functions use specific device
- information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
+ information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
structure. The read/write address information is contained by the Nand_Address_Typedef
structure passed as parameter.
@@ -55,7 +58,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -119,16 +122,7 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @defgroup NAND_Private_Functions NAND Private Functions
- * @{
- */
-static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address);
-/**
- * @}
- */
-
-/* Exported functions ---------------------------------------------------------*/
-
+/* Exported functions --------------------------------------------------------*/
/** @defgroup NAND_Exported_Functions NAND Exported Functions
* @{
*/
@@ -168,7 +162,6 @@
{
/* Allocate lock resource and initialize it */
hnand->Lock = HAL_UNLOCKED;
-
/* Initialize the low level hardware (MSP) */
HAL_NAND_MspInit(hnand);
}
@@ -291,8 +284,7 @@
/* Clear NAND interrupt FIFO empty pending bit */
__FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
- }
-
+ }
}
/**
@@ -338,8 +330,9 @@
*/
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
{
- __IO uint32_t data = 0;
- uint32_t deviceaddress = 0;
+ __IO uint32_t data = 0U;
+ __IO uint32_t data1 = 0U;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -367,20 +360,34 @@
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- /* Read the electronic signature from NAND flash */
- data = *(__IO uint32_t *)deviceaddress;
-
- /* Return the data read */
- pNAND_ID->Maker_Id = ADDR_1st_CYCLE(data);
- pNAND_ID->Device_Id = ADDR_2nd_CYCLE(data);
- pNAND_ID->Third_Id = ADDR_3rd_CYCLE(data);
- pNAND_ID->Fourth_Id = ADDR_4th_CYCLE(data);
+ /* Read the electronic signature from NAND flash */
+ if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8)
+ {
+ data = *(__IO uint32_t *)deviceaddress;
+
+ /* Return the data read */
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
+ pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
+ pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
+ pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
+ }
+ else
+ {
+ data = *(__IO uint32_t *)deviceaddress;
+ data1 = *((__IO uint32_t *)deviceaddress + 4U);
+
+ /* Return the data read */
+ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
+ pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
+ pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
+ pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
+ }
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
+ __HAL_UNLOCK(hnand);
return HAL_OK;
}
@@ -393,18 +400,18 @@
*/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
{
- uint32_t deviceaddress = 0;
-
+ uint32_t deviceaddress = 0U;
+
/* Process Locked */
__HAL_LOCK(hnand);
-
+
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
- /* Identify the device address */
+ /* Identify the device address */
if(hnand->Init.NandBank == FSMC_NAND_BANK2)
{
deviceaddress = NAND_DEVICE1;
@@ -414,25 +421,45 @@
deviceaddress = NAND_DEVICE2;
}
- /* Update the NAND controller state */
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* Send NAND reset command */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
-
-
- /* Update the NAND controller state */
+
+
+ /* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+
+}
+
+/**
+ * @brief Configure the device: Enter the physical parameters of the device
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
+{
+ hnand->Config.PageSize = pDeviceConfig->PageSize;
+ hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
+ hnand->Config.BlockSize = pDeviceConfig->BlockSize;
+ hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
+ hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
+ hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
+ hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
return HAL_OK;
-
}
/**
- * @brief Read Page(s) from NAND memory block
+ * @brief Read Page(s) from NAND memory block (8-bits addressing)
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
@@ -440,12 +467,142 @@
* @param NumPageToRead : number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
{
- __IO uint32_t index = 0;
- uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
- NAND_AddressTypeDef nandaddress;
- uint32_t addressoffset = 0;
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Page(s) read loop */
+ while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
+
+ /* Send read page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ /* Check if an extra command is needed for reading pages */
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ }
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+ }
+
+ /* Increment read pages number */
+ numPagesRead++;
+
+ /* Decrement pages to read */
+ NumPageToRead--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Page(s) from NAND memory block (16-bits addressing)
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress : pointer to NAND address structure
+ * @param pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned
+ * @param NumPageToRead : number of pages to read from block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -469,50 +626,88 @@
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
- /* Save the content of pAddress as it will be modified */
- nandaddress.Block = pAddress->Block;
- nandaddress.Page = pAddress->Page;
- nandaddress.Zone = pAddress->Zone;
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) read loop */
- while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
- {
+ while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
/* update the buffer size */
- size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
-
- /* Get the address offset */
- addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+ size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
/* Send read page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
-
- /* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024)
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
{
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
}
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ }
+
/* Get Data into Buffer */
for(; index < size; index++)
{
- *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
+ *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
}
/* Increment read pages number */
- numpagesread++;
+ numPagesRead++;
/* Decrement pages to read */
NumPageToRead--;
/* Increment the NAND address */
- addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -522,11 +717,10 @@
__HAL_UNLOCK(hnand);
return HAL_OK;
-
}
/**
- * @brief Write Page(s) to NAND memory block
+ * @brief Write Page(s) to NAND memory block (8-bits addressing)
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
@@ -534,13 +728,11 @@
* @param NumPageToWrite : number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
{
- __IO uint32_t index = 0;
- uint32_t tickstart = 0;
- uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
- NAND_AddressTypeDef nandaddress;
- uint32_t addressoffset = 0;
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -564,35 +756,56 @@
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
- /* Save the content of pAddress as it will be modified */
- nandaddress.Block = pAddress->Block;
- nandaddress.Page = pAddress->Page;
- nandaddress.Zone = pAddress->Zone;
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) write loop */
- while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
- {
+ while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
/* update the buffer size */
- size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
-
- /* Get the address offset */
- addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
+ size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten);
/* Send write page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
-
- /* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024)
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
{
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
}
+
/* Write data to memory */
for(; index < size; index++)
{
@@ -601,39 +814,164 @@
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
- /* Get tick */
- tickstart = HAL_GetTick();
-
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
- }
- }
+ }
+ }
/* Increment written pages number */
- numpageswritten++;
+ numPagesWritten++;
/* Decrement pages to write */
NumPageToWrite--;
/* Increment the NAND address */
- addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
- __HAL_UNLOCK(hnand);
+ __HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
- * @brief Read Spare area(s) from NAND memory
+ * @brief Write Page(s) to NAND memory block (16-bits addressing)
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress : pointer to NAND address structure
+ * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned
+ * @param NumPageToWrite : number of pages to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Page(s) write loop */
+ while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
+
+ /* Send write page command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ /* Write data to memory */
+ for(; index < size; index++)
+ {
+ *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written pages number */
+ numPagesWritten++;
+
+ /* Decrement pages to write */
+ NumPageToWrite--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Spare area(s) from NAND memory (8-bits addressing)
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
@@ -641,12 +979,11 @@
* @param NumSpareAreaToRead: Number of spare area to read
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
{
- __IO uint32_t index = 0;
- uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
- NAND_AddressTypeDef nandaddress;
- uint32_t addressoffset = 0;
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -670,50 +1007,230 @@
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
- /* Save the content of pAddress as it will be modified */
- nandaddress.Block = pAddress->Block;
- nandaddress.Page = pAddress->Page;
- nandaddress.Zone = pAddress->Zone;
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = COLUMN_ADDRESS(hnand);
/* Spare area(s) read loop */
- while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
+ while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
{
/* update the buffer size */
- size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
- /* Get the address offset */
- addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
-
- /* Send read spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
-
- /* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024)
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
{
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
- }
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ }
/* Get Data into Buffer */
- for ( ;index < size; index++)
+ for(; index < size; index++)
{
*(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
}
/* Increment read spare areas number */
- num_spare_area_read++;
+ numSpareAreaRead++;
/* Decrement spare areas to read */
NumSpareAreaToRead--;
/* Increment the NAND address */
- addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Read Spare area(s) from NAND memory (16-bits addressing)
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress : pointer to NAND address structure
+ * @param pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned.
+ * @param NumSpareAreaToRead: Number of spare area to read
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
+
+ /* Spare area(s) read loop */
+ while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send read spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
+
+ if(hnand->Config.ExtraCommandEnable == ENABLE)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Go back to read mode */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
+ }
+
+ /* Get Data into Buffer */
+ for(; index < size; index++)
+ {
+ *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
+ }
+
+ /* Increment read spare areas number */
+ numSpareAreaRead++;
+
+ /* Decrement spare areas to read */
+ NumSpareAreaToRead--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -726,7 +1243,7 @@
}
/**
- * @brief Write Spare area(s) to NAND memory
+ * @brief Write Spare area(s) to NAND memory (8-bits addressing)
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
@@ -734,13 +1251,11 @@
* @param NumSpareAreaTowrite : number of spare areas to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
- __IO uint32_t index = 0;
- uint32_t tickstart = 0;
- uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
- NAND_AddressTypeDef nandaddress;
- uint32_t addressoffset = 0;
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -764,33 +1279,60 @@
/* Update the FSMC_NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
- /* Save the content of pAddress as it will be modified */
- nandaddress.Block = pAddress->Block;
- nandaddress.Page = pAddress->Page;
- nandaddress.Zone = pAddress->Zone;
+ /* Page address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = COLUMN_ADDRESS(hnand);
/* Spare area(s) write loop */
- while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
- {
+ while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
/* update the buffer size */
- size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
- /* Get the address offset */
- addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
-
- /* Send write Spare area command sequence */
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
-
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
-
- /* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024)
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
{
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
}
/* Write data to memory */
@@ -814,13 +1356,13 @@
}
/* Increment written spare areas number */
- num_spare_area_written++;
+ numSpareAreaWritten++;
/* Decrement spare areas to write */
NumSpareAreaTowrite--;
/* Increment the NAND address */
- addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
+ nandaddress = (uint32_t)(nandaddress + 1U);
}
/* Update the NAND controller state */
@@ -829,6 +1371,138 @@
/* Process unlocked */
__HAL_UNLOCK(hnand);
+ return HAL_OK;
+}
+
+/**
+ * @brief Write Spare area(s) to NAND memory (16-bits addressing)
+ * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * the configuration information for NAND module.
+ * @param pAddress : pointer to NAND address structure
+ * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned.
+ * @param NumSpareAreaTowrite : number of spare areas to write to block
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
+{
+ __IO uint32_t index = 0U;
+ uint32_t tickstart = 0U;
+ uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
+
+ /* Process Locked */
+ __HAL_LOCK(hnand);
+
+ /* Check the NAND controller state */
+ if(hnand->State == HAL_NAND_STATE_BUSY)
+ {
+ return HAL_BUSY;
+ }
+
+ /* Identify the device address */
+ if(hnand->Init.NandBank == FSMC_NAND_BANK2)
+ {
+ deviceaddress = NAND_DEVICE1;
+ }
+ else
+ {
+ deviceaddress = NAND_DEVICE2;
+ }
+
+ /* Update the FSMC_NAND controller state */
+ hnand->State = HAL_NAND_STATE_BUSY;
+
+ /* NAND raw address calculation */
+ nandaddress = ARRAY_ADDRESS(pAddress, hnand);
+
+ /* Column in page address */
+ columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
+
+ /* Spare area(s) write loop */
+ while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
+ {
+ /* update the buffer size */
+ size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
+
+ /* Cards with page size <= 512 bytes */
+ if((hnand->Config.PageSize) <= 512U)
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+ else /* (hnand->Config.PageSize) > 512 */
+ {
+ /* Send write Spare area command sequence */
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
+
+ if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ }
+ else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
+ {
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
+ }
+ }
+
+ /* Write data to memory */
+ for(; index < size; index++)
+ {
+ *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
+ }
+
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
+
+ /* Read status until NAND is ready */
+ while(HAL_NAND_Read_Status(hnand) != NAND_READY)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Increment written spare areas number */
+ numSpareAreaWritten++;
+
+ /* Decrement spare areas to write */
+ NumSpareAreaTowrite--;
+
+ /* Increment the NAND address */
+ nandaddress = (uint32_t)(nandaddress + 1U);
+ }
+
+ /* Update the NAND controller state */
+ hnand->State = HAL_NAND_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hnand);
+
return HAL_OK;
}
@@ -841,8 +1515,8 @@
*/
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
{
- uint32_t deviceaddress = 0;
- uint32_t tickstart = 0;
+ uint32_t deviceaddress = 0U;
+ uint32_t tickstart = 0U;
/* Process Locked */
__HAL_LOCK(hnand);
@@ -869,15 +1543,9 @@
/* Send Erase block command sequence */
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
-
- /* for 512 and 1 GB devices, 4th cycle is required */
- if(hnand->Info.BlockNbr >= 1024)
- {
- *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
- }
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
+ *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
@@ -913,8 +1581,8 @@
*/
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
{
- uint32_t data = 0;
- uint32_t deviceaddress = 0;
+ uint32_t data = 0U;
+ uint32_t deviceaddress = 0U;
/* Identify the device address */
if(hnand->Init.NandBank == FSMC_NAND_BANK2)
@@ -962,17 +1630,17 @@
pAddress->Page++;
/* Check NAND address is valid */
- if(pAddress->Page == hnand->Info.BlockSize)
+ if(pAddress->Page == hnand->Config.BlockSize)
{
- pAddress->Page = 0;
+ pAddress->Page = 0U;
pAddress->Block++;
- if(pAddress->Block == hnand->Info.ZoneSize)
+ if(pAddress->Block == hnand->Config.PlaneSize)
{
- pAddress->Block = 0;
- pAddress->Zone++;
+ pAddress->Block = 0U;
+ pAddress->Plane++;
- if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
+ if(pAddress->Plane == (hnand->Config.PlaneNbr))
{
status = NAND_INVALID_ADDRESS;
}
@@ -1024,7 +1692,7 @@
/* Update the NAND state */
hnand->State = HAL_NAND_STATE_READY;
- return HAL_OK;
+ return HAL_OK;
}
/**
@@ -1033,7 +1701,7 @@
* the configuration information for NAND module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
{
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
@@ -1082,7 +1750,7 @@
return status;
}
-
+
/**
* @}
*/
@@ -1122,49 +1790,6 @@
* @}
*/
-/** @addtogroup NAND_Private_Functions
- * @{
- */
-
-/**
- * @brief Increment the NAND memory address.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
- * the configuration information for NAND module.
- * @param Address: address to be incremented.
- * @retval The new status of the increment address operation. It can be:
- * - NAND_VALID_ADDRESS: When the new address is valid address
- * - NAND_INVALID_ADDRESS: When the new address is invalid address
- */
-static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address)
-{
- uint32_t status = NAND_VALID_ADDRESS;
-
- Address->Page++;
-
- if(Address->Page == hnand->Info.BlockSize)
- {
- Address->Page = 0;
- Address->Block++;
-
- if(Address->Block == hnand->Info.ZoneSize)
- {
- Address->Block = 0;
- Address->Zone++;
-
- if(Address->Zone == hnand->Info.BlockNbr)
- {
- status = NAND_INVALID_ADDRESS;
- }
- }
- }
-
- return (status);
-}
-
-/**
- * @}
- */
-
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_nor.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_nor.c
index 4e89427..d2d8f0b 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_nor.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_nor.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_nor.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
@@ -295,6 +295,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hnor);
+ UNUSED(Timeout);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_NOR_MspWait could be implemented in the user file
*/
@@ -327,7 +328,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -387,7 +388,7 @@
*/
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -437,7 +438,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -496,7 +497,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -557,7 +558,7 @@
*/
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -595,10 +596,10 @@
NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
/* Read buffer */
- while( uwBufferSize > 0)
+ while( uwBufferSize > 0U)
{
*pData++ = *(__IO uint16_t *)uwAddress;
- uwAddress += 2;
+ uwAddress += 2U;
uwBufferSize--;
}
@@ -629,7 +630,7 @@
{
uint16_t * p_currentaddress = (uint16_t *)NULL;
uint16_t * p_endaddress = (uint16_t *)NULL;
- uint32_t lastloadedaddress = 0, deviceaddress = 0;
+ uint32_t lastloadedaddress = 0U, deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -663,7 +664,7 @@
/* Initialize variables */
p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
- p_endaddress = p_currentaddress + (uwBufferSize-1);
+ p_endaddress = p_currentaddress + (uwBufferSize-1U);
lastloadedaddress = (uint32_t)(uwAddress);
/* Issue unlock command sequence */
@@ -672,7 +673,7 @@
/* Write Buffer Load Command */
NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
- NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
+ NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1U));
/* Load Data into NOR Buffer */
while(p_currentaddress <= p_endaddress)
@@ -707,7 +708,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -766,7 +767,10 @@
*/
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
{
- uint32_t deviceaddress = 0;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Address);
+
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -824,7 +828,7 @@
*/
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
{
- uint32_t deviceaddress = 0;
+ uint32_t deviceaddress = 0U;
/* Process Locked */
__HAL_LOCK(hnor);
@@ -985,7 +989,7 @@
{
HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Poll on NOR memory Ready/Busy signal ------------------------------------*/
HAL_NOR_MspWait(hnor, Timeout);
@@ -997,7 +1001,7 @@
/* Check for the Timeout */
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
status = HAL_NOR_STATUS_TIMEOUT;
}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pccard.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pccard.c
index e080eec..5450feb 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pccard.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pccard.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_pccard.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief PCCARD HAL module driver.
* This file provides a generic firmware to drive PCCARD memories mounted
* as external device.
@@ -95,9 +95,9 @@
* @{
*/
-#define PCCARD_TIMEOUT_READ_ID (uint32_t)0x0000FFFF
-#define PCCARD_TIMEOUT_SECTOR (uint32_t)0x0000FFFF
-#define PCCARD_TIMEOUT_STATUS (uint32_t)0x01000000
+#define PCCARD_TIMEOUT_READ_ID 0x0000FFFFU
+#define PCCARD_TIMEOUT_SECTOR 0x0000FFFFU
+#define PCCARD_TIMEOUT_STATUS 0x01000000U
#define PCCARD_STATUS_OK (uint8_t)0x58
#define PCCARD_STATUS_WRITE_OK (uint8_t)0x50
@@ -262,8 +262,8 @@
*/
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus)
{
- uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0;
- uint8_t status = 0;
+ uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U;
+ uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -281,7 +281,7 @@
*pStatus = PCCARD_READY;
/* Send the Identify Command */
- *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECEC;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECECU;
/* Read CF IDs and timeout treatment */
do
@@ -292,14 +292,14 @@
timeout--;
}while((status != PCCARD_STATUS_OK) && timeout);
- if(timeout == 0)
+ if(timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
else
{
/* Read CF ID bytes */
- for(index = 0; index < 16; index++)
+ for(index = 0U; index < 16U; index++)
{
CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA);
}
@@ -325,8 +325,8 @@
*/
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
{
- uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0;
- uint8_t status = 0;
+ uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U;
+ uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -345,22 +345,22 @@
/* Set the parameters to write a sector */
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
- *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
- *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0;
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0;
do
{
/* wait till the Status = 0x80 */
status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE);
timeout--;
- }while((status == 0x80) && timeout);
+ }while((status == 0x80U) && timeout);
- if(timeout == 0)
+ if(timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
- timeout = 0xFFFF;
+ timeout = 0xFFFFU;
do
{
@@ -369,7 +369,7 @@
timeout--;
}while((status != PCCARD_STATUS_OK) && timeout);
- if(timeout == 0)
+ if(timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
@@ -401,8 +401,8 @@
*/
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
{
- uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0;
- uint8_t status = 0;
+ uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U;
+ uint8_t status = 0U;
/* Process Locked */
__HAL_LOCK(hpccard);
@@ -421,7 +421,7 @@
/* Set the parameters to write a sector */
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00;
- *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress);
+ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress);
*(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0;
do
@@ -431,7 +431,7 @@
timeout--;
}while((status != PCCARD_STATUS_OK) && timeout);
- if(timeout == 0)
+ if(timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
@@ -449,7 +449,7 @@
timeout--;
}while((status != PCCARD_STATUS_WRITE_OK) && timeout);
- if(timeout == 0)
+ if(timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
@@ -474,7 +474,7 @@
*/
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
{
- uint32_t timeout = 0x400;
+ uint32_t timeout = 0x400U;
uint8_t status = 0;
/* Process Locked */
@@ -509,7 +509,7 @@
timeout--;
}
- if(timeout == 0)
+ if(timeout == 0U)
{
*pStatus = PCCARD_TIMEOUT_ERROR;
}
@@ -684,7 +684,7 @@
timeout--;
}
- if(timeout == 0)
+ if(timeout == 0U)
{
status_cf = PCCARD_TIMEOUT_ERROR;
}
@@ -704,7 +704,7 @@
*/
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard)
{
- uint8_t data = 0, status_cf = PCCARD_BUSY;
+ uint8_t data = 0U, status_cf = PCCARD_BUSY;
/* Check the PCCARD controller state */
if(hpccard->State == HAL_PCCARD_STATE_BUSY)
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pcd.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pcd.c
index 47a214f..ad37eff 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pcd.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pcd.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -149,7 +149,7 @@
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
- uint32_t index = 0;
+ uint32_t index = 0U;
/* Check the PCD handle allocation */
if(hpcd == NULL)
@@ -173,7 +173,7 @@
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
-
+
/*Init the Core (common init.) */
USB_CoreInit(hpcd->Instance, hpcd->Init);
@@ -181,35 +181,35 @@
USB_SetCurrentMode(hpcd->Instance , USB_DEVICE_MODE);
/* Init endpoints structures */
- for (index = 0; index < 15 ; index++)
+ for (index = 0U; index < 15U ; index++)
{
/* Init ep structure */
- hpcd->IN_ep[index].is_in = 1;
+ hpcd->IN_ep[index].is_in = 1U;
hpcd->IN_ep[index].num = index;
hpcd->IN_ep[index].tx_fifo_num = index;
/* Control until ep is actvated */
hpcd->IN_ep[index].type = EP_TYPE_CTRL;
- hpcd->IN_ep[index].maxpacket = 0;
- hpcd->IN_ep[index].xfer_buff = 0;
- hpcd->IN_ep[index].xfer_len = 0;
+ hpcd->IN_ep[index].maxpacket = 0U;
+ hpcd->IN_ep[index].xfer_buff = 0U;
+ hpcd->IN_ep[index].xfer_len = 0U;
}
-
- for (index = 0; index < 15 ; index++)
+
+ for (index = 0U; index < 15U ; index++)
{
- hpcd->OUT_ep[index].is_in = 0;
+ hpcd->OUT_ep[index].is_in = 0U;
hpcd->OUT_ep[index].num = index;
hpcd->IN_ep[index].tx_fifo_num = index;
/* Control until ep is activated */
hpcd->OUT_ep[index].type = EP_TYPE_CTRL;
- hpcd->OUT_ep[index].maxpacket = 0;
- hpcd->OUT_ep[index].xfer_buff = 0;
- hpcd->OUT_ep[index].xfer_len = 0;
+ hpcd->OUT_ep[index].maxpacket = 0U;
+ hpcd->OUT_ep[index].xfer_buff = 0U;
+ hpcd->OUT_ep[index].xfer_len = 0U;
}
/* Init Device */
USB_DevInit(hpcd->Instance, hpcd->Init);
- hpcd->USB_Address = 0;
+ hpcd->USB_Address = 0U;
hpcd->State= HAL_PCD_STATE_READY;
USB_DevDisconnect (hpcd->Instance);
@@ -228,7 +228,7 @@
{
return HAL_ERROR;
}
-
+
hpcd->State = HAL_PCD_STATE_BUSY;
/* Stop Device */
@@ -310,7 +310,7 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
-{
+{
__HAL_LOCK(hpcd);
__HAL_PCD_DISABLE(hpcd);
USB_StopDevice(hpcd->Instance);
@@ -328,8 +328,8 @@
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
- uint32_t index = 0, ep_intr = 0, epint = 0, epnum = 0;
- uint32_t fifoemptymsk = 0, temp = 0;
+ uint32_t index = 0U, ep_intr = 0U, epint = 0U, epnum = 0U;
+ uint32_t fifoemptymsk = 0U, temp = 0U;
USB_OTG_EPTypeDef *ep = NULL;
/* ensure that we are in device mode */
@@ -349,14 +349,14 @@
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
{
- epnum = 0;
+ epnum = 0U;
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
while ( ep_intr )
{
- if (ep_intr & 0x1)
+ if (ep_intr & 0x1U)
{
epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
@@ -380,7 +380,7 @@
}
}
epnum++;
- ep_intr >>= 1;
+ ep_intr >>= 1U;
}
}
@@ -389,17 +389,17 @@
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
- epnum = 0;
+ epnum = 0U;
while ( ep_intr )
{
- if (ep_intr & 0x1) /* In ITR */
+ if (ep_intr & 0x1U) /* In ITR */
{
epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum);
-
+
if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
{
- fifoemptymsk = 0x1 << epnum;
+ fifoemptymsk = 0x1U << epnum;
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
@@ -428,7 +428,7 @@
}
}
epnum++;
- ep_intr >>= 1;
+ ep_intr >>= 1U;
}
}
@@ -453,20 +453,20 @@
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
}
-
+
/* Handle Reset Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
{
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
- USB_FlushTxFifo(hpcd->Instance , 0 );
+ USB_FlushTxFifo(hpcd->Instance , 0x10U);
- for (index = 0; index < hpcd->Init.dev_endpoints ; index++)
+ for (index = 0U; index < hpcd->Init.dev_endpoints ; index++)
{
- USBx_INEP(index)->DIEPINT = 0xFF;
- USBx_OUTEP(index)->DOEPINT = 0xFF;
+ USBx_INEP(index)->DIEPINT = 0xFFU;
+ USBx_OUTEP(index)->DOEPINT = 0xFFU;
}
- USBx_DEVICE->DAINT = 0xFFFFFFFF;
- USBx_DEVICE->DAINTMSK |= 0x10001;
+ USBx_DEVICE->DAINT = 0xFFFFFFFFU;
+ USBx_DEVICE->DAINTMSK |= 0x10001U;
USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
@@ -488,13 +488,13 @@
hpcd->Init.speed = USB_OTG_SPEED_FULL;
hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ;
- hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
+ hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT);
HAL_PCD_ResetCallback(hpcd);
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
}
-
+
/* Handle RxQLevel Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
{
@@ -502,19 +502,19 @@
temp = USBx->GRXSTSP;
ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
- if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
+ if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_DATA_UPDT)
{
- if((temp & USB_OTG_GRXSTSP_BCNT) != 0)
+ if((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
{
- USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4);
- ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
- ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4U);
+ ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
}
}
- else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
+ else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_SETUP_UPDT)
{
- USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8);
- ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+ USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
+ ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U;
}
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
@@ -569,9 +569,7 @@
* @retval HAL status
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
-{
- uint32_t wInterrupt_Mask = 0;
-
+{
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
{
/* servicing of the endpoint correct transfer interrupt */
@@ -583,7 +581,7 @@
{
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
HAL_PCD_ResetCallback(hpcd);
- HAL_PCD_SetAddress(hpcd, 0);
+ HAL_PCD_SetAddress(hpcd, 0U);
}
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR))
@@ -596,30 +594,25 @@
}
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
- {
+ {
hpcd->Instance->CNTR &= ~(USB_CNTR_LP_MODE);
-
- /*set wInterrupt_Mask global variable*/
- wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
- | USB_CNTR_ESOFM | USB_CNTR_RESETM;
-
- /*Set interrupt mask*/
- hpcd->Instance->CNTR = wInterrupt_Mask;
+ hpcd->Instance->CNTR &= ~(USB_CNTR_FSUSP);
HAL_PCD_ResumeCallback(hpcd);
-
+
__HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);
}
if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
- {
- /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
-
+ {
/* Force low-power mode in the macrocell */
hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
+
+ /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);
+
hpcd->Instance->CNTR |= USB_CNTR_LP_MODE;
- if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0)
+ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0U)
{
HAL_PCD_SuspendCallback(hpcd);
}
@@ -841,7 +834,7 @@
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
{
__HAL_LOCK(hpcd);
- HAL_PCDEx_SetConnectionState (hpcd, 0);
+ HAL_PCDEx_SetConnectionState (hpcd, 0U);
USB_DevDisconnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
@@ -874,17 +867,17 @@
HAL_StatusTypeDef ret = HAL_OK;
PCD_EPTypeDef *ep = NULL;
- if ((ep_addr & 0x80) == 0x80)
+ if ((ep_addr & 0x80U) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ ep = &hpcd->IN_ep[ep_addr & 0x7FU];
}
else
{
- ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
}
- ep->num = ep_addr & 0x7F;
+ ep->num = ep_addr & 0x7FU;
- ep->is_in = (0x80 & ep_addr) != 0;
+ ep->is_in = (0x80U & ep_addr) != 0U;
ep->maxpacket = ep_mps;
ep->type = ep_type;
@@ -904,17 +897,17 @@
{
PCD_EPTypeDef *ep = NULL;
- if ((ep_addr & 0x80) == 0x80)
+ if ((ep_addr & 0x80U) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ ep = &hpcd->IN_ep[ep_addr & 0x7FU];
}
else
{
- ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
}
- ep->num = ep_addr & 0x7F;
+ ep->num = ep_addr & 0x7FU;
- ep->is_in = (0x80 & ep_addr) != 0;
+ ep->is_in = (0x80U & ep_addr) != 0U;
__HAL_LOCK(hpcd);
USB_DeactivateEndpoint(hpcd->Instance , ep);
@@ -935,18 +928,16 @@
{
PCD_EPTypeDef *ep = NULL;
- ep = &hpcd->OUT_ep[ep_addr & 0x7F];
+ ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
- ep->xfer_count = 0;
- ep->is_in = 0;
- ep->num = ep_addr & 0x7F;
-
- __HAL_LOCK(hpcd);
-
- if ((ep_addr & 0x7F) == 0 )
+ ep->xfer_count = 0U;
+ ep->is_in = 0U;
+ ep->num = ep_addr & 0x7FU;
+
+ if ((ep_addr & 0x7FU) == 0U)
{
USB_EP0StartXfer(hpcd->Instance , ep);
}
@@ -954,8 +945,7 @@
{
USB_EPStartXfer(hpcd->Instance , ep);
}
- __HAL_UNLOCK(hpcd);
-
+
return HAL_OK;
}
@@ -967,7 +957,7 @@
*/
uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
- return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
+ return hpcd->OUT_ep[ep_addr & 0xF].xfer_count;
}
/**
* @brief Send an amount of data
@@ -981,18 +971,16 @@
{
PCD_EPTypeDef *ep = NULL;
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ ep = &hpcd->IN_ep[ep_addr & 0x7FU];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
- ep->xfer_count = 0;
- ep->is_in = 1;
- ep->num = ep_addr & 0x7F;
-
- __HAL_LOCK(hpcd);
-
- if ((ep_addr & 0x7F) == 0 )
+ ep->xfer_count = 0U;
+ ep->is_in = 1U;
+ ep->num = ep_addr & 0x7FU;
+
+ if ((ep_addr & 0x7FU) == 0U)
{
USB_EP0StartXfer(hpcd->Instance , ep);
}
@@ -1000,9 +988,7 @@
{
USB_EPStartXfer(hpcd->Instance , ep);
}
-
- __HAL_UNLOCK(hpcd);
-
+
return HAL_OK;
}
@@ -1016,22 +1002,22 @@
{
PCD_EPTypeDef *ep = NULL;
- if ((0x80 & ep_addr) == 0x80)
+ if ((0x80U & ep_addr) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ ep = &hpcd->IN_ep[ep_addr & 0x7FU];
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
}
- ep->is_stall = 1;
- ep->num = ep_addr & 0x7F;
- ep->is_in = ((ep_addr & 0x80) == 0x80);
+ ep->is_stall = 1U;
+ ep->num = ep_addr & 0x7FU;
+ ep->is_in = ((ep_addr & 0x80U) == 0x80U);
__HAL_LOCK(hpcd);
USB_EPSetStall(hpcd->Instance , ep);
- if((ep_addr & 0x7F) == 0)
+ if((ep_addr & 0x7FU) == 0U)
{
USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
}
@@ -1050,18 +1036,18 @@
{
PCD_EPTypeDef *ep = NULL;
- if ((0x80 & ep_addr) == 0x80)
+ if ((0x80U & ep_addr) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ ep = &hpcd->IN_ep[ep_addr & 0x7FU];
}
else
{
ep = &hpcd->OUT_ep[ep_addr];
}
- ep->is_stall = 0;
- ep->num = ep_addr & 0x7F;
- ep->is_in = ((ep_addr & 0x80) == 0x80);
+ ep->is_stall = 0U;
+ ep->num = ep_addr & 0x7FU;
+ ep->is_in = ((ep_addr & 0x80U) == 0x80U);
__HAL_LOCK(hpcd);
USB_EPClearStall(hpcd->Instance , ep);
@@ -1080,9 +1066,9 @@
{
__HAL_LOCK(hpcd);
- if ((ep_addr & 0x80) == 0x80)
+ if ((ep_addr & 0x80U) == 0x80U)
{
- USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
+ USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7FU);
}
else
{
@@ -1167,8 +1153,8 @@
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
USB_OTG_EPTypeDef *ep = NULL;
int32_t len = 0;
- uint32_t len32b = 0;
- uint32_t fifoemptymsk = 0;
+ uint32_t len32b = 0U;
+ uint32_t fifoemptymsk = 0U;
ep = &hpcd->IN_ep[epnum];
len = ep->xfer_len - ep->xfer_count;
@@ -1178,20 +1164,20 @@
len = ep->maxpacket;
}
- len32b = (len + 3) / 4;
+ len32b = (len + 3U) / 4U;
while ((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
ep->xfer_count < ep->xfer_len &&
- ep->xfer_len != 0)
+ ep->xfer_len != 0U)
{
/* Write the FIFO */
len = ep->xfer_len - ep->xfer_count;
- if (len > ep->maxpacket)
+ if ((uint32_t)len > ep->maxpacket)
{
len = ep->maxpacket;
}
- len32b = (len + 3) / 4;
+ len32b = (len + 3U) / 4U;
USB_WritePacket(USBx, ep->xfer_buff, epnum, len);
@@ -1201,7 +1187,7 @@
if(len <= 0)
{
- fifoemptymsk = 0x1 << epnum;
+ fifoemptymsk = 0x01U << epnum;
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
}
@@ -1248,13 +1234,13 @@
ep->xfer_buff += ep->xfer_count;
/* TX COMPLETE */
- HAL_PCD_DataInStageCallback(hpcd, 0);
+ HAL_PCD_DataInStageCallback(hpcd, 0U);
- if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0))
+ if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U))
{
hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
- hpcd->USB_Address = 0;
+ hpcd->USB_Address = 0U;
}
}
@@ -1264,10 +1250,10 @@
/* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
- ep = &hpcd->OUT_ep[0];
+ ep = &hpcd->OUT_ep[0U];
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
- if ((wEPVal & USB_EP_SETUP) != 0)
+ if ((wEPVal & USB_EP_SETUP) != 0U)
{
/* Get SETUP Packet*/
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
@@ -1279,20 +1265,20 @@
HAL_PCD_SetupStageCallback(hpcd);
}
- else if ((wEPVal & USB_EP_CTR_RX) != 0)
+ else if ((wEPVal & USB_EP_CTR_RX) != 0U)
{
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
/* Get Control Data OUT Packet*/
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0)
+ if (ep->xfer_count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
ep->xfer_buff+=ep->xfer_count;
}
/* Process Control Data OUT Packet*/
- HAL_PCD_DataOutStageCallback(hpcd, 0);
+ HAL_PCD_DataOutStageCallback(hpcd, 0U);
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
@@ -1305,17 +1291,17 @@
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
- if ((wEPVal & USB_EP_CTR_RX) != 0)
+ if ((wEPVal & USB_EP_CTR_RX) != 0U)
{
/* clear int flag */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
ep = &hpcd->OUT_ep[epindex];
/* OUT double Buffering*/
- if (ep->doublebuffer == 0)
+ if (ep->doublebuffer == 0U)
{
count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
- if (count != 0)
+ if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
}
@@ -1326,7 +1312,7 @@
{
/*read from endpoint BUF0Addr buffer*/
count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
- if (count != 0)
+ if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
}
@@ -1335,7 +1321,7 @@
{
/*read from endpoint BUF1Addr buffer*/
count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
- if (count != 0)
+ if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
}
@@ -1346,7 +1332,7 @@
ep->xfer_count+=count;
ep->xfer_buff+=count;
- if ((ep->xfer_len == 0) || (count < ep->maxpacket))
+ if ((ep->xfer_len == 0U) || (count < ep->maxpacket))
{
/* RX COMPLETE */
HAL_PCD_DataOutStageCallback(hpcd, ep->num);
@@ -1358,7 +1344,7 @@
} /* if((wEPVal & EP_CTR_RX) */
- if ((wEPVal & USB_EP_CTR_TX) != 0)
+ if ((wEPVal & USB_EP_CTR_TX) != 0U)
{
ep = &hpcd->IN_ep[epindex];
@@ -1366,10 +1352,10 @@
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
/* IN double Buffering*/
- if (ep->doublebuffer == 0)
+ if (ep->doublebuffer == 0U)
{
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0)
+ if (ep->xfer_count != 0U)
{
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
}
@@ -1380,7 +1366,7 @@
{
/*read from endpoint BUF0Addr buffer*/
ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0)
+ if (ep->xfer_count != 0U)
{
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
}
@@ -1389,7 +1375,7 @@
{
/*read from endpoint BUF1Addr buffer*/
ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
- if (ep->xfer_count != 0)
+ if (ep->xfer_count != 0U)
{
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
}
@@ -1401,7 +1387,7 @@
ep->xfer_buff+=ep->xfer_count;
/* Zero Length Packet? */
- if (ep->xfer_len == 0)
+ if (ep->xfer_len == 0U)
{
/* TX COMPLETE */
HAL_PCD_DataInStageCallback(hpcd, ep->num);
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pcd_ex.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pcd_ex.c
index a50e16c..558de9c 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pcd_ex.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pcd_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_pcd_ex.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Extended PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -97,7 +97,7 @@
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{
uint8_t index = 0;
- uint32_t Tx_Offset = 0;
+ uint32_t Tx_Offset = 0U;
/* TXn min size = 16 words. (n : Transmit FIFO index)
When a TxFIFO is not used, the Configuration should be as follows:
@@ -111,20 +111,20 @@
Tx_Offset = hpcd->Instance->GRXFSIZ;
- if(fifo == 0)
+ if(fifo == 0U)
{
- hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset;
+ hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16U) | Tx_Offset;
}
else
{
- Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
- for (index = 0; index < (fifo - 1); index++)
+ Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U;
+ for(index = 0; index < (fifo - 1); index++)
{
- Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16);
+ Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16U);
}
/* Multiply Tx_Size by 2 to get higher performance */
- hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset;
+ hpcd->Instance->DIEPTXF[fifo - 1U] = (size << 16U) | Tx_Offset;
}
@@ -171,9 +171,9 @@
PCD_EPTypeDef *ep = NULL;
/* initialize ep structure*/
- if ((0x80 & ep_addr) == 0x80)
+ if ((ep_addr & 0x80U) == 0x80U)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7F];
+ ep = &hpcd->IN_ep[ep_addr & 0x7FU];
}
else
{
@@ -184,17 +184,17 @@
if (ep_kind == PCD_SNG_BUF)
{
/*Single Buffer*/
- ep->doublebuffer = 0;
+ ep->doublebuffer = 0U;
/*Configure te PMA*/
ep->pmaadress = (uint16_t)pmaadress;
}
else /*USB_DBL_BUF*/
{
/*Double Buffer Endpoint*/
- ep->doublebuffer = 1;
+ ep->doublebuffer = 1U;
/*Configure the PMA*/
- ep->pmaaddr0 = pmaadress & 0xFFFF;
- ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16;
+ ep->pmaaddr0 = pmaadress & 0x0000FFFFU;
+ ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16U;
}
return HAL_OK;
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pwr.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pwr.c
index 3c63c61..3915d8b 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pwr.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_pwr.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief PWR HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -65,10 +65,10 @@
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
-#define PVD_MODE_IT ((uint32_t)0x00010000)
-#define PVD_MODE_EVT ((uint32_t)0x00020000)
-#define PVD_RISING_EDGE ((uint32_t)0x00000001)
-#define PVD_FALLING_EDGE ((uint32_t)0x00000002)
+#define PVD_MODE_IT 0x00010000U
+#define PVD_MODE_EVT 0x00020000U
+#define PVD_RISING_EDGE 0x00000001U
+#define PVD_FALLING_EDGE 0x00000002U
/**
* @}
*/
@@ -79,8 +79,8 @@
*/
/* ------------- PWR registers bit address in the alias region ---------------*/
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
-#define PWR_CR_OFFSET 0x00
-#define PWR_CSR_OFFSET 0x04
+#define PWR_CR_OFFSET 0x00U
+#define PWR_CSR_OFFSET 0x04U
#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
/**
@@ -92,16 +92,16 @@
*/
/* --- CR Register ---*/
/* Alias word address of LPSDSR bit */
-#define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPDS)
-#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4)))
+#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos
+#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U)))
/* Alias word address of DBP bit */
-#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
-#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4)))
+#define DBP_BIT_NUMBER PWR_CR_DBP_Pos
+#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)))
/* Alias word address of PVDE bit */
-#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
-#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4)))
+#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
+#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)))
/**
* @}
@@ -113,7 +113,7 @@
/* --- CSR Register ---*/
/* Alias word address of EWUP1 bit */
-#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4)))
+#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U)))
/**
* @}
*/
@@ -436,6 +436,9 @@
{
/* Check the parameters */
/* No check on Regulator because parameter not used in SLEEP mode */
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Regulator);
+
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
/* Clear SLEEPDEEP bit of Cortex System Control Register */
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rcc.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rcc.c
index a597cdf..a2baa61 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rcc.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rcc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -96,10 +96,6 @@
/** @defgroup RCC_Private_Constants RCC Private Constants
* @{
*/
-/* Bits position in in the CFGR register */
-#define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE)
-#define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1)
-#define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2)
/**
* @}
*/
@@ -125,7 +121,9 @@
*/
/* Private function prototypes -----------------------------------------------*/
-/* Exported functions ---------------------------------------------------------*/
+static void RCC_Delay(uint32_t mdelay);
+
+/* Exported functions --------------------------------------------------------*/
/** @defgroup RCC_Exported_Functions RCC Exported Functions
* @{
@@ -233,13 +231,13 @@
CLEAR_REG(RCC->CFGR);
/* Set HSITRIM bits to the reset value */
- MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM)));
+ MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos));
-#if (defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE))
+#if defined(RCC_CFGR2_SUPPORT)
/* Reset CFGR2 register */
CLEAR_REG(RCC->CFGR2);
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
+#endif /* RCC_CFGR2_SUPPORT */
/* Disable all interrupts */
CLEAR_REG(RCC->CIR);
@@ -264,7 +262,7 @@
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(RCC_OscInitStruct != NULL);
@@ -412,7 +410,7 @@
}
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
- HAL_Delay(1);
+ RCC_Delay(1);
}
else
{
@@ -435,25 +433,35 @@
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
{
+ FlagStatus pwrclkchanged = RESET;
+
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
- /* Enable Power Clock*/
+ /* Update LSE configuration in Backup Domain control register */
+ /* Requires to enable write access to Backup Domain of necessary */
+ if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ {
__HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+ if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ {
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
- while((PWR->CR & PWR_CR_DBP) == RESET)
+ while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
+ }
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
@@ -486,6 +494,12 @@
}
}
}
+
+ /* Require to disable power clock if necessary */
+ if(pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
}
#if defined(RCC_CR_PLL2ON)
@@ -694,7 +708,7 @@
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check the parameters */
assert_param(RCC_ClkInitStruct != NULL);
@@ -827,7 +841,7 @@
}
/* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
@@ -887,13 +901,17 @@
*/
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
{
- GPIO_InitTypeDef gpio = {0};
+ GPIO_InitTypeDef gpio = {0U};
/* Check the parameters */
assert_param(IS_RCC_MCO(RCC_MCOx));
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(RCC_MCOx);
+ UNUSED(RCC_MCODiv);
+
/* Configure the MCO1 pin in alternate function mode */
gpio.Mode = GPIO_MODE_AF_PP;
gpio.Speed = GPIO_SPEED_FREQ_HIGH;
@@ -902,9 +920,9 @@
/* MCO1 Clock Enable */
MCO1_CLK_ENABLE();
-
+
HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
-
+
/* Configure the MCO clock source */
__HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
}
@@ -963,22 +981,22 @@
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
-#if defined(RCC_CFGR2_PREDIV1SRC)
- const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
- const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
+#if defined(RCC_CFGR2_PREDIV1SRC)
+ const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
+ const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
- const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
+ const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
#if defined(RCC_CFGR2_PREDIV1)
- const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
+ const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
#else
- const uint8_t aPredivFactorTable[2] = { 1, 2};
+ const uint8_t aPredivFactorTable[2] = {1, 2};
#endif /*RCC_CFGR2_PREDIV1*/
#endif
- uint32_t tmpreg = 0, prediv = 0, pllclk = 0, pllmul = 0;
- uint32_t sysclockfreq = 0;
+ uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
+ uint32_t sysclockfreq = 0U;
#if defined(RCC_CFGR2_PREDIV1SRC)
- uint32_t prediv2 = 0, pll2mul = 0;
+ uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/
tmpreg = RCC->CFGR;
@@ -993,13 +1011,13 @@
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
- pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
+ pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
{
#if defined(RCC_CFGR2_PREDIV1)
- prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
+ prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
- prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
+ prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
#endif /*RCC_CFGR2_PREDIV1*/
#if defined(RCC_CFGR2_PREDIV1SRC)
@@ -1007,8 +1025,8 @@
{
/* PLL2 selected as Prediv1 source */
/* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
- pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
+ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
+ pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv) * pllmul);
}
else
@@ -1019,7 +1037,7 @@
/* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
/* In this case need to divide pllclk by 2 */
- if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
+ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
{
pllclk = pllclk / 2;
}
@@ -1069,7 +1087,7 @@
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
}
/**
@@ -1081,7 +1099,7 @@
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
+ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
}
/**
@@ -1130,7 +1148,7 @@
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
- RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
/* Get the LSE configuration -----------------------------------------------*/
if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
@@ -1240,6 +1258,21 @@
}
/**
+ * @brief This function provides delay (in milliseconds) based on CPU cycles method.
+ * @param mdelay: specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+static void RCC_Delay(uint32_t mdelay)
+{
+ __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
+ do
+ {
+ __NOP();
+ }
+ while (Delay --);
+}
+
+/**
* @brief RCC Clock Security System interrupt callback
* @retval none
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rcc_ex.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rcc_ex.c
index 3bbe938..02d132a 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rcc_ex.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rcc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Extended RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@@ -56,16 +56,16 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
- * @{
- */
+ * @{
+ */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
- * @{
- */
+ * @{
+ */
/**
* @}
*/
@@ -79,8 +79,8 @@
*/
/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
- * @brief Extended Peripheral Control functions
- *
+ * @brief Extended Peripheral Control functions
+ *
@verbatim
===============================================================================
##### Extended Peripheral Control functions #####
@@ -117,9 +117,9 @@
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
- uint32_t tickstart = 0, temp_reg = 0;
+ uint32_t tickstart = 0U, temp_reg = 0U;
#if defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t pllactive = 0;
+ uint32_t pllactive = 0U;
#endif /* STM32F105xC || STM32F107xC */
/* Check the parameters */
@@ -131,21 +131,32 @@
/* check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
-
- /* Enable write access to Backup domain */
- SET_BIT(PWR->CR, PWR_CR_DBP);
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while((PWR->CR & PWR_CR_DBP) == RESET)
+ FlagStatus pwrclkchanged = RESET;
+
+ /* As soon as function is called to change RTC clock source, activation of the
+ power domain is done. */
+ /* Requires to enable write access to Backup Domain of necessary */
+ if(__HAL_RCC_PWR_IS_CLK_DISABLED())
{
- if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+
+ if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+ {
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
- return HAL_TIMEOUT;
- }
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
@@ -163,7 +174,7 @@
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
{
- /* Get timeout */
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
@@ -177,6 +188,12 @@
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+
+ /* Require to disable power clock if necessary */
+ if(pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
}
/*------------------------------ ADC clock Configuration ------------------*/
@@ -294,7 +311,7 @@
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
- uint32_t srcclk = 0;
+ uint32_t srcclk = 0U;
/* Set all possible values for the extended clock type parameter------------*/
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
@@ -387,26 +404,21 @@
*/
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
#if defined(STM32F105xC) || defined(STM32F107xC)
- const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
- const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
-#else
- const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
- const uint8_t aPredivFactorTable[2] = { 1, 2};
-#endif
-#endif
- uint32_t temp_reg = 0, frequency = 0;
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t prediv1 = 0, pllclk = 0, pllmul = 0;
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-#if defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t pll2mul = 0, pll3mul = 0, prediv2 = 0;
+ const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
+ const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+
+ uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
+ uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
#endif /* STM32F105xC || STM32F107xC */
+#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \
+ defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
+ const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
+ const uint8_t aPredivFactorTable[2] = {1, 2};
+
+ uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
+#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
+ uint32_t temp_reg = 0U, frequency = 0U;
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
@@ -424,14 +436,14 @@
/* Check if PLL is enabled */
if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))
{
- pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
+ pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
{
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
|| defined(STM32F100xE)
- prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
+ prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
- prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
+ prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
#if defined(STM32F105xC) || defined(STM32F107xC)
@@ -439,8 +451,8 @@
{
/* PLL2 selected as Prediv1 source */
/* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
- pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
+ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
+ pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
}
else
@@ -451,7 +463,7 @@
/* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
/* In this case need to divide pllclk by 2 */
- if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
+ if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
{
pllclk = pllclk / 2;
}
@@ -499,8 +511,7 @@
break;
}
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
+#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
case RCC_PERIPHCLK_I2S2:
{
#if defined(STM32F103xE) || defined(STM32F103xG)
@@ -518,8 +529,8 @@
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
{
/* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
- pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2;
+ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
+ pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
}
}
@@ -543,8 +554,8 @@
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
{
/* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
- prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
- pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2;
+ prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
+ pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
}
}
@@ -569,18 +580,18 @@
}
else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
{
- frequency = HSE_VALUE / 128;
+ frequency = HSE_VALUE / 128U;
}
/* Clock not enabled for RTC*/
else
{
- frequency = 0;
+ frequency = 0U;
}
break;
}
case RCC_PERIPHCLK_ADC:
{
- frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> POSITION_VAL(RCC_CFGR_ADCPRE_DIV4)) + 1) * 2);
+ frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
break;
}
default:
@@ -597,8 +608,8 @@
#if defined(STM32F105xC) || defined(STM32F107xC)
/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
- * @brief PLLI2S Management functions
- *
+ * @brief PLLI2S Management functions
+ *
@verbatim
===============================================================================
##### Extended PLLI2S Management functions #####
@@ -619,7 +630,7 @@
*/
HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
@@ -689,7 +700,7 @@
*/
HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Disable PLL I2S as not requested by I2S2 or I2S3*/
if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
@@ -723,8 +734,8 @@
*/
/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
- * @brief PLL2 Management functions
- *
+ * @brief PLL2 Management functions
+ *
@verbatim
===============================================================================
##### Extended PLL2 Management functions #####
@@ -745,7 +756,7 @@
*/
HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* This bit can not be cleared if the PLL2 clock is used indirectly as system
clock (i.e. it is used as PLL clock entry that is used as system clock). */
@@ -816,7 +827,7 @@
*/
HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* This bit can not be cleared if the PLL2 clock is used indirectly as system
clock (i.e. it is used as PLL clock entry that is used as system clock). */
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rtc.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rtc.c
index 8642ae6..cedfc2f 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rtc.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rtc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@@ -171,7 +171,7 @@
* @{
*/
#define RTC_ALARM_RESETVALUE_REGISTER (uint16_t)0xFFFF
-#define RTC_ALARM_RESETVALUE (uint32_t)0xFFFFFFFF
+#define RTC_ALARM_RESETVALUE 0xFFFFFFFFU
/**
* @}
@@ -243,7 +243,7 @@
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
- uint32_t prescaler = 0;
+ uint32_t prescaler = 0U;
/* Check input parameters */
if(hrtc == NULL)
{
@@ -310,7 +310,7 @@
prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC);
/* Check that RTC clock is enabled*/
- if (prescaler == 0)
+ if (prescaler == 0U)
{
/* Should not happen. Frequency is not available*/
hrtc->State = HAL_RTC_STATE_ERROR;
@@ -319,12 +319,12 @@
else
{
/* RTC period = RTCCLK/(RTC_PR + 1) */
- prescaler = prescaler - 1;
+ prescaler = prescaler - 1U;
}
}
/* Configure the RTC_PRLH / RTC_PRLL */
- MODIFY_REG(hrtc->Instance->PRLH, RTC_PRLH_PRL, (prescaler >> 16));
+ MODIFY_REG(hrtc->Instance->PRLH, RTC_PRLH_PRL, (prescaler >> 16U));
MODIFY_REG(hrtc->Instance->PRLL, RTC_PRLL_PRL, (prescaler & RTC_PRLL_PRL));
/* Wait for synchro */
@@ -336,9 +336,9 @@
}
/* Initialize date to 1st of January 2000 */
- hrtc->DateToUpdate.Year = 0x00;
+ hrtc->DateToUpdate.Year = 0x00U;
hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY;
- hrtc->DateToUpdate.Date = 0x01;
+ hrtc->DateToUpdate.Date = 0x01U;
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_READY;
@@ -383,7 +383,7 @@
{
CLEAR_REG(hrtc->Instance->CNTL);
CLEAR_REG(hrtc->Instance->CNTH);
- WRITE_REG(hrtc->Instance->PRLL, 0x00008000);
+ WRITE_REG(hrtc->Instance->PRLL, 0x00008000U);
CLEAR_REG(hrtc->Instance->PRLH);
/* Reset All CRH/CRL bits */
@@ -479,7 +479,7 @@
*/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
- uint32_t counter_time = 0, counter_alarm = 0;
+ uint32_t counter_time = 0U, counter_alarm = 0U;
/* Check input parameters */
if((hrtc == NULL) || (sTime == NULL))
@@ -501,8 +501,8 @@
assert_param(IS_RTC_MINUTES(sTime->Minutes));
assert_param(IS_RTC_SECONDS(sTime->Seconds));
- counter_time = (uint32_t)(((uint32_t)sTime->Hours * 3600) + \
- ((uint32_t)sTime->Minutes * 60) + \
+ counter_time = (uint32_t)(((uint32_t)sTime->Hours * 3600U) + \
+ ((uint32_t)sTime->Minutes * 60U) + \
((uint32_t)sTime->Seconds));
}
else
@@ -511,8 +511,8 @@
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
- counter_time = (((uint32_t)(RTC_Bcd2ToByte(sTime->Hours)) * 3600) + \
- ((uint32_t)(RTC_Bcd2ToByte(sTime->Minutes)) * 60) + \
+ counter_time = (((uint32_t)(RTC_Bcd2ToByte(sTime->Hours)) * 3600U) + \
+ ((uint32_t)(RTC_Bcd2ToByte(sTime->Minutes)) * 60U) + \
((uint32_t)(RTC_Bcd2ToByte(sTime->Seconds))));
}
@@ -541,7 +541,7 @@
if(counter_alarm < counter_time)
{
/* Add 1 day to alarm counter*/
- counter_alarm += (uint32_t)(24 * 3600);
+ counter_alarm += (uint32_t)(24U * 3600U);
/* Write new Alarm counter in RTC registers */
if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
@@ -578,7 +578,7 @@
*/
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
- uint32_t counter_time = 0, counter_alarm = 0, days_elapsed = 0, hours = 0;
+ uint32_t counter_time = 0U, counter_alarm = 0U, days_elapsed = 0U, hours = 0U;
/* Check input parameters */
if((hrtc == NULL) || (sTime == NULL))
@@ -599,17 +599,17 @@
counter_time = RTC_ReadTimeCounter(hrtc);
/* Fill the structure fields with the read parameters */
- hours = counter_time / 3600;
- sTime->Minutes = (uint8_t)((counter_time % 3600) / 60);
- sTime->Seconds = (uint8_t)((counter_time % 3600) % 60);
+ hours = counter_time / 3600U;
+ sTime->Minutes = (uint8_t)((counter_time % 3600U) / 60U);
+ sTime->Seconds = (uint8_t)((counter_time % 3600U) % 60U);
- if (hours >= 24)
+ if (hours >= 24U)
{
/* Get number of days elapsed from last calculation */
- days_elapsed = (hours / 24);
+ days_elapsed = (hours / 24U);
/* Set Hours in RTC_TimeTypeDef structure*/
- sTime->Hours = (hours % 24);
+ sTime->Hours = (hours % 24U);
/* Read Alarm counter in RTC registers */
counter_alarm = RTC_ReadAlarmCounter(hrtc);
@@ -627,7 +627,7 @@
}
/* Set updated time in decreasing counter by number of days elapsed */
- counter_time -= (days_elapsed * 24 * 3600);
+ counter_time -= (days_elapsed * 24U * 3600U);
/* Write time counter in RTC registers */
if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK)
@@ -689,7 +689,7 @@
*/
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
- uint32_t counter_time = 0, counter_alarm = 0, hours = 0;
+ uint32_t counter_time = 0U, counter_alarm = 0U, hours = 0U;
/* Check input parameters */
if((hrtc == NULL) || (sDate == NULL))
@@ -737,11 +737,11 @@
counter_time = RTC_ReadTimeCounter(hrtc);
/* Fill the structure fields with the read parameters */
- hours = counter_time / 3600;
- if (hours > 24)
+ hours = counter_time / 3600U;
+ if (hours > 24U)
{
/* Set updated time in decreasing counter by number of days elapsed */
- counter_time -= ((hours / 24) * 24 * 3600);
+ counter_time -= ((hours / 24U) * 24U * 3600U);
/* Write time counter in RTC registers */
if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK)
{
@@ -763,7 +763,7 @@
if(counter_alarm < counter_time)
{
/* Add 1 day to alarm counter*/
- counter_alarm += (uint32_t)(24 * 3600);
+ counter_alarm += (uint32_t)(24U * 3600U);
/* Write new Alarm counter in RTC registers */
if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK)
@@ -803,7 +803,7 @@
*/
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
- RTC_TimeTypeDef stime = {0};
+ RTC_TimeTypeDef stime = {0U};
/* Check input parameters */
if((hrtc == NULL) || (sDate == NULL))
@@ -868,8 +868,8 @@
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
- uint32_t counter_alarm = 0, counter_time;
- RTC_TimeTypeDef stime = {0};
+ uint32_t counter_alarm = 0U, counter_time;
+ RTC_TimeTypeDef stime = {0U};
/* Check input parameters */
if((hrtc == NULL) || (sAlarm == NULL))
@@ -893,8 +893,8 @@
}
/* Convert time in seconds */
- counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600) + \
- ((uint32_t)stime.Minutes * 60) + \
+ counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \
+ ((uint32_t)stime.Minutes * 60U) + \
((uint32_t)stime.Seconds));
if(Format == RTC_FORMAT_BIN)
@@ -903,8 +903,8 @@
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
- counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600) + \
- ((uint32_t)sAlarm->AlarmTime.Minutes * 60) + \
+ counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \
+ ((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \
((uint32_t)sAlarm->AlarmTime.Seconds));
}
else
@@ -913,8 +913,8 @@
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
- counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600) + \
- ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60) + \
+ counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \
+ ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \
((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
}
@@ -922,7 +922,7 @@
if (counter_alarm < counter_time)
{
/* Add 1 day to alarm counter*/
- counter_alarm += (uint32_t)(24 * 3600);
+ counter_alarm += (uint32_t)(24U * 3600U);
}
/* Write Alarm counter in RTC registers */
@@ -960,8 +960,8 @@
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
- uint32_t counter_alarm = 0, counter_time;
- RTC_TimeTypeDef stime = {0};
+ uint32_t counter_alarm = 0U, counter_time;
+ RTC_TimeTypeDef stime = {0U};
/* Check input parameters */
if((hrtc == NULL) || (sAlarm == NULL))
@@ -985,8 +985,8 @@
}
/* Convert time in seconds */
- counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600) + \
- ((uint32_t)stime.Minutes * 60) + \
+ counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \
+ ((uint32_t)stime.Minutes * 60U) + \
((uint32_t)stime.Seconds));
if(Format == RTC_FORMAT_BIN)
@@ -995,8 +995,8 @@
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
- counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600) + \
- ((uint32_t)sAlarm->AlarmTime.Minutes * 60) + \
+ counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \
+ ((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \
((uint32_t)sAlarm->AlarmTime.Seconds));
}
else
@@ -1005,16 +1005,16 @@
assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
- counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600) + \
- ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60) + \
- ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
+ counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \
+ ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \
+ ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
}
/* Check that requested alarm should expire in the same day (otherwise add 1 day) */
if (counter_alarm < counter_time)
{
/* Add 1 day to alarm counter*/
- counter_alarm += (uint32_t)(24 * 3600);
+ counter_alarm += (uint32_t)(24U * 3600U);
}
/* Write alarm counter in RTC registers */
@@ -1065,12 +1065,15 @@
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
{
- uint32_t counter_alarm = 0;
+ uint32_t counter_alarm = 0U;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Alarm);
/* Check input parameters */
if((hrtc == NULL) || (sAlarm == NULL))
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
/* Check the parameters */
@@ -1082,9 +1085,9 @@
/* Fill the structure with the read parameters */
/* Set hours in a day range (between 0 to 24)*/
- sAlarm->AlarmTime.Hours = (uint32_t)((counter_alarm / 3600) % 24);
- sAlarm->AlarmTime.Minutes = (uint32_t)((counter_alarm % 3600) / 60);
- sAlarm->AlarmTime.Seconds = (uint32_t)((counter_alarm % 3600) % 60);
+ sAlarm->AlarmTime.Hours = (uint32_t)((counter_alarm / 3600U) % 24U);
+ sAlarm->AlarmTime.Minutes = (uint32_t)((counter_alarm % 3600U) / 60U);
+ sAlarm->AlarmTime.Seconds = (uint32_t)((counter_alarm % 3600U) % 60U);
if(Format != RTC_FORMAT_BIN)
{
@@ -1107,6 +1110,9 @@
*/
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Alarm);
+
/* Check the parameters */
assert_param(IS_RTC_ALARM(Alarm));
@@ -1306,7 +1312,7 @@
*/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Check input parameters */
if(hrtc == NULL)
@@ -1353,8 +1359,8 @@
*/
static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef* hrtc)
{
- uint16_t high1 = 0, high2 = 0, low = 0;
- uint32_t timecounter = 0;
+ uint16_t high1 = 0U, high2 = 0U, low = 0U;
+ uint32_t timecounter = 0U;
high1 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT);
low = READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT);
@@ -1363,12 +1369,12 @@
if (high1 != high2)
{ /* In this case the counter roll over during reading of CNTL and CNTH registers,
read again CNTL register then return the counter value */
- timecounter = (((uint32_t) high2 << 16 ) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT));
+ timecounter = (((uint32_t) high2 << 16U) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT));
}
else
{ /* No counter roll over during reading of CNTL and CNTH registers, counter
value is equal to first value of CNTL and CNTH */
- timecounter = (((uint32_t) high1 << 16 ) | low);
+ timecounter = (((uint32_t) high1 << 16U) | low);
}
return timecounter;
@@ -1393,7 +1399,7 @@
else
{
/* Set RTC COUNTER MSB word */
- WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16));
+ WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16U));
/* Set RTC COUNTER LSB word */
WRITE_REG(hrtc->Instance->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT));
@@ -1415,12 +1421,12 @@
*/
static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef* hrtc)
{
- uint16_t high1 = 0, low = 0;
+ uint16_t high1 = 0U, low = 0U;
high1 = READ_REG(hrtc->Instance->ALRH & RTC_CNTH_RTC_CNT);
low = READ_REG(hrtc->Instance->ALRL & RTC_CNTL_RTC_CNT);
- return (((uint32_t) high1 << 16 ) | low);
+ return (((uint32_t) high1 << 16U) | low);
}
/**
@@ -1442,7 +1448,7 @@
else
{
/* Set RTC COUNTER MSB word */
- WRITE_REG(hrtc->Instance->ALRH, (AlarmCounter >> 16));
+ WRITE_REG(hrtc->Instance->ALRH, (AlarmCounter >> 16U));
/* Set RTC COUNTER LSB word */
WRITE_REG(hrtc->Instance->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR));
@@ -1464,7 +1470,7 @@
*/
static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
tickstart = HAL_GetTick();
/* Wait till RTC is in INIT state and if Time out is reached exit */
@@ -1491,7 +1497,7 @@
*/
static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef* hrtc)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -1516,15 +1522,15 @@
*/
static uint8_t RTC_ByteToBcd2(uint8_t Value)
{
- uint32_t bcdhigh = 0;
+ uint32_t bcdhigh = 0U;
- while(Value >= 10)
+ while(Value >= 10U)
{
bcdhigh++;
- Value -= 10;
+ Value -= 10U;
}
- return ((uint8_t)(bcdhigh << 4) | Value);
+ return ((uint8_t)(bcdhigh << 4U) | Value);
}
/**
@@ -1534,8 +1540,8 @@
*/
static uint8_t RTC_Bcd2ToByte(uint8_t Value)
{
- uint32_t tmp = 0;
- tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+ uint32_t tmp = 0U;
+ tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U;
return (tmp + (Value & (uint8_t)0x0F));
}
@@ -1548,8 +1554,8 @@
*/
static void RTC_DateUpdate(RTC_HandleTypeDef* hrtc, uint32_t DayElapsed)
{
- uint32_t year = 0, month = 0, day = 0;
- uint32_t loop = 0;
+ uint32_t year = 0U, month = 0U, day = 0U;
+ uint32_t loop = 0U;
/* Get the current year*/
year = hrtc->DateToUpdate.Year;
@@ -1558,35 +1564,35 @@
month = hrtc->DateToUpdate.Month;
day = hrtc->DateToUpdate.Date;
- for (loop = 0; loop < DayElapsed; loop++)
+ for (loop = 0U; loop < DayElapsed; loop++)
{
- if((month == 1) || (month == 3) || (month == 5) || (month == 7) || \
- (month == 8) || (month == 10) || (month == 12))
+ if((month == 1U) || (month == 3U) || (month == 5U) || (month == 7U) || \
+ (month == 8U) || (month == 10U) || (month == 12U))
{
- if(day < 31)
+ if(day < 31U)
{
day++;
}
/* Date structure member: day = 31 */
else
{
- if(month != 12)
+ if(month != 12U)
{
month++;
- day = 1;
+ day = 1U;
}
/* Date structure member: day = 31 & month =12 */
else
{
- month = 1;
- day = 1;
+ month = 1U;
+ day = 1U;
year++;
}
}
}
- else if((month == 4) || (month == 6) || (month == 9) || (month == 11))
+ else if((month == 4U) || (month == 6U) || (month == 9U) || (month == 11U))
{
- if(day < 30)
+ if(day < 30U)
{
day++;
}
@@ -1594,16 +1600,16 @@
else
{
month++;
- day = 1;
+ day = 1U;
}
}
- else if(month == 2)
+ else if(month == 2U)
{
- if(day < 28)
+ if(day < 28U)
{
day++;
}
- else if(day == 28)
+ else if(day == 28U)
{
/* Leap year */
if(RTC_IsLeapYear(year))
@@ -1613,13 +1619,13 @@
else
{
month++;
- day = 1;
+ day = 1U;
}
}
- else if(day == 29)
+ else if(day == 29U)
{
month++;
- day = 1;
+ day = 1U;
}
}
}
@@ -1643,23 +1649,23 @@
*/
static uint8_t RTC_IsLeapYear(uint16_t nYear)
{
- if((nYear % 4) != 0)
+ if((nYear % 4U) != 0U)
{
- return 0;
+ return 0U;
}
- if((nYear % 100) != 0)
+ if((nYear % 100U) != 0U)
{
- return 1;
+ return 1U;
}
- if((nYear % 400) == 0)
+ if((nYear % 400U) == 0U)
{
- return 1;
+ return 1U;
}
else
{
- return 0;
+ return 0U;
}
}
@@ -1680,19 +1686,19 @@
*/
static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay)
{
- uint32_t year = 0, weekday = 0;
+ uint32_t year = 0U, weekday = 0U;
- year = 2000 + nYear;
+ year = 2000U + nYear;
- if(nMonth < 3)
+ if(nMonth < 3U)
{
/*D = { [(23 x month)/9] + day + 4 + year + [(year-1)/4] - [(year-1)/100] + [(year-1)/400] } mod 7*/
- weekday = (((23 * nMonth)/9) + nDay + 4 + year + ((year-1)/4) - ((year-1)/100) + ((year-1)/400)) % 7;
+ weekday = (((23U * nMonth)/9U) + nDay + 4U + year + ((year-1U)/4U) - ((year-1U)/100U) + ((year-1U)/400U)) % 7U;
}
else
{
/*D = { [(23 x month)/9] + day + 4 + year + [year/4] - [year/100] + [year/400] - 2 } mod 7*/
- weekday = (((23 * nMonth)/9) + nDay + 4 + year + (year/4) - (year/100) + (year/400) - 2 ) % 7;
+ weekday = (((23U * nMonth)/9U) + nDay + 4U + year + (year/4U) - (year/100U) + (year/400U) - 2U ) % 7U;
}
return (uint8_t)weekday;
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rtc_ex.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rtc_ex.c
index d296287..3e002a8 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rtc_ex.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_rtc_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Extended RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
@@ -197,7 +197,9 @@
{
return HAL_ERROR;
}
-
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(Tamper);
+
assert_param(IS_RTC_TAMPER(Tamper));
/* Process Locked */
@@ -287,7 +289,7 @@
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@@ -485,13 +487,16 @@
*/
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
{
- uint32_t tmp = 0;
+ uint32_t tmp = 0U;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
tmp = (uint32_t)BKP_BASE;
- tmp += (BackupRegister * 4);
+ tmp += (BackupRegister * 4U);
*(__IO uint32_t *) tmp = (Data & BKP_DR1_D);
}
@@ -507,14 +512,17 @@
*/
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
{
- uint32_t backupregister = 0;
- uint32_t pvalue = 0;
+ uint32_t backupregister = 0U;
+ uint32_t pvalue = 0U;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hrtc);
/* Check the parameters */
assert_param(IS_RTC_BKP(BackupRegister));
backupregister = (uint32_t)BKP_BASE;
- backupregister += (BackupRegister * 4);
+ backupregister += (BackupRegister * 4U);
pvalue = (*(__IO uint32_t *)(backupregister)) & BKP_DR1_D;
@@ -539,7 +547,10 @@
{
return HAL_ERROR;
}
-
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(SmoothCalibPeriod);
+ UNUSED(SmoothCalibPlusPulses);
+
/* Check the parameters */
assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sd.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sd.c
index d13fb26..c20f35f 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sd.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sd.c
@@ -2,15 +2,15 @@
******************************************************************************
* @file stm32f1xx_hal_sd.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief SD card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
- * + Peripheral State functions
+ * + SD card Control functions
*
@verbatim
==============================================================================
@@ -43,45 +43,58 @@
(+++) Configure the SDIO and DMA interrupt priorities using functions
HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
(+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
- (+++) SDIO interrupts are managed using the macros __HAL_SD_SDIO_ENABLE_IT()
- and __HAL_SD_SDIO_DISABLE_IT() inside the communication process.
- (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_SDIO_GET_IT()
- and __HAL_SD_SDIO_CLEAR_IT()
+ (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+ and __HAL_SD_DISABLE_IT() inside the communication process.
+ (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+ and __HAL_SD_CLEAR_IT()
+ (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT()
+ and HAL_SD_WriteBlocks_IT() APIs).
+ (+++) Configure the SDIO interrupt priorities using function
+ HAL_NVIC_SetPriority();
+ (+++) Enable the NVIC SDIO IRQs using function HAL_NVIC_EnableIRQ()
+ (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT()
+ and __HAL_SD_DISABLE_IT() inside the communication process.
+ (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT()
+ and __HAL_SD_CLEAR_IT()
(#) At this stage, you can perform SD read/write/erase operations after SD card initialization
*** SD Card Initialization and configuration ***
================================================
[..]
- To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
- the SD Card and put it into StandBy State (Ready for data transfer).
+ To initialize the SD Card, use the HAL_SD_Init() function. It Initializes
+ SDIO IP(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer).
This function provide the following operations:
-
- (#) Apply the SD Card initialization process at 400KHz and check the SD Card
- type (Standard Capacity or High Capacity). You can change or adapt this
- frequency by adjusting the "ClockDiv" field.
+
+ (#) Initialize the SDIO peripheral interface with defaullt configuration.
+ The initialization process is done at 400KHz. You can change or adapt
+ this frequency by adjusting the "ClockDiv" field.
The SD Card frequency (SDIO_CK) is computed as follows:
SDIO_CK = SDIOCLK / (ClockDiv + 2)
In initialization mode and according to the SD Card standard,
make sure that the SDIO_CK frequency doesn't exceed 400KHz.
+
+ This phase of initialization is done through SDIO_Init() and
+ SDIO_PowerState_ON() SDIO low level APIs.
+
+ (#) Initialize the SD card. The API used is HAL_SD_InitCard().
+ This phase allows the card initialization and identification
+ and check the SD Card type (Standard Capacity or High Capacity)
+ The initialization flow is compatible with SD standard.
+
+ This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case
+ of plug-off plug-in.
- (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo
- structure. This structure provide also ready computed SD Card capacity
- and Block size.
-
- -@- These information are stored in SD handle structure in case of future use.
-
- (#) Configure the SD Card Data transfer frequency. The card transfer
- frequency is set to SDIOCLK / (SDIO_TRANSFER_CLK_DIV + 2). You can change or adapt this frequency by adjusting
+ (#) Configure the SD Card Data transfer frequency. By Default, the card transfer
+ frequency is set to 24MHz. You can change or adapt this frequency by adjusting
the "ClockDiv" field.
- The SD Card frequency (SDIO_CK) is computed as follows:
-
- SDIO_CK = SDIOCLK / (ClockDiv + 2)
-
In transfer mode and according to the SD Card standard, make sure that the
SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
+ To be able to use a frequency higher than 24MHz, you should use the SDIO
+ peripheral in bypass mode. Refer to the corresponding reference manual
+ for more details.
(#) Select the corresponding SD Card according to the address read with the step 2.
@@ -91,65 +104,101 @@
==============================
[..]
(+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks().
- This function support only 512-bytes block length (the block size should be
- chosen as 512 bytes).
+ This function allows the read of 512 bytes blocks.
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
(+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
- This function support only 512-bytes block length (the block size should be
- chosen as 512 bytes).
+ This function allows the read of 512 bytes blocks.
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
- After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
- that the read transfer is done correctly in both DMA and SD sides.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+ You could also check the DMA transfer process through the SD Rx interrupt event.
+
+ (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+ You could also check the IT transfer process through the SD Rx interrupt event.
*** SD Card Write operation ***
===============================
[..]
(+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks().
- This function support only 512-bytes block length (the block size should be
- chosen as 512 bytes).
+ This function allows the read of 512 bytes blocks.
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
(+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
- This function support only 512-bytes block length (the block size should be
- chosen as 512 byte).
+ This function allows the read of 512 bytes blocks.
You can choose either one block read operation or multiple block read operation
by adjusting the "NumberOfBlocks" parameter.
- After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure
- that the write transfer is done correctly in both DMA and SD sides.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+ You could also check the DMA transfer process through the SD Tx interrupt event.
+
+ (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT().
+ This function allows the read of 512 bytes blocks.
+ You can choose either one block read operation or multiple block read operation
+ by adjusting the "NumberOfBlocks" parameter.
+ After this, you have to ensure that the transfer is done correctly. The check is done
+ through HAL_SD_GetCardState() function for SD card state.
+ You could also check the IT transfer process through the SD Tx interrupt event.
*** SD card status ***
======================
[..]
- (+) At any time, you can check the SD Card status and get the SD card state
- by using the HAL_SD_GetStatus() function. This function checks first if the
- SD card is still connected and then get the internal SD Card transfer state.
- (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus()
- function.
+ (+) The SD Status contains status bits that are related to the SD Memory
+ Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus().
+
+ *** SD card information ***
+ ===========================
+ [..]
+ (+) To get SD card information, you can use the function HAL_SD_GetCardInfo().
+ It returns useful information about the SD card such as block size, card type,
+ block number ...
+
+ *** SD card CSD register ***
+ ============================
+ [..]
+ (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register.
+ Some of the CSD parameters are useful for card initialization and identification.
+
+ *** SD card CID register ***
+ ============================
+ [..]
+ (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register.
+ Some of the CSD parameters are useful for card initialization and identification.
*** SD HAL driver macros list ***
==================================
[..]
Below the list of most used macros in SD HAL driver.
- (+) __HAL_SD_SDIO_ENABLE : Enable the SD device
- (+) __HAL_SD_SDIO_DISABLE : Disable the SD device
- (+) __HAL_SD_SDIO_DMA_ENABLE: Enable the SDIO DMA transfer
- (+) __HAL_SD_SDIO_DMA_DISABLE: Disable the SDIO DMA transfer
- (+) __HAL_SD_SDIO_ENABLE_IT: Enable the SD device interrupt
- (+) __HAL_SD_SDIO_DISABLE_IT: Disable the SD device interrupt
- (+) __HAL_SD_SDIO_GET_FLAG:Check whether the specified SD flag is set or not
- (+) __HAL_SD_SDIO_CLEAR_FLAG: Clear the SD's pending flags
-
- -@- You can refer to the SD HAL driver header file for more useful macros
+
+ (+) __HAL_SD_ENABLE : Enable the SD device
+ (+) __HAL_SD_DISABLE : Disable the SD device
+ (+) __HAL_SD_DMA_ENABLE: Enable the SDIO DMA transfer
+ (+) __HAL_SD_DMA_DISABLE: Disable the SDIO DMA transfer
+ (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt
+ (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt
+ (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not
+ (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags
+ [..]
+ (@) You can refer to the SD HAL driver header file for more useful macros
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -179,105 +228,23 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
-#ifdef HAL_SD_MODULE_ENABLED
-
#if defined(STM32F103xE) || defined(STM32F103xG)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
-/** @defgroup SD SD
- * @brief SD HAL module driver
+/** @addtogroup SD
* @{
*/
+#ifdef HAL_SD_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-
-/** @defgroup SD_Private_Define SD Private Constant
+/** @addtogroup SD_Private_Defines
* @{
*/
-/**
- * @brief SDIO Data block size
- */
-#define DATA_BLOCK_SIZE ((uint32_t)(9 << 4))
-/**
- * @brief SDIO Static flags, TimeOut, FIFO Address
- */
-#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
- SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\
- SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\
- SDIO_FLAG_DBCKEND))
-
-#define SDIO_CMD0TIMEOUT ((uint32_t)0x00010000)
-
-/**
- * @brief Mask for errors Card Status R1 (OCR Register)
- */
-#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000)
-#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000)
-#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000)
-#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000)
-#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000)
-#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000)
-#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000)
-#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000)
-#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000)
-#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000)
-#define SD_OCR_CC_ERROR ((uint32_t)0x00100000)
-#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000)
-#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000)
-#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000)
-#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000)
-#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000)
-#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000)
-#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000)
-#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008)
-#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008)
-
-/**
- * @brief Masks for R6 Response
- */
-#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000)
-#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000)
-#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000)
-
-#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000)
-#define SD_HIGH_CAPACITY ((uint32_t)0x40000000)
-#define SD_STD_CAPACITY ((uint32_t)0x00000000)
-#define SD_CHECK_PATTERN ((uint32_t)0x000001AA)
-
-#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF)
-#define SD_ALLZERO ((uint32_t)0x00000000)
-
-#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000)
-#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000)
-#define SD_CARD_LOCKED ((uint32_t)0x02000000)
-
-#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF)
-#define SD_0TO7BITS ((uint32_t)0x000000FF)
-#define SD_8TO15BITS ((uint32_t)0x0000FF00)
-#define SD_16TO23BITS ((uint32_t)0x00FF0000)
-#define SD_24TO31BITS ((uint32_t)0xFF000000)
-#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF)
-
-#define SD_HALFFIFO ((uint32_t)0x00000008)
-#define SD_HALFFIFOBYTES ((uint32_t)0x00000020)
-
-/**
- * @brief Command Class Supported
- */
-#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080)
-#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040)
-#define SD_CCCC_ERASE ((uint32_t)0x00000020)
-
-/**
- * @brief Following commands are SD Card Specific commands.
- * SDIO_APP_CMD should be sent before sending these commands.
- */
-#define SD_SDIO_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
-
+
/**
* @}
*/
@@ -286,120 +253,170 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
/** @defgroup SD_Private_Functions SD Private Functions
* @{
*/
-
-static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t Addr);
-static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
-static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus);
-static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD);
-static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA);
-static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
-static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMA_RxError(DMA_HandleTypeDef *hdma);
-static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);
-
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd);
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd);
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd);
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd);
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
+static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd);
+static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd);
+static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd);
+static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SD_DMAError(DMA_HandleTypeDef *hdma);
+static void SD_DMATxAbort(DMA_HandleTypeDef *hdma);
+static void SD_DMARxAbort(DMA_HandleTypeDef *hdma);
/**
* @}
*/
-
-/** @defgroup SD_Exported_Functions SD Exported Functions
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SD_Exported_Functions
* @{
*/
-/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @addtogroup SD_Exported_Functions_Group1
+ * @brief Initialization and de-initialization functions
*
@verbatim
- ===============================================================================
- ##### Initialization and de-initialization functions #####
- ===============================================================================
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
[..]
This section provides functions allowing to initialize/de-initialize the SD
card device to be ready for use.
-
-
+
@endverbatim
* @{
*/
/**
- * @brief Initializes the SD card according to the specified parameters in the
+ * @brief Initializes the SD according to the specified parameters in the
SD_HandleTypeDef and create the associated handle.
- * @param hsd: SD handle
- * @param SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information
- * @retval HAL SD error state
+ * @param hsd: Pointer to the SD handle
+ * @retval HAL status
*/
-HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
-{
- __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
- SD_InitTypeDef tmpinit = {0};
+HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
+{
+ /* Check the SD handle allocation */
+ if(hsd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
+ assert_param(IS_SDIO_CLOCK_EDGE(hsd->Init.ClockEdge));
+ assert_param(IS_SDIO_CLOCK_BYPASS(hsd->Init.ClockBypass));
+ assert_param(IS_SDIO_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave));
+ assert_param(IS_SDIO_BUS_WIDE(hsd->Init.BusWide));
+ assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl));
+ assert_param(IS_SDIO_CLKDIV(hsd->Init.ClockDiv));
+
+ if(hsd->State == HAL_SD_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hsd->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_SD_MspInit(hsd);
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize the Card parameters */
+ HAL_SD_InitCard(hsd);
+
+ /* Initialize the error code */
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
- /* Initialize the low level hardware (MSP) */
- HAL_SD_MspInit(hsd);
+ /* Initialize the SD operation */
+ hsd->Context = SD_CONTEXT_NONE;
+
+ /* Initialize the SD state */
+ hsd->State = HAL_SD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the SD Card.
+ * @param hsd: Pointer to SD handle
+ * @note This function initializes the SD card. It could be used when a card
+ re-initialization is needed.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
+{
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ SD_InitTypeDef Init;
/* Default SDIO peripheral configuration for SD card initialization */
- tmpinit.ClockEdge = SDIO_CLOCK_EDGE_RISING;
- tmpinit.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
- tmpinit.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
- tmpinit.BusWide = SDIO_BUS_WIDE_1B;
- tmpinit.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
- tmpinit.ClockDiv = SDIO_INIT_CLK_DIV;
-
+ Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
+ Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
+ Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
+ Init.BusWide = SDIO_BUS_WIDE_1B;
+ Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+ Init.ClockDiv = SDIO_INIT_CLK_DIV;
+
/* Initialize SDIO peripheral interface with default configuration */
- SDIO_Init(hsd->Instance, tmpinit);
+ SDIO_Init(hsd->Instance, Init);
+
+ /* Disable SDIO Clock */
+ __HAL_SD_DISABLE(hsd);
+
+ /* Set Power State to ON */
+ SDIO_PowerState_ON(hsd->Instance);
+
+ /* Enable SDIO Clock */
+ __HAL_SD_ENABLE(hsd);
+
+ /* Required power up waiting time before starting the SD initialization
+ sequence */
+ HAL_Delay(2U);
/* Identify card operating voltage */
- errorstate = SD_PowerON(hsd);
-
- if(errorstate != SD_OK)
+ errorstate = SD_PowerON(hsd);
+ if(errorstate != HAL_SD_ERROR_NONE)
{
- return errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->ErrorCode |= errorstate;
+ return HAL_ERROR;
}
-
- /* Initialize the present SDIO card(s) and put them in idle state */
- errorstate = SD_Initialize_Cards(hsd);
-
- if (errorstate != SD_OK)
+
+ /* Card initialization */
+ errorstate = SD_InitCard(hsd);
+ if(errorstate != HAL_SD_ERROR_NONE)
{
- return errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->ErrorCode |= errorstate;
+ return HAL_ERROR;
}
-
- /* Read CSD/CID MSD registers */
- errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo);
-
- if (errorstate == SD_OK)
- {
- /* Select the Card */
- errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16));
- }
-
- /* Configure SDIO peripheral interface */
- SDIO_Init(hsd->Instance, hsd->Init);
-
- return errorstate;
+
+ return HAL_OK;
}
/**
* @brief De-Initializes the SD card.
- * @param hsd: SD handle
+ * @param hsd: Pointer to SD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
{
+ /* Check the SD handle allocation */
+ if(hsd == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance));
+
+ hsd->State = HAL_SD_STATE_BUSY;
/* Set SD power state to off */
SD_PowerOFF(hsd);
@@ -407,19 +424,23 @@
/* De-Initialize the MSP layer */
HAL_SD_MspDeInit(hsd);
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ hsd->State = HAL_SD_STATE_RESET;
+
return HAL_OK;
}
/**
* @brief Initializes the SD MSP.
- * @param hsd: SD handle
+ * @param hsd: Pointer to SD handle
* @retval None
*/
__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SD_MspInit could be implemented in the user file
*/
@@ -427,13 +448,14 @@
/**
* @brief De-Initialize SD MSP.
- * @param hsd: SD handle
+ * @param hsd: Pointer to SD handle
* @retval None
*/
__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SD_MspDeInit could be implemented in the user file
*/
@@ -443,13 +465,13 @@
* @}
*/
-/** @defgroup SD_Exported_Functions_Group2 IO operation functions
+/** @addtogroup SD_Exported_Functions_Group2
* @brief Data transfer functions
*
@verbatim
- ===============================================================================
- ##### IO operation functions #####
- ===============================================================================
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
[..]
This subsection provides a set of functions allowing to manage the data
transfer from/to SD card.
@@ -460,1038 +482,1132 @@
/**
* @brief Reads block(s) from a specified address in a card. The Data transfer
- * is managed by polling mode.
- * @param hsd: SD handle
- * @param pReadBuffer: pointer to the buffer that will contain the received data
- * @param ReadAddr: Address from where data is to be read
- * @param BlockSize: SD card Data block size (in bytes)
- * This parameter should be 512
- * @param NumberOfBlocks: Number of SD blocks to read
- * @retval SD Card error state
+ * is managed by polling mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @param hsd: Pointer to SD handle
+ * @param pData: pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of SD blocks to read
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
*/
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
{
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
- SDIO_DataInitTypeDef sdio_datainitstructure = {0};
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer;
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count = 0U, *tempbuff = (uint32_t *)pData;
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0;
-
- if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+ if(NULL == pData)
{
- BlockSize = 512;
- ReadAddr /= 512;
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
}
-
- /* Set Block Size for Card */
- sdio_cmdinitstructure.Argument = (uint32_t) BlockSize;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
- if (errorstate != SD_OK)
+
+ if(hsd->State == HAL_SD_STATE_READY)
{
- return errorstate;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
- sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize;
- sdio_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE;
- sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
- SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-
- if(NumberOfBlocks > 1)
- {
- /* Send CMD18 READ_MULT_BLOCK with argument data address */
- sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
- }
- else
- {
- /* Send CMD17 READ_SINGLE_BLOCK */
- sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
- }
-
- sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Read block(s) in polling mode */
- if(NumberOfBlocks > 1)
- {
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
- if (errorstate != SD_OK)
+ if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
- return errorstate;
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
}
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
+
+ /* Read block(s) in polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK;
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
+ }
+ else
+ {
+ hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK;
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
/* Poll on SDIO flags */
- while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+ while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_STA_STBITERR))
{
- if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
{
/* Read data from SDIO Rx FIFO */
- for (count = 0; count < 8; count++)
+ for(count = 0U; count < 8U; count++)
{
*(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
}
-
- tempbuff += 8;
+ tempbuff += 8U;
}
- }
- }
- else
- {
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
-
- if (errorstate != SD_OK)
- {
- return errorstate;
- }
-
- /* In case of single block transfer, no need of stop transfer at all */
- while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
- {
- if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+
+ if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
{
- /* Read data from SDIO Rx FIFO */
- for (count = 0; count < 8; count++)
- {
- *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
- }
-
- tempbuff += 8;
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+ hsd->State= HAL_SD_STATE_READY;
+ return HAL_TIMEOUT;
}
}
- }
-
- /* Send stop transmission command in case of multiblock read */
- if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1))
- {
- if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\
- (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
- (hsd->CardType == HIGH_CAPACITY_SD_CARD))
- {
- /* Send stop transmission command */
- errorstate = HAL_SD_StopTransfer(hsd);
+
+ /* Send stop transmission command in case of multiblock read */
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ {
+ if(hsd->SdCard.CardType != CARD_SECURED)
+ {
+ /* Send stop transmission command */
+ errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
}
- }
-
- /* Get error state */
- if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
- errorstate = SD_DATA_TIMEOUT;
+ /* Get error state */
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
- return errorstate;
- }
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+ /* Empty FIFO if there is still any data */
+ while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)))
+ {
+ *tempbuff = SDIO_ReadFIFO(hsd->Instance);
+ tempbuff++;
+
+ if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT;
+ hsd->State= HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
- errorstate = SD_DATA_CRC_FAIL;
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
- return errorstate;
- }
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
+ hsd->State = HAL_SD_STATE_READY;
- errorstate = SD_RX_OVERRUN;
-
- return errorstate;
- }
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-
- errorstate = SD_START_BIT_ERR;
-
- return errorstate;
+ return HAL_OK;
}
else
{
- /* No error flag set */
+ hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+ return HAL_ERROR;
}
-
- count = SD_DATATIMEOUT;
-
- /* Empty FIFO if there is still any data */
- while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
- {
- *tempbuff = SDIO_ReadFIFO(hsd->Instance);
- tempbuff++;
- count--;
- }
-
- /* Clear all the static flags */
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- return errorstate;
}
/**
* @brief Allows to write block(s) to a specified address in a card. The Data
- * transfer is managed by polling mode.
- * @param hsd: SD handle
- * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit
- * @param WriteAddr: Address from where data is to be written
- * @param BlockSize: SD card Data block size (in bytes)
- * This parameter should be 512.
- * @param NumberOfBlocks: Number of SD blocks to write
- * @retval SD Card error state
+ * transfer is managed by polling mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @param hsd: Pointer to SD handle
+ * @param pData: pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of SD blocks to write
+ * @param Timeout: Specify timeout value
+ * @retval HAL status
*/
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
{
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
- SDIO_DataInitTypeDef sdio_datainitstructure = {0};
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0;
- uint32_t *tempbuff = (uint32_t *)pWriteBuffer;
- uint8_t cardstate = 0;
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count = 0U;
+ uint32_t *tempbuff = (uint32_t *)pData;
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0;
-
- if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+ if(NULL == pData)
{
- BlockSize = 512;
- WriteAddr /= 512;
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
}
-
- /* Set Block Size for Card */
- sdio_cmdinitstructure.Argument = (uint32_t)BlockSize;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
- if (errorstate != SD_OK)
+
+ if(hsd->State == HAL_SD_STATE_READY)
{
- return errorstate;
- }
-
- if(NumberOfBlocks > 1)
- {
- /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
- sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
- }
- else
- {
- /* Send CMD24 WRITE_SINGLE_BLOCK */
- sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
- }
-
- sdio_cmdinitstructure.Argument = (uint32_t)WriteAddr;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- if(NumberOfBlocks > 1)
- {
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
- }
- else
- {
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
- }
-
- if (errorstate != SD_OK)
- {
- return errorstate;
- }
-
- /* Set total number of bytes to write */
- totalnumberofbytes = NumberOfBlocks * BlockSize;
-
- /* Configure the SD DPSM (Data Path State Machine) */
- sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
- sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize;
- sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
- sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
- SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-
- /* Write block(s) in polling mode */
- if(NumberOfBlocks > 1)
- {
- while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
{
- if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
- {
- if ((totalnumberofbytes - bytestransferred) < 32)
- {
- restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1);
-
- /* Write data to SDIO Tx FIFO */
- for (count = 0; count < restwords; count++)
- {
- SDIO_WriteFIFO(hsd->Instance, tempbuff);
- tempbuff++;
- bytestransferred += 4;
- }
- }
- else
- {
- /* Write data to SDIO Tx FIFO */
- for (count = 0; count < 8; count++)
- {
- SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
- }
-
- tempbuff += 8;
- bytestransferred += 32;
- }
- }
- }
- }
- else
- {
- /* In case of single data block transfer no need of stop command at all */
- while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
- {
- if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
- {
- if ((totalnumberofbytes - bytestransferred) < 32)
- {
- restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1);
-
- /* Write data to SDIO Tx FIFO */
- for (count = 0; count < restwords; count++)
- {
- SDIO_WriteFIFO(hsd->Instance, tempbuff);
- tempbuff++;
- bytestransferred += 4;
- }
- }
- else
- {
- /* Write data to SDIO Tx FIFO */
- for (count = 0; count < 8; count++)
- {
- SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
- }
-
- tempbuff += 8;
- bytestransferred += 32;
- }
- }
- }
- }
-
- /* Send stop transmission command in case of multiblock write */
- if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1))
- {
- if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
- (hsd->CardType == HIGH_CAPACITY_SD_CARD))
- {
- /* Send stop transmission command */
- errorstate = HAL_SD_StopTransfer(hsd);
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
}
- }
-
- /* Get error state */
- if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
- errorstate = SD_DATA_TIMEOUT;
+ hsd->State = HAL_SD_STATE_BUSY;
- return errorstate;
- }
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ BlockAdd *= 512U;
+ }
- errorstate = SD_DATA_CRC_FAIL;
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
- return errorstate;
- }
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR);
+ /* Write Blocks in Polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK;
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
+ }
+ else
+ {
+ hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK;
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
- errorstate = SD_TX_UNDERRUN;
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = NumberOfBlocks * BLOCKSIZE;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
- return errorstate;
- }
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
+ /* Write block(s) in polling mode */
+ while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
+ {
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
+ {
+ /* Write data to SDIO Tx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
+ }
+ tempbuff += 8U;
+ }
+
+ if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
- errorstate = SD_START_BIT_ERR;
+ /* Send stop transmission command in case of multiblock write */
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U))
+ {
+ if(hsd->SdCard.CardType != CARD_SECURED)
+ {
+ /* Send stop transmission command */
+ errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+ }
- return errorstate;
+ /* Get error state */
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ hsd->State = HAL_SD_STATE_READY;
+
+ return HAL_OK;
}
else
{
- /* No error flag set */
+ hsd->ErrorCode |= HAL_SD_ERROR_BUSY;
+ return HAL_ERROR;
}
+}
+
+/**
+ * @brief Reads block(s) from a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @note You could also check the IT transfer process through the SD Rx
+ * interrupt event.
+ * @param hsd: Pointer to SD handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
+ * @param NumberOfBlocks: Number of blocks to read.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
- /* Clear all the static flags */
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- /* Wait till the card is in programming state */
- errorstate = SD_IsCardProgramming(hsd, &cardstate);
-
- while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
+ if(NULL == pData)
{
- errorstate = SD_IsCardProgramming(hsd, &cardstate);
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
}
- return errorstate;
+ if(hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ hsd->pRxBuffPtr = (uint32_t *)pData;
+ hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF | SDIO_IT_STBITERR));
+
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Read Blocks in IT mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
+ }
+ else
+ {
+ hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Writes block(s) to a specified address in a card. The Data transfer
+ * is managed in interrupt mode.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @note You could also check the IT transfer process through the SD Tx
+ * interrupt event.
+ * @param hsd: Pointer to SD handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
+ * @param NumberOfBlocks: Number of blocks to write
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
+ if(NULL == pData)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hsd->State == HAL_SD_STATE_READY)
+ {
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ hsd->pTxBuffPtr = (uint32_t *)pData;
+ hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks;
+
+ /* Enable transfer interrupts */
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE | SDIO_IT_STBITERR));
+
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Write Blocks in Polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
+ }
+ else
+ {
+ hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
}
/**
* @brief Reads block(s) from a specified address in a card. The Data transfer
* is managed by DMA mode.
- * @note This API should be followed by the function HAL_SD_CheckReadOperation()
- * to check the completion of the read process
- * @param hsd: SD handle
- * @param pReadBuffer: Pointer to the buffer that will contain the received data
- * @param ReadAddr: Address from where data is to be read
- * @param BlockSize: SD card Data block size
- * @note BlockSize must be 512 bytes.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @note You could also check the DMA transfer process through the SD Rx
+ * interrupt event.
+ * @param hsd: Pointer SD handle
+ * @param pData: Pointer to the buffer that will contain the received data
+ * @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Number of blocks to read.
- * @retval SD Card error state
+ * @retval HAL status
*/
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
- SDIO_DataInitTypeDef sdio_datainitstructure = {0};
- HAL_SD_ErrorTypedef errorstate = SD_OK;
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0;
-
- /* Initialize handle flags */
- hsd->SdTransferCplt = 0;
- hsd->DmaTransferCplt = 0;
- hsd->SdTransferErr = SD_OK;
-
- /* Initialize SD Read operation */
- if(NumberOfBlocks > 1)
+ if(NULL == pData)
{
- hsd->SdOperation = SD_READ_MULTIPLE_BLOCK;
- }
- else
- {
- hsd->SdOperation = SD_READ_SINGLE_BLOCK;
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
}
- /* Enable transfer interrupts */
- __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
- SDIO_IT_DTIMEOUT |\
- SDIO_IT_DATAEND |\
- SDIO_IT_RXOVERR |\
- SDIO_IT_STBITERR));
-
- /* Enable SDIO DMA transfer */
- __HAL_SD_SDIO_DMA_ENABLE(hsd);
-
- /* Configure DMA user callbacks */
- hsd->hdmarx->XferCpltCallback = SD_DMA_RxCplt;
- hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4);
-
- if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+ if(hsd->State == HAL_SD_STATE_READY)
{
- BlockSize = 512;
- ReadAddr /= 512;
- }
-
- /* Set Block Size for Card */
- sdio_cmdinitstructure.Argument = (uint32_t)BlockSize;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
- if (errorstate != SD_OK)
- {
- return errorstate;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
- sdio_datainitstructure.DataLength = BlockSize * NumberOfBlocks;
- sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
- SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-
- /* Check number of blocks command */
- if(NumberOfBlocks > 1)
- {
- /* Send CMD18 READ_MULT_BLOCK with argument data address */
- sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
- }
- else
- {
- /* Send CMD17 READ_SINGLE_BLOCK */
- sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
- }
-
- sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- if(NumberOfBlocks > 1)
- {
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
- }
- else
- {
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
- }
-
- /* Update the SD transfer error in SD handle */
- hsd->SdTransferErr = errorstate;
-
- return errorstate;
-}
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
+
+ if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR));
+
+ /* Set the DMA transfer complete callback */
+ hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hsd->hdmarx->XferErrorCallback = SD_DMAError;
+
+ /* Set the DMA Abort callback */
+ hsd->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
+
+ /* Enable SD DMA transfer */
+ __HAL_SD_DMA_ENABLE(hsd);
+
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Read Blocks in DMA mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Read Multi Block command */
+ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd);
+ }
+ else
+ {
+ hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Read Single Block command */
+ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
/**
* @brief Writes block(s) to a specified address in a card. The Data transfer
* is managed by DMA mode.
- * @note This API should be followed by the function HAL_SD_CheckWriteOperation()
- * to check the completion of the write process (by SD current status polling).
- * @param hsd: SD handle
- * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit
- * @param WriteAddr: Address from where data is to be read
- * @param BlockSize: the SD card Data block size
- * @note BlockSize must be 512 bytes.
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @note You could also check the DMA transfer process through the SD Tx
+ * interrupt event.
+ * @param hsd: Pointer to SD handle
+ * @param pData: Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd: Block Address where data will be written
* @param NumberOfBlocks: Number of blocks to write
- * @retval SD Card error state
+ * @retval HAL status
*/
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
- SDIO_DataInitTypeDef sdio_datainitstructure = {0};
- HAL_SD_ErrorTypedef errorstate = SD_OK;
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
- /* Initialize data control register */
- hsd->Instance->DCTRL = 0;
-
- /* Initialize handle flags */
- hsd->SdTransferCplt = 0;
- hsd->DmaTransferCplt = 0;
- hsd->SdTransferErr = SD_OK;
-
- /* Initialize SD Write operation */
- if(NumberOfBlocks > 1)
+ if(NULL == pData)
{
- hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK;
- }
- else
- {
- hsd->SdOperation = SD_WRITE_SINGLE_BLOCK;
- }
-
- /* Enable transfer interrupts */
- __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
- SDIO_IT_DTIMEOUT |\
- SDIO_IT_DATAEND |\
- SDIO_IT_TXUNDERR |\
- SDIO_IT_STBITERR));
-
- /* Configure DMA user callbacks */
- hsd->hdmatx->XferCpltCallback = SD_DMA_TxCplt;
- hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;
-
- /* Enable the DMA Channel */
- HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4);
-
- /* Enable SDIO DMA transfer */
- __HAL_SD_SDIO_DMA_ENABLE(hsd);
-
- if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
- {
- BlockSize = 512;
- WriteAddr /= 512;
- }
-
- /* Set Block Size for Card */
- sdio_cmdinitstructure.Argument = (uint32_t)BlockSize;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
- if (errorstate != SD_OK)
- {
- return errorstate;
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
}
- /* Check number of blocks command */
- if(NumberOfBlocks <= 1)
+ if(hsd->State == HAL_SD_STATE_READY)
{
- /* Send CMD24 WRITE_SINGLE_BLOCK */
- sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
- }
- else
- {
- /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
- sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
- }
-
- sdio_cmdinitstructure.Argument = (uint32_t)WriteAddr;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- if(NumberOfBlocks > 1)
- {
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
- }
- else
- {
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
- }
-
- if (errorstate != SD_OK)
- {
- return errorstate;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
- sdio_datainitstructure.DataLength = BlockSize * NumberOfBlocks;
- sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
- sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
- sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
- SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-
- hsd->SdTransferErr = errorstate;
-
- return errorstate;
-}
-
-/**
- * @brief This function waits until the SD DMA data read transfer is finished.
- * This API should be called after HAL_SD_ReadBlocks_DMA() function
- * to insure that all data sent by the card is already transferred by the
- * DMA controller.
- * @param hsd: SD handle
- * @param Timeout: Timeout duration
- * @retval SD Card error state
- */
-HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
-{
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- uint32_t timeout = Timeout;
- uint32_t tmp1, tmp2;
- HAL_SD_ErrorTypedef tmp3;
-
- /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
- tmp1 = hsd->DmaTransferCplt;
- tmp2 = hsd->SdTransferCplt;
- tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
- while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))
- {
- tmp1 = hsd->DmaTransferCplt;
- tmp2 = hsd->SdTransferCplt;
- tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
- timeout--;
- }
-
- timeout = Timeout;
-
- /* Wait until the Rx transfer is no longer active */
- while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXACT)) && (timeout > 0))
- {
- timeout--;
- }
-
- /* Send stop command in multiblock read */
- if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK)
- {
- errorstate = HAL_SD_StopTransfer(hsd);
- }
-
- if ((timeout == 0) && (errorstate == SD_OK))
- {
- errorstate = SD_DATA_TIMEOUT;
- }
-
- /* Clear all the static flags */
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- /* Return error state */
- if (hsd->SdTransferErr != SD_OK)
- {
- return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
- }
-
- return errorstate;
-}
-
-/**
- * @brief This function waits until the SD DMA data write transfer is finished.
- * This API should be called after HAL_SD_WriteBlocks_DMA() function
- * to insure that all data sent by the card is already transferred by the
- * DMA controller.
- * @param hsd: SD handle
- * @param Timeout: Timeout duration
- * @retval SD Card error state
- */
-HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
-{
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- uint32_t timeout = Timeout;
- uint32_t tmp1, tmp2;
- HAL_SD_ErrorTypedef tmp3;
-
- /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
- tmp1 = hsd->DmaTransferCplt;
- tmp2 = hsd->SdTransferCplt;
- tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
+ if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr))
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
+ }
- while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0))
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Initialize data control register */
+ hsd->Instance->DCTRL = 0U;
+
+ /* Enable SD Error interrupts */
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR));
+
+ /* Set the DMA transfer complete callback */
+ hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hsd->hdmatx->XferErrorCallback = SD_DMAError;
+
+ /* Set the DMA Abort callback */
+ hsd->hdmatx->XferAbortCallback = NULL;
+
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ BlockAdd *= 512U;
+ }
+
+ /* Set Block Size for Card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Write Blocks in Polling mode */
+ if(NumberOfBlocks > 1U)
+ {
+ hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Write Multi Block command */
+ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd);
+ }
+ else
+ {
+ hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA);
+
+ /* Write Single Block command */
+ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd);
+ }
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Enable SDIO DMA transfer */
+ __HAL_SD_DMA_ENABLE(hsd);
+
+ /* Enable the DMA Channel */
+ HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4);
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = BLOCKSIZE * NumberOfBlocks;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
+
+ return HAL_OK;
+ }
+ else
{
- tmp1 = hsd->DmaTransferCplt;
- tmp2 = hsd->SdTransferCplt;
- tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
- timeout--;
+ return HAL_BUSY;
}
-
- timeout = Timeout;
-
- /* Wait until the Tx transfer is no longer active */
- while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXACT)) && (timeout > 0))
- {
- timeout--;
- }
-
- /* Send stop command in multiblock write */
- if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK)
- {
- errorstate = HAL_SD_StopTransfer(hsd);
- }
-
- if ((timeout == 0) && (errorstate == SD_OK))
- {
- errorstate = SD_DATA_TIMEOUT;
- }
-
- /* Clear all the static flags */
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- /* Return error state */
- if (hsd->SdTransferErr != SD_OK)
- {
- return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
- }
-
- /* Wait until write is complete */
- while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK)
- {
- }
-
- return errorstate;
}
/**
* @brief Erases the specified memory area of the given SD card.
- * @param hsd: SD handle
- * @param Startaddr: Start byte address
- * @param Endaddr: End byte address
- * @retval SD Card error state
+ * @note This API should be followed by a check on the card state through
+ * HAL_SD_GetCardState().
+ * @param hsd: Pointer to SD handle
+ * @param BlockStartAdd: Start Block address
+ * @param BlockEndAdd: End Block address
+ * @retval HAL status
*/
-HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t Startaddr, uint64_t Endaddr)
+HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
{
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
- uint32_t delay = 0;
- __IO uint32_t maxdelay = 0;
- uint8_t cardstate = 0;
-
- /* Check if the card command class supports erase command */
- if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0)
+ if(hsd->State == HAL_SD_STATE_READY)
{
- errorstate = SD_REQUEST_NOT_APPLICABLE;
+ hsd->ErrorCode = HAL_DMA_ERROR_NONE;
- return errorstate;
- }
-
- /* Get max delay value */
- maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2);
-
- if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
- {
- errorstate = SD_LOCK_UNLOCK_FAILED;
-
- return errorstate;
- }
-
- /* Get start and end block for high capacity cards */
- if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
- {
- Startaddr /= 512;
- Endaddr /= 512;
- }
-
- /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
- if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
- (hsd->CardType == HIGH_CAPACITY_SD_CARD))
- {
- /* Send CMD32 SD_ERASE_GRP_START with argument as addr */
- sdio_cmdinitstructure.Argument =(uint32_t)Startaddr;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_START;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);
-
- if (errorstate != SD_OK)
+ if(BlockEndAdd < BlockStartAdd)
{
- return errorstate;
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
+ return HAL_ERROR;
}
- /* Send CMD33 SD_ERASE_GRP_END with argument as addr */
- sdio_cmdinitstructure.Argument = (uint32_t)Endaddr;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_END;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);
-
- if (errorstate != SD_OK)
+ if(BlockEndAdd > (hsd->SdCard.LogBlockNbr))
{
- return errorstate;
+ hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
+ return HAL_ERROR;
}
+
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ /* Check if the card command class supports erase command */
+ if(((hsd->SdCard.Class) & SDIO_CCCC_ERASE) == 0U)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Get start and end block for high capacity cards */
+ if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
+ {
+ BlockStartAdd *= 512U;
+ BlockEndAdd *= 512U;
+ }
+
+ /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
+ if(hsd->SdCard.CardType != CARD_SECURED)
+ {
+ /* Send CMD32 SD_ERASE_GRP_START with argument as addr */
+ errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, BlockStartAdd);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Send CMD33 SD_ERASE_GRP_END with argument as addr */
+ errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, BlockEndAdd);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ }
+
+ /* Send CMD38 ERASE */
+ errorstate = SDMMC_CmdErase(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ hsd->State = HAL_SD_STATE_READY;
+
+ return HAL_OK;
}
-
- /* Send CMD38 ERASE */
- sdio_cmdinitstructure.Argument = 0;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_ERASE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE);
-
- if (errorstate != SD_OK)
+ else
{
- return errorstate;
+ return HAL_BUSY;
}
-
- for (; delay < maxdelay; delay++)
- {
- }
-
- /* Wait untill the card is in programming state */
- errorstate = SD_IsCardProgramming(hsd, &cardstate);
-
- delay = SD_DATATIMEOUT;
-
- while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
- {
- errorstate = SD_IsCardProgramming(hsd, &cardstate);
- delay--;
- }
-
- return errorstate;
}
/**
* @brief This function handles SD card interrupt request.
- * @param hsd: SD handle
+ * @param hsd: Pointer to SD handle
* @retval None
*/
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
-{
+{
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
/* Check for SDIO interrupt flags */
- if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DATAEND))
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DATAEND) != RESET)
{
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_IT_DATAEND);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DATAEND);
+
+ __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
+
+ if((hsd->Context & SD_CONTEXT_IT) != RESET)
+ {
+ if(((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET))
+ {
+ errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= errorstate;
+ HAL_SD_ErrorCallback(hsd);
+ }
+ }
- /* SD transfer is complete */
- hsd->SdTransferCplt = 1;
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ hsd->State = HAL_SD_STATE_READY;
+ if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET))
+ {
+ HAL_SD_RxCpltCallback(hsd);
+ }
+ else
+ {
+ HAL_SD_TxCpltCallback(hsd);
+ }
+ }
+ else if((hsd->Context & SD_CONTEXT_DMA) != RESET)
+ {
+ if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)
+ {
+ errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= errorstate;
+ HAL_SD_ErrorCallback(hsd);
+ }
+ }
+ if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == RESET))
+ {
+ /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+ in the SD DCTRL register */
+ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+ hsd->State = HAL_SD_STATE_READY;
+
+ HAL_SD_TxCpltCallback(hsd);
+ }
+ }
+ }
+
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_TXFIFOHE) != RESET)
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_TXFIFOHE);
+
+ SD_Write_IT(hsd);
+ }
+
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_RXFIFOHF) != RESET)
+ {
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXFIFOHF);
+
+ SD_Read_IT(hsd);
+ }
+
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR) != RESET)
+ {
+ /* Set Error code */
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL;
+ }
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DTIMEOUT) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ }
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_RXOVERR) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN;
+ }
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_TXUNDERR) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN;
+ }
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_STBITERR) != RESET)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT;
+ }
- /* No transfer error */
- hsd->SdTransferErr = SD_OK;
-
- HAL_SD_XferCpltCallback(hsd);
- }
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DCRCFAIL))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS | SDIO_FLAG_STBITERR);
- hsd->SdTransferErr = SD_DATA_CRC_FAIL;
+ /* Disable all interrupts */
+ __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR |SDIO_IT_STBITERR);
- HAL_SD_XferErrorCallback(hsd);
-
+ if((hsd->Context & SD_CONTEXT_DMA) != RESET)
+ {
+ /* Abort the SD DMA Streams */
+ if(hsd->hdmatx != NULL)
+ {
+ /* Set the DMA Tx abort callback */
+ hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+ /* Abort DMA in IT mode */
+ if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+ {
+ SD_DMATxAbort(hsd->hdmatx);
+ }
+ }
+ else if(hsd->hdmarx != NULL)
+ {
+ /* Set the DMA Rx abort callback */
+ hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+ /* Abort DMA in IT mode */
+ if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+ {
+ SD_DMARxAbort(hsd->hdmarx);
+ }
+ }
+ else
+ {
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ hsd->State = HAL_SD_STATE_READY;
+ HAL_SD_AbortCallback(hsd);
+ }
+ }
+ else if((hsd->Context & SD_CONTEXT_IT) != RESET)
+ {
+ /* Set the SD state to ready to be able to start again the process */
+ hsd->State = HAL_SD_STATE_READY;
+ HAL_SD_ErrorCallback(hsd);
+ }
}
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DTIMEOUT))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-
- hsd->SdTransferErr = SD_DATA_TIMEOUT;
-
- HAL_SD_XferErrorCallback(hsd);
- }
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_RXOVERR))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-
- hsd->SdTransferErr = SD_RX_OVERRUN;
-
- HAL_SD_XferErrorCallback(hsd);
- }
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_TXUNDERR))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR);
-
- hsd->SdTransferErr = SD_TX_UNDERRUN;
-
- HAL_SD_XferErrorCallback(hsd);
- }
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_STBITERR))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-
- hsd->SdTransferErr = SD_START_BIT_ERR;
-
- HAL_SD_XferErrorCallback(hsd);
- }
- else
- {
- /* No error flag set */
- }
-
- /* Disable all SDIO peripheral interrupt sources */
- __HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND |\
- SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\
- SDIO_IT_RXOVERR | SDIO_IT_STBITERR);
}
+/**
+ * @brief return the SD state
+ * @param hsd: Pointer to sd handle
+ * @retval HAL state
+ */
+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
+{
+ return hsd->State;
+}
/**
- * @brief SD end of transfer callback.
- * @param hsd: SD handle
+* @brief Return the SD error code
+* @param hsd : Pointer to a SD_HandleTypeDef structure that contains
+ * the configuration information.
+* @retval SD Error Code
+*/
+uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd)
+{
+ return hsd->ErrorCode;
+}
+
+/**
+ * @brief Tx Transfer completed callbacks
+ * @param hsd: Pointer to SD handle
* @retval None
*/
-__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)
+ __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SD_XferCpltCallback could be implemented in the user file
- */
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SD_TxCpltCallback can be implemented in the user file
+ */
}
/**
- * @brief SD Transfer Error callback.
- * @param hsd: SD handle
+ * @brief Rx Transfer completed callbacks
+ * @param hsd: Pointer SD handle
* @retval None
*/
-__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
+__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsd);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SD_XferErrorCallback could be implemented in the user file
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SD_RxCpltCallback can be implemented in the user file
+ */
+}
+
+/**
+ * @brief SD error callbacks
+ * @param hsd: Pointer SD handle
+ * @retval None
+ */
+__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SD_ErrorCallback can be implemented in the user file
*/
}
/**
- * @brief SD Transfer complete Rx callback in non blocking mode.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief SD Abort callbacks
+ * @param hsd: Pointer SD handle
* @retval None
*/
-__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
+__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
{
/* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SD_DMA_RxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief SD DMA transfer complete Rx error callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SD_DMA_RxErrorCallback could be implemented in the user file
+ UNUSED(hsd);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SD_ErrorCallback can be implemented in the user file
*/
}
-/**
- * @brief SD Transfer complete Tx callback in non blocking mode.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SD_DMA_TxCpltCallback could be implemented in the user file
- */
-}
-
-/**
- * @brief SD DMA transfer complete error Tx callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hdma);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SD_DMA_TxErrorCallback could be implemented in the user file
- */
-}
/**
* @}
*/
-/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
+/** @addtogroup SD_Exported_Functions_Group3
* @brief management functions
*
@verbatim
@@ -1500,730 +1616,562 @@
==============================================================================
[..]
This subsection provides a set of functions allowing to control the SD card
- operations.
+ operations and get the related information
@endverbatim
* @{
*/
/**
- * @brief Returns information about specific card.
- * @param hsd: SD handle
- * @param pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that
- * contains all SD cardinformation
- * @retval SD Card error state
+ * @brief Returns information the information of the card which are stored on
+ * the CID register.
+ * @param hsd: Pointer to SD handle
+ * @param pCID: Pointer to a HAL_SD_CIDTypeDef structure that
+ * contains all CID register parameters
+ * @retval HAL status
*/
-HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
+HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID)
{
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- uint32_t tmp = 0;
-
- pCardInfo->CardType = (uint8_t)(hsd->CardType);
- pCardInfo->RCA = (uint16_t)(hsd->RCA);
+ uint32_t tmp = 0U;
/* Byte 0 */
- tmp = (hsd->CSD[0] & 0xFF000000) >> 24;
- pCardInfo->SD_csd.CSDStruct = (uint8_t)((tmp & 0xC0) >> 6);
- pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
- pCardInfo->SD_csd.Reserved1 = tmp & 0x03;
+ tmp = (uint8_t)((hsd->CID[0U] & 0xFF000000U) >> 24U);
+ pCID->ManufacturerID = tmp;
/* Byte 1 */
- tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;
- pCardInfo->SD_csd.TAAC = (uint8_t)tmp;
+ tmp = (uint8_t)((hsd->CID[0U] & 0x00FF0000U) >> 16U);
+ pCID->OEM_AppliID = tmp << 8U;
/* Byte 2 */
- tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;
- pCardInfo->SD_csd.NSAC = (uint8_t)tmp;
+ tmp = (uint8_t)((hsd->CID[0U] & 0x000000FF00U) >> 8U);
+ pCID->OEM_AppliID |= tmp;
/* Byte 3 */
- tmp = hsd->CSD[0] & 0x000000FF;
- pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;
+ tmp = (uint8_t)(hsd->CID[0U] & 0x000000FFU);
+ pCID->ProdName1 = tmp << 24U;
/* Byte 4 */
- tmp = (hsd->CSD[1] & 0xFF000000) >> 24;
- pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4);
+ tmp = (uint8_t)((hsd->CID[1U] & 0xFF000000U) >> 24U);
+ pCID->ProdName1 |= tmp << 16;
/* Byte 5 */
- tmp = (hsd->CSD[1] & 0x00FF0000) >> 16;
- pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
- pCardInfo->SD_csd.RdBlockLen = (uint8_t)(tmp & 0x0F);
+ tmp = (uint8_t)((hsd->CID[1U] & 0x00FF0000U) >> 16U);
+ pCID->ProdName1 |= tmp << 8U;
/* Byte 6 */
- tmp = (hsd->CSD[1] & 0x0000FF00) >> 8;
- pCardInfo->SD_csd.PartBlockRead = (uint8_t)((tmp & 0x80) >> 7);
- pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
- pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
- pCardInfo->SD_csd.DSRImpl = (uint8_t)((tmp & 0x10) >> 4);
- pCardInfo->SD_csd.Reserved2 = 0; /*!< Reserved */
+ tmp = (uint8_t)((hsd->CID[1U] & 0x0000FF00U) >> 8U);
+ pCID->ProdName1 |= tmp;
- if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0))
+ /* Byte 7 */
+ tmp = (uint8_t)(hsd->CID[1U] & 0x000000FFU);
+ pCID->ProdName2 = tmp;
+
+ /* Byte 8 */
+ tmp = (uint8_t)((hsd->CID[2U] & 0xFF000000U) >> 24U);
+ pCID->ProdRev = tmp;
+
+ /* Byte 9 */
+ tmp = (uint8_t)((hsd->CID[2U] & 0x00FF0000U) >> 16U);
+ pCID->ProdSN = tmp << 24U;
+
+ /* Byte 10 */
+ tmp = (uint8_t)((hsd->CID[2U] & 0x0000FF00U) >> 8U);
+ pCID->ProdSN |= tmp << 16U;
+
+ /* Byte 11 */
+ tmp = (uint8_t)(hsd->CID[2U] & 0x000000FFU);
+ pCID->ProdSN |= tmp << 8U;
+
+ /* Byte 12 */
+ tmp = (uint8_t)((hsd->CID[3U] & 0xFF000000U) >> 24U);
+ pCID->ProdSN |= tmp;
+
+ /* Byte 13 */
+ tmp = (uint8_t)((hsd->CID[3U] & 0x00FF0000U) >> 16U);
+ pCID->Reserved1 |= (tmp & 0xF0U) >> 4U;
+ pCID->ManufactDate = (tmp & 0x0FU) << 8U;
+
+ /* Byte 14 */
+ tmp = (uint8_t)((hsd->CID[3U] & 0x0000FF00U) >> 8U);
+ pCID->ManufactDate |= tmp;
+
+ /* Byte 15 */
+ tmp = (uint8_t)(hsd->CID[3U] & 0x000000FFU);
+ pCID->CID_CRC = (tmp & 0xFEU) >> 1U;
+ pCID->Reserved2 = 1U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Returns information the information of the card which are stored on
+ * the CSD register.
+ * @param hsd: Pointer to SD handle
+ * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
+ * contains all CSD register parameters
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD)
+{
+ uint32_t tmp = 0U;
+
+ /* Byte 0 */
+ tmp = (hsd->CSD[0U] & 0xFF000000U) >> 24U;
+ pCSD->CSDStruct = (uint8_t)((tmp & 0xC0U) >> 6U);
+ pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3CU) >> 2U);
+ pCSD->Reserved1 = tmp & 0x03U;
+
+ /* Byte 1 */
+ tmp = (hsd->CSD[0U] & 0x00FF0000U) >> 16U;
+ pCSD->TAAC = (uint8_t)tmp;
+
+ /* Byte 2 */
+ tmp = (hsd->CSD[0U] & 0x0000FF00U) >> 8U;
+ pCSD->NSAC = (uint8_t)tmp;
+
+ /* Byte 3 */
+ tmp = hsd->CSD[0U] & 0x000000FFU;
+ pCSD->MaxBusClkFrec = (uint8_t)tmp;
+
+ /* Byte 4 */
+ tmp = (hsd->CSD[1U] & 0xFF000000U) >> 24U;
+ pCSD->CardComdClasses = (uint16_t)(tmp << 4U);
+
+ /* Byte 5 */
+ tmp = (hsd->CSD[1U] & 0x00FF0000U) >> 16U;
+ pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0U) >> 4U);
+ pCSD->RdBlockLen = (uint8_t)(tmp & 0x0FU);
+
+ /* Byte 6 */
+ tmp = (hsd->CSD[1U] & 0x0000FF00U) >> 8U;
+ pCSD->PartBlockRead = (uint8_t)((tmp & 0x80U) >> 7U);
+ pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40U) >> 6U);
+ pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20U) >> 5U);
+ pCSD->DSRImpl = (uint8_t)((tmp & 0x10U) >> 4U);
+ pCSD->Reserved2 = 0U; /*!< Reserved */
+
+ if(hsd->SdCard.CardType == CARD_SDSC)
{
- pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;
+ pCSD->DeviceSize = (tmp & 0x03U) << 10U;
/* Byte 7 */
- tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
- pCardInfo->SD_csd.DeviceSize |= (tmp) << 2;
+ tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU);
+ pCSD->DeviceSize |= (tmp) << 2U;
/* Byte 8 */
- tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
- pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
+ tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U);
+ pCSD->DeviceSize |= (tmp & 0xC0U) >> 6U;
- pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
- pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
+ pCSD->MaxRdCurrentVDDMin = (tmp & 0x38U) >> 3U;
+ pCSD->MaxRdCurrentVDDMax = (tmp & 0x07U);
/* Byte 9 */
- tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
- pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
- pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
- pCardInfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1;
+ tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U);
+ pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0U) >> 5U;
+ pCSD->MaxWrCurrentVDDMax = (tmp & 0x1CU) >> 2U;
+ pCSD->DeviceSizeMul = (tmp & 0x03U) << 1U;
/* Byte 10 */
- tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
- pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
+ tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U);
+ pCSD->DeviceSizeMul |= (tmp & 0x80U) >> 7U;
- pCardInfo->CardCapacity = (pCardInfo->SD_csd.DeviceSize + 1) ;
- pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2));
- pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen);
- pCardInfo->CardCapacity *= pCardInfo->CardBlockSize;
+ hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ;
+ hsd->SdCard.BlockNbr *= (1U << (pCSD->DeviceSizeMul + 2U));
+ hsd->SdCard.BlockSize = 1U << (pCSD->RdBlockLen);
+
+ hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U);
+ hsd->SdCard.LogBlockSize = 512U;
}
- else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
+ else if(hsd->SdCard.CardType == CARD_SDHC_SDXC)
{
/* Byte 7 */
- tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
- pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;
+ tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU);
+ pCSD->DeviceSize = (tmp & 0x3FU) << 16U;
/* Byte 8 */
- tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
+ tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U);
- pCardInfo->SD_csd.DeviceSize |= (tmp << 8);
+ pCSD->DeviceSize |= (tmp << 8U);
/* Byte 9 */
- tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
+ tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U);
- pCardInfo->SD_csd.DeviceSize |= (tmp);
+ pCSD->DeviceSize |= (tmp);
/* Byte 10 */
- tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
+ tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U);
- pCardInfo->CardCapacity = (uint64_t)(((uint64_t)pCardInfo->SD_csd.DeviceSize + 1) * 512 * 1024);
- pCardInfo->CardBlockSize = 512;
+ hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr = (((uint64_t)pCSD->DeviceSize + 1U) * 1024U);
+ hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize = 512U;
}
else
{
- /* Not supported card type */
- errorstate = SD_ERROR;
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
}
+
+ pCSD->EraseGrSize = (tmp & 0x40U) >> 6U;
+ pCSD->EraseGrMul = (tmp & 0x3FU) << 1U;
+
+ /* Byte 11 */
+ tmp = (uint8_t)(hsd->CSD[2U] & 0x000000FFU);
+ pCSD->EraseGrMul |= (tmp & 0x80U) >> 7U;
+ pCSD->WrProtectGrSize = (tmp & 0x7FU);
+
+ /* Byte 12 */
+ tmp = (uint8_t)((hsd->CSD[3U] & 0xFF000000U) >> 24U);
+ pCSD->WrProtectGrEnable = (tmp & 0x80U) >> 7U;
+ pCSD->ManDeflECC = (tmp & 0x60U) >> 5U;
+ pCSD->WrSpeedFact = (tmp & 0x1CU) >> 2U;
+ pCSD->MaxWrBlockLen = (tmp & 0x03U) << 2U;
+
+ /* Byte 13 */
+ tmp = (uint8_t)((hsd->CSD[3U] & 0x00FF0000U) >> 16U);
+ pCSD->MaxWrBlockLen |= (tmp & 0xC0U) >> 6U;
+ pCSD->WriteBlockPaPartial = (tmp & 0x20U) >> 5U;
+ pCSD->Reserved3 = 0U;
+ pCSD->ContentProtectAppli = (tmp & 0x01U);
+
+ /* Byte 14 */
+ tmp = (uint8_t)((hsd->CSD[3U] & 0x0000FF00U) >> 8U);
+ pCSD->FileFormatGrouop = (tmp & 0x80U) >> 7U;
+ pCSD->CopyFlag = (tmp & 0x40U) >> 6U;
+ pCSD->PermWrProtect = (tmp & 0x20U) >> 5U;
+ pCSD->TempWrProtect = (tmp & 0x10U) >> 4U;
+ pCSD->FileFormat = (tmp & 0x0CU) >> 2U;
+ pCSD->ECC = (tmp & 0x03U);
+
+ /* Byte 15 */
+ tmp = (uint8_t)(hsd->CSD[3U] & 0x000000FFU);
+ pCSD->CSD_CRC = (tmp & 0xFEU) >> 1U;
+ pCSD->Reserved4 = 1U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets the SD status info.
+ * @param hsd: Pointer to SD handle
+ * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
+ * will contain the SD card status information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus)
+{
+ uint32_t tmp = 0U;
+ uint32_t sd_status[16U];
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+
+ errorstate = SD_SendSDStatus(hsd, sd_status);
+ if(errorstate != HAL_OK)
+ {
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->ErrorCode |= errorstate;
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Byte 0 */
+ tmp = (sd_status[0U] & 0xC0U) >> 6U;
+ pStatus->DataBusWidth = (uint8_t)tmp;
- pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
- pCardInfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1;
+ /* Byte 0 */
+ tmp = (sd_status[0U] & 0x20U) >> 5U;
+ pStatus->SecuredMode = (uint8_t)tmp;
+
+ /* Byte 2 */
+ tmp = (sd_status[0U] & 0x00FF0000U) >> 16U;
+ pStatus->CardType = (uint16_t)(tmp << 8U);
+
+ /* Byte 3 */
+ tmp = (sd_status[0U] & 0xFF000000U) >> 24U;
+ pStatus->CardType |= (uint16_t)tmp;
+
+ /* Byte 4 */
+ tmp = (sd_status[1U] & 0xFFU);
+ pStatus->ProtectedAreaSize = (uint32_t)(tmp << 24U);
+
+ /* Byte 5 */
+ tmp = (sd_status[1U] & 0xFF00U) >> 8U;
+ pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 16U);
+
+ /* Byte 6 */
+ tmp = (sd_status[1U] & 0xFF0000U) >> 16U;
+ pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 8U);
+
+ /* Byte 7 */
+ tmp = (sd_status[1U] & 0xFF000000U) >> 24U;
+ pStatus->ProtectedAreaSize |= (uint32_t)tmp;
+
+ /* Byte 8 */
+ tmp = (sd_status[2U] & 0xFFU);
+ pStatus->SpeedClass = (uint8_t)tmp;
+
+ /* Byte 9 */
+ tmp = (sd_status[2U] & 0xFF00U) >> 8U;
+ pStatus->PerformanceMove = (uint8_t)tmp;
+
+ /* Byte 10 */
+ tmp = (sd_status[2U] & 0xF00000U) >> 20U;
+ pStatus->AllocationUnitSize = (uint8_t)tmp;
+
+ /* Byte 11 */
+ tmp = (sd_status[2U] & 0xFF000000U) >> 24U;
+ pStatus->EraseSize = (uint16_t)(tmp << 8U);
+
+ /* Byte 12 */
+ tmp = (sd_status[3U] & 0xFFU);
+ pStatus->EraseSize |= (uint16_t)tmp;
+
+ /* Byte 13 */
+ tmp = (sd_status[3U] & 0xFC00U) >> 10U;
+ pStatus->EraseTimeout = (uint8_t)tmp;
+
+ /* Byte 13 */
+ tmp = (sd_status[3U] & 0x0300U) >> 8U;
+ pStatus->EraseOffset = (uint8_t)tmp;
+ }
- /* Byte 11 */
- tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);
- pCardInfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7;
- pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);
+ return HAL_OK;
+}
+
+/**
+ * @brief Gets the SD card info.
+ * @param hsd: Pointer to SD handle
+ * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
+ * will contain the SD card status information
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo)
+{
+ pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType);
+ pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion);
+ pCardInfo->Class = (uint32_t)(hsd->SdCard.Class);
+ pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd);
+ pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr);
+ pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize);
+ pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr);
+ pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize);
- /* Byte 12 */
- tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24);
- pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
- pCardInfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5;
- pCardInfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2;
- pCardInfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2;
-
- /* Byte 13 */
- tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);
- pCardInfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6;
- pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;
- pCardInfo->SD_csd.Reserved3 = 0;
- pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01);
-
- /* Byte 14 */
- tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);
- pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;
- pCardInfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6;
- pCardInfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5;
- pCardInfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4;
- pCardInfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2;
- pCardInfo->SD_csd.ECC = (tmp & 0x03);
-
- /* Byte 15 */
- tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);
- pCardInfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1;
- pCardInfo->SD_csd.Reserved4 = 1;
-
- /* Byte 0 */
- tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24);
- pCardInfo->SD_cid.ManufacturerID = tmp;
-
- /* Byte 1 */
- tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);
- pCardInfo->SD_cid.OEM_AppliID = tmp << 8;
-
- /* Byte 2 */
- tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);
- pCardInfo->SD_cid.OEM_AppliID |= tmp;
-
- /* Byte 3 */
- tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);
- pCardInfo->SD_cid.ProdName1 = tmp << 24;
-
- /* Byte 4 */
- tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24);
- pCardInfo->SD_cid.ProdName1 |= tmp << 16;
-
- /* Byte 5 */
- tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);
- pCardInfo->SD_cid.ProdName1 |= tmp << 8;
-
- /* Byte 6 */
- tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);
- pCardInfo->SD_cid.ProdName1 |= tmp;
-
- /* Byte 7 */
- tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);
- pCardInfo->SD_cid.ProdName2 = tmp;
-
- /* Byte 8 */
- tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24);
- pCardInfo->SD_cid.ProdRev = tmp;
-
- /* Byte 9 */
- tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);
- pCardInfo->SD_cid.ProdSN = tmp << 24;
-
- /* Byte 10 */
- tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);
- pCardInfo->SD_cid.ProdSN |= tmp << 16;
-
- /* Byte 11 */
- tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);
- pCardInfo->SD_cid.ProdSN |= tmp << 8;
-
- /* Byte 12 */
- tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24);
- pCardInfo->SD_cid.ProdSN |= tmp;
-
- /* Byte 13 */
- tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);
- pCardInfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4;
- pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;
-
- /* Byte 14 */
- tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);
- pCardInfo->SD_cid.ManufactDate |= tmp;
-
- /* Byte 15 */
- tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);
- pCardInfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1;
- pCardInfo->SD_cid.Reserved2 = 1;
-
- return errorstate;
+ return HAL_OK;
}
/**
* @brief Enables wide bus operation for the requested card if supported by
* card.
- * @param hsd: SD handle
+ * @param hsd: Pointer to SD handle
* @param WideMode: Specifies the SD card wide bus mode
* This parameter can be one of the following values:
- * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)
+ * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
* @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
* @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
- * @retval SD Card error state
+ * @retval HAL status
*/
-HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode)
+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode)
{
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- SDIO_InitTypeDef init = {0};
+ SDIO_InitTypeDef Init;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
- /* MMC Card does not support this feature */
- if (hsd->CardType == MULTIMEDIA_CARD)
+ /* Check the parameters */
+ assert_param(IS_SDIO_BUS_WIDE(WideMode));
+
+ /* Chnage Satte */
+ hsd->State = HAL_SD_STATE_BUSY;
+
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
- errorstate = SD_UNSUPPORTED_FEATURE;
- }
- else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
- (hsd->CardType == HIGH_CAPACITY_SD_CARD))
- {
- if (WideMode == SDIO_BUS_WIDE_8B)
+ if(WideMode == SDIO_BUS_WIDE_8B)
{
- errorstate = SD_UNSUPPORTED_FEATURE;
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
- else if (WideMode == SDIO_BUS_WIDE_4B)
+ else if(WideMode == SDIO_BUS_WIDE_4B)
{
errorstate = SD_WideBus_Enable(hsd);
+
+ hsd->ErrorCode |= errorstate;
}
- else if (WideMode == SDIO_BUS_WIDE_1B)
+ else if(WideMode == SDIO_BUS_WIDE_1B)
{
errorstate = SD_WideBus_Disable(hsd);
+
+ hsd->ErrorCode |= errorstate;
}
else
{
/* WideMode is not a valid argument*/
- errorstate = SD_INVALID_PARAMETER;
+ hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
}
-
- if (errorstate == SD_OK)
- {
- /* Configure the SDIO peripheral */
- init.ClockEdge = hsd->Init.ClockEdge;
- init.ClockBypass = hsd->Init.ClockBypass;
- init.ClockPowerSave = hsd->Init.ClockPowerSave;
- init.BusWide = WideMode;
- init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
- init.ClockDiv = hsd->Init.ClockDiv;
-
- /* Configure SDIO peripheral interface */
- SDIO_Init(hsd->Instance, init);
- }
- else
- {
- /* An error occured while enabling/disabling the wide bus*/
- }
- }
+ }
else
{
- /* Not supported card type */
- errorstate = SD_ERROR;
+ /* MMC Card does not support this feature */
+ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
- return errorstate;
-}
-
-/**
- * @brief Aborts an ongoing data transfer.
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)
-{
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
- HAL_SD_ErrorTypedef errorstate = SD_OK;
-
- /* Send CMD12 STOP_TRANSMISSION */
- sdio_cmdinitstructure.Argument = 0;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_STOP_TRANSMISSION;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);
-
- return errorstate;
-}
-
-/**
- * @brief Switches the SD card to High Speed mode.
- * This API must be used after "Transfer State"
- * @note This operation should be followed by the configuration
- * of PLL to have SDIOCK clock between 67 and 75 MHz
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
-{
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
- SDIO_DataInitTypeDef sdio_datainitstructure = {0};
-
- uint8_t SD_hs[64] = {0};
- uint32_t SD_scr[2] = {0, 0};
- uint32_t SD_SPEC = 0 ;
- uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs;
-
- /* Initialize the Data control register */
- hsd->Instance->DCTRL = 0;
-
- /* Get SCR Register */
- errorstate = SD_FindSCR(hsd, SD_scr);
-
- if (errorstate != SD_OK)
+ if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
- return errorstate;
- }
-
- /* Test the Version supported by the card*/
- SD_SPEC = (SD_scr[1] & 0x01000000) | (SD_scr[1] & 0x02000000);
-
- if (SD_SPEC != SD_ALLZERO)
- {
- /* Set Block Size for Card */
- sdio_cmdinitstructure.Argument = (uint32_t)64;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
- if (errorstate != SD_OK)
- {
- return errorstate;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
- sdio_datainitstructure.DataLength = 64;
- sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B ;
- sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
- SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-
- /* Send CMD6 switch mode */
- sdio_cmdinitstructure.Argument = 0x80FFFF01;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_HS_SWITCH;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);
-
- if (errorstate != SD_OK)
- {
- return errorstate;
- }
-
- while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
- {
- if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
- {
- for (count = 0; count < 8; count++)
- {
- *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
- }
-
- tempbuff += 8;
- }
- }
-
- if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-
- errorstate = SD_DATA_TIMEOUT;
-
- return errorstate;
- }
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-
- errorstate = SD_DATA_CRC_FAIL;
-
- return errorstate;
- }
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-
- errorstate = SD_RX_OVERRUN;
-
- return errorstate;
- }
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-
- errorstate = SD_START_BIT_ERR;
-
- return errorstate;
- }
- else
- {
- /* No error flag set */
- }
-
- count = SD_DATATIMEOUT;
-
- while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
- {
- *tempbuff = SDIO_ReadFIFO(hsd->Instance);
- tempbuff++;
- count--;
- }
-
/* Clear all the static flags */
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- /* Test if the switch mode HS is ok */
- if ((SD_hs[13]& 2) != 2)
- {
- errorstate = SD_UNSUPPORTED_FEATURE;
- }
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+ hsd->State = HAL_SD_STATE_READY;
+ return HAL_ERROR;
}
+ else
+ {
+ /* Configure the SDIO peripheral */
+ Init.ClockEdge = hsd->Init.ClockEdge;
+ Init.ClockBypass = hsd->Init.ClockBypass;
+ Init.ClockPowerSave = hsd->Init.ClockPowerSave;
+ Init.BusWide = WideMode;
+ Init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
+ Init.ClockDiv = hsd->Init.ClockDiv;
+ SDIO_Init(hsd->Instance, Init);
+ }
+
+ /* Change State */
+ hsd->State = HAL_SD_STATE_READY;
- return errorstate;
+ return HAL_OK;
+}
+
+
+/**
+ * @brief Gets the current sd card data state.
+ * @param hsd: pointer to SD handle
+ * @retval Card state
+ */
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
+{
+ HAL_SD_CardStateTypeDef cardstate = HAL_SD_CARD_TRANSFER;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t resp1 = 0;
+
+ errorstate = SD_SendStatus(hsd, &resp1);
+ if(errorstate != HAL_OK)
+ {
+ hsd->ErrorCode |= errorstate;
+ }
+
+ cardstate = (HAL_SD_CardStateTypeDef)((resp1 >> 9U) & 0x0FU);
+
+ return cardstate;
}
/**
- * @}
+ * @brief Abort the current transfer and disable the SD.
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * the configuration information for SD module.
+ * @retval HAL status
*/
-
-/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in runtime the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the current SD card's status.
- * @param hsd: SD handle
- * @param pSDstatus: Pointer to the buffer that will contain the SD card status
- * SD Status register)
- * @retval SD Card error state
- */
-HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
+HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
{
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
- SDIO_DataInitTypeDef sdio_datainitstructure = {0};
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- uint32_t count = 0;
+ HAL_SD_CardStateTypeDef CardState;
- /* Check SD response */
- if ((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
+ /* DIsable All interrupts */
+ __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))
{
- errorstate = SD_LOCK_UNLOCK_FAILED;
+ /* Disable the SD DMA request */
+ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
- return errorstate;
- }
-
- /* Set block size for card if it is not equal to current block size for card */
- sdio_cmdinitstructure.Argument = 64;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
- if (errorstate != SD_OK)
- {
- return errorstate;
- }
-
- /* Send CMD55 */
- sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
- sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-
- if (errorstate != SD_OK)
- {
- return errorstate;
- }
-
- /* Configure the SD DPSM (Data Path State Machine) */
- sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
- sdio_datainitstructure.DataLength = 64;
- sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
- sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
- SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-
- /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
- sdio_cmdinitstructure.Argument = 0;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STATUS;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS);
-
- if (errorstate != SD_OK)
- {
- return errorstate;
- }
-
- /* Get status data */
- while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
- {
- if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+ /* Abort the SD DMA Tx Stream */
+ if(hsd->hdmatx != NULL)
{
- for (count = 0; count < 8; count++)
- {
- *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance);
- }
-
- pSDstatus += 8;
+ HAL_DMA_Abort(hsd->hdmatx);
+ }
+ /* Abort the SD DMA Rx Stream */
+ if(hsd->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(hsd->hdmarx);
}
}
- if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ hsd->State = HAL_SD_STATE_READY;
+ CardState = HAL_SD_GetCardState(hsd);
+ if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
{
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-
- errorstate = SD_DATA_TIMEOUT;
-
- return errorstate;
+ hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
}
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+ if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
{
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-
- errorstate = SD_DATA_CRC_FAIL;
-
- return errorstate;
+ return HAL_ERROR;
}
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-
- errorstate = SD_RX_OVERRUN;
-
- return errorstate;
- }
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-
- errorstate = SD_START_BIT_ERR;
-
- return errorstate;
- }
- else
- {
- /* No error flag set */
- }
-
- count = SD_DATATIMEOUT;
- while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
- {
- *pSDstatus = SDIO_ReadFIFO(hsd->Instance);
- pSDstatus++;
- count--;
- }
-
- /* Clear all the static status flags*/
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- return errorstate;
+ return HAL_OK;
}
/**
- * @brief Gets the current sd card data status.
- * @param hsd: SD handle
- * @retval Data Transfer state
+ * @brief Abort the current transfer and disable the SD (IT mode).
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * the configuration information for SD module.
+ * @retval HAL status
*/
-HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd)
+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd)
{
- HAL_SD_CardStateTypedef cardstate = SD_CARD_TRANSFER;
-
- /* Get SD card state */
- cardstate = SD_GetState(hsd);
+ HAL_SD_CardStateTypeDef CardState;
+
+ /* DIsable All interrupts */
+ __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
- /* Find SD status according to card state*/
- if (cardstate == SD_CARD_TRANSFER)
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL))
{
- return SD_TRANSFER_OK;
+ /* Disable the SD DMA request */
+ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+ /* Abort the SD DMA Tx Stream */
+ if(hsd->hdmatx != NULL)
+ {
+ hsd->hdmatx->XferAbortCallback = SD_DMATxAbort;
+ if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK)
+ {
+ hsd->hdmatx = NULL;
+ }
+ }
+ /* Abort the SD DMA Rx Stream */
+ if(hsd->hdmarx != NULL)
+ {
+ hsd->hdmarx->XferAbortCallback = SD_DMARxAbort;
+ if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK)
+ {
+ hsd->hdmarx = NULL;
+ }
+ }
}
- else if(cardstate == SD_CARD_ERROR)
+
+ /* No transfer ongoing on both DMA channels*/
+ if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL))
{
- return SD_TRANSFER_ERROR;
+ CardState = HAL_SD_GetCardState(hsd);
+ hsd->State = HAL_SD_STATE_READY;
+ if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ {
+ hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
+ }
+ if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ HAL_SD_AbortCallback(hsd);
+ }
}
- else
- {
- return SD_TRANSFER_BUSY;
- }
+
+ return HAL_OK;
}
/**
- * @brief Gets the SD card status.
- * @param hsd: SD handle
- * @param pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that
- * will contain the SD card status information
- * @retval SD Card error state
- */
-HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
-{
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- uint32_t tmp = 0;
- uint32_t sd_status[16];
-
- errorstate = HAL_SD_SendSDStatus(hsd, sd_status);
-
- if (errorstate != SD_OK)
- {
- return errorstate;
- }
-
- /* Byte 0 */
- tmp = (sd_status[0] & 0xC0) >> 6;
- pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp;
-
- /* Byte 0 */
- tmp = (sd_status[0] & 0x20) >> 5;
- pCardStatus->SECURED_MODE = (uint8_t)tmp;
-
- /* Byte 2 */
- tmp = (sd_status[2] & 0xFF);
- pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8);
-
- /* Byte 3 */
- tmp = (sd_status[3] & 0xFF);
- pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp;
-
- /* Byte 4 */
- tmp = (sd_status[4] & 0xFF);
- pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24);
-
- /* Byte 5 */
- tmp = (sd_status[5] & 0xFF);
- pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16);
-
- /* Byte 6 */
- tmp = (sd_status[6] & 0xFF);
- pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8);
-
- /* Byte 7 */
- tmp = (sd_status[7] & 0xFF);
- pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp;
-
- /* Byte 8 */
- tmp = (sd_status[8] & 0xFF);
- pCardStatus->SPEED_CLASS = (uint8_t)tmp;
-
- /* Byte 9 */
- tmp = (sd_status[9] & 0xFF);
- pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;
-
- /* Byte 10 */
- tmp = (sd_status[10] & 0xF0) >> 4;
- pCardStatus->AU_SIZE = (uint8_t)tmp;
-
- /* Byte 11 */
- tmp = (sd_status[11] & 0xFF);
- pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8);
-
- /* Byte 12 */
- tmp = (sd_status[12] & 0xFF);
- pCardStatus->ERASE_SIZE |= (uint8_t)tmp;
-
- /* Byte 13 */
- tmp = (sd_status[13] & 0xFC) >> 2;
- pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;
-
- /* Byte 13 */
- tmp = (sd_status[13] & 0x3);
- pCardStatus->ERASE_OFFSET = (uint8_t)tmp;
-
- return errorstate;
-}
-
-/**
* @}
*/
@@ -2231,331 +2179,330 @@
* @}
*/
+/* Private function ----------------------------------------------------------*/
/** @addtogroup SD_Private_Functions
* @{
*/
/**
- * @brief SD DMA transfer complete Rx callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief DMA SD transmit process complete callback
+ * @param hdma: DMA handle
* @retval None
*/
-static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)
+static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
- /* DMA transfer is complete */
- hsd->DmaTransferCplt = 1;
+ /* Enable DATAEND Interrupt */
+ __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND));
+}
+
+/**
+ * @brief DMA SD receive process complete callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
- /* Wait until SD transfer is complete */
- while(hsd->SdTransferCplt == 0)
+ /* Send stop command in multiblock write */
+ if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA))
{
+ errorstate = SDMMC_CmdStopTransfer(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= errorstate;
+ HAL_SD_ErrorCallback(hsd);
+ }
}
- /* Transfer complete user callback */
- HAL_SD_DMA_RxCpltCallback(hsd->hdmarx);
+ /* Disable the DMA transfer for transmit request by setting the DMAEN bit
+ in the SD DCTRL register */
+ hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN);
+
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ hsd->State = HAL_SD_STATE_READY;
+
+ HAL_SD_RxCpltCallback(hsd);
}
/**
- * @brief SD DMA transfer Error Rx callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief DMA SD communication error callback
+ * @param hdma: DMA handle
* @retval None
*/
-static void SD_DMA_RxError(DMA_HandleTypeDef *hdma)
+static void SD_DMAError(DMA_HandleTypeDef *hdma)
{
- SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ HAL_SD_CardStateTypeDef CardState;
- /* Transfer complete user callback */
- HAL_SD_DMA_RxErrorCallback(hsd->hdmarx);
-}
-
-/**
- * @brief SD DMA transfer complete Tx callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)
-{
- SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
- /* DMA transfer is complete */
- hsd->DmaTransferCplt = 1;
-
- /* Wait until SD transfer is complete */
- while(hsd->SdTransferCplt == 0)
+ if((hsd->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hsd->hdmatx->ErrorCode == HAL_DMA_ERROR_TE))
{
+ /* Clear All flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ /* Disable All interrupts */
+ __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\
+ SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR);
+
+ hsd->ErrorCode |= HAL_SD_ERROR_DMA;
+ CardState = HAL_SD_GetCardState(hsd);
+ if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ {
+ hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+ }
+
+ hsd->State= HAL_SD_STATE_READY;
+ }
+
+ HAL_SD_ErrorCallback(hsd);
+}
+
+/**
+ * @brief DMA SD Tx Abort callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
+{
+ SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ HAL_SD_CardStateTypeDef CardState;
+
+ if(hsd->hdmatx != NULL)
+ {
+ hsd->hdmatx = NULL;
}
- /* Transfer complete user callback */
- HAL_SD_DMA_TxCpltCallback(hsd->hdmatx);
-}
-
-/**
- * @brief SD DMA transfer Error Tx callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SD_DMA_TxError(DMA_HandleTypeDef *hdma)
-{
- SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* Transfer complete user callback */
- HAL_SD_DMA_TxErrorCallback(hsd->hdmatx);
-}
-
-/**
- * @brief Returns the SD current state.
- * @param hsd: SD handle
- * @retval SD card current state
- */
-static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd)
-{
- uint32_t resp1 = 0;
-
- if (SD_SendStatus(hsd, &resp1) != SD_OK)
+ /* All DMA channels are aborted */
+ if(hsd->hdmarx == NULL)
{
- return SD_CARD_ERROR;
- }
- else
- {
- return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F);
+ CardState = HAL_SD_GetCardState(hsd);
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ hsd->State = HAL_SD_STATE_READY;
+ if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ {
+ hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+
+ if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ {
+ HAL_SD_AbortCallback(hsd);
+ }
+ else
+ {
+ HAL_SD_ErrorCallback(hsd);
+ }
+ }
}
}
/**
- * @brief Initializes all cards or single card as the case may be Card(s) come
- * into standby state.
- * @param hsd: SD handle
+ * @brief DMA SD Rx Abort callback
+ * @param hdma: DMA handle
+ * @retval None
+ */
+static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
+{
+ SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent);
+ HAL_SD_CardStateTypeDef CardState;
+
+ if(hsd->hdmarx != NULL)
+ {
+ hsd->hdmarx = NULL;
+ }
+
+ /* All DMA channels are aborted */
+ if(hsd->hdmatx == NULL)
+ {
+ CardState = HAL_SD_GetCardState(hsd);
+ hsd->ErrorCode = HAL_SD_ERROR_NONE;
+ hsd->State = HAL_SD_STATE_READY;
+ if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+ {
+ hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance);
+
+ if(hsd->ErrorCode != HAL_SD_ERROR_NONE)
+ {
+ HAL_SD_AbortCallback(hsd);
+ }
+ else
+ {
+ HAL_SD_ErrorCallback(hsd);
+ }
+ }
+ }
+}
+
+
+/**
+ * @brief Initializes the sd card.
+ * @param hsd: Pointer to SD handle
* @retval SD Card error state
*/
-static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
+static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
{
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- uint16_t sd_rca = 1;
+ HAL_SD_CardCSDTypeDef CSD;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint16_t sd_rca = 1U;
- if(SDIO_GetPowerState(hsd->Instance) == 0) /* Power off */
+ /* Check the power State */
+ if(SDIO_GetPowerState(hsd->Instance) == 0U)
{
- errorstate = SD_REQUEST_NOT_APPLICABLE;
-
- return errorstate;
+ /* Power off */
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
- if(hsd->CardType != SECURE_DIGITAL_IO_CARD)
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD2 ALL_SEND_CID */
- sdio_cmdinitstructure.Argument = 0;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_ALL_SEND_CID;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_LONG;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp2Error(hsd);
-
- if(errorstate != SD_OK)
+ errorstate = SDMMC_CmdSendCID(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
- /* Get Card identification number data */
- hsd->CID[0] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
- hsd->CID[1] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
- hsd->CID[2] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
- hsd->CID[3] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
+ else
+ {
+ /* Get Card identification number data */
+ hsd->CID[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+ hsd->CID[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
+ hsd->CID[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
+ hsd->CID[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
+ }
}
- if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
- (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD))
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Send CMD3 SET_REL_ADDR with argument 0 */
/* SD Card publishes its RCA. */
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_REL_ADDR;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);
-
- if(errorstate != SD_OK)
+ errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
}
-
- if (hsd->CardType != SECURE_DIGITAL_IO_CARD)
+ if(hsd->SdCard.CardType != CARD_SECURED)
{
/* Get the SD card RCA */
- hsd->RCA = sd_rca;
+ hsd->SdCard.RelCardAdd = sd_rca;
/* Send CMD9 SEND_CSD with argument as card's RCA */
- sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_CSD;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_LONG;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp2Error(hsd);
-
- if(errorstate != SD_OK)
+ errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
-
- /* Get Card Specific Data */
- hsd->CSD[0] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
- hsd->CSD[1] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
- hsd->CSD[2] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
- hsd->CSD[3] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
+ else
+ {
+ /* Get Card Specific Data */
+ hsd->CSD[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+ hsd->CSD[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2);
+ hsd->CSD[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3);
+ hsd->CSD[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4);
+ }
}
- /* All cards are initialized */
- return errorstate;
-}
+ /* Get the Card Class */
+ hsd->SdCard.Class = (SDIO_GetResponse(hsd->Instance, SDIO_RESP2) >> 20U);
+
+ /* Get CSD parameters */
+ HAL_SD_GetCardCSD(hsd, &CSD);
-/**
- * @brief Selects od Deselects the corresponding card.
- * @param hsd: SD handle
- * @param Addr: Address of the card to be selected
- * @retval SD Card error state
- */
-static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t Addr)
-{
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
- HAL_SD_ErrorTypedef errorstate = SD_OK;
-
- /* Send CMD7 SDIO_SEL_DESEL_CARD */
- sdio_cmdinitstructure.Argument = (uint32_t)Addr;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SEL_DESEL_CARD;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);
-
- return errorstate;
+ /* Select the Card */
+ errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return errorstate;
+ }
+
+ /* Configure SDIO peripheral interface */
+ SDIO_Init(hsd->Instance, hsd->Init);
+
+ /* All cards are initialized */
+ return HAL_SD_ERROR_NONE;
}
/**
* @brief Enquires cards about their operating voltage and configures clock
* controls and stores SD information that will be needed in future
* in the SD handle.
- * @param hsd: SD handle
- * @retval SD Card error state
+ * @param hsd: Pointer to SD handle
+ * @retval error state
*/
-static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
+static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
{
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
- __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
- uint32_t response = 0, count = 0, validvoltage = 0;
- uint32_t sdtype = SD_STD_CAPACITY;
+ __IO uint32_t count = 0U;
+ uint32_t response = 0U, validvoltage = 0U;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
- /* Power ON Sequence -------------------------------------------------------*/
- /* Disable SDIO Clock */
- __HAL_SD_SDIO_DISABLE(hsd);
-
- /* Set Power State to ON */
- SDIO_PowerState_ON(hsd->Instance);
-
- /* 1ms: required power up waiting time before starting the SD initialization
- sequence */
- HAL_Delay(1);
-
- /* Enable SDIO Clock */
- __HAL_SD_SDIO_ENABLE(hsd);
-
- /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/
- /* No CMD response required */
- sdio_cmdinitstructure.Argument = 0;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_GO_IDLE_STATE;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_NO;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdError(hsd);
-
- if(errorstate != SD_OK)
+ /* CMD0: GO_IDLE_STATE */
+ errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
{
- /* CMD Response TimeOut (wait for CMDSENT flag) */
return errorstate;
}
- /* CMD8: SEND_IF_COND ------------------------------------------------------*/
- /* Send CMD8 to verify SD card interface operating condition */
- /* Argument: - [31:12]: Reserved (shall be set to '0')
- - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
- - [7:0]: Check Pattern (recommended 0xAA) */
- /* CMD Response: R7 */
- sdio_cmdinitstructure.Argument = SD_CHECK_PATTERN;
- sdio_cmdinitstructure.CmdIndex = SD_SDIO_SEND_IF_COND;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp7Error(hsd);
-
- if (errorstate == SD_OK)
+ /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
+ errorstate = SDMMC_CmdOperCond(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
{
- /* SD Card 2.0 */
- hsd->CardType = STD_CAPACITY_SD_CARD_V2_0;
- sdtype = SD_HIGH_CAPACITY;
- }
-
- /* Send CMD55 */
- sdio_cmdinitstructure.Argument = 0;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-
- /* If errorstate is Command TimeOut, it is a MMC card */
- /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
- or SD card 1.x */
- if(errorstate == SD_OK)
- {
- /* SD CARD */
+ hsd->SdCard.CardVersion = CARD_V1_X;
+
/* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
- while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
+ while(validvoltage == 0U)
{
+ if(count++ == SDMMC_MAX_VOLT_TRIAL)
+ {
+ return HAL_SD_ERROR_INVALID_VOLTRANGE;
+ }
/* SEND CMD55 APP_CMD with RCA as 0 */
- sdio_cmdinitstructure.Argument = 0;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0U);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ }
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
+ /* Send CMD41 */
+ errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_STD_CAPACITY);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+ }
- if(errorstate != SD_OK)
+ /* Get command response */
+ response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
+
+ /* Get operating voltage*/
+ validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
+ }
+ /* Card type is SDSC */
+ hsd->SdCard.CardType = CARD_SDSC;
+ }
+ else
+ {
+ hsd->SdCard.CardVersion = CARD_V2_X;
+
+ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
+ while(validvoltage == 0U)
+ {
+ if(count++ == SDMMC_MAX_VOLT_TRIAL)
+ {
+ return HAL_SD_ERROR_INVALID_VOLTRANGE;
+ }
+
+ /* SEND CMD55 APP_CMD with RCA as 0 */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0U);
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send CMD41 */
- sdio_cmdinitstructure.Argument = SD_VOLTAGE_WINDOW_SD | sdtype;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_OP_COND;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp3Error(hsd);
-
- if(errorstate != SD_OK)
+ errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_HIGH_CAPACITY);
+ if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
@@ -2564,74 +2511,156 @@
response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
/* Get operating voltage*/
- validvoltage = (((response >> 31) == 1) ? 1 : 0);
-
- count++;
+ validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
}
- if(count >= SD_MAX_VOLT_TRIAL)
+ if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
{
- errorstate = SD_INVALID_VOLTRANGE;
-
- return errorstate;
+ hsd->SdCard.CardType = CARD_SDHC_SDXC;
}
-
- if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+ else
{
- hsd->CardType = HIGH_CAPACITY_SD_CARD;
+ hsd->SdCard.CardType = CARD_SDSC;
}
-
- } /* else MMC Card */
+ }
- return errorstate;
+ return HAL_SD_ERROR_NONE;
}
/**
* @brief Turns the SDIO output signals off.
- * @param hsd: SD handle
- * @retval SD Card error state
+ * @param hsd: Pointer to SD handle
+ * @retval HAL status
*/
-static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)
+static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd)
{
- HAL_SD_ErrorTypedef errorstate = SD_OK;
-
/* Set Power State to OFF */
SDIO_PowerState_OFF(hsd->Instance);
- return errorstate;
+ return HAL_OK;
+}
+
+/**
+ * @brief Send Status info command.
+ * @param hsd: pointer to SD handle
+ * @param pSDstatus: Pointer to the buffer that will contain the SD card status
+ * SD Status register)
+ * @retval error state
+ */
+static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
+{
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count = 0U;
+
+ /* Check SD response */
+ if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
+ {
+ return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
+ }
+
+ /* Set block size for card if it is not equal to current block size for card */
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+ return errorstate;
+ }
+
+ /* Send CMD55 */
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+ return errorstate;
+ }
+
+ /* Configure the SD DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = 64U;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
+
+ /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */
+ errorstate = SDMMC_CmdStatusRegister(hsd->Instance);
+ if(errorstate != HAL_SD_ERROR_NONE)
+ {
+ hsd->ErrorCode |= HAL_SD_ERROR_NONE;
+ return errorstate;
+ }
+
+ /* Get status data */
+ while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
+ {
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
+ {
+ for(count = 0U; count < 8U; count++)
+ {
+ *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance);
+ }
+
+ pSDstatus += 8U;
+ }
+
+ if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ return HAL_SD_ERROR_TIMEOUT;
+ }
+ }
+
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ {
+ return HAL_SD_ERROR_DATA_TIMEOUT;
+ }
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+ {
+ return HAL_SD_ERROR_DATA_CRC_FAIL;
+ }
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+ {
+ return HAL_SD_ERROR_RX_OVERRUN;
+ }
+
+ while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)))
+ {
+ *pSDstatus = SDIO_ReadFIFO(hsd->Instance);
+ pSDstatus++;
+
+ if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ return HAL_SD_ERROR_TIMEOUT;
+ }
+ }
+
+ /* Clear all the static status flags*/
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ return HAL_SD_ERROR_NONE;
}
/**
* @brief Returns the current card's status.
- * @param hsd: SD handle
+ * @param hsd: Pointer to SD handle
* @param pCardStatus: pointer to the buffer that will contain the SD card
* status (Card Status register)
- * @retval SD Card error state
+ * @retval error state
*/
-static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
+static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
{
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
- HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
if(pCardStatus == NULL)
{
- errorstate = SD_INVALID_PARAMETER;
-
- return errorstate;
+ return HAL_SD_ERROR_PARAM;
}
/* Send Status command */
- sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);
-
- if(errorstate != SD_OK)
+ errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if(errorstate != HAL_OK)
{
return errorstate;
}
@@ -2639,810 +2668,247 @@
/* Get SD card status */
*pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
- return errorstate;
-}
-
-/**
- * @brief Checks for error conditions for CMD0.
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)
-{
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- uint32_t timeout = SDIO_CMD0TIMEOUT, tmp;
-
- tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT);
-
- while((timeout > 0) && (!tmp))
- {
- tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT);
- timeout--;
- }
-
- if(timeout == 0)
- {
- errorstate = SD_CMD_RSP_TIMEOUT;
- return errorstate;
- }
-
- /* Clear all the static flags */
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- return errorstate;
-}
-
-/**
- * @brief Checks for error conditions for R7 response.
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)
-{
- HAL_SD_ErrorTypedef errorstate = SD_ERROR;
- uint32_t timeout = SDIO_CMD0TIMEOUT, tmp;
-
- tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT);
-
- while((!tmp) && (timeout > 0))
- {
- tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT);
- timeout--;
- }
-
- tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-
- if((timeout == 0) || tmp)
- {
- /* Card is not V2.0 compliant or card does not support the set voltage range */
- errorstate = SD_CMD_RSP_TIMEOUT;
-
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-
- return errorstate;
- }
-
- if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDREND))
- {
- /* Card is SD V2.0 compliant */
- errorstate = SD_OK;
-
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CMDREND);
-
- return errorstate;
- }
-
- return errorstate;
-}
-
-/**
- * @brief Checks for error conditions for R1 response.
- * @param hsd: SD handle
- * @param SD_CMD: The sent command index
- * @retval SD Card error state
- */
-static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD)
-{
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- uint32_t response_r1 = 0;
-
- while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
- {
- }
-
- if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
- {
- errorstate = SD_CMD_RSP_TIMEOUT;
-
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-
- return errorstate;
- }
- else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
- {
- errorstate = SD_CMD_CRC_FAIL;
-
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-
- return errorstate;
- }
- else
- {
- /* No error flag set */
- }
-
- /* Check response received is of desired command */
- if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
- {
- errorstate = SD_ILLEGAL_CMD;
-
- return errorstate;
- }
-
- /* Clear all the static flags */
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- /* We have received response, retrieve it for analysis */
- response_r1 = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
-
- if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
- {
- return errorstate;
- }
-
- if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
- {
- return(SD_ADDR_OUT_OF_RANGE);
- }
-
- if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
- {
- return(SD_ADDR_MISALIGNED);
- }
-
- if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
- {
- return(SD_BLOCK_LEN_ERR);
- }
-
- if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
- {
- return(SD_ERASE_SEQ_ERR);
- }
-
- if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
- {
- return(SD_BAD_ERASE_PARAM);
- }
-
- if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
- {
- return(SD_WRITE_PROT_VIOLATION);
- }
-
- if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
- {
- return(SD_LOCK_UNLOCK_FAILED);
- }
-
- if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
- {
- return(SD_COM_CRC_FAILED);
- }
-
- if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
- {
- return(SD_ILLEGAL_CMD);
- }
-
- if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
- {
- return(SD_CARD_ECC_FAILED);
- }
-
- if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
- {
- return(SD_CC_ERROR);
- }
-
- if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
- {
- return(SD_GENERAL_UNKNOWN_ERROR);
- }
-
- if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
- {
- return(SD_STREAM_READ_UNDERRUN);
- }
-
- if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
- {
- return(SD_STREAM_WRITE_OVERRUN);
- }
-
- if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
- {
- return(SD_CID_CSD_OVERWRITE);
- }
-
- if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
- {
- return(SD_WP_ERASE_SKIP);
- }
-
- if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
- {
- return(SD_CARD_ECC_DISABLED);
- }
-
- if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
- {
- return(SD_ERASE_RESET);
- }
-
- if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
- {
- return(SD_AKE_SEQ_ERROR);
- }
-
- return errorstate;
-}
-
-/**
- * @brief Checks for error conditions for R3 (OCR) response.
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)
-{
- HAL_SD_ErrorTypedef errorstate = SD_OK;
-
- while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
- {
- }
-
- if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
- {
- errorstate = SD_CMD_RSP_TIMEOUT;
-
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-
- return errorstate;
- }
-
- /* Clear all the static flags */
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- return errorstate;
-}
-
-/**
- * @brief Checks for error conditions for R2 (CID or CSD) response.
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)
-{
- HAL_SD_ErrorTypedef errorstate = SD_OK;
-
- while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
- {
- }
-
- if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
- {
- errorstate = SD_CMD_RSP_TIMEOUT;
-
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-
- return errorstate;
- }
- else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
- {
- errorstate = SD_CMD_CRC_FAIL;
-
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-
- return errorstate;
- }
- else
- {
- /* No error flag set */
- }
-
- /* Clear all the static flags */
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- return errorstate;
-}
-
-/**
- * @brief Checks for error conditions for R6 (RCA) response.
- * @param hsd: SD handle
- * @param SD_CMD: The sent command index
- * @param pRCA: Pointer to the variable that will contain the SD card relative
- * address RCA
- * @retval SD Card error state
- */
-static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
-{
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- uint32_t response_r1 = 0;
-
- while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
- {
- }
-
- if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
- {
- errorstate = SD_CMD_RSP_TIMEOUT;
-
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-
- return errorstate;
- }
- else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
- {
- errorstate = SD_CMD_CRC_FAIL;
-
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-
- return errorstate;
- }
- else
- {
- /* No error flag set */
- }
-
- /* Check response received is of desired command */
- if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
- {
- errorstate = SD_ILLEGAL_CMD;
-
- return errorstate;
- }
-
- /* Clear all the static flags */
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- /* We have received response, retrieve it. */
- response_r1 = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
-
- if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)
- {
- *pRCA = (uint16_t) (response_r1 >> 16);
-
- return errorstate;
- }
-
- if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)
- {
- return(SD_GENERAL_UNKNOWN_ERROR);
- }
-
- if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)
- {
- return(SD_ILLEGAL_CMD);
- }
-
- if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)
- {
- return(SD_COM_CRC_FAILED);
- }
-
- return errorstate;
+ return HAL_SD_ERROR_NONE;
}
/**
* @brief Enables the SDIO wide bus mode.
- * @param hsd: SD handle
- * @retval SD Card error state
+ * @param hsd: pointer to SD handle
+ * @retval error state
*/
-static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)
+static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
{
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
- HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t scr[2U] = {0U, 0U};
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
- uint32_t scr[2] = {0, 0};
-
- if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
+ if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
- errorstate = SD_LOCK_UNLOCK_FAILED;
-
- return errorstate;
+ return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
-
- if(errorstate != SD_OK)
+ if(errorstate != HAL_OK)
{
return errorstate;
}
/* If requested card supports wide bus operation */
- if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
+ if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA.*/
- sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
- sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-
- if(errorstate != SD_OK)
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if(errorstate != HAL_OK)
{
return errorstate;
}
/* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
- sdio_cmdinitstructure.Argument = 2;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
-
- if(errorstate != SD_OK)
+ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);
+ if(errorstate != HAL_OK)
{
return errorstate;
}
-
- return errorstate;
+
+ return HAL_SD_ERROR_NONE;
}
else
{
- errorstate = SD_REQUEST_NOT_APPLICABLE;
-
- return errorstate;
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
-}
+}
/**
* @brief Disables the SDIO wide bus mode.
- * @param hsd: SD handle
- * @retval SD Card error state
+ * @param hsd: Pointer to SD handle
+ * @retval error state
*/
-static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)
+static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
{
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
- HAL_SD_ErrorTypedef errorstate = SD_OK;
+ uint32_t scr[2U] = {0U, 0U};
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
- uint32_t scr[2] = {0, 0};
-
- if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
+ if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)
{
- errorstate = SD_LOCK_UNLOCK_FAILED;
-
- return errorstate;
+ return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;
}
/* Get SCR Register */
errorstate = SD_FindSCR(hsd, scr);
-
- if(errorstate != SD_OK)
+ if(errorstate != HAL_OK)
{
return errorstate;
}
/* If requested card supports 1 bit mode operation */
- if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
+ if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO)
{
/* Send CMD55 APP_CMD with argument as card's RCA */
- sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
- sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-
- if(errorstate != SD_OK)
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));
+ if(errorstate != HAL_OK)
{
return errorstate;
}
/* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
- sdio_cmdinitstructure.Argument = 0;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
-
- if(errorstate != SD_OK)
+ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U);
+ if(errorstate != HAL_OK)
{
return errorstate;
}
- return errorstate;
+ return HAL_SD_ERROR_NONE;
}
else
{
- errorstate = SD_REQUEST_NOT_APPLICABLE;
-
- return errorstate;
+ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
}
/**
* @brief Finds the SD card SCR register value.
- * @param hsd: SD handle
+ * @param hsd: Pointer to SD handle
* @param pSCR: pointer to the buffer that will contain the SCR value
- * @retval SD Card error state
+ * @retval error state
*/
-static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
+static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
{
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
- SDIO_DataInitTypeDef sdio_datainitstructure = {0};
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- uint32_t index = 0;
- uint32_t tempscr[2] = {0, 0};
+ SDIO_DataInitTypeDef config;
+ uint32_t errorstate = HAL_SD_ERROR_NONE;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t index = 0U;
+ uint32_t tempscr[2U] = {0U, 0U};
/* Set Block Size To 8 Bytes */
- /* Send CMD55 APP_CMD with argument as card's RCA */
- sdio_cmdinitstructure.Argument = (uint32_t)8;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
- if(errorstate != SD_OK)
+ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U);
+ if(errorstate != HAL_OK)
{
return errorstate;
}
-
+
/* Send CMD55 APP_CMD with argument as card's RCA */
- sdio_cmdinitstructure.Argument = (uint32_t)((hsd->RCA) << 16);
- sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-
- if(errorstate != SD_OK)
+ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_OK)
{
return errorstate;
}
- sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT;
- sdio_datainitstructure.DataLength = 8;
- sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
- sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
- sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
- sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE;
- SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
+
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = 8U;
+ config.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
+ config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO;
+ config.TransferMode = SDIO_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDIO_DPSM_ENABLE;
+ SDIO_ConfigData(hsd->Instance, &config);
/* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
- sdio_cmdinitstructure.Argument = 0;
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_SEND_SCR;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- /* Check for error conditions */
- errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);
-
- if(errorstate != SD_OK)
+ errorstate = SDMMC_CmdSendSCR(hsd->Instance);
+ if(errorstate != HAL_OK)
{
return errorstate;
}
- while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
+ while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND))
{
- if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
{
*(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
index++;
}
+
+ if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
+ {
+ return HAL_SD_ERROR_TIMEOUT;
+ }
}
- if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
+ if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
{
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
- errorstate = SD_DATA_TIMEOUT;
-
- return errorstate;
+ return HAL_SD_ERROR_DATA_TIMEOUT;
}
- else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
{
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
- errorstate = SD_DATA_CRC_FAIL;
-
- return errorstate;
+ return HAL_SD_ERROR_DATA_CRC_FAIL;
}
- else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
+ else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
{
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
- errorstate = SD_RX_OVERRUN;
-
- return errorstate;
- }
- else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
- {
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-
- errorstate = SD_START_BIT_ERR;
-
- return errorstate;
+ return HAL_SD_ERROR_RX_OVERRUN;
}
else
{
/* No error flag set */
+ /* Clear all the static flags */
+ __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+
+ *(pSCR + 1U) = ((tempscr[0U] & SDMMC_0TO7BITS) << 24U) | ((tempscr[0U] & SDMMC_8TO15BITS) << 8U) |\
+ ((tempscr[0U] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[0U] & SDMMC_24TO31BITS) >> 24U);
+
+ *(pSCR) = ((tempscr[1U] & SDMMC_0TO7BITS) << 24U) | ((tempscr[1U] & SDMMC_8TO15BITS) << 8U) |\
+ ((tempscr[1U] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[1U] & SDMMC_24TO31BITS) >> 24U);
}
-
- /* Clear all the static flags */
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
- *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) |\
- ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);
-
- *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) |\
- ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);
-
- return errorstate;
+
+ return HAL_SD_ERROR_NONE;
}
/**
- * @brief Checks if the SD card is in programming state.
- * @param hsd: SD handle
- * @param pStatus: pointer to the variable that will contain the SD card state
- * @retval SD Card error state
+ * @brief Wrap up reading in non-blocking mode.
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * the configuration information.
+ * @retval HAL status
*/
-static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus)
+static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd)
{
- SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0};
- HAL_SD_ErrorTypedef errorstate = SD_OK;
- __IO uint32_t responseR1 = 0;
+ uint32_t count = 0U;
+ uint32_t* tmp;
+
+ tmp = (uint32_t*)hsd->pRxBuffPtr;
- sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16);
- sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS;
- sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT;
- sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
- sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE;
- SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
- while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
+ /* Read data from SDIO Rx FIFO */
+ for(count = 0U; count < 8U; count++)
{
+ *(tmp + count) = SDIO_ReadFIFO(hsd->Instance);
}
- if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
+ hsd->pRxBuffPtr += 8U;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Wrap up writing in non-blocking mode.
+ * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * the configuration information.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd)
+{
+ uint32_t count = 0U;
+ uint32_t* tmp;
+
+ tmp = (uint32_t*)hsd->pTxBuffPtr;
+
+ /* Write data to SDIO Tx FIFO */
+ for(count = 0U; count < 8U; count++)
{
- errorstate = SD_CMD_RSP_TIMEOUT;
-
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-
- return errorstate;
- }
- else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
- {
- errorstate = SD_CMD_CRC_FAIL;
-
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-
- return errorstate;
- }
- else
- {
- /* No error flag set */
+ SDIO_WriteFIFO(hsd->Instance, (tmp + count));
}
- /* Check response received is of desired command */
- if((uint32_t)SDIO_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS)
- {
- errorstate = SD_ILLEGAL_CMD;
-
- return errorstate;
- }
+ hsd->pTxBuffPtr += 8U;
- /* Clear all the static flags */
- __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-
-
- /* We have received response, retrieve it for analysis */
- responseR1 = SDIO_GetResponse(hsd->Instance, SDIO_RESP1);
-
- /* Find out card status */
- *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F);
-
- if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
- {
- return errorstate;
- }
-
- if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
- {
- return(SD_ADDR_OUT_OF_RANGE);
- }
-
- if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
- {
- return(SD_ADDR_MISALIGNED);
- }
-
- if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
- {
- return(SD_BLOCK_LEN_ERR);
- }
-
- if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
- {
- return(SD_ERASE_SEQ_ERR);
- }
-
- if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
- {
- return(SD_BAD_ERASE_PARAM);
- }
-
- if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
- {
- return(SD_WRITE_PROT_VIOLATION);
- }
-
- if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
- {
- return(SD_LOCK_UNLOCK_FAILED);
- }
-
- if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
- {
- return(SD_COM_CRC_FAILED);
- }
-
- if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
- {
- return(SD_ILLEGAL_CMD);
- }
-
- if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
- {
- return(SD_CARD_ECC_FAILED);
- }
-
- if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
- {
- return(SD_CC_ERROR);
- }
-
- if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
- {
- return(SD_GENERAL_UNKNOWN_ERROR);
- }
-
- if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
- {
- return(SD_STREAM_READ_UNDERRUN);
- }
-
- if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
- {
- return(SD_STREAM_WRITE_OVERRUN);
- }
-
- if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE)
- {
- return(SD_CID_CSD_OVERWRITE);
- }
-
- if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
- {
- return(SD_WP_ERASE_SKIP);
- }
-
- if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
- {
- return(SD_CARD_ECC_DISABLED);
- }
-
- if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
- {
- return(SD_ERASE_RESET);
- }
-
- if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
- {
- return(SD_AKE_SEQ_ERROR);
- }
-
- return errorstate;
-}
+ return HAL_OK;
+}
/**
* @}
*/
-
+
#endif /* STM32F103xE || STM32F103xG */
#endif /* HAL_SD_MODULE_ENABLED */
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_smartcard.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_smartcard.c
index 315580e..6a366eb 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_smartcard.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_smartcard.c
@@ -2,16 +2,15 @@
******************************************************************************
* @file stm32f1xx_hal_smartcard.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral State and Errors functions
* + Peripheral Control functions
- *
+ * + Peripheral State and Errors functions
@verbatim
==============================================================================
##### How to use this driver #####
@@ -21,10 +20,10 @@
(#) Declare a SMARTCARD_HandleTypeDef handle structure.
(#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
- (##) Enable the interface clock of the USARTx associated to the SMARTCARD.
+ (##) Enable the USARTx interface clock.
(##) SMARTCARD pins configuration:
(+++) Enable the clock for the SMARTCARD GPIOs.
- (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+ (+++) Configure the SMARTCARD pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
and HAL_SMARTCARD_Receive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
@@ -35,75 +34,84 @@
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initilalized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+ (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
(+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
(used for last byte sending completion detection in DMA non circular mode)
- (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.
(#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
- (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_SMARTCARD_MspInit(&hsc) API.
-
- -@@- The specific SMARTCARD interrupts (Transmission complete interrupt,
- RXNE interrupt and Error Interrupts) will be managed using the macros
- __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
-
- (#) Three operation modes are available within this driver :
-
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
- (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT()
- (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT()
- (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
- (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
-
- *** DMA mode IO operation ***
- ==============================
+ (++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+ by calling the customized HAL_SMARTCARD_MspInit() API.
[..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
- (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
- (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
- (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
+ (@)The specific SMARTCARD interrupts (Transmission complete interrupt,
+ RXNE interrupt and Error Interrupts) will be managed using the macros
+ __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
- *** SMARTCARD HAL driver macros list ***
- ========================================
[..]
- Below the list of most used macros in SMARTCARD HAL driver.
-
- (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
- (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
- (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
- (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
- (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
- (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
- (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether the specified SMARTCARD interrupt has occurred or not
-
- [..]
- (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+ Three operation modes are available within this driver:
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
+ (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
+
+ *** DMA mode IO operation ***
+ ==============================
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+ (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+ (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback
+ (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
+
+ *** SMARTCARD HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in SMARTCARD HAL driver.
+
+ (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral
+ (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral
+ (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
+ (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+ (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+ (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
+
+ [..]
+ (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+
@endverbatim
+ [..]
+ (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ the possible SMARTCARD frame formats are as listed in the following table:
+ +-------------------------------------------------------------+
+ | M bit | PCE bit | SMARTCARD frame |
+ |---------------------|---------------------------------------|
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ +-------------------------------------------------------------+
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -141,42 +149,50 @@
* @brief HAL SMARTCARD module driver
* @{
*/
-
#ifdef HAL_SMARTCARD_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macros --------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+/** @addtogroup SMARTCARD_Private_Constants
* @{
*/
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
-static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
/**
* @}
*/
-
-/* Exported functions ---------------------------------------------------------*/
-
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Functions
+ * @{
+ */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc);
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc);
+static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+/**
+ * @}
+ */
+/* Exported functions --------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
* @{
*/
-/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
-
==============================================================================
- ##### Initialization and Configuration functions #####
+ ##### Initialization and Configuration functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USART
@@ -193,7 +209,7 @@
(++) Baud Rate
(++) Word Length => Should be 9 bits (8 bits + parity)
(++) Stop Bit
- (++) Parity: => Should be enabled
+ (++) Parity: => Should be enabled
(++) USART polarity
(++) USART phase
(++) USART LastBit
@@ -211,32 +227,23 @@
[..]
Please refer to the ISO 7816-3 specification for more details.
- (@) It is also possible to choose 0.5 stop bit for receiving but it is recommended
- to use 1.5 stop bits for both transmitting and receiving to avoid switching
- between the two configurations.
[..]
- The HAL_SMARTCARD_Init() function follows the USART SmartCard configuration
- procedure (details for the procedure are available in reference manuals
- (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)).
+ (@) It is also possible to choose 0.5 stop bit for receiving but it is recommended
+ to use 1.5 stop bits for both transmitting and receiving to avoid switching
+ between the two configurations.
+ [..]
+ The HAL_SMARTCARD_Init() function follows the USART SmartCard configuration
+ procedure (details for the procedure are available in reference manual (RM0329)).
@endverbatim
* @{
*/
-/*
- Additionnal remark on the smartcard frame:
- +-------------------------------------------------------------+
- | M bit | PCE bit | SMARTCARD frame |
- |---------------------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
-*/
-
/**
- * @brief Initializes the SmartCard mode according to the specified
- * parameters in the SMARTCARD_HandleTypeDef and create the associated handle.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @brief Initializes the SmartCard mode according to the specified
+ * parameters in the SMARTCARD_InitTypeDef and create the associated handle.
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
@@ -247,38 +254,26 @@
return HAL_ERROR;
}
- /* Check Wordlength, Parity and Stop bits parameters */
- if ( (!(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength)))
- ||(!(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits)))
- ||(!(IS_SMARTCARD_PARITY(hsc->Init.Parity))) )
- {
- return HAL_ERROR;
- }
-
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
- assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
- assert_param(IS_SMARTCARD_PRESCALER(hsc->Init.Prescaler));
- if(hsc->State == HAL_SMARTCARD_STATE_RESET)
+
+ if(hsc->gState == HAL_SMARTCARD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsc->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_SMARTCARD_MspInit(hsc);
}
-
- hsc->State = HAL_SMARTCARD_STATE_BUSY;
- /* Disable the Peripheral */
- __HAL_SMARTCARD_DISABLE(hsc);
-
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY;
+
/* Set the Prescaler */
MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler);
/* Set the Guard Time */
- MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8));
+ MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8U));
/* Set the Smartcard Communication parameters */
SMARTCARD_SetConfig(hsc);
@@ -289,26 +284,33 @@
CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN);
CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
- /* Enable the Peripharal */
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the SMARTCARD Framing Error Interrupt */
+ SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the Peripheral */
__HAL_SMARTCARD_ENABLE(hsc);
/* Configure the Smartcard NACK state */
MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState);
/* Enable the SC mode by setting the SCEN bit in the CR3 register */
- SET_BIT(hsc->Instance->CR3, USART_CR3_SCEN);
+ hsc->Instance->CR3 |= (USART_CR3_SCEN);
/* Initialize the SMARTCARD state*/
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->State= HAL_SMARTCARD_STATE_READY;
+ hsc->gState= HAL_SMARTCARD_STATE_READY;
+ hsc->RxState= HAL_SMARTCARD_STATE_READY;
return HAL_OK;
}
/**
- * @brief DeInitializes the SMARTCARD peripheral
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @brief DeInitializes the USART SmartCard peripheral
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
@@ -322,22 +324,14 @@
/* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
- hsc->State = HAL_SMARTCARD_STATE_BUSY;
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY;
- /* Disable the Peripheral */
- __HAL_SMARTCARD_DISABLE(hsc);
-
- hsc->Instance->CR1 = 0x0;
- hsc->Instance->CR2 = 0x0;
- hsc->Instance->CR3 = 0x0;
- hsc->Instance->BRR = 0x0;
- hsc->Instance->GTPR = 0x0;
-
/* DeInit the low level hardware */
HAL_SMARTCARD_MspDeInit(hsc);
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- hsc->State = HAL_SMARTCARD_STATE_RESET;
+ hsc->gState = HAL_SMARTCARD_STATE_RESET;
+ hsc->RxState = HAL_SMARTCARD_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hsc);
@@ -346,33 +340,33 @@
}
/**
- * @brief SMARTCARD MSP Init.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @brief SMARTCARD MSP Init.
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
+__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspInit can be implemented in the user file
- */
+ the HAL_SMARTCARD_MspInit could be implemented in the user file
+ */
}
/**
- * @brief SMARTCARD MSP DeInit.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @brief SMARTCARD MSP DeInit
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
+__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_MspDeInit can be implemented in the user file
- */
+ the HAL_SMARTCARD_MspDeInit could be implemented in the user file
+ */
}
/**
@@ -383,33 +377,32 @@
* @brief SMARTCARD Transmit and Receive functions
*
@verbatim
- ==============================================================================
- ##### IO operation functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+ ===============================================================================
+ ##### IO operation functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
- [..]
+ [..]
(#) Smartcard is a single wire half duplex communication protocol.
The Smartcard interface is designed to support asynchronous protocol Smartcards as
defined in the ISO 7816-3 standard.
(#) The USART should be configured as:
- (++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
- (++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+ (++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+ (++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
(#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
- or DMA, the relevant API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
- using DMA mode.
- The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
- will be executed respectively at the end of the Transmit or Receive process
- The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
- error is detected.
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) Non Blocking mode: The communication is performed using Interrupts
+ or DMA, These APIs return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
+ using DMA mode.
+ The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+ will be executed respectively at the end of the Transmit or Receive process
+ The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected
(#) Blocking mode APIs are :
(++) HAL_SMARTCARD_Transmit()
@@ -434,22 +427,22 @@
*/
/**
- * @brief Sends an amount of data in blocking mode.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Specify timeout value
+ * @brief Send an amount of data in blocking mode
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tmp_state = 0;
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
- tmp_state = hsc->State;
- if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_RX))
+ if(hsc->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -458,42 +451,33 @@
__HAL_LOCK(hsc);
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- /* Check if a non-blocking receive process is ongoing or not */
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
- }
- else
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
- }
-
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
+
hsc->TxXferSize = Size;
hsc->TxXferCount = Size;
- while(hsc->TxXferCount > 0)
+ while(hsc->TxXferCount > 0U)
{
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ hsc->TxXferCount--;
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- WRITE_REG(hsc->Instance->DR, (*pData++ & (uint8_t)0xFF));
- hsc->TxXferCount--;
+ tmp = (uint16_t*) pData;
+ hsc->Instance->DR = (*tmp & (uint16_t)0x01FF);
+ pData +=1U;
}
-
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
+
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- /* Check if a non-blocking receive process is ongoing or not */
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
- }
- else
- {
- hsc->State = HAL_SMARTCARD_STATE_READY;
- }
+ /* At end of Tx process, restore hsc->gState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hsc);
@@ -506,22 +490,22 @@
}
/**
- * @brief Receive an amount of data in blocking mode.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @param Timeout: Specify timeout value
+ * @brief Receive an amount of data in blocking mode
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- uint32_t tmp_state = 0;
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
- tmp_state = hsc->State;
- if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX))
+ if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -530,40 +514,30 @@
__HAL_LOCK(hsc);
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
- /* Check if a non-blocking transmit process is ongoing or not */
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
- }
- else
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
- }
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
hsc->RxXferSize = Size;
hsc->RxXferCount = Size;
+
/* Check the remain data to be received */
- while(hsc->RxXferCount > 0)
+ while(hsc->RxXferCount > 0U)
{
- if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ hsc->RxXferCount--;
+ if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
- hsc->RxXferCount--;
+ tmp = (uint16_t*) pData;
+ *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
+ pData +=1U;
}
- /* Check if a non-blocking transmit process is ongoing or not */
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
- }
- else
- {
- hsc->State = HAL_SMARTCARD_STATE_READY;
- }
-
+ /* At end of Rx process, restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(hsc);
@@ -576,25 +550,22 @@
}
/**
- * @brief Sends an amount of data in non-blocking mode.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
+ * @brief Send an amount of data in non blocking mode
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
- uint32_t tmp_state = 0;
-
- tmp_state = hsc->State;
- if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_RX))
+ /* Check that a Tx process is not already ongoing */
+ if(hsc->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
-
/* Process Locked */
__HAL_LOCK(hsc);
@@ -603,24 +574,19 @@
hsc->TxXferCount = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- /* Check if a non-blocking receive process is ongoing or not */
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
- }
- else
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
- }
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
/* Process Unlocked */
__HAL_UNLOCK(hsc);
+
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
- /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
/* Enable the SMARTCARD Transmit data register empty Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE);
+ SET_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
return HAL_OK;
}
@@ -631,21 +597,19 @@
}
/**
- * @brief Receives an amount of data in non-blocking mode.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
+ * @brief Receive an amount of data in non blocking mode
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
- uint32_t tmp_state = 0;
-
- tmp_state = hsc->State;
- if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX))
+ /* Check that a Rx process is not already ongoing */
+ if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -658,27 +622,16 @@
hsc->RxXferCount = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- /* Check if a non-blocking transmit process is ongoing or not */
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
- }
- else
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
- }
-
+ hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
+
/* Process Unlocked */
__HAL_UNLOCK(hsc);
- /* Enable the SMARTCARD Data Register not empty Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE);
-
- /* Enable the SMARTCARD Parity Error Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
+ /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */
+ SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE);
/* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
+ SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
return HAL_OK;
}
@@ -689,22 +642,21 @@
}
/**
- * @brief Sends an amount of data in non-blocking mode.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
+ * @brief Send an amount of data in non blocking mode
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
- uint32_t *tmp = 0;
- uint32_t tmp_state = 0;
+ uint32_t *tmp;
- tmp_state = hsc->State;
- if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_RX))
+ /* Check that a Tx process is not already ongoing */
+ if(hsc->gState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -717,15 +669,7 @@
hsc->TxXferCount = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- /* Check if a non-blocking receive process is ongoing or not */
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
- }
- else
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
- }
+ hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX;
/* Set the SMARTCARD DMA transfer complete callback */
hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
@@ -733,20 +677,23 @@
/* Set the DMA error callback */
hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
- /* Enable the SMARTCARD transmit DMA channel */
+ /* Set the DMA abort callback */
+ hsc->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the SMARTCARD transmit DMA Channel */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
- /* Clear the TC flag in the SR register by writing 0 to it */
+ /* Clear the TC flag in the SR register by writing 0 to it */
__HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC);
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the SMARTCARD CR3 register */
- SET_BIT(hsc->Instance->CR3,USART_CR3_DMAT);
-
/* Process Unlocked */
__HAL_UNLOCK(hsc);
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the SMARTCARD CR3 register */
+ SET_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
return HAL_OK;
}
else
@@ -756,23 +703,22 @@
}
/**
- * @brief Receive an amount of data in non-blocking mode.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.
+ * @brief Receive an amount of data in non blocking mode
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
+ * @param pData: pointer to data buffer
+ * @param Size: amount of data to be received
+ * @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
{
- uint32_t *tmp = 0;
- uint32_t tmp_state = 0;
+ uint32_t *tmp;
- tmp_state = hsc->State;
- if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX))
+ /* Check that a Rx process is not already ongoing */
+ if(hsc->RxState == HAL_SMARTCARD_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -784,15 +730,7 @@
hsc->RxXferSize = Size;
hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
- /* Check if a non-blocking transmit process is ongoing or not */
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
- }
- else
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
- }
+ hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX;
/* Set the SMARTCARD DMA transfer complete callback */
hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
@@ -800,17 +738,29 @@
/* Set the DMA error callback */
hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
- /* Enable the DMA channel */
+ /* Set the DMA abort callback */
+ hsc->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA Channel */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the SMARTCARD CR3 register */
- SET_BIT(hsc->Instance->CR3,USART_CR3_DMAR);
+ /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
+ __HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
/* Process Unlocked */
__HAL_UNLOCK(hsc);
+ /* Enable the SMARTCARD Parity Error Interrupt */
+ SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the SMARTCARD CR3 register */
+ SET_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
return HAL_OK;
}
else
@@ -820,124 +770,621 @@
}
/**
- * @brief This function handles SMARTCARD interrupt request.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param hsc SMARTCARD handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel: use blocking DMA Abort API (no callback) */
+ if(hsc->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsc->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsc->hdmatx);
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel: use blocking DMA Abort API (no callback) */
+ if(hsc->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsc->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsc->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ hsc->TxXferCount = 0x00U;
+ hsc->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Restore hsc->RxState and hsc->gState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param hsc SMARTCARD handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel: use blocking DMA Abort API (no callback) */
+ if(hsc->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsc->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsc->hdmatx);
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ hsc->TxXferCount = 0x00U;
+
+ /* Restore hsc->gState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param hsc SMARTCARD handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel: use blocking DMA Abort API (no callback) */
+ if(hsc->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ hsc->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(hsc->hdmarx);
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ hsc->RxXferCount = 0x00U;
+
+ /* Restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param hsc SMARTCARD handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc)
+{
+ uint32_t AbortCplt = 0x01U;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(hsc->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
+ {
+ hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
+ }
+ else
+ {
+ hsc->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(hsc->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+ {
+ hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
+ }
+ else
+ {
+ hsc->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at SMARTCARD level */
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(hsc->hdmatx != NULL)
+ {
+ /* SMARTCARD Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
+ {
+ hsc->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(hsc->hdmarx != NULL)
+ {
+ /* SMARTCARD Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
+ {
+ hsc->hdmarx->XferAbortCallback = NULL;
+ AbortCplt = 0x01U;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if(AbortCplt == 0x01U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hsc->TxXferCount = 0x00U;
+ hsc->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Restore hsc->gState and hsc->RxState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsc);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param hsc SMARTCARD handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the SMARTCARD DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hsc->hdmatx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK)
+ {
+ /* Call Directly hsc->hdmatx->XferAbortCallback function in case of error */
+ hsc->hdmatx->XferAbortCallback(hsc->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hsc->TxXferCount = 0x00U;
+
+ /* Restore hsc->gState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ hsc->TxXferCount = 0x00U;
+
+ /* Restore hsc->gState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param hsc SMARTCARD handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hsc->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+ hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
+ {
+ /* Call Directly hsc->hdmarx->XferAbortCallback function in case of error */
+ hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsc->RxXferCount = 0x00U;
+
+ /* Restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ hsc->RxXferCount = 0x00U;
+
+ /* Restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief This function handles SMARTCARD interrupt request.
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
{
- uint32_t tmp_flag = 0, tmp_it_source = 0;
+ uint32_t isrflags = READ_REG(hsc->Instance->SR);
+ uint32_t cr1its = READ_REG(hsc->Instance->CR1);
+ uint32_t cr3its = READ_REG(hsc->Instance->CR3);
+ uint32_t dmarequest = 0x00U;
+ uint32_t errorflags = 0x00U;
+
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+ if(errorflags == RESET)
+ {
+ /* SMARTCARD in mode Receiver -------------------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ SMARTCARD_Receive_IT(hsc);
+ return;
+ }
+ }
+
+ /* If some errors occur */
+ if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+ {
+ /* SMARTCARD parity error interrupt occurred ---------------------------*/
+ if(((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+ }
+
+ /* SMARTCARD noise error interrupt occurred ----------------------------*/
+ if(((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+ }
+
+ /* SMARTCARD frame error interrupt occurred ----------------------------*/
+ if(((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+ }
+
+ /* SMARTCARD Over-Run interrupt occurred -------------------------------*/
+ if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+ }
+
+ /* Call SMARTCARD Error Call back function if need be ------------------*/
+ if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+ {
+ /* SMARTCARD in mode Receiver ----------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ SMARTCARD_Receive_IT(hsc);
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
+ if(((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest)
+ {
+ /* Blocking error : transfer is aborted
+ Set the SMARTCARD state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ SMARTCARD_EndRxTransfer(hsc);
+
+ /* Disable the SMARTCARD DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the SMARTCARD DMA Rx channel */
+ if(hsc->hdmarx != NULL)
+ {
+ /* Set the SMARTCARD DMA Abort callback :
+ will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+ hsc->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+ if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ hsc->hdmarx->XferAbortCallback(hsc->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsc);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsc);
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_SMARTCARD_ErrorCallback(hsc);
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+ }
+ }
+ return;
+ } /* End if some error occurs */
- tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_PE);
- tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE);
- /* SMARTCARD parity error interrupt occurred -----------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
- }
-
- tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_FE);
- tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
- /* SMARTCARD frame error interrupt occurred ------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
- }
-
- tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_NE);
- /* SMARTCARD noise error interrupt occurred ------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
- }
-
- tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_ORE);
- /* SMARTCARD Over-Run interrupt occurred ---------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
- }
-
- tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_RXNE);
- tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE);
- /* SMARTCARD in mode Receiver --------------------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- SMARTCARD_Receive_IT(hsc);
- }
-
- tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TXE);
- tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TXE);
- /* SMARTCARD in mode Transmitter -----------------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ /* SMARTCARD in mode Transmitter -------------------------------------------*/
+ if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
SMARTCARD_Transmit_IT(hsc);
+ return;
}
- tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TC);
- tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC);
/* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
SMARTCARD_EndTransmit_IT(hsc);
- }
-
- /* Call the Error call Back in case of Errors */
- if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
- {
- /* Clear all the error flag at once */
- __HAL_SMARTCARD_CLEAR_PEFLAG(hsc);
-
- /* Set the SMARTCARD state ready to be able to start again the process */
- hsc->State= HAL_SMARTCARD_STATE_READY;
- HAL_SMARTCARD_ErrorCallback(hsc);
+ return;
}
}
/**
- * @brief Tx Transfer completed callback.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @brief Tx Transfer completed callbacks
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
+__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file
- */
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file
+ */
}
/**
- * @brief Rx Transfer completed callback.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @brief Rx Transfer completed callbacks
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_RxCpltCallback could be implemented in the user file
*/
}
/**
- * @brief SMARTCARD error callback.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @brief SMARTCARD error callbacks
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
- __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
+__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsc);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_SMARTCARD_ErrorCallback can be implemented in the user file
- */
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Complete callback.
+ * @param hsc SMARTCARD handle.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort Transmit Complete callback.
+ * @param hsc SMARTCARD handle.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief SMARTCARD Abort ReceiveComplete callback.
+ * @param hsc SMARTCARD handle.
+ * @retval None
+ */
+__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hsc);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
+ */
}
/**
@@ -948,36 +1395,36 @@
* @brief SMARTCARD State and Errors functions
*
@verbatim
- ==============================================================================
- ##### Peripheral State and Errors functions #####
- ==============================================================================
- [..]
- This subsection provides a set of functions allowing to return the State of SmartCard
- communication process and also return Peripheral Errors occurred during communication process
- (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
- of the SMARTCARD peripheral.
- (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during
- communication.
-
+ ===============================================================================
+ ##### Peripheral State and Errors functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the SmartCard.
+ (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SmartCard peripheral.
+ (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during communication.
@endverbatim
* @{
*/
/**
- * @brief Returns the SMARTCARD state.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @brief return the SMARTCARD state
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval HAL state
*/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
{
- return hsc->State;
+ uint32_t temp1= 0x00U, temp2 = 0x00U;
+ temp1 = hsc->gState;
+ temp2 = hsc->RxState;
+
+ return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
}
/**
* @brief Return the SMARTCARD error code
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @param hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for the specified SMARTCARD.
* @retval SMARTCARD Error Code
*/
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
@@ -988,142 +1435,114 @@
/**
* @}
*/
-
-/**
- * @}
- */
-/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
- * @brief SMARTCARD Private functions
- * @{
- */
/**
- * @brief DMA SMARTCARD transmit process complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief DMA SMARTCARD transmit process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- hsc->TxXferCount = 0;
-
+
+ hsc->TxXferCount = 0U;
+
/* Disable the DMA transfer for transmit request by setting the DMAT bit
- in the SMARTCARD CR3 register */
+ in the USART CR3 register */
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
- /* Enable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
}
/**
- * @brief DMA SMARTCARD receive process complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief DMA SMARTCARD receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hsc->RxXferCount = 0;
-
+ hsc->RxXferCount = 0U;
+
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+
/* Disable the DMA transfer for the receiver request by setting the DMAR bit
- in the USART CR3 register */
+ in the USART CR3 register */
CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
- /* Check if a non-blocking transmit process is ongoing or not */
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
- }
- else
- {
- hsc->State = HAL_SMARTCARD_STATE_READY;
- }
-
+ /* At end of Rx process, restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
HAL_SMARTCARD_RxCpltCallback(hsc);
}
/**
- * @brief DMA SMARTCARD communication error callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief DMA SMARTCARD communication error callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
{
+ uint32_t dmarequest = 0x00U;
SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hsc->RxXferCount = 0U;
+ hsc->TxXferCount = 0U;
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
- hsc->RxXferCount = 0;
- hsc->TxXferCount = 0;
- hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA;
- hsc->State= HAL_SMARTCARD_STATE_READY;
-
+ /* Stop SMARTCARD DMA Tx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT);
+ if((hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) && dmarequest)
+ {
+ SMARTCARD_EndTxTransfer(hsc);
+ }
+
+ /* Stop SMARTCARD DMA Rx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR);
+ if((hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) && dmarequest)
+ {
+ SMARTCARD_EndRxTransfer(hsc);
+ }
+
HAL_SMARTCARD_ErrorCallback(hsc);
}
/**
* @brief This function handles SMARTCARD Communication Timeout.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @param hsc: SMARTCARD handle
* @param Flag: specifies the SMARTCARD flag to check.
* @param Status: The new Flag status (SET or RESET).
* @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
- uint32_t tickstart = 0;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
/* Wait until flag is set */
- if(Status == RESET)
+ while((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status)
{
- while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) == RESET)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable TXE and RXNE interrupts for the interrupt process */
- __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
- __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
-
- hsc->State= HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) != RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable TXE and RXNE interrupts for the interrupt process */
- __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
- __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
-
- hsc->State= HAL_SMARTCARD_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hsc);
+ /* Disable TXE and RXNE interrupts for the interrupt process */
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
- return HAL_TIMEOUT;
- }
+ hsc->gState= HAL_SMARTCARD_STATE_READY;
+ hsc->RxState= HAL_SMARTCARD_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsc);
+
+ return HAL_TIMEOUT;
}
}
}
@@ -1131,31 +1550,196 @@
}
/**
- * @brief Send an amount of data in non-blocking mode.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
- * Function called under interruption only, once
- * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+ * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
+ * @param hsc: SMARTCARD handle.
+ * @retval None
+ */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* At end of Tx process, restore hsc->gState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+}
+
+
+/**
+ * @brief End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).
+ * @param hsc: SMARTCARD handle.
+ * @retval None
+ */
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)
+{
+ /* At end of Rx process, restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
+}
+
+
+
+/**
+ * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsc = (SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hsc->RxXferCount = 0x00U;
+ hsc->TxXferCount = 0x00U;
+
+ HAL_SMARTCARD_ErrorCallback(hsc);
+}
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hsc->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hsc->hdmarx != NULL)
+ {
+ if(hsc->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsc->TxXferCount = 0x00U;
+ hsc->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Restore hsc->gState and hsc->RxState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsc);
+}
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hsc->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(hsc->hdmatx != NULL)
+ {
+ if(hsc->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hsc->TxXferCount = 0x00U;
+ hsc->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+ /* Restore hsc->gState and hsc->RxState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortCpltCallback(hsc);
+}
+
+/**
+ * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hsc->TxXferCount = 0x00U;
+
+ /* Restore hsc->gState to Ready */
+ hsc->gState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortTransmitCpltCallback(hsc);
+}
+
+/**
+ * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
+ * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hsc->RxXferCount = 0x00U;
+
+ /* Restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SMARTCARD_AbortReceiveCpltCallback(hsc);
+}
+
+/**
+ * @brief Send an amount of data in non blocking mode
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
{
- uint32_t tmp_state = 0;
-
- tmp_state = hsc->State;
- if((tmp_state == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX_RX))
+ uint16_t* tmp;
+
+ /* Check that a Tx process is ongoing */
+ if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX)
{
- WRITE_REG(hsc->Instance->DR, (*hsc->pTxBuffPtr++ & (uint8_t)0xFF));
+ tmp = (uint16_t*) hsc->pTxBuffPtr;
+ hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+ hsc->pTxBuffPtr += 1U;
- if(--hsc->TxXferCount == 0)
+ if(--hsc->TxXferCount == 0U)
{
- /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
- __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
+ /* Disable the SMARTCARD Transmit data register empty Interrupt */
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE);
- /* Enable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
+ /* Enable the SMARTCARD Transmit Complete Interrupt */
+ SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE);
}
-
+
return HAL_OK;
}
else
@@ -1164,7 +1748,6 @@
}
}
-
/**
* @brief Wraps up transmission in non blocking mode.
* @param hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains
@@ -1173,62 +1756,49 @@
*/
static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
- /* Disable the SMARTCARD Transmit Complete Interrupt */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
+ /* Disable the SMARTCARD Transmit Complete Interrupt */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TCIE);
- /* Check if a receive process is ongoing or not */
- if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
- {
- hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
- }
- else
- {
- /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
-
- hsmartcard->State = HAL_SMARTCARD_STATE_READY;
- }
-
+ /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+ CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+ /* Tx process is ended, restore hsmartcard->gState to Ready */
+ hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
HAL_SMARTCARD_TxCpltCallback(hsmartcard);
return HAL_OK;
}
-
/**
- * @brief Receive an amount of data in non-blocking mode.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @brief Receive an amount of data in non blocking mode
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
{
- uint32_t tmp_state = 0;
-
- tmp_state = hsc->State;
- if((tmp_state == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX_RX))
+ uint16_t* tmp;
+
+ /* Check that a Rx process is ongoing */
+ if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
{
- *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
+ tmp = (uint16_t*) hsc->pRxBuffPtr;
+ *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
+ hsc->pRxBuffPtr += 1U;
- if(--hsc->RxXferCount == 0)
+ if(--hsc->RxXferCount == 0U)
{
- __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE);
/* Disable the SMARTCARD Parity Error Interrupt */
- __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
-
+ CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE);
+
/* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
+ CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE);
- /* Check if a non-blocking transmit process is ongoing or not */
- if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX)
- {
- hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
- }
- else
- {
- hsc->State = HAL_SMARTCARD_STATE_READY;
- }
+ /* Rx process is completed, restore hsc->RxState to Ready */
+ hsc->RxState = HAL_SMARTCARD_STATE_READY;
HAL_SMARTCARD_RxCpltCallback(hsc);
@@ -1238,19 +1808,22 @@
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Configures the SMARTCARD peripheral.
- * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
- * the configuration information for the specified SMARTCARD module.
+ * @brief Configure the SMARTCARD peripheral
+ * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * the configuration information for SMARTCARD module.
* @retval None
*/
static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
{
+ uint32_t tmpreg = 0x00U;
+
/* Check the parameters */
+ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));
assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));
assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit));
@@ -1261,38 +1834,58 @@
assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));
assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
+
/* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
- CLEAR_BIT(hsc->Instance->CR1, (uint32_t)(USART_CR1_TE | USART_CR1_RE));
+ CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
- /*------ SMARTCARD-associated USART registers setting : CR2 Configuration ------*/
+ /*---------------------------- USART CR2 Configuration ---------------------*/
+ tmpreg = hsc->Instance->CR2;
/* Clear CLKEN, CPOL, CPHA and LBCL bits */
+ tmpreg &= (uint32_t)~((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL));
/* Configure the SMARTCARD Clock, CPOL, CPHA and LastBit -----------------------*/
/* Set CPOL bit according to hsc->Init.CLKPolarity value */
/* Set CPHA bit according to hsc->Init.CLKPhase value */
/* Set LBCL bit according to hsc->Init.CLKLastBit value */
- MODIFY_REG(hsc->Instance->CR2,
- ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL)),
- ((uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity | hsc->Init.CLKPhase| hsc->Init.CLKLastBit)) );
-
/* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
- MODIFY_REG(hsc->Instance->CR2, USART_CR2_STOP,(uint32_t)(hsc->Init.StopBits));
+ tmpreg |= (uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity |
+ hsc->Init.CLKPhase| hsc->Init.CLKLastBit | hsc->Init.StopBits);
+ /* Write to USART CR2 */
+ WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
+
+ tmpreg = hsc->Instance->CR2;
- /*------ SMARTCARD-associated USART registers setting : CR1 Configuration ------*/
+ /* Clear STOP[13:12] bits */
+ tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
+
+ /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
+ tmpreg |= (uint32_t)(hsc->Init.StopBits);
+
+ /* Write to USART CR2 */
+ WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg);
+
+ /*-------------------------- USART CR1 Configuration -----------------------*/
+ tmpreg = hsc->Instance->CR1;
+
/* Clear M, PCE, PS, TE and RE bits */
- /* Configure the SMARTCARD Word Length, Parity and mode:
- Set the M according to hsc->Init.WordLength value (forced to 1 as 9B data frame should be selected)
- Set PCE and PS bits according to hsc->Init.Parity value (PCE bit forced to 1 as parity control should always be enabled)
- Set TE and RE bits according to hsc->Init.Mode value */
- MODIFY_REG(hsc->Instance->CR1,
- ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)),
- ((uint32_t)(USART_CR1_M | USART_CR1_PCE | hsc->Init.Parity | hsc->Init.Mode)) );
+ tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
+ USART_CR1_RE));
- /*------ SMARTCARD-associated USART registers setting : CR3 Configuration ------*/
+ /* Configure the SMARTCARD Word Length, Parity and mode:
+ Set the M bits according to hsc->Init.WordLength value
+ Set PCE and PS bits according to hsc->Init.Parity value
+ Set TE and RE bits according to hsc->Init.Mode value */
+ tmpreg |= (uint32_t)hsc->Init.WordLength | hsc->Init.Parity | hsc->Init.Mode;
+
+ /* Write to USART CR1 */
+ WRITE_REG(hsc->Instance->CR1, (uint32_t)tmpreg);
+
+ /*-------------------------- USART CR3 Configuration -----------------------*/
/* Clear CTSE and RTSE bits */
CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
- /*------ SMARTCARD-associated USART registers setting : BRR Configuration ------*/
+ /*-------------------------- USART BRR Configuration -----------------------*/
+
if(hsc->Instance == USART1)
{
hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_spi.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_spi.c
index 0d873e5..9e2e79f 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_spi.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_spi.c
@@ -2,16 +2,16 @@
******************************************************************************
* @file stm32f1xx_hal_spi.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief SPI HAL module driver.
- *
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Serial Peripheral Interface (SPI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
+ * + Peripheral Control functions
* + Peripheral State functions
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -20,12 +20,12 @@
The SPI HAL driver can be used as follows:
(#) Declare a SPI_HandleTypeDef handle structure, for example:
- SPI_HandleTypeDef hspi;
+ SPI_HandleTypeDef hspi;
- (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
- (##) Enable the SPIx interface clock
+ (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
+ (##) Enable the SPIx interface clock
(##) SPI pins configuration
- (+++) Enable the clock for the SPI GPIOs
+ (+++) Enable the clock for the SPI GPIOs
(+++) Configure these SPI pins as alternate function push-pull
(##) NVIC configuration if you need to use interrupt process
(+++) Configure the SPIx interrupt priority
@@ -38,26 +38,94 @@
(+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
- (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
+ (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_SPI_MspInit() API.
+ by calling the customized HAL_SPI_MspInit() API.
[..]
Circular mode restriction:
(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
(##) Master 2Lines RxOnly
(##) Master 1Line Rx
(#) The CRC feature is not managed when the DMA circular mode is enabled
- (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
+ (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
+ [..]
+ Master Receive mode restriction:
+ (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
+ bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
+ does not initiate a new transfer the following procedure has to be respected:
+ (##) HAL_SPI_DeInit()
+ (##) HAL_SPI_Init()
@endverbatim
+
+ Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
+ the following tables resume the max SPI frequency reached with data size 8bits/16bits,
+ according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
+
+ DataSize = SPI_DATASIZE_8BIT:
+ +--------------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |-----------------------|-----------------------|-----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==================================================================================================|
+ | T | Polling | fPCLK/2 | fPCLK/16 | NA | NA | NA | NA |
+ | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | / | Interrupt | fPCLK/8 | fPCLK/32 | NA | NA | NA | NA |
+ | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA |
+ |=========|================|===========|===========|===========|===========|===========|===========|
+ | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/8 | fPCLK/16 | fPCLK/64 | fPCLK/2 |
+ | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | R | Interrupt | fPCLK/8 | fPCLK/16 | fPCLK/32 | fPCLK/16 | fPCLK/64 | fPCLK/4 |
+ | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | | DMA | fPCLK/2 | fPCLK/16 | fPCLK/8 | fPCLK/16 | fPCLK/64 | fPCLK/2 |
+ |=========|================|===========|===========|===========|===========|===========|===========|
+ | | Polling | fPCLK/2 | fPCLK/2 | NA | NA | fPCLK/2 | fPCLK/32 |
+ | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | T | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | fPCLK/2 | fPCLK/64 |
+ | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/32 |
+ +--------------------------------------------------------------------------------------------------+
+
+ DataSize = SPI_DATASIZE_16BIT:
+ +--------------------------------------------------------------------------------------------------+
+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
+ | Process | Tranfert mode |-----------------------|-----------------------|-----------------------|
+ | | | Master | Slave | Master | Slave | Master | Slave |
+ |==================================================================================================|
+ | T | Polling | fPCLK/4 | fPCLK/4 | NA | NA | NA | NA |
+ | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | / | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | NA | NA |
+ | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA |
+ |=========|================|===========|===========|===========|===========|===========|===========|
+ | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/4 | fPCLK/8 | fPCLK/64 | fPCLK/2 |
+ | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | R | Interrupt | fPCLK/8 | fPCLK/8 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/4 |
+ | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/16 | fPCLK/64 | fPCLK/2 |
+ |=========|================|===========|===========|===========|===========|===========|===========|
+ | | Polling | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/4 | fPCLK/8 |
+ | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | T | Interrupt | fPCLK/4 | fPCLK/8 | NA | NA | fPCLK/4 | fPCLK/4 |
+ | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
+ | | DMA | fPCLK/2 | fPCLK/2 | NA | NA | fPCLK/4 | fPCLK/8 |
+ +--------------------------------------------------------------------------------------------------+
+ [..]
+ (@) The max SPI frequency depend on SPI data size (8bits, 16bits),
+ SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
+ (@)
+ (+@) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
+ (+@) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
+ (+@) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -84,107 +152,34 @@
******************************************************************************
*/
-/*
- Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
- the following table resume the max SPI frequency reached with data size 8bits/16bits,
- according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
-
- For 8 bits SPI data size transfers :
- +--------------------------------------------------------------------------------------------------+
- | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
- | Process | Tranfert mode |-----------------------|-----------------------|-----------------------|
- | | | Master | Slave | Master | Slave | Master | Slave |
- |==================================================================================================|
- | T | Polling | fPCLK/8 | fPCLK/8 | NA | NA | NA | NA |
- | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA |
- | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA |
- |=========|================|===========|===========|===========|===========|===========|===========|
- | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/8 |
- | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | R | Interrupt | fPCLK/32 | fPCLK/16 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/16 |
- | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/2 |
- |=========|================|===========|===========|===========|===========|===========|===========|
- | | Polling | fPCLK/4 | fPCLK/4 | NA | NA | fPCLK/4 | fPCLK/64 |
- | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | T | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/128 |
- | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 |
- +--------------------------------------------------------------------------------------------------+
-
- For 16 bits SPI data size transfers :
- +--------------------------------------------------------------------------------------------------+
- | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
- | Process | Tranfert mode |-----------------------|-----------------------|-----------------------|
- | | | Master | Slave | Master | Slave | Master | Slave |
- |==================================================================================================|
- | T | Polling | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA |
- | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | / | Interrupt | fPCLK/16 | fPCLK/16 | NA | NA | NA | NA |
- | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA |
- |=========|================|===========|===========|===========|===========|===========|===========|
- | | Polling | fPCLK/2 | fPCLK/4 | fPCLK/64 | fPCLK/8 | fPCLK/64 | fPCLK/4 |
- | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | R | Interrupt | fPCLK/16 | fPCLK/8 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/8 |
- | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/2 |
- |=========|================|===========|===========|===========|===========|===========|===========|
- | | Polling | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 |
- | |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | T | Interrupt | fPCLK/4 | fPCLK/8 | NA | NA | fPCLK/4 | fPCLK/256 |
- | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------|
- | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/32 |
- +--------------------------------------------------------------------------------------------------+
-
- note:
- The max SPI frequency depend on SPI data size (8bits, 16bits),
- SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
-
- note:
- TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
- RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
- TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
-
-*/
-
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
-
/** @defgroup SPI SPI
* @brief SPI HAL module driver
* @{
*/
-
#ifdef HAL_SPI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
/** @defgroup SPI_Private_Constants SPI Private Constants
* @{
*/
-#define SPI_TIMEOUT_VALUE 10
+#define SPI_DEFAULT_TIMEOUT 100U
/**
* @}
*/
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
+/** @addtogroup SPI_Private_Functions
* @{
*/
-static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
-static void SPI_TxISR(SPI_HandleTypeDef *hspi);
-static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
-static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
-static void SPI_RxISR(SPI_HandleTypeDef *hspi);
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
@@ -192,34 +187,56 @@
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
static void SPI_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
+#if (USE_SPI_CRC != 0U)
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
+#endif /* USE_SPI_CRC */
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
+static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
/**
* @}
*/
-/* Exported functions ---------------------------------------------------------*/
-
+/* Exported functions --------------------------------------------------------*/
/** @defgroup SPI_Exported_Functions SPI Exported Functions
* @{
*/
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
- [..] This subsection provides a set of functions allowing to initialize and
- de-initialiaze the SPIx peripheral:
+ [..] This subsection provides a set of functions allowing to initialize and
+ de-initialize the SPIx peripheral:
- (+) User must implement HAL_SPI_MspInit() function in which he configures
+ (+) User must implement HAL_SPI_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
- (+) Call the function HAL_SPI_Init() to configure the selected device with
+ (+) Call the function HAL_SPI_Init() to configure the selected device with
the selected configuration:
(++) Mode
- (++) Direction
+ (++) Direction
(++) Data Size
(++) Clock Polarity and Phase
(++) NSS Management
@@ -229,18 +246,18 @@
(++) CRC Calculation
(++) CRC Polynomial if CRC enabled
- (+) Call the function HAL_SPI_DeInit() to restore the default configuration
- of the selected SPIx periperal.
+ (+) Call the function HAL_SPI_DeInit() to restore the default configuration
+ of the selected SPIx peripheral.
@endverbatim
* @{
*/
/**
- * @brief Initializes the SPI according to the specified parameters
- * in the SPI_InitTypeDef and create the associated handle.
+ * @brief Initialize the SPI according to the specified parameters
+ * in the SPI_InitTypeDef and initialize the associated handle.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
@@ -254,29 +271,36 @@
/* Check the parameters */
assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
assert_param(IS_SPI_MODE(hspi->Init.Mode));
- assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
+ assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
- assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+
+#if (USE_SPI_CRC != 0U)
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
- assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+ }
+#else
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+#endif /* USE_SPI_CRC */
if(hspi->State == HAL_SPI_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
-
+
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
}
-
+
hspi->State = HAL_SPI_STATE_BUSY;
- /* Disble the selected SPI peripheral */
+ /* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
@@ -287,22 +311,32 @@
hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
/* Configure : NSS management */
- WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode));
+ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
+#if (USE_SPI_CRC != 0U)
/*---------------------------- SPIx CRCPOLY Configuration ------------------*/
/* Configure : CRC Polynomial */
- WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
+ }
+#endif /* USE_SPI_CRC */
+
+#if defined(SPI_I2SCFGR_I2SMOD)
+ /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
+ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
- hspi->State = HAL_SPI_STATE_READY;
-
+ hspi->State = HAL_SPI_STATE_READY;
+
return HAL_OK;
}
/**
- * @brief DeInitializes the SPI peripheral
+ * @brief De Initialize the SPI peripheral.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
@@ -313,6 +347,9 @@
return HAL_ERROR;
}
+ /* Check SPI Instance parameter */
+ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
+
hspi->State = HAL_SPI_STATE_BUSY;
/* Disable the SPI Peripheral Clock */
@@ -331,33 +368,33 @@
}
/**
- * @brief SPI MSP Init
+ * @brief Initialize the SPI MSP.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
- __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
- {
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hspi);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_MspInit could be implenetd in the user file
- */
-}
-
-/**
- * @brief SPI MSP DeInit
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
- __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_MspDeInit could be implenetd in the user file
- */
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspInit should be implemented in the user file
+ */
+}
+
+/**
+ * @brief De-Initialize the SPI MSP.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_MspDeInit should be implemented in the user file
+ */
}
/**
@@ -371,6 +408,7 @@
==============================================================================
##### IO operation functions #####
===============================================================================
+ [..]
This subsection provides a set of functions allowing to manage the SPI
data transfers.
@@ -382,11 +420,11 @@
after finishing transfer.
(++) No-Blocking mode: The communication is performed using Interrupts
or DMA, These APIs return the HAL status.
- The end of the data processing will be indicated through the
- dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
+ The end of the data processing will be indicated through the
+ dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
- The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
- will be executed respectivelly at the end of the transmit or Receive process
+ The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
+ will be executed respectively at the end of the transmit or Receive process
The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
@@ -397,9 +435,9 @@
*/
/**
- * @brief Transmit an amount of data in blocking mode
+ * @brief Transmit an amount of data in blocking mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @param Timeout: Timeout duration
@@ -407,293 +445,345 @@
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
+ uint32_t tickstart = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
- if(hspi->State == HAL_SPI_STATE_READY)
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if(hspi->State != HAL_SPI_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pData == NULL ) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit data in 16 Bit mode */
+ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
+ if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
{
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Configure communication */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-
- hspi->pTxBuffPtr = pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->TxISR = 0;
- hspi->RxISR = 0;
- hspi->pRxBuffPtr = NULL;
- hspi->RxXferSize = 0;
- hspi->RxXferCount = 0;
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- /* Configure communication direction : 1Line */
- SPI_1LINE_TX(hspi);
- }
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Transmit data in 8 Bit mode */
- if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
- {
- if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
- {
- hspi->Instance->DR = (*hspi->pTxBuffPtr++);
- hspi->TxXferCount--;
- }
-
- while(hspi->TxXferCount > 0)
- {
- /* Wait until TXE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
- hspi->Instance->DR = (*hspi->pTxBuffPtr++);
- hspi->TxXferCount--;
- }
- /* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
+ hspi->TxXferCount--;
}
/* Transmit data in 16 Bit mode */
- else
+ while (hspi->TxXferCount > 0U)
{
- if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
+ /* Wait until TXE flag is set to send data */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
{
- hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr+=2;
- hspi->TxXferCount--;
+ hspi->Instance->DR = *((uint16_t *)pData);
+ pData += sizeof(uint16_t);
+ hspi->TxXferCount--;
}
-
- while(hspi->TxXferCount > 0)
+ else
{
- /* Wait until TXE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
+ /* Timeout management */
+ if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
- hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr+=2;
- hspi->TxXferCount--;
- }
- /* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
}
-
- /* Wait until TXE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
-
- /* Wait until Busy flag is reset before disabling SPI */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
-
- /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
- if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
}
+ /* Transmit data in 8 Bit mode */
else
{
- return HAL_BUSY;
+ if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
+ {
+ *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
+ pData += sizeof(uint8_t);
+ hspi->TxXferCount--;
+ }
+ while (hspi->TxXferCount > 0U)
+ {
+ /* Wait until TXE flag is set to send data */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
+ {
+ *((__IO uint8_t*)&hspi->Instance->DR) = (*pData);
+ pData += sizeof(uint8_t);
+ hspi->TxXferCount--;
+ }
+ else
+ {
+ /* Timeout management */
+ if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+ }
+ }
}
+
+ /* Wait until TXE flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
+
+ /* Check Busy flag */
+ if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
+ {
+ errorcode = HAL_ERROR;
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ goto error;
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ errorcode = HAL_ERROR;
+ }
+
+error:
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
- * @brief Receive an amount of data in blocking mode
+ * @brief Receive an amount of data in blocking mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param Size: amount of data to be received
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- __IO uint16_t tmpreg = 0;
+#if (USE_SPI_CRC != 0U)
+ __IO uint16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ uint32_t tickstart = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
- if(hspi->State == HAL_SPI_STATE_READY)
+ if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
{
- if((pData == NULL ) || (Size == 0))
- {
- return HAL_ERROR;
- }
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
+ }
- /* Process Locked */
- __HAL_LOCK(hspi);
+ /* Process Locked */
+ __HAL_LOCK(hspi);
- /* Configure communication */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
- hspi->pRxBuffPtr = pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
- /*Init field not used in handle to zero */
- hspi->RxISR = 0;
- hspi->TxISR = 0;
- hspi->pTxBuffPtr = NULL;
- hspi->TxXferSize = 0;
- hspi->TxXferCount = 0;
+ if((pData == NULL ) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
- /* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_RX(hspi);
- }
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
+ /*Init field not used in handle to zero */
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
- }
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ /* this is done to handle the CRCNEXT before the latest data */
+ hspi->RxXferCount--;
+ }
+#endif /* USE_SPI_CRC */
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
+ /* Configure communication direction: 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
/* Receive data in 8 Bit mode */
- if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+ if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+ {
+ /* Transfer loop */
+ while(hspi->RxXferCount > 0U)
{
- while(hspi->RxXferCount > 1)
+ /* Check the RXNE flag */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
- /* Wait until RXNE flag is set */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+ /* read the received data */
+ (* (uint8_t *)pData)= *(__IO uint8_t *)&hspi->Instance->DR;
+ pData += sizeof(uint8_t);
hspi->RxXferCount--;
}
- /* Enable CRC Reception */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ else
{
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Timeout management */
+ if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
}
}
- /* Receive data in 16 Bit mode */
- else
+ }
+ else
+ {
+ /* Transfer loop */
+ while(hspi->RxXferCount > 0U)
{
- while(hspi->RxXferCount > 1)
+ /* Check the RXNE flag */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
{
- /* Wait until RXNE flag is set to read data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr+=2;
+ *((uint16_t*)pData) = hspi->Instance->DR;
+ pData += sizeof(uint16_t);
hspi->RxXferCount--;
}
- /* Enable CRC Reception */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ else
{
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Timeout management */
+ if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
+ }
}
}
+ }
- /* Wait until RXNE flag is set */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
+#if (USE_SPI_CRC != 0U)
+ /* Handle the CRC Transmission */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* freeze the CRC before the latest data */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- /* Receive last data in 8 Bit mode */
- if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+ /* Read the latest data */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
- (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
+ /* the latest data has not been received */
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
+
/* Receive last data in 16 Bit mode */
+ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
+ *((uint16_t*)pData) = hspi->Instance->DR;
+ }
+ /* Receive last data in 8 Bit mode */
else
{
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr+=2;
+ (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR;
}
- hspi->RxXferCount--;
- /* If CRC computation is enabled */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ /* Wait the CRC data */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
- /* Wait until RXNE flag is set: CRC Received */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- return HAL_TIMEOUT;
- }
-
- /* Read CRC to clear RXNE flag */
- tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg);
- }
-
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
- hspi->State = HAL_SPI_STATE_READY;
+ /* Read CRC to Flush DR and RXNE flag */
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+#endif /* USE_SPI_CRC */
+ /* Check the end of the transaction */
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
- if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
- {
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
/* Check if CRC error is valid or not (workaround to be applied or not) */
if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
{
@@ -701,838 +791,1126 @@
/* Reset CRC Calculation */
SPI_RESET_CRC(hspi);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_ERROR;
}
else
{
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
}
+#endif /* USE_SPI_CRC */
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
- }
- else
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- return HAL_BUSY;
+ errorcode = HAL_ERROR;
}
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
- * @brief Transmit and Receive an amount of data in blocking mode
+ * @brief Transmit and Receive an amount of data in blocking mode.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer to be
- * @param Size: amount of data to be sent
+ * @param pRxData: pointer to reception data buffer
+ * @param Size: amount of data to be sent and received
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
{
- __IO uint16_t tmpreg = 0;
+ uint32_t tmp = 0U, tmp1 = 0U;
+#if (USE_SPI_CRC != 0U)
+ __IO uint16_t tmpreg1 = 0U;
+#endif /* USE_SPI_CRC */
+ uint32_t tickstart = 0U;
+ /* Variable used to alternate Rx and Tx during transfer */
+ uint32_t txallowed = 1U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
- if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX))
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+
+ if(!((tmp == HAL_SPI_STATE_READY) || \
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
{
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
+ errorcode = HAL_BUSY;
+ goto error;
+ }
+
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if(hspi->State == HAL_SPI_STATE_READY)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
+
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferCount = Size;
+ hspi->RxXferSize = Size;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferCount = Size;
+ hspi->TxXferSize = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Transmit and Receive data in 16 Bit mode */
+ if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
+ {
+ if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
{
- return HAL_ERROR;
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
+ hspi->TxXferCount--;
}
-
- /* Check the parameters */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if(hspi->State == HAL_SPI_STATE_READY)
+ while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
{
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
-
- /* Configure communication */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-
- hspi->pRxBuffPtr = pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- hspi->pTxBuffPtr = pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->RxISR = 0;
- hspi->TxISR = 0;
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Transmit and Receive data in 16 Bit mode */
- if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
- {
- if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
+ /* Check TXE flag */
+ if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
{
- hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr+=2;
+ hspi->Instance->DR = *((uint16_t *)pTxData);
+ pTxData += sizeof(uint16_t);
hspi->TxXferCount--;
- }
- if(hspi->TxXferCount == 0)
- {
+ /* Next Data is a reception (Rx). Tx not allowed */
+ txallowed = 0U;
+
+#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
-
- /* Wait until RXNE flag is set */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr+=2;
- hspi->RxXferCount--;
+#endif /* USE_SPI_CRC */
}
- else
+
+ /* Check RXNE flag */
+ if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
{
- while(hspi->TxXferCount > 0)
- {
- /* Wait until TXE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr+=2;
- hspi->TxXferCount--;
-
- /* Enable CRC Transmission */
- if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-
- /* Wait until RXNE flag is set */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr+=2;
- hspi->RxXferCount--;
- }
- /* Receive the last byte */
- if(hspi->Init.Mode == SPI_MODE_SLAVE)
- {
- /* Wait until RXNE flag is set */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr+=2;
- hspi->RxXferCount--;
- }
+ *((uint16_t *)pRxData) = hspi->Instance->DR;
+ pRxData += sizeof(uint16_t);
+ hspi->RxXferCount--;
+ /* Next Data is a Transmission (Tx). Tx is allowed */
+ txallowed = 1U;
+ }
+ if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
+ {
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
}
- /* Transmit and Receive data in 8 Bit mode */
- else
+ }
+ /* Transmit and Receive data in 8 Bit mode */
+ else
+ {
+ if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U))
{
- if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
+ *((__IO uint8_t*)&hspi->Instance->DR) = (*pTxData);
+ pTxData += sizeof(uint8_t);
+ hspi->TxXferCount--;
+ }
+ while((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
+ {
+ /* check TXE flag */
+ if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)))
{
- hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++);
hspi->TxXferCount--;
- }
- if(hspi->TxXferCount == 0)
- {
+ /* Next Data is a reception (Rx). Tx not allowed */
+ txallowed = 0U;
+
+#if (USE_SPI_CRC != 0U)
/* Enable CRC Transmission */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
{
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
+#endif /* USE_SPI_CRC */
+ }
- /* Wait until RXNE flag is set */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- (*hspi->pRxBuffPtr) = hspi->Instance->DR;
+ /* Wait until RXNE flag is reset */
+ if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)))
+ {
+ (*(uint8_t *)pRxData++) = hspi->Instance->DR;
hspi->RxXferCount--;
+ /* Next Data is a Transmission (Tx). Tx is allowed */
+ txallowed = 1U;
}
- else
+ if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))
{
- while(hspi->TxXferCount > 0)
- {
- /* Wait until TXE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- hspi->Instance->DR = (*hspi->pTxBuffPtr++);
- hspi->TxXferCount--;
-
- /* Enable CRC Transmission */
- if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
- {
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-
- /* Wait until RXNE flag is set */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
- hspi->RxXferCount--;
- }
- if(hspi->Init.Mode == SPI_MODE_SLAVE)
- {
- /* Wait until RXNE flag is set */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- return HAL_TIMEOUT;
- }
-
- (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
- hspi->RxXferCount--;
- }
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
}
+ }
- /* Read CRC from DR to close CRC calculation process */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+#if (USE_SPI_CRC != 0U)
+ /* Read CRC from DR to close CRC calculation process */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait until TXE flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
{
- /* Wait until RXNE flag is set */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- return HAL_TIMEOUT;
- }
- /* Read CRC */
- tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg);
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
+ /* Read CRC */
+ tmpreg1 = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg1);
+ }
- /* Wait until Busy flag is reset before disabling SPI */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- return HAL_TIMEOUT;
- }
-
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Check if CRC error occurred */
- if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ /* Check if CRC error is valid or not (workaround to be applied or not) */
+ if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ /* Reset CRC Calculation */
SPI_RESET_CRC(hspi);
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_ERROR;
+ errorcode = HAL_ERROR;
}
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
+ else
+ {
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
}
- else
+#endif /* USE_SPI_CRC */
+
+ /* Wait until TXE flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK)
{
- return HAL_BUSY;
+ errorcode = HAL_TIMEOUT;
+ goto error;
}
+
+ /* Check Busy flag */
+ if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK)
+ {
+ errorcode = HAL_ERROR;
+ hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
+ goto error;
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+error :
+ hspi->State = HAL_SPI_STATE_READY;
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
- * @brief Transmit an amount of data in no-blocking mode with Interrupt
+ * @brief Transmit an amount of data in non-blocking mode with Interrupt.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- if(hspi->State == HAL_SPI_STATE_READY)
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if((pData == NULL) || (Size == 0U))
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
+ errorcode = HAL_ERROR;
+ goto error;
+ }
- /* Check the parameters */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
- /* Process Locked */
- __HAL_LOCK(hspi);
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
- /* Configure communication */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ /* Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->RxISR = NULL;
- hspi->TxISR = &SPI_TxISR;
- hspi->pTxBuffPtr = pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->RxISR = 0;
- hspi->pRxBuffPtr = NULL;
- hspi->RxXferSize = 0;
- hspi->RxXferCount = 0;
-
- /* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_TX(hspi);
- }
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
- {
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
- }
- else
- {
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
- }
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- return HAL_OK;
+ /* Set the function for IT treatment */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ {
+ hspi->TxISR = SPI_TxISR_16BIT;
}
else
{
- return HAL_BUSY;
+ hspi->TxISR = SPI_TxISR_8BIT;
}
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ /* Enable TXE interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
+ }
+ else
+ {
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
+ }
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
- * @brief Receive an amount of data in no-blocking mode with Interrupt
+ * @brief Receive an amount of data in non-blocking mode with Interrupt.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- if(hspi->State == HAL_SPI_STATE_READY)
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
+ }
- /* Process Locked */
- __HAL_LOCK(hspi);
+ /* Process Locked */
+ __HAL_LOCK(hspi);
- /* Configure communication */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ if(hspi->State != HAL_SPI_STATE_READY)
+ {
+ errorcode = HAL_BUSY;
+ goto error;
+ }
- hspi->RxISR = &SPI_RxISR;
- hspi->pRxBuffPtr = pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size ;
+ if((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
- /*Init field not used in handle to zero */
- hspi->TxISR = 0;
- hspi->pTxBuffPtr = NULL;
- hspi->TxXferSize = 0;
- hspi->TxXferCount = 0;
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
- /* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_RX(hspi);
- }
- else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
+ /* Init field not used in handle to zero */
+ hspi->pTxBuffPtr = (uint8_t *)NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+ hspi->TxISR = NULL;
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
- }
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- /* Enable TXE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- /* Note : The SPI must be enabled after unlocking current process
- to avoid the risk of SPI interrupt handle execution before current
- process unlock */
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- return HAL_OK;
+ /* Set the function for IT treatment */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ {
+ hspi->RxISR = SPI_RxISR_16BIT;
}
else
{
- return HAL_BUSY;
+ hspi->RxISR = SPI_RxISR_8BIT;
}
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Enable TXE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Note : The SPI must be enabled after unlocking current process
+ to avoid the risk of SPI interrupt handle execution before current
+ process unlock */
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
- * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
+ * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer to be
- * @param Size: amount of data to be sent
+ * @param pRxData: pointer to reception data buffer
+ * @param Size: amount of data to be sent and received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
+ uint32_t tmp = 0U, tmp1 = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
- if((hspi->State == HAL_SPI_STATE_READY) || \
- ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+
+ if(!((tmp == HAL_SPI_STATE_READY) || \
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
{
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
- {
- return HAL_ERROR;
- }
+ errorcode = HAL_BUSY;
+ goto error;
+ }
- /* Check the parameters */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
- /* Process locked */
- __HAL_LOCK(hspi);
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if(hspi->State == HAL_SPI_STATE_READY)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if(hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t *)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
- /* Configure communication */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-
- hspi->TxISR = &SPI_TxISR;
- hspi->pTxBuffPtr = pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- hspi->RxISR = &SPI_2LinesRxISR;
- hspi->pRxBuffPtr = pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- /* Enable TXE, RXNE and ERR interrupt */
- __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- return HAL_OK;
+ /* Set the function for IT treatment */
+ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
+ {
+ hspi->RxISR = SPI_2linesRxISR_16BIT;
+ hspi->TxISR = SPI_2linesTxISR_16BIT;
}
else
{
- return HAL_BUSY;
+ hspi->RxISR = SPI_2linesRxISR_8BIT;
+ hspi->TxISR = SPI_2linesTxISR_8BIT;
}
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Enable TXE, RXNE and ERR interrupt */
+ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
- * @brief Transmit an amount of data in no-blocking mode with DMA
+ * @brief Transmit an amount of data in non-blocking mode with DMA.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
* @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- if(hspi->State == HAL_SPI_STATE_READY)
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Configure communication */
- hspi->State = HAL_SPI_STATE_BUSY_TX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-
- hspi->pTxBuffPtr = pData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->TxISR = 0;
- hspi->RxISR = 0;
- hspi->pRxBuffPtr = NULL;
- hspi->RxXferSize = 0;
- hspi->RxXferCount = 0;
-
- /* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_TX(hspi);
- }
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- /* Set the SPI TxDMA Half transfer complete callback */
- hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
-
- /* Set the SPI TxDMA transfer complete callback */
- hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
-
- /* Set the DMA error callback */
- hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
- /* Enable the Tx DMA Channel */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
- /* Enable Tx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- return HAL_OK;
+ errorcode = HAL_BUSY;
+ goto error;
}
- else
+
+ if((pData == NULL) || (Size == 0U))
{
- return HAL_BUSY;
+ errorcode = HAL_ERROR;
+ goto error;
}
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_TX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t *)pData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+
+ /* Init field not used in handle to zero */
+ hspi->pRxBuffPtr = (uint8_t *)NULL;
+ hspi->TxISR = NULL;
+ hspi->RxISR = NULL;
+ hspi->RxXferSize = 0U;
+ hspi->RxXferCount = 0U;
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_TX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Set the SPI TxDMA Half transfer complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
+
+ /* Set the SPI TxDMA transfer complete callback */
+ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmatx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the Tx DMA Stream */
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Enable the SPI Error Interrupt Bit */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
- * @brief Receive an amount of data in no-blocking mode with DMA
+ * @brief Receive an amount of data in non-blocking mode with DMA.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @param pData: pointer to data buffer
- * @note When the CRC feature is enabled the pData Length must be Size + 1.
+ * @note When the CRC feature is enabled the pData Length must be Size + 1.
* @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
{
- if(hspi->State == HAL_SPI_STATE_READY)
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
{
- if((pData == NULL) || (Size == 0))
- {
- return HAL_ERROR;
- }
-
- /* Process Locked */
- __HAL_LOCK(hspi);
-
- /* Configure communication */
- hspi->State = HAL_SPI_STATE_BUSY_RX;
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-
- hspi->pRxBuffPtr = pData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
-
- /*Init field not used in handle to zero */
- hspi->RxISR = 0;
- hspi->TxISR = 0;
- hspi->pTxBuffPtr = NULL;
- hspi->TxXferSize = 0;
- hspi->TxXferCount = 0;
-
- /* Configure communication direction : 1Line */
- if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
- {
- SPI_1LINE_RX(hspi);
- }
- else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
- {
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
- return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
- }
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- /* Set the SPI RxDMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-
- /* Set the SPI Rx DMA transfer complete callback */
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
-
- /* Set the DMA error callback */
- hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
- /* Enable the Rx DMA Channel */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
- /* Enable Rx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- return HAL_OK;
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
+ return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
}
- else
+
+ /* Process Locked */
+ __HAL_LOCK(hspi);
+
+ if(hspi->State != HAL_SPI_STATE_READY)
{
- return HAL_BUSY;
+ errorcode = HAL_BUSY;
+ goto error;
}
+
+ if((pData == NULL) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
+
+ /* Set the transaction information */
+ hspi->State = HAL_SPI_STATE_BUSY_RX;
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pRxBuffPtr = (uint8_t *)pData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
+
+ /*Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
+ hspi->TxXferSize = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Configure communication direction : 1Line */
+ if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ {
+ SPI_1LINE_RX(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Set the SPI RxDMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+
+ /* Set the SPI Rx DMA transfer complete callback */
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+
+ /* Enable the SPI Error Interrupt Bit */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+error:
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
/**
- * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
+ * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @param pTxData: pointer to transmission data buffer
* @param pRxData: pointer to reception data buffer
- * @note When the CRC feature is enabled the pRxData Length must be Size + 1
+ * @note When the CRC feature is enabled the pRxData Length must be Size + 1
* @param Size: amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
- if((hspi->State == HAL_SPI_STATE_READY) || \
- ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
+ uint32_t tmp = 0U, tmp1 = 0U;
+ HAL_StatusTypeDef errorcode = HAL_OK;
+
+ /* Check Direction parameter */
+ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
+
+ /* Process locked */
+ __HAL_LOCK(hspi);
+
+ tmp = hspi->State;
+ tmp1 = hspi->Init.Mode;
+ if(!((tmp == HAL_SPI_STATE_READY) ||
+ ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX))))
{
- if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
- {
- return HAL_ERROR;
- }
+ errorcode = HAL_BUSY;
+ goto error;
+ }
- /* Check the parameters */
- assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
- /* Process locked */
- __HAL_LOCK(hspi);
+ if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U))
+ {
+ errorcode = HAL_ERROR;
+ goto error;
+ }
- /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
- if(hspi->State != HAL_SPI_STATE_BUSY_RX)
- {
- hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
- }
+ /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
+ if(hspi->State == HAL_SPI_STATE_READY)
+ {
+ hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
+ }
- /* Configure communication */
- hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ /* Set the transaction information */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+ hspi->pTxBuffPtr = (uint8_t*)pTxData;
+ hspi->TxXferSize = Size;
+ hspi->TxXferCount = Size;
+ hspi->pRxBuffPtr = (uint8_t*)pRxData;
+ hspi->RxXferSize = Size;
+ hspi->RxXferCount = Size;
- hspi->pTxBuffPtr = (uint8_t*)pTxData;
- hspi->TxXferSize = Size;
- hspi->TxXferCount = Size;
+ /* Init field not used in handle to zero */
+ hspi->RxISR = NULL;
+ hspi->TxISR = NULL;
- hspi->pRxBuffPtr = (uint8_t*)pRxData;
- hspi->RxXferSize = Size;
- hspi->RxXferCount = Size;
+#if (USE_SPI_CRC != 0U)
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+#endif /* USE_SPI_CRC */
- /*Init field not used in handle to zero */
- hspi->RxISR = 0;
- hspi->TxISR = 0;
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
- if(hspi->State == HAL_SPI_STATE_BUSY_RX)
- {
- /* Set the SPI Rx DMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-
- hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
- }
- else
- {
- /* Set the SPI Tx/Rx DMA Half transfer complete callback */
- hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
-
- hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
- }
-
- /* Set the DMA error callback */
- hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
- /* Enable the Rx DMA Channel */
- HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
- /* Enable Rx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
- is performed in DMA reception complete callback */
- if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
- {
- /* Set the DMA error callback */
- hspi->hdmatx->XferErrorCallback = SPI_DMAError;
- }
- else
- {
- hspi->hdmatx->XferErrorCallback = NULL;
- }
-
- /* Enable the Tx DMA Channel */
- HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
- /* Check if the SPI is already enabled */
- if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
- {
- /* Enable SPI peripheral */
- __HAL_SPI_ENABLE(hspi);
- }
-
- /* Enable Tx DMA Request */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_OK;
+ /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
+ if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ /* Set the SPI Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
}
else
{
- return HAL_BUSY;
+ /* Set the SPI Tx/Rx DMA Half transfer complete callback */
+ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+ hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
}
+
+ /* Set the DMA error callback */
+ hspi->hdmarx->XferErrorCallback = SPI_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the Rx DMA Stream */
+ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
+
+ /* Enable Rx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
+ is performed in DMA reception complete callback */
+ hspi->hdmatx->XferHalfCpltCallback = NULL;
+ hspi->hdmatx->XferCpltCallback = NULL;
+ hspi->hdmatx->XferErrorCallback = NULL;
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the Tx DMA Stream */
+ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
+
+ /* Check if the SPI is already enabled */
+ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
+ {
+ /* Enable SPI peripheral */
+ __HAL_SPI_ENABLE(hspi);
+ }
+ /* Enable the SPI Error Interrupt Bit */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Enable Tx DMA Request */
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+
+error :
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+ return errorcode;
}
+/**
+ * @brief Abort ongoing transfer (blocking mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
+ * before starting new SPI receive process.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ }
+
+ if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ }
+
+ /* Clear ERRIE interrupts in case of DMA Mode */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */
+ if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ {
+ /* Abort the SPI DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(hspi->hdmatx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ HAL_DMA_Abort(hspi->hdmatx);
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
+
+ /* Wait until TXE flag is set */
+ do
+ {
+ if(count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ break;
+ }
+ }
+ while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+ }
+ /* Abort the SPI DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(hspi->hdmarx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ HAL_DMA_Abort(hspi->hdmarx);
+
+ /* Disable peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
+
+ }
+ }
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+
+ /* Restore hspi->state to ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ return HAL_OK;
+}
/**
- * @brief Pauses the DMA Transfer.
+ * @brief Abort ongoing transfer (Interrupt mode).
+ * @param hspi SPI handle.
+ * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
+ * started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable SPI Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application
+ * before starting new SPI receive process.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
+{
+ uint32_t abortcplt;
+
+ /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
+ if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
+ {
+ hspi->TxISR = SPI_AbortTx_ISR;
+ }
+
+ if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
+ {
+ hspi->RxISR = SPI_AbortRx_ISR;
+ }
+
+ /* Clear ERRIE interrupts in case of DMA Mode */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
+
+ abortcplt = 1U;
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
+ if(hspi->hdmatx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
+ }
+ else
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ }
+ }
+ /* DMA Rx Handle is valid */
+ if(hspi->hdmarx != NULL)
+ {
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
+ }
+ else
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ }
+ }
+
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)))
+ {
+ /* Abort the SPI DMA Tx channel */
+ if(hspi->hdmatx != NULL)
+ {
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ /* Abort the SPI DMA Rx channel */
+ if(hspi->hdmarx != NULL)
+ {
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK)
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ abortcplt = 1U;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
+ {
+ /* Abort the SPI DMA Tx channel */
+ if(hspi->hdmatx != NULL)
+ {
+ /* Abort DMA Tx Handle linked to SPI Peripheral */
+ if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
+ {
+ hspi->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+ /* Disable the SPI DMA Tx or the SPI Rx request if enabled */
+ if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
+ {
+ /* Abort the SPI DMA Rx channel */
+ if(hspi->hdmarx != NULL)
+ {
+ /* Abort DMA Rx Handle linked to SPI Peripheral */
+ if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK)
+ {
+ hspi->hdmarx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ abortcplt = 0U;
+ }
+ }
+ }
+
+ if(abortcplt == 1U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Pause the DMA Transfer.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
+ * the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
{
/* Process Locked */
__HAL_LOCK(hspi);
-
+
/* Disable the SPI DMA Tx & Rx requests */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
/* Process Unlocked */
__HAL_UNLOCK(hspi);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
- * @brief Resumes the DMA Transfer.
+ * @brief Resume the DMA Transfer.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
+ * the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
{
/* Process Locked */
__HAL_LOCK(hspi);
-
+
/* Enable the SPI DMA Tx & Rx requests */
- SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
- SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
+ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
/* Process Unlocked */
__HAL_UNLOCK(hspi);
-
+
return HAL_OK;
}
/**
- * @brief Stops the DMA Transfer.
+ * @brief Stop the DMA Transfer.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for the specified SPI module.
+ * the configuration information for the specified SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
@@ -1542,188 +1920,233 @@
when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
*/
-
- /* Abort the SPI DMA tx Channel */
+
+ /* Abort the SPI DMA tx Stream */
if(hspi->hdmatx != NULL)
{
HAL_DMA_Abort(hspi->hdmatx);
}
- /* Abort the SPI DMA rx Channel */
+ /* Abort the SPI DMA rx Stream */
if(hspi->hdmarx != NULL)
{
HAL_DMA_Abort(hspi->hdmarx);
}
-
+
/* Disable the SPI DMA Tx & Rx requests */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
hspi->State = HAL_SPI_STATE_READY;
-
return HAL_OK;
}
/**
- * @brief This function handles SPI interrupt request.
+ * @brief Handle SPI interrupt request.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for the specified SPI module.
* @retval None
*/
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
{
- /* SPI in mode Receiver and Overrun not occurred ---------------------------*/
- if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
+ uint32_t itsource = hspi->Instance->CR2;
+ uint32_t itflag = hspi->Instance->SR;
+
+ /* SPI in mode Receiver ----------------------------------------------------*/
+ if(((itflag & SPI_FLAG_OVR) == RESET) &&
+ ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET))
{
hspi->RxISR(hspi);
return;
}
- /* SPI in mode Tramitter ---------------------------------------------------*/
- if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
+ /* SPI in mode Transmitter -------------------------------------------------*/
+ if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET))
{
hspi->TxISR(hspi);
return;
}
- if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
+ /* SPI in Error Treatment --------------------------------------------------*/
+ if(((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR)) != RESET) && ((itsource & SPI_IT_ERR) != RESET))
{
- /* SPI CRC error interrupt occurred ---------------------------------------*/
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- /* SPI Mode Fault error interrupt occurred --------------------------------*/
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
- __HAL_SPI_CLEAR_MODFFLAG(hspi);
- }
-
- /* SPI Overrun error interrupt occurred -----------------------------------*/
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
+ /* SPI Overrun error interrupt occurred ----------------------------------*/
+ if((itflag & SPI_FLAG_OVR) != RESET)
{
if(hspi->State != HAL_SPI_STATE_BUSY_TX)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
- __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+ else
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ return;
}
}
- /* Call the Error call Back in case of Errors */
- if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
+ /* SPI Mode Fault error interrupt occurred -------------------------------*/
+ if((itflag & SPI_FLAG_MODF) != RESET)
{
- __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_ErrorCallback(hspi);
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
+ __HAL_SPI_CLEAR_MODFFLAG(hspi);
}
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ /* Disable all interrupts */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
+
+ hspi->State = HAL_SPI_STATE_READY;
+ /* Disable the SPI DMA requests if enabled */
+ if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
+ {
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
+
+ /* Abort the SPI DMA Rx channel */
+ if(hspi->hdmarx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
+ HAL_DMA_Abort_IT(hspi->hdmarx);
+ }
+ /* Abort the SPI DMA Tx channel */
+ if(hspi->hdmatx != NULL)
+ {
+ /* Set the SPI DMA Abort callback :
+ will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
+ hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
+ HAL_DMA_Abort_IT(hspi->hdmatx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ }
+ return;
}
}
/**
- * @brief Tx Transfer completed callbacks
+ * @brief Tx Transfer completed callback.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_TxCpltCallback could be implenetd in the user file
- */
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxCpltCallback should be implemented in the user file
+ */
}
/**
- * @brief Rx Transfer completed callbacks
+ * @brief Rx Transfer completed callback.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_RxCpltCallback() could be implenetd in the user file
- */
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxCpltCallback should be implemented in the user file
+ */
}
/**
- * @brief Tx and Rx Transfer completed callbacks
+ * @brief Tx and Rx Transfer completed callback.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
- */
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxCpltCallback should be implemented in the user file
+ */
}
/**
- * @brief Tx Half Transfer completed callbacks
+ * @brief Tx Half Transfer completed callback.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
- */
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
+ */
}
/**
- * @brief Rx Half Transfer completed callbacks
+ * @brief Rx Half Transfer completed callback.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
- */
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
+ */
}
/**
- * @brief Tx and Rx Transfer completed callbacks
+ * @brief Tx and Rx Half Transfer callback.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
- /* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
- */
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
+ */
}
/**
- * @brief SPI error callbacks
+ * @brief SPI error callback.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hspi);
- /* NOTE : - This function Should not be modified, when the callback is needed,
- the HAL_SPI_ErrorCallback() could be implenetd in the user file.
- - The ErrorCode parameter in the hspi handle is updated by the SPI processes
- and user can use HAL_SPI_GetError() API to check the latest error occurred.
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_ErrorCallback should be implemented in the user file
+ */
+ /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
+ and user can use HAL_SPI_GetError() API to check the latest error occurred
+ */
+}
+
+/**
+ * @brief SPI Abort Complete callback.
+ * @param hspi SPI handle.
+ * @retval None
+ */
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_SPI_AbortCpltCallback can be implemented in the user file.
*/
}
@@ -1731,13 +2154,13 @@
* @}
*/
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief SPI control functions
+/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief SPI control functions
*
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides a set of functions allowing to control the SPI.
(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
@@ -1747,324 +2170,1008 @@
*/
/**
- * @brief Return the SPI state
+ * @brief Return the SPI handle state.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @retval SPI state
*/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
{
+ /* Return SPI handle state */
return hspi->State;
}
/**
- * @brief Return the SPI error code
+ * @brief Return the SPI error code.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval SPI Error Code
+ * the configuration information for SPI module.
+ * @retval SPI error code in bitmap format
*/
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
{
+ /* Return SPI ErrorCode */
return hspi->ErrorCode;
}
/**
* @}
*/
-
+
/**
- * @}
- */
-
-
+ * @}
+ */
/** @addtogroup SPI_Private_Functions
- * @{
- */
+ * @brief Private functions
+ * @{
+ */
-
- /**
- * @brief Interrupt Handler to close Tx transfer
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+/**
+ * @brief DMA SPI transmit process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
-static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
+static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
- /* Wait until TXE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint32_t tickstart = 0U;
+
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* DMA Normal Mode */
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
{
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
- /* Disable TXE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
-
- /* Disable ERR interrupt if Receive process is finished */
- if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
- {
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
-
- /* Wait until Busy flag is reset before disabling SPI */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ /* Check the end of the transaction */
+ if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
- /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+ /* Clear overrun flag in 2 Lines communication mode because received data is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
-
- /* Check if Errors has been detected during transfer */
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+
+ hspi->TxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
- /* Check if we are in Tx or in Rx/Tx Mode */
- if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
- {
- /* Set state to READY before run the Callback Complete */
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_TxRxCpltCallback(hspi);
- }
- else
- {
- /* Set state to READY before run the Callback Complete */
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_TxCpltCallback(hspi);
- }
- }
- else
- {
- /* Set state to READY before run the Callback Complete */
- hspi->State = HAL_SPI_STATE_READY;
- /* Call Error call back in case of Error */
HAL_SPI_ErrorCallback(hspi);
+ return;
}
}
+ HAL_SPI_TxCpltCallback(hspi);
}
/**
- * @brief Interrupt Handler to transmit amount of data in no-blocking mode
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * @brief DMA SPI receive process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
-static void SPI_TxISR(SPI_HandleTypeDef *hspi)
+static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
- /* Transmit data in 8 Bit mode */
- if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
- {
- hspi->Instance->DR = (*hspi->pTxBuffPtr++);
- }
- /* Transmit data in 16 Bit mode */
- else
- {
- hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
- hspi->pTxBuffPtr+=2;
- }
- hspi->TxXferCount--;
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+#if (USE_SPI_CRC != 0U)
+ uint32_t tickstart = 0U;
+ __IO uint16_t tmpreg = 0U;
- if(hspi->TxXferCount == 0)
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+#endif /* USE_SPI_CRC */
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
{
+#if (USE_SPI_CRC != 0U)
+ /* CRC handling */
if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- /* calculate and transfer CRC on Tx line */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ /* Wait until RXNE flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ /* Error on the CRC reception */
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read CRC */
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
}
- SPI_TxCloseIRQHandler(hspi);
- }
-}
+#endif /* USE_SPI_CRC */
-/**
- * @brief Interrupt Handler to close Rx transfer
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
-{
- __IO uint16_t tmpreg = 0;
+ /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Wait until RXNE flag is set to read CRC data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ /* Check the end of the transaction */
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
{
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
}
- /* Read CRC to reset RXNE flag */
- tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg);
+ hspi->RxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
- /* Wait until RXNE flag is reset */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
+#if (USE_SPI_CRC != 0U)
/* Check if CRC error occurred */
if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
{
/* Check if CRC error is valid or not (workaround to be applied or not) */
- if ( (hspi->State != HAL_SPI_STATE_BUSY_RX)
- || (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) )
+ if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
/* Reset CRC Calculation */
SPI_RESET_CRC(hspi);
+ }
+ else
+ {
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_RxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI transmit receive process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ uint32_t tickstart = 0U;
+#if (USE_SPI_CRC != 0U)
+ __IO int16_t tmpreg = 0U;
+#endif /* USE_SPI_CRC */
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
+
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
+ {
+#if (USE_SPI_CRC != 0U)
+ /* CRC handling */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Wait the CRC data */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+ }
+ /* Read CRC to Flush DR and RXNE flag */
+ tmpreg = hspi->Instance->DR;
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+ }
+#endif /* USE_SPI_CRC */
+ /* Check the end of the transaction */
+ if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Disable Rx/Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ hspi->TxXferCount = 0U;
+ hspi->RxXferCount = 0U;
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ /* Check if CRC error is valid or not (workaround to be applied or not) */
+ if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+
+ /* Reset CRC Calculation */
+ SPI_RESET_CRC(hspi);
+ }
+ else
+ {
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+ }
+#endif /* USE_SPI_CRC */
+
+ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+ {
+ HAL_SPI_ErrorCallback(hspi);
+ return;
+ }
+ }
+ HAL_SPI_TxRxCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half transmit process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_TxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half receive process complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_RxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI half transmit receive process complete callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ HAL_SPI_TxRxHalfCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI communication error callback.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void SPI_DMAError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+/* Stop the disable DMA transfer on SPI side */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
+
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_ErrorCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ HAL_SPI_ErrorCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ hspi->hdmatx->XferAbortCallback = NULL;
+
+ /* Disable Tx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN );
+
+ /* Wait until TXE flag is set */
+ do
+ {
+ if(count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ break;
+ }
+ }
+ while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+
+ /* Check if an Abort process is still ongoing */
+ if(hspi->hdmarx != NULL)
+ {
+ if(hspi->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+}
+
+/**
+ * @brief DMA SPI Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ hspi->hdmarx->XferAbortCallback = NULL;
+
+ /* Disable Rx DMA Request */
+ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
+
+ /* Check if an Abort process is still ongoing */
+ if(hspi->hdmatx != NULL)
+ {
+ if(hspi->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ hspi->RxXferCount = 0U;
+ hspi->TxXferCount = 0U;
+
+ /* Reset errorCode */
+ hspi->ErrorCode = HAL_SPI_ERROR_NONE;
+
+ /* Clear the Error flags in the SR register */
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+
+ /* Restore hspi->State to Ready */
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_SPI_AbortCpltCallback(hspi);
+}
+
+/**
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 8bit mode */
+ *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
+ hspi->RxXferCount--;
+
+ /* check end of the reception */
+ if(hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_2linesRxISR_8BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ if(hspi->TxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint8_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
+
+ /* To avoid GCC warning */
+
+ UNUSED(tmpreg);
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ if(hspi->TxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+
+ /* check the end of the transmission */
+ if(hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+ if(hspi->RxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+/**
+ * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 16 Bit mode */
+ *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+ if(hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_2linesRxISR_16BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ if(hspi->TxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Receive data in 16 Bit mode */
+ __IO uint16_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = hspi->Instance->DR;
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ /* Disable RXNE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
+
+ SPI_CloseRxTx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 16 Bit mode */
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ /* Enable CRC Transmission */
+ if(hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+ return;
+ }
+#endif /* USE_SPI_CRC */
+
+ /* Disable TXE interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
+
+ if(hspi->RxXferCount == 0U)
+ {
+ SPI_CloseRxTx_ISR(hspi);
+ }
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Manage the CRC 8-bit receive in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint8_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ SPI_CloseRx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Manage the receive 8-bit in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
+ hspi->RxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
+ if(hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_RxISR_8BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+#if (USE_SPI_CRC != 0U)
+/**
+ * @brief Manage the CRC 16-bit receive in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
+{
+ __IO uint16_t tmpreg = 0U;
+
+ /* Read data register to flush CRC */
+ tmpreg = hspi->Instance->DR;
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ SPI_CloseRx_ISR(hspi);
+}
+#endif /* USE_SPI_CRC */
+
+/**
+ * @brief Manage the 16-bit receive in Interrupt context.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
+ hspi->pRxBuffPtr += sizeof(uint16_t);
+ hspi->RxXferCount--;
+
+#if (USE_SPI_CRC != 0U)
+ /* Enable CRC Transmission */
+ if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+
+ if(hspi->RxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ hspi->RxISR = SPI_RxISR_16BITCRC;
+ return;
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseRx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle the data 8-bit transmit in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
+ hspi->TxXferCount--;
+
+ if(hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Enable CRC Transmission */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseTx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle the data 16-bit transmit in Interrupt mode.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
+{
+ /* Transmit data in 16 Bit mode */
+ hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
+ hspi->pTxBuffPtr += sizeof(uint16_t);
+ hspi->TxXferCount--;
+
+ if(hspi->TxXferCount == 0U)
+ {
+#if (USE_SPI_CRC != 0U)
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ /* Enable CRC Transmission */
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
+ }
+#endif /* USE_SPI_CRC */
+ SPI_CloseTx_ISR(hspi);
+ }
+}
+
+/**
+ * @brief Handle SPI Communication Timeout.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Flag: SPI flag to check
+ * @param State: flag state to check
+ * @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
+{
+ while((((hspi->Instance->SR & Flag) == (Flag)) ? SET : RESET) != State)
+ {
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout))
+ {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State= HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ return HAL_OK;
+}
+/**
+ * @brief Handle to check BSY flag before start a new transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Timeout: Timeout duration
+ * @param Tickstart: tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
+{
+ /* Control the BSY flag */
+ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ return HAL_TIMEOUT;
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle the end of the RXTX transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ uint32_t tickstart = 0U;
+ __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+ /* Init tickstart for timeout managment*/
+ tickstart = HAL_GetTick();
+
+ /* Disable ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
+
+ /* Wait until TXE flag is set */
+ do
+ {
+ if(count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ break;
+ }
+ }
+ while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+
+ /* Check the end of the transaction */
+ if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ /* Check if CRC error is valid or not (workaround to be applied or not) */
+ if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+
+ /* Reset CRC Calculation */
+ SPI_RESET_CRC(hspi);
+
+ HAL_SPI_ErrorCallback(hspi);
+ }
+ else
+ {
+ __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
+ }
+ }
+ else
+ {
+#endif /* USE_SPI_CRC */
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
+ {
+ if(hspi->State == HAL_SPI_STATE_BUSY_RX)
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_RxCpltCallback(hspi);
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_TxRxCpltCallback(hspi);
+ }
+ }
+ else
+ {
+ hspi->State = HAL_SPI_STATE_READY;
+ HAL_SPI_ErrorCallback(hspi);
+ }
+#if (USE_SPI_CRC != 0U)
+ }
+#endif /* USE_SPI_CRC */
+}
+
+/**
+ * @brief Handle the end of the RX transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable RXNE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
+
+ /* Check the end of the transaction */
+ if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
+ if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
+ {
+ __HAL_SPI_CLEAR_OVRFLAG(hspi);
+ }
+ hspi->State = HAL_SPI_STATE_READY;
+
+#if (USE_SPI_CRC != 0U)
+ /* Check if CRC error occurred */
+ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
+ {
+ /* Check if CRC error is valid or not (workaround to be applied or not) */
+ if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
+
+ /* Reset CRC Calculation */
+ SPI_RESET_CRC(hspi);
+
+ HAL_SPI_ErrorCallback(hspi);
}
else
{
__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
}
}
- }
-
- /* Disable RXNE interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
-
- /* if Transmit process is finished */
- if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
- {
- /* Disable ERR interrupt */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
-
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ else
{
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- /* Check if Errors has been detected during transfer */
- if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
- {
- /* Check if we are in Rx or in Rx/Tx Mode */
- if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
+#endif /* USE_SPI_CRC */
+ if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
{
- /* Set state to READY before run the Callback Complete */
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_TxRxCpltCallback(hspi);
+ HAL_SPI_RxCpltCallback(hspi);
}
else
{
- /* Set state to READY before run the Callback Complete */
- hspi->State = HAL_SPI_STATE_READY;
- HAL_SPI_RxCpltCallback(hspi);
+ HAL_SPI_ErrorCallback(hspi);
}
+#if (USE_SPI_CRC != 0U)
}
- else
- {
- /* Set state to READY before run the Callback Complete */
- hspi->State = HAL_SPI_STATE_READY;
- /* Call Error call back in case of Error */
- HAL_SPI_ErrorCallback(hspi);
- }
- }
+#endif /* USE_SPI_CRC */
}
/**
- * @brief Interrupt Handler to receive amount of data in 2Lines mode
+ * @brief Handle the end of the TX transaction.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
+ * the configuration information for SPI module.
* @retval None
*/
-static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
+static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
{
- /* Receive data in 8 Bit mode */
- if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
- {
- (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
- }
- /* Receive data in 16 Bit mode */
- else
- {
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr+=2;
- }
- hspi->RxXferCount--;
+ uint32_t tickstart = 0U;
+ __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
- if(hspi->RxXferCount==0)
- {
- SPI_RxCloseIRQHandler(hspi);
- }
-}
+ /* Init tickstart for timeout management*/
+ tickstart = HAL_GetTick();
-/**
- * @brief Interrupt Handler to receive amount of data in no-blocking mode
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @retval None
- */
-static void SPI_RxISR(SPI_HandleTypeDef *hspi)
-{
- /* Receive data in 8 Bit mode */
- if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
+ /* Wait until TXE flag is set */
+ do
{
- (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
- }
- /* Receive data in 16 Bit mode */
- else
- {
- *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
- hspi->pRxBuffPtr+=2;
- }
- hspi->RxXferCount--;
-
- /* Enable CRC Transmission */
- if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
- {
- /* Set CRC Next to calculate CRC on Rx side */
- SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
- }
-
- if(hspi->RxXferCount == 0)
- {
- SPI_RxCloseIRQHandler(hspi);
- }
-}
-
-/**
- * @brief DMA SPI transmit process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* DMA Normal Mode */
- if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
- {
- /* Wait until TXE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
+ if(count-- == 0U)
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ break;
}
+ }
+ while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
+ /* Disable TXE and ERR interrupt */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
- /* Wait until Busy flag is reset before disabling SPI */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- hspi->TxXferCount = 0;
- hspi->State = HAL_SPI_STATE_READY;
+ /* Check Busy flag */
+ if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
}
- /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
+ /* Clear overrun flag in 2 Lines communication mode because received is not read */
if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
}
- /* Check if Errors has been detected during transfer */
+ hspi->State = HAL_SPI_STATE_READY;
if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
{
HAL_SPI_ErrorCallback(hspi);
@@ -2076,311 +3183,58 @@
}
/**
- * @brief DMA SPI receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- __IO uint16_t tmpreg = 0;
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- /* DMA Normal mode */
- if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
- {
- /* Disable Rx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
- /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
- /* CRC Calculation handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Wait until RXNE flag is set (CRC ready) */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Read CRC */
- tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg);
-
- /* Wait until RXNE flag is reset */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- /* Check if CRC error is valid or not (workaround to be applied or not) */
- if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
- /* Reset CRC Calculation */
- SPI_RESET_CRC(hspi);
- }
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
-
- if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- hspi->RxXferCount = 0;
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Check if Errors has been detected during transfer */
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_ErrorCallback(hspi);
- }
- else
- {
- HAL_SPI_RxCpltCallback(hspi);
- }
- }
- else
- {
- HAL_SPI_RxCpltCallback(hspi);
- }
-}
-
-/**
- * @brief DMA SPI transmit receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- __IO uint16_t tmpreg = 0;
-
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
- {
- /* CRC Calculation handling */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- /* Check if CRC is done on going (RXNE flag set) */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
- {
- /* Wait until RXNE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
- }
- /* Read CRC */
- tmpreg = hspi->Instance->DR;
- UNUSED(tmpreg);
-
- /* Check if CRC error occurred */
- if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
- __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
- }
- }
-
- /* Wait until TXE flag is set to send data */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Disable Tx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
- /* Wait until Busy flag is reset before disabling SPI */
- if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
- {
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
- }
-
- /* Disable Rx DMA Request */
- CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
- hspi->TxXferCount = 0;
- hspi->RxXferCount = 0;
-
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Check if Errors has been detected during transfer */
- if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
- {
- HAL_SPI_ErrorCallback(hspi);
- }
- else
- {
- HAL_SPI_TxRxCpltCallback(hspi);
- }
- }
- else
- {
- HAL_SPI_TxRxCpltCallback(hspi);
- }
-}
-
-/**
- * @brief DMA SPI half transmit process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_SPI_TxHalfCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI half receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_SPI_RxHalfCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI Half transmit receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
- HAL_SPI_TxRxHalfCpltCallback(hspi);
-}
-
-/**
- * @brief DMA SPI communication error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
- * @retval None
- */
-static void SPI_DMAError(DMA_HandleTypeDef *hdma)
-{
- SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- hspi->TxXferCount = 0;
- hspi->RxXferCount = 0;
- hspi->State= HAL_SPI_STATE_READY;
- SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
- HAL_SPI_ErrorCallback(hspi);
-}
-
-/**
- * @brief This function handles SPI Communication Timeout.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Flag: SPI flag to check
- * @param Status: Flag status to check: RESET or set
- * @param Timeout: Timeout duration
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
-{
- uint32_t tickstart = 0;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until flag is set */
- if(Status == RESET)
- {
- while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable the SPI and reset the CRC: the CRC value should be cleared
- on both master and slave sides in order to resynchronize the master
- and slave for their respective CRC calculation */
-
- /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- hspi->State= HAL_SPI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
- {
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable the SPI and reset the CRC: the CRC value should be cleared
- on both master and slave sides in order to resynchronize the master
- and slave for their respective CRC calculation */
-
- /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
-
- /* Reset CRC Calculation */
- if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- hspi->State= HAL_SPI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
- return HAL_OK;
-}
-
-/**
* @}
*/
-/** @addtogroup SPI_Private_Functions
- * @{
+/**
+ * @brief Handle abort a Tx or Rx transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
*/
+static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
+{
+ __IO uint32_t tmpreg = 0U;
+ __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
+
+ /* Wait until TXE flag is set */
+ do
+ {
+ if(count-- == 0U)
+ {
+ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
+ break;
+ }
+ }
+ while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+
+ /* Flush DR Register */
+ tmpreg = (*(__IO uint32_t *)&hspi->Instance->DR);
+
+ /* To avoid GCC warning */
+ UNUSED(tmpreg);
+}
+
+/**
+ * @brief Handle abort a Tx or Rx transaction.
+ * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @retval None
+ */
+static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
+{
+ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
+ CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
+
+ /* Disable SPI Peripheral */
+ __HAL_SPI_DISABLE(hspi);
+}
/**
* @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
@@ -2391,14 +3245,16 @@
*/
__weak uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
return (SPI_VALID_CRC_ERROR);
}
/**
* @}
*/
-
-
#endif /* HAL_SPI_MODULE_ENABLED */
+
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_spi_ex.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_spi_ex.c
index 03e1d7e..e5e90e7 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_spi_ex.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_spi_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_spi_ex.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Extended SPI HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -53,8 +53,9 @@
#ifdef HAL_SPI_MODULE_ENABLED
/** @defgroup SPI_Private_Variables SPI Private Variables
- * @{
- */
+ * @{
+ */
+#if (USE_SPI_CRC != 0U)
/* Variable used to determine if device is impacted by implementation of workaround
related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are:
- STM32F101CDE/STM32F103CDE
@@ -66,7 +67,8 @@
+ Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
If CRCERR is found reset, the complete data transfer is considered successful.
*/
-uint8_t uCRCErrorWorkaroundCheck = 0;
+uint8_t uCRCErrorWorkaroundCheck = 0U;
+#endif /* USE_SPI_CRC */
/**
* @}
*/
@@ -84,7 +86,7 @@
*/
/** @addtogroup SPI_Exported_Functions_Group1
- *
+ *
* @{
*/
@@ -106,16 +108,23 @@
/* Check the parameters */
assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
assert_param(IS_SPI_MODE(hspi->Init.Mode));
- assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
+ assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
- assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
+
+#if (USE_SPI_CRC != 0U)
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
- assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
+ }
+#else
+ hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+#endif /* USE_SPI_CRC */
if(hspi->State == HAL_SPI_STATE_RESET)
{
@@ -136,17 +145,18 @@
hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
/* Configure : NSS management */
- WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode));
+ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
/*---------------------------- SPIx CRCPOLY Configuration ------------------*/
/* Configure : CRC Polynomial */
WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
-#if defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
+#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif
+#endif /* SPI_I2SCFGR_I2SMOD */
+#if (USE_SPI_CRC != 0U)
#if defined (STM32F101xE) || defined (STM32F103xE)
/* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
CRC errors wrongly detected */
@@ -154,10 +164,11 @@
Revision ID information is only available in Debug mode, so Workaround could not be implemented
to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */
- uCRCErrorWorkaroundCheck = 0;
+ uCRCErrorWorkaroundCheck = 0U;
#else
- uCRCErrorWorkaroundCheck = 0;
-#endif
+ uCRCErrorWorkaroundCheck = 0U;
+#endif /* STM32F101xE || STM32F103xE */
+#endif /* USE_SPI_CRC */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
hspi->State = HAL_SPI_STATE_READY;
@@ -176,7 +187,7 @@
/** @addtogroup SPI_Private_Functions
* @{
*/
-
+#if (USE_SPI_CRC != 0U)
/**
* @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
* according to SPI instance, Device type, and revision ID.
@@ -186,21 +197,26 @@
*/
uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
{
-#if defined (STM32F101xE) || defined (STM32F103xE)
+#if defined(STM32F101xE) || defined(STM32F103xE)
/* Check how to handle this CRC error (workaround to be applied or not) */
/* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
- if ( (uCRCErrorWorkaroundCheck != 0) && (hspi->Instance == SPI2) )
+ if((uCRCErrorWorkaroundCheck != 0U) && (hspi->Instance == SPI2))
{
- if (hspi->Instance->RXCRCR == 0)
+ if(hspi->Instance->RXCRCR == 0U)
{
return (SPI_INVALID_CRC_ERROR);
}
}
return (SPI_VALID_CRC_ERROR);
#else
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hspi);
+
return (SPI_VALID_CRC_ERROR);
#endif
}
+#endif /* USE_SPI_CRC */
+
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sram.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sram.c
index a1dbe0d..aea83e0 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sram.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_sram.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_sram.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
@@ -291,7 +291,7 @@
hsram->State = HAL_SRAM_STATE_BUSY;
/* Read data from memory */
- for(; BufferSize != 0; BufferSize--)
+ for(; BufferSize != 0U; BufferSize--)
{
*pDstBuffer = *(__IO uint8_t *)psramaddress;
pDstBuffer++;
@@ -333,7 +333,7 @@
hsram->State = HAL_SRAM_STATE_BUSY;
/* Write data to memory */
- for(; BufferSize != 0; BufferSize--)
+ for(; BufferSize != 0U; BufferSize--)
{
*(__IO uint8_t *)psramaddress = *pSrcBuffer;
pSrcBuffer++;
@@ -369,7 +369,7 @@
hsram->State = HAL_SRAM_STATE_BUSY;
/* Read data from memory */
- for(; BufferSize != 0; BufferSize--)
+ for(; BufferSize != 0U; BufferSize--)
{
*pDstBuffer = *(__IO uint16_t *)psramaddress;
pDstBuffer++;
@@ -411,7 +411,7 @@
hsram->State = HAL_SRAM_STATE_BUSY;
/* Write data to memory */
- for(; BufferSize != 0; BufferSize--)
+ for(; BufferSize != 0U; BufferSize--)
{
*(__IO uint16_t *)psramaddress = *pSrcBuffer;
pSrcBuffer++;
@@ -445,7 +445,7 @@
hsram->State = HAL_SRAM_STATE_BUSY;
/* Read data from memory */
- for(; BufferSize != 0; BufferSize--)
+ for(; BufferSize != 0U; BufferSize--)
{
*pDstBuffer = *(__IO uint32_t *)pAddress;
pDstBuffer++;
@@ -485,7 +485,7 @@
hsram->State = HAL_SRAM_STATE_BUSY;
/* Write data to memory */
- for(; BufferSize != 0; BufferSize--)
+ for(; BufferSize != 0U; BufferSize--)
{
*(__IO uint32_t *)pAddress = *pSrcBuffer;
pSrcBuffer++;
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim.c
index 11f5bae..c548545 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_tim.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief TIM HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@@ -215,6 +215,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if(htim->State == HAL_TIM_STATE_RESET)
{
@@ -396,7 +397,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((pData == 0 ) && (Length > 0))
+ if((pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -490,6 +491,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if(htim->State == HAL_TIM_STATE_RESET)
{
@@ -787,7 +789,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -994,6 +996,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if(htim->State == HAL_TIM_STATE_RESET)
{
@@ -1141,7 +1144,7 @@
/**
* @brief Starts the PWM signal generation in interrupt mode.
* @param htim : TIM handle
- * @param Channel : TIM Channel to be disabled
+ * @param Channel : TIM Channel to be enabled
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1294,7 +1297,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1501,6 +1504,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if(htim->State == HAL_TIM_STATE_RESET)
{
@@ -1774,7 +1778,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((pData == 0 ) && (Length > 0))
+ if((pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1974,6 +1978,7 @@
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_OPM_MODE(OnePulseMode));
if(htim->State == HAL_TIM_STATE_RESET)
@@ -2069,6 +2074,9 @@
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
/* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
@@ -2102,6 +2110,9 @@
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
/* Disable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
@@ -2135,6 +2146,9 @@
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
/* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
@@ -2174,6 +2188,9 @@
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
@@ -2234,9 +2251,9 @@
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
{
- uint32_t tmpsmcr = 0;
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpsmcr = 0U;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
/* Check the TIM handle allocation */
if(htim == NULL)
@@ -2246,6 +2263,9 @@
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
+ assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
@@ -2288,18 +2308,18 @@
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
+ tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
/* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
- tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
+ tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
/* Set the TI1 and the TI2 Polarities */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
- tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
+ tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
@@ -2581,7 +2601,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
+ if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -2761,7 +2781,7 @@
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
/* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
{
HAL_TIM_IC_CaptureCallback(htim);
}
@@ -2783,7 +2803,7 @@
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
- if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
+ if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
{
HAL_TIM_IC_CaptureCallback(htim);
}
@@ -2804,7 +2824,7 @@
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
/* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
{
HAL_TIM_IC_CaptureCallback(htim);
}
@@ -2825,7 +2845,7 @@
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
/* Input capture event */
- if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
+ if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
{
HAL_TIM_IC_CaptureCallback(htim);
}
@@ -3022,7 +3042,7 @@
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
/* Set the IC2PSC value */
- htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
+ htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
}
else if (Channel == TIM_CHANNEL_3)
{
@@ -3054,7 +3074,7 @@
htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
/* Set the IC4PSC value */
- htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
+ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
}
htim->State = HAL_TIM_STATE_READY;
@@ -3328,7 +3348,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((BurstBuffer == 0 ) && (BurstLength > 0))
+ if((BurstBuffer == 0U) && (BurstLength > 0U))
{
return HAL_ERROR;
}
@@ -3348,7 +3368,7 @@
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC1:
@@ -3360,7 +3380,7 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC2:
@@ -3372,7 +3392,7 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC3:
@@ -3384,7 +3404,7 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC4:
@@ -3396,7 +3416,7 @@
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_COM:
@@ -3408,7 +3428,7 @@
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_TRIGGER:
@@ -3420,7 +3440,7 @@
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U);
}
break;
default:
@@ -3551,7 +3571,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if((BurstBuffer == 0 ) && (BurstLength > 0))
+ if((BurstBuffer == 0U) && (BurstLength > 0U))
{
return HAL_ERROR;
}
@@ -3571,7 +3591,7 @@
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC1:
@@ -3583,7 +3603,7 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC2:
@@ -3595,7 +3615,7 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC3:
@@ -3607,7 +3627,7 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_CC4:
@@ -3619,7 +3639,7 @@
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_COM:
@@ -3631,7 +3651,7 @@
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
}
break;
case TIM_DMA_TRIGGER:
@@ -3643,7 +3663,7 @@
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
+ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U);
}
break;
default:
@@ -3779,7 +3799,7 @@
*/
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
{
- uint32_t tmpsmcr = 0;
+ uint32_t tmpsmcr = 0U;
/* Check the parameters */
assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
@@ -3797,8 +3817,6 @@
{
case TIM_CLEARINPUTSOURCE_NONE:
{
- /* Clear the OCREF clear selection bit */
- tmpsmcr &= ~TIM_SMCR_OCCS;
/* Clear the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
@@ -3815,8 +3833,6 @@
sClearInputConfig->ClearInputPolarity,
sClearInputConfig->ClearInputFilter);
- /* Set the OCREF clear selection bit */
- htim->Instance->SMCR |= TIM_SMCR_OCCS;
}
break;
default:
@@ -3904,7 +3920,7 @@
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
{
- uint32_t tmpsmcr = 0;
+ uint32_t tmpsmcr = 0U;
/* Process Locked */
__HAL_LOCK(htim);
@@ -4078,7 +4094,7 @@
*/
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
{
- uint32_t tmpcr2 = 0;
+ uint32_t tmpcr2 = 0U;
/* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
@@ -4183,7 +4199,7 @@
*/
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
__HAL_LOCK(htim);
@@ -4552,7 +4568,7 @@
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
- uint32_t tmpcr1 = 0;
+ uint32_t tmpcr1 = 0U;
tmpcr1 = TIMx->CR1;
/* Set TIM Time Base Unit parameters ---------------------------------------*/
@@ -4570,6 +4586,10 @@
tmpcr1 |= (uint32_t)Structure->ClockDivision;
}
+ /* Set the auto-reload preload */
+ tmpcr1 &= ~TIM_CR1_ARPE;
+ tmpcr1 |= (uint32_t)Structure->AutoReloadPreload;
+
TIMx->CR1 = tmpcr1;
/* Set the Autoreload value */
@@ -4597,9 +4617,9 @@
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
@@ -4671,9 +4691,9 @@
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
@@ -4691,12 +4711,12 @@
tmpccmrx &= ~TIM_CCMR1_CC2S;
/* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8);
+ tmpccmrx |= (OC_Config->OCMode << 8U);
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
/* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 4);
+ tmpccer |= (OC_Config->OCPolarity << 4U);
if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
{
@@ -4705,7 +4725,7 @@
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
/* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 4);
+ tmpccer |= (OC_Config->OCNPolarity << 4U);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
@@ -4747,9 +4767,9 @@
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
@@ -4771,7 +4791,7 @@
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
/* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 8);
+ tmpccer |= (OC_Config->OCPolarity << 8U);
if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
{
@@ -4780,7 +4800,7 @@
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
/* Set the Output N Polarity */
- tmpccer |= (OC_Config->OCNPolarity << 8);
+ tmpccer |= (OC_Config->OCNPolarity << 8U);
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
}
@@ -4795,9 +4815,9 @@
tmpcr2 &= ~TIM_CR2_OIS3;
tmpcr2 &= ~TIM_CR2_OIS3N;
/* Set the Output Idle state */
- tmpcr2 |= (OC_Config->OCIdleState << 4);
+ tmpcr2 |= (OC_Config->OCIdleState << 4U);
/* Set the Output N Idle state */
- tmpcr2 |= (OC_Config->OCNIdleState << 4);
+ tmpcr2 |= (OC_Config->OCNIdleState << 4U);
}
/* Write to TIMx CR2 */
@@ -4821,9 +4841,9 @@
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- uint32_t tmpccmrx = 0;
- uint32_t tmpccer = 0;
- uint32_t tmpcr2 = 0;
+ uint32_t tmpccmrx = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
@@ -4841,12 +4861,12 @@
tmpccmrx &= ~TIM_CCMR2_CC4S;
/* Select the Output Compare Mode */
- tmpccmrx |= (OC_Config->OCMode << 8);
+ tmpccmrx |= (OC_Config->OCMode << 8U);
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
/* Set the Output Compare Polarity */
- tmpccer |= (OC_Config->OCPolarity << 12);
+ tmpccer |= (OC_Config->OCPolarity << 12U);
if(IS_TIM_BREAK_INSTANCE(TIMx))
{
@@ -4882,9 +4902,9 @@
static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef * sSlaveConfig)
{
- uint32_t tmpsmcr = 0;
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpsmcr = 0U;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
@@ -4933,7 +4953,7 @@
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
+ tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
/* Write to TIMx CCMR1 and CCER registers */
htim->Instance->CCMR1 = tmpccmr1;
@@ -5010,7 +5030,6 @@
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
* @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
@@ -5026,8 +5045,8 @@
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
@@ -5047,7 +5066,7 @@
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
+ tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
@@ -5064,16 +5083,15 @@
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @arg TIM_ICPOLARITY_FALLING
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
@@ -5082,7 +5100,7 @@
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
- tmpccmr1 |= (TIM_ICFilter << 4);
+ tmpccmr1 |= (TIM_ICFilter << 4U);
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
@@ -5099,8 +5117,7 @@
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @arg TIM_ICPOLARITY_FALLING
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
@@ -5116,8 +5133,8 @@
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
@@ -5126,15 +5143,15 @@
/* Select the Input */
tmpccmr1 &= ~TIM_CCMR1_CC2S;
- tmpccmr1 |= (TIM_ICSelection << 8);
+ tmpccmr1 |= (TIM_ICSelection << 8U);
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
+ tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
+ tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
@@ -5147,16 +5164,15 @@
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @arg TIM_ICPOLARITY_FALLING
* @param TIM_ICFilter : Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr1 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
@@ -5165,11 +5181,11 @@
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
- tmpccmr1 |= (TIM_ICFilter << 12);
+ tmpccmr1 |= (TIM_ICFilter << 12U);
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (TIM_ICPolarity << 4);
+ tmpccer |= (TIM_ICPolarity << 4U);
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
@@ -5182,8 +5198,7 @@
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @arg TIM_ICPOLARITY_FALLING
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
@@ -5199,8 +5214,8 @@
static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr2 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
/* Disable the Channel 3: Reset the CC3E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
@@ -5213,11 +5228,11 @@
/* Set the filter */
tmpccmr2 &= ~TIM_CCMR2_IC3F;
- tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
+ tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
/* Select the Polarity and set the CC3E Bit */
tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
- tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
+ tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
/* Write to TIMx CCMR2 and CCER registers */
TIMx->CCMR2 = tmpccmr2;
@@ -5230,8 +5245,7 @@
* @param TIM_ICPolarity : The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPOLARITY_RISING
- * @arg TIM_ICPOLARITY_FALLING
- * @arg TIM_ICPOLARITY_BOTHEDGE
+ * @arg TIM_ICPOLARITY_FALLING
* @param TIM_ICSelection : specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
@@ -5247,8 +5261,8 @@
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
- uint32_t tmpccmr2 = 0;
- uint32_t tmpccer = 0;
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
@@ -5257,15 +5271,15 @@
/* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC4S;
- tmpccmr2 |= (TIM_ICSelection << 8);
+ tmpccmr2 |= (TIM_ICSelection << 8U);
/* Set the filter */
tmpccmr2 &= ~TIM_CCMR2_IC4F;
- tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
+ tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
/* Select the Polarity and set the CC4E Bit */
- tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
- tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
+ tmpccer &= ~TIM_CCER_CC4P;
+ tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P);
/* Write to TIMx CCMR2 and CCER registers */
TIMx->CCMR2 = tmpccmr2;
@@ -5289,7 +5303,7 @@
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
{
- uint32_t tmpsmcr = 0;
+ uint32_t tmpsmcr = 0U;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
@@ -5320,7 +5334,7 @@
static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
- uint32_t tmpsmcr = 0;
+ uint32_t tmpsmcr = 0U;
tmpsmcr = TIMx->SMCR;
@@ -5328,7 +5342,7 @@
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
/* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
+ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
@@ -5349,7 +5363,7 @@
*/
void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
{
- uint32_t tmp = 0;
+ uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim_ex.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim_ex.c
index d2c2626..b028276 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim_ex.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_tim_ex.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_tim_ex.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer Extended peripheral:
@@ -177,6 +177,7 @@
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+ assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
@@ -400,7 +401,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -625,7 +626,7 @@
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
- uint32_t tmpccer = 0;
+ uint32_t tmpccer = 0U;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -709,7 +710,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1041,7 +1042,7 @@
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
{
- uint32_t tmpccer = 0;
+ uint32_t tmpccer = 0U;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
@@ -1125,7 +1126,7 @@
}
else if((htim->State == HAL_TIM_STATE_READY))
{
- if(((uint32_t)pData == 0 ) && (Length > 0))
+ if(((uint32_t)pData == 0U) && (Length > 0U))
{
return HAL_ERROR;
}
@@ -1625,6 +1626,8 @@
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
+ uint32_t tmpbdtr = 0U;
+
/* Check the parameters */
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
@@ -1638,21 +1641,22 @@
/* Process Locked */
__HAL_LOCK(htim);
- htim->State = HAL_TIM_STATE_BUSY;
-
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
- htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode |
- sBreakDeadTimeConfig->OffStateIDLEMode |
- sBreakDeadTimeConfig->LockLevel |
- sBreakDeadTimeConfig->DeadTime |
- sBreakDeadTimeConfig->BreakState |
- sBreakDeadTimeConfig->BreakPolarity |
- sBreakDeadTimeConfig->AutomaticOutput;
-
-
- htim->State = HAL_TIM_STATE_READY;
-
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
+
+ /* Set TIMx_BDTR */
+ htim->Instance->BDTR = tmpbdtr;
+
__HAL_UNLOCK(htim);
return HAL_OK;
@@ -1826,7 +1830,7 @@
*/
static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
{
- uint32_t tmp = 0;
+ uint32_t tmp = 0U;
tmp = TIM_CCER_CC1NE << Channel;
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_rtc_alarm_template.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_rtc_alarm_template.c
new file mode 100644
index 0000000..afbab19
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_rtc_alarm_template.c
@@ -0,0 +1,307 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_timebase_rtc_alarm_template.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief HAL time base based on the hardware RTC_ALARM.
+ *
+ * This file override the native HAL time base functions (defined as weak)
+ * to use the RTC ALARM for time base generation:
+ * + Intializes the RTC peripheral to increment the seconds registers each 1ms
+ * + The alarm is configured to assert an interrupt when the RTC reaches 1ms
+ * + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00
+ * + HSE (default), LSE or LSI can be selected as RTC clock source
+ @verbatim
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This file must be copied to the application folder and modified as follows:
+ (#) Rename it to 'stm32f1xx_hal_timebase_rtc_alarm.c'
+ (#) Add this file and the RTC HAL drivers to your project and uncomment
+ HAL_RTC_MODULE_ENABLED define in stm32f1xx_hal_conf.h
+
+ [..]
+ (@) HAL RTC alarm and HAL RTC wakeup drivers canÂ’t be used with low power modes:
+ The wake up capability of the RTC may be intrusive in case of prior low power mode
+ configuration requiring different wake up sources.
+ Application/Example behavior is no more guaranteed
+ (@) The stm32f1xx_hal_timebase_tim use is recommended for the Applications/Examples
+ requiring low power modes
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup HAL_TimeBase_RTC_Alarm_Template HAL TimeBase RTC Alarm Template
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Uncomment the line below to select the appropriate RTC Clock source for your application:
+ + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
+ + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
+ precision.
+ + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
+ precision.
+ */
+#define RTC_CLOCK_SOURCE_HSE
+/* #define RTC_CLOCK_SOURCE_LSE */
+/* #define RTC_CLOCK_SOURCE_LSI */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+RTC_HandleTypeDef hRTC_Handle;
+/* Private function prototypes -----------------------------------------------*/
+void RTC_Alarm_IRQHandler(void);
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief This function configures the RTC_ALARMA as a time base source.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+ * @param TickPriority: Tick interrupt priority.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
+{
+ __IO uint32_t counter = 0U;
+
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+#ifdef RTC_CLOCK_SOURCE_LSE
+ /* Configue LSE as RTC clock soucre */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+#elif defined (RTC_CLOCK_SOURCE_LSI)
+ /* Configue LSI as RTC clock soucre */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
+#elif defined (RTC_CLOCK_SOURCE_HSE)
+ /* Configue HSE as RTC clock soucre */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV128;
+#else
+#error Please select the RTC Clock source
+#endif /* RTC_CLOCK_SOURCE_LSE */
+
+ if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
+ {
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
+ if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
+ {
+ /* Enable RTC Clock */
+ __HAL_RCC_RTC_ENABLE();
+
+ hRTC_Handle.Instance = RTC;
+ /* Configure RTC time base to 10Khz */
+ hRTC_Handle.Init.AsynchPrediv = (HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC) / 10000) - 1;
+ hRTC_Handle.Init.OutPut = RTC_OUTPUTSOURCE_NONE;
+ HAL_RTC_Init(&hRTC_Handle);
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+
+ /* Clear flag alarm A */
+ __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF);
+
+ counter = 0U;
+ /* Wait till RTC ALRAF flag is set and if Time out is reached exit */
+ while(__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF) != RESET)
+ {
+ if(counter++ == SystemCoreClock /48U) /* Timeout = ~ 1s */
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ /* Set RTC COUNTER MSB word */
+ hRTC_Handle.Instance->ALRH = 0x00U;
+ /* Set RTC COUNTER LSB word */
+ hRTC_Handle.Instance->ALRL = 0x09U;
+
+ /* RTC Alarm Interrupt Configuration: EXTI configuration */
+ __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
+
+ /* Clear Second and overflow flags */
+ CLEAR_BIT(hRTC_Handle.Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW));
+
+ /* Set RTC COUNTER MSB word */
+ hRTC_Handle.Instance->CNTH = 0x00U;
+ /* Set RTC COUNTER LSB word */
+ hRTC_Handle.Instance->CNTL = 0x00U;
+
+ /* Configure the Alarm interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ counter = 0U;
+ while((hRTC_Handle.Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
+ {
+ if(counter++ == SystemCoreClock /48U) /* Timeout = ~ 1s */
+ {
+ return HAL_ERROR;
+ }
+ }
+
+ HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U);
+ HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
+ return HAL_OK;
+ }
+ }
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note Disable the tick increment by disabling RTC ALARM interrupt.
+ * @param None
+ * @retval None
+ */
+void HAL_SuspendTick(void)
+{
+ /* Disable RTC ALARM update Interrupt */
+ __HAL_RTC_ALARM_DISABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note Enable the tick increment by Enabling RTC ALARM interrupt.
+ * @param None
+ * @retval None
+ */
+void HAL_ResumeTick(void)
+{
+ __IO uint32_t counter = 0U;
+
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
+
+ /* Set RTC COUNTER MSB word */
+ hRTC_Handle.Instance->CNTH = 0x00U;
+ /* Set RTC COUNTER LSB word */
+ hRTC_Handle.Instance->CNTL = 0x00U;
+
+ /* Clear Second and overflow flags */
+ CLEAR_BIT(hRTC_Handle.Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW | RTC_FLAG_ALRAF));
+
+ /* Enable RTC ALARM Update interrupt */
+ __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ while((hRTC_Handle.Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
+ {
+ if(counter++ == SystemCoreClock /48U) /* Timeout = ~ 1s */
+ {
+ break;
+ }
+ }
+}
+
+/**
+ * @brief ALARM A Event Callback in non blocking mode
+ * @note This function is called when RTC_ALARM interrupt took place, inside
+ * RTC_ALARM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+ * a global variable "uwTick" used as application time base.
+ * @param hrtc : RTC handle
+ * @retval None
+ */
+void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
+{
+ __IO uint32_t counter = 0U;
+
+ HAL_IncTick();
+
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
+ /* Set RTC COUNTER MSB word */
+ WRITE_REG(hrtc->Instance->CNTH, 0x00U);
+ /* Set RTC COUNTER LSB word */
+ WRITE_REG(hrtc->Instance->CNTL, 0x00U);
+
+ /* Clear Second and overflow flags */
+ CLEAR_BIT(hrtc->Instance->CRL, (RTC_FLAG_SEC | RTC_FLAG_OW));
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ while((hrtc->Instance->CRL & RTC_CRL_RTOFF) == (uint32_t)RESET)
+ {
+ if(counter++ == SystemCoreClock /48U) /* Timeout = ~ 1s */
+ {
+ break;
+ }
+ }
+}
+
+/**
+ * @brief This function handles RTC ALARM interrupt request.
+ * @retval None
+ */
+void RTC_Alarm_IRQHandler(void)
+{
+ HAL_RTC_AlarmIRQHandler(&hRTC_Handle);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_tim_template.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_tim_template.c
new file mode 100644
index 0000000..00b0fe5
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_timebase_tim_template.c
@@ -0,0 +1,184 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_hal_timebase_tim_template.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief HAL time base based on the hardware TIM Template.
+ *
+ * This file overrides the native HAL time base functions (defined as weak)
+ * the TIM time base:
+ * + Intializes the TIM peripheral generate a Period elapsed Event each 1ms
+ * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_hal.h"
+
+/** @addtogroup STM32F1xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup HAL_TimeBase_TIM
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+TIM_HandleTypeDef TimHandle;
+/* Private function prototypes -----------------------------------------------*/
+void TIM2_IRQHandler(void);
+/* Private functions ---------------------------------------------------------*/
+
+/**
+ * @brief This function configures the TIM2 as a time base source.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * @note This function is called automatically at the beginning of program after
+ * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+ * @param TickPriority: Tick interrupt priority.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
+{
+ RCC_ClkInitTypeDef clkconfig;
+ uint32_t uwTimclock, uwAPB1Prescaler = 0U;
+ uint32_t uwPrescalerValue = 0U;
+ uint32_t pFLatency;
+
+ /*Configure the TIM2 IRQ priority */
+ HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority ,0U);
+
+ /* Enable the TIM2 global Interrupt */
+ HAL_NVIC_EnableIRQ(TIM2_IRQn);
+
+ /* Enable TIM2 clock */
+ __HAL_RCC_TIM2_CLK_ENABLE();
+
+ /* Get clock configuration */
+ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
+
+ /* Get APB1 prescaler */
+ uwAPB1Prescaler = clkconfig.APB1CLKDivider;
+
+ /* Compute TIM2 clock */
+ if (uwAPB1Prescaler == RCC_HCLK_DIV1)
+ {
+ uwTimclock = HAL_RCC_GetPCLK1Freq();
+ }
+ else
+ {
+ uwTimclock = 2*HAL_RCC_GetPCLK1Freq();
+ }
+
+ /* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */
+ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
+
+ /* Initialize TIM2 */
+ TimHandle.Instance = TIM2;
+
+ /* Initialize TIMx peripheral as follow:
+ + Period = [(TIM2CLK/1000) - 1]. to have a (1/1000) s time base.
+ + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ + ClockDivision = 0
+ + Counter direction = Up
+ */
+ TimHandle.Init.Period = (1000000U / 1000U) - 1U;
+ TimHandle.Init.Prescaler = uwPrescalerValue;
+ TimHandle.Init.ClockDivision = 0U;
+ TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
+ TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
+ {
+ /* Start the TIM time Base generation in interrupt mode */
+ return HAL_TIM_Base_Start_IT(&TimHandle);
+ }
+
+ /* Return function status */
+ return HAL_ERROR;
+}
+
+/**
+ * @brief Suspend Tick increment.
+ * @note Disable the tick increment by disabling TIM2 update interrupt.
+ * @retval None
+ */
+void HAL_SuspendTick(void)
+{
+ /* Disable TIM2 update Interrupt */
+ __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE);
+}
+
+/**
+ * @brief Resume Tick increment.
+ * @note Enable the tick increment by Enabling TIM2 update interrupt.
+ * @retval None
+ */
+void HAL_ResumeTick(void)
+{
+ /* Enable TIM2 Update interrupt */
+ __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE);
+}
+
+/**
+ * @brief Period elapsed callback in non blocking mode
+ * @note This function is called when TIM2 interrupt took place, inside
+ * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
+ * a global variable "uwTick" used as application time base.
+ * @param htim : TIM handle
+ * @retval None
+ */
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+ HAL_IncTick();
+}
+
+/**
+ * @brief This function handles TIM interrupt request.
+ * @retval None
+ */
+void TIM2_IRQHandler(void)
+{
+ HAL_TIM_IRQHandler(&TimHandle);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_uart.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_uart.c
index 600d936..6145b22 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_uart.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_uart.c
@@ -2,29 +2,28 @@
******************************************************************************
* @file stm32f1xx_hal_uart.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Errors functions
+ * + Peripheral Control functions
+ * + Peripheral State and Errors functions
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The UART HAL driver can be used as follows:
-
- (#) Declare a UART_HandleTypeDef handle structure.
+ (#) Declare a UART_HandleTypeDef handle structure.
(#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
(##) Enable the USARTx interface clock.
(##) UART pins configuration:
(+++) Enable the clock for the UART GPIOs.
- (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+ (+++) Configure the UART pins (TX as alternate function pull-up, RX as alternate function Input).
(##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
and HAL_UART_Receive_IT() APIs):
(+++) Configure the USARTx interrupt priority.
@@ -64,18 +63,18 @@
[..]
(@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
- low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customed
+ low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
HAL_UART_MspInit() API.
- [..]
- Three operation modes are available within this driver :
+ [..]
+ Three operation modes are available within this driver:
*** Polling mode IO operation ***
=================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
(+) Receive an amount of data in blocking mode using HAL_UART_Receive()
-
+
*** Interrupt mode IO operation ***
===================================
[..]
@@ -122,12 +121,27 @@
[..]
(@) You can refer to the UART HAL driver header file for more useful macros
-
@endverbatim
+ [..]
+ (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ the possible UART frame formats are as listed in the following table:
+ +-------------------------------------------------------------+
+ | M bit | PCE bit | UART frame |
+ |---------------------|---------------------------------------|
+ | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ +-------------------------------------------------------------+
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -166,31 +180,42 @@
* @{
*/
#ifdef HAL_UART_MODULE_ENABLED
-
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup UART_Private_Functions UART Private Functions
+/** @addtogroup UART_Private_Constants
* @{
*/
-static void UART_SetConfig (UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
/**
* @}
*/
-
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions
+ * @{
+ */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void UART_SetConfig (UART_HandleTypeDef *huart);
+/**
+ * @}
+ */
/* Exported functions ---------------------------------------------------------*/
-
/** @defgroup UART_Exported_Functions UART Exported Functions
* @{
*/
@@ -199,9 +224,9 @@
* @brief Initialization and Configuration functions
*
@verbatim
-===============================================================================
+ ==============================================================================
##### Initialization and Configuration functions #####
- ===============================================================================
+ ==============================================================================
[..]
This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
in asynchronous mode.
@@ -209,42 +234,27 @@
(++) Baud Rate
(++) Word Length
(++) Stop Bit
- (++) Parity
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ please refer to Reference manual for possible UART frame formats.
(++) Hardware flow control
(++) Receiver/transmitter modes
+ (++) Over Sampling Method
[..]
The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
configuration procedures (details for the procedures are available in reference manuals
(RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)).
-
@endverbatim
* @{
*/
-/*
- Additionnal remark: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible UART frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | UART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
-*/
-
/**
* @brief Initializes the UART mode according to the specified parameters in
* the UART_InitTypeDef and create the associated handle.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -268,18 +278,20 @@
assert_param(IS_UART_INSTANCE(huart->Instance));
}
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+#if defined(USART_CR1_OVER8)
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+#endif /* USART_CR1_OVER8 */
- if(huart->State == HAL_UART_STATE_RESET)
+ if(huart->gState == HAL_UART_STATE_RESET)
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
-
+
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
@@ -298,7 +310,8 @@
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->State= HAL_UART_STATE_READY;
+ huart->gState= HAL_UART_STATE_READY;
+ huart->RxState= HAL_UART_STATE_READY;
return HAL_OK;
}
@@ -306,7 +319,7 @@
/**
* @brief Initializes the half-duplex mode according to the specified
* parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -317,22 +330,22 @@
{
return HAL_ERROR;
}
-
- /* Check UART instance */
+
+ /* Check the parameters */
assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+#if defined(USART_CR1_OVER8)
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-
- if(huart->State == HAL_UART_STATE_RESET)
- {
+#endif /* USART_CR1_OVER8 */
+ if(huart->gState == HAL_UART_STATE_RESET)
+ {
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
-
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
@@ -340,7 +353,7 @@
/* Set the UART Communication parameters */
UART_SetConfig(huart);
- /* In half-duplex mode, the following bits must be kept cleared:
+ /* In half-duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
@@ -354,7 +367,8 @@
/* Initialize the UART state*/
huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->State= HAL_UART_STATE_READY;
+ huart->gState= HAL_UART_STATE_READY;
+ huart->RxState= HAL_UART_STATE_READY;
return HAL_OK;
}
@@ -362,7 +376,7 @@
/**
* @brief Initializes the LIN mode according to the specified
* parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param BreakDetectLength: Specifies the LIN break detection length.
* This parameter can be one of the following values:
@@ -383,18 +397,19 @@
/* Check the Break detection length parameter */
assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
+#if defined(USART_CR1_OVER8)
assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
+#endif /* USART_CR1_OVER8 */
- if(huart->State == HAL_UART_STATE_RESET)
- {
+ if(huart->gState == HAL_UART_STATE_RESET)
+ {
/* Allocate lock resource and initialize it */
- huart->Lock = HAL_UNLOCKED;
-
+ huart->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
@@ -419,7 +434,8 @@
/* Initialize the UART state*/
huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->State= HAL_UART_STATE_READY;
+ huart->gState= HAL_UART_STATE_READY;
+ huart->RxState= HAL_UART_STATE_READY;
return HAL_OK;
}
@@ -427,13 +443,13 @@
/**
* @brief Initializes the Multi-Processor mode according to the specified
* parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @param Address: UART node address
- * @param WakeUpMethod: specifies the UART wakeup method.
+ * @param Address: USART address
+ * @param WakeUpMethod: specifies the USART wake-up method.
* This parameter can be one of the following values:
- * @arg UART_WAKEUPMETHOD_IDLELINE: Wakeup by an idle line detection
- * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wakeup by an address mark
+ * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
+ * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
@@ -451,18 +467,19 @@
assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
assert_param(IS_UART_ADDRESS(Address));
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+#if defined(USART_CR1_OVER8)
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+#endif /* USART_CR1_OVER8 */
- if(huart->State == HAL_UART_STATE_RESET)
- {
+ if(huart->gState == HAL_UART_STATE_RESET)
+ {
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
-
/* Init the low level hardware */
HAL_UART_MspInit(huart);
}
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
@@ -487,14 +504,15 @@
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->State= HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the UART peripheral.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -505,24 +523,18 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
- huart->State = HAL_UART_STATE_BUSY;
-
- /* Disable the Peripheral */
- __HAL_UART_DISABLE(huart);
-
- huart->Instance->CR1 = 0x0;
- huart->Instance->CR2 = 0x0;
- huart->Instance->CR3 = 0x0;
-
+ huart->gState = HAL_UART_STATE_BUSY;
+
/* DeInit the low level hardware */
HAL_UART_MspDeInit(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->State = HAL_UART_STATE_RESET;
+ huart->gState = HAL_UART_STATE_RESET;
+ huart->RxState = HAL_UART_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(huart);
@@ -532,32 +544,32 @@
/**
* @brief UART MSP Init.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
- __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_MspInit can be implemented in the user file
- */
+ the HAL_UART_MspInit could be implemented in the user file
+ */
}
/**
* @brief UART MSP DeInit.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
- __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_MspDeInit can be implemented in the user file
- */
+ the HAL_UART_MspDeInit could be implemented in the user file
+ */
}
/**
@@ -570,7 +582,7 @@
@verbatim
==============================================================================
##### IO operation functions #####
- ==============================================================================
+ ==============================================================================
[..]
This subsection provides a set of functions allowing to manage the UART asynchronous
and Half duplex data transfers.
@@ -612,18 +624,18 @@
(++) HAL_UART_RxCpltCallback()
(++) HAL_UART_ErrorCallback()
- [..]
+ [..]
(@) In the Half duplex communication, it is forbidden to run the transmit
- and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX
+ and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX
can't be useful.
-
+
@endverbatim
* @{
*/
/**
- * @brief Sends an amount of data in blocking mode.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @brief Sends an amount of data in blocking mode.
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -633,12 +645,12 @@
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint16_t* tmp;
- uint32_t tmp_state = 0;
+ uint32_t tickstart = 0U;
- tmp_state = huart->State;
- if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_RX))
+ /* Check that a Tx process is not already ongoing */
+ if(huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -647,24 +659,19 @@
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Check if a non-blocking receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_BUSY_TX;
- }
+ huart->gState = HAL_UART_STATE_BUSY_TX;
+
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
huart->TxXferSize = Size;
huart->TxXferCount = Size;
- while(huart->TxXferCount > 0)
+ while(huart->TxXferCount > 0U)
{
huart->TxXferCount--;
if(huart->Init.WordLength == UART_WORDLENGTH_9B)
{
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -672,16 +679,16 @@
huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
if(huart->Init.Parity == UART_PARITY_NONE)
{
- pData +=2;
+ pData +=2U;
}
else
- {
- pData +=1;
+ {
+ pData +=1U;
}
- }
+ }
else
{
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -689,20 +696,13 @@
}
}
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK)
- {
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
}
- /* Check if a non-blocking receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_READY;
- }
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -716,8 +716,8 @@
}
/**
- * @brief Receives an amount of data in blocking mode.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @brief Receive an amount of data in blocking mode.
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
@@ -727,59 +727,54 @@
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint16_t* tmp;
- uint32_t tmp_state = 0;
-
- tmp_state = huart->State;
- if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_TX))
+ uint32_t tickstart = 0U;
+
+ /* Check that a Rx process is not already ongoing */
+ if(huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(huart);
-
+
huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Check if a non-blocking transmit process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
huart->RxXferSize = Size;
huart->RxXferCount = Size;
/* Check the remain data to be received */
- while(huart->RxXferCount > 0)
+ while(huart->RxXferCount > 0U)
{
huart->RxXferCount--;
if(huart->Init.WordLength == UART_WORDLENGTH_9B)
{
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- tmp = (uint16_t*) pData ;
+ tmp = (uint16_t*)pData;
if(huart->Init.Parity == UART_PARITY_NONE)
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
- pData +=2;
+ pData +=2U;
}
else
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
- pData +=1;
+ pData +=1U;
}
- }
+ }
else
{
- if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -795,15 +790,9 @@
}
}
- /* Check if a non-blocking transmit process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX;
- }
- else
- {
- huart->State = HAL_UART_STATE_READY;
- }
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -817,7 +806,7 @@
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -825,40 +814,29 @@
*/
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
- uint32_t tmp_state = 0;
-
- tmp_state = huart->State;
- if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_RX))
+ /* Check that a Tx process is not already ongoing */
+ if(huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
-
/* Process Locked */
__HAL_LOCK(huart);
-
+
huart->pTxBuffPtr = pData;
huart->TxXferSize = Size;
huart->TxXferCount = Size;
huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Check if a receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_BUSY_TX;
- }
+ huart->gState = HAL_UART_STATE_BUSY_TX;
/* Process Unlocked */
__HAL_UNLOCK(huart);
/* Enable the UART Transmit data register empty Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
-
+
return HAL_OK;
}
else
@@ -868,8 +846,8 @@
}
/**
- * @brief Receives an amount of data in non blocking mode
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @brief Receives an amount of data in non blocking mode.
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
@@ -877,12 +855,10 @@
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
- uint32_t tmp_state = 0;
-
- tmp_state = huart->State;
- if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_TX))
+ /* Check that a Rx process is not already ongoing */
+ if(huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -895,16 +871,8 @@
huart->RxXferCount = Size;
huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Check if a transmit process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
-
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -927,7 +895,7 @@
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -936,12 +904,11 @@
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
- uint32_t tmp_state = 0;
-
- tmp_state = huart->State;
- if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_RX))
+
+ /* Check that a Tx process is not already ongoing */
+ if(huart->gState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -954,15 +921,7 @@
huart->TxXferCount = Size;
huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Check if a receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_BUSY_TX;
- }
+ huart->gState = HAL_UART_STATE_BUSY_TX;
/* Set the UART DMA transfer complete callback */
huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
@@ -973,6 +932,9 @@
/* Set the DMA error callback */
huart->hdmatx->XferErrorCallback = UART_DMAError;
+ /* Set the DMA abort callback */
+ huart->hdmatx->XferAbortCallback = NULL;
+
/* Enable the UART transmit DMA channel */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
@@ -980,13 +942,13 @@
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
else
@@ -997,23 +959,21 @@
/**
* @brief Receives an amount of data in non blocking mode.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param pData: Pointer to data buffer
* @param Size: Amount of data to be received
- * @note When the UART parity is enabled (PCE = 1), the received data contain
- * the parity bit (MSB position)
+ * @note When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
uint32_t *tmp;
- uint32_t tmp_state = 0;
-
- tmp_state = huart->State;
- if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_TX))
+
+ /* Check that a Rx process is not already ongoing */
+ if(huart->RxState == HAL_UART_STATE_READY)
{
- if((pData == NULL ) || (Size == 0))
+ if((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1025,15 +985,7 @@
huart->RxXferSize = Size;
huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Check if a transmit process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
/* Set the UART DMA transfer complete callback */
huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
@@ -1044,17 +996,29 @@
/* Set the DMA error callback */
huart->hdmarx->XferErrorCallback = UART_DMAError;
+ /* Set the DMA abort callback */
+ huart->hdmarx->XferAbortCallback = NULL;
+
/* Enable the DMA channel */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the UART CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
+ __HAL_UART_CLEAR_OREFLAG(huart);
/* Process Unlocked */
__HAL_UNLOCK(huart);
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
return HAL_OK;
}
else
@@ -1062,50 +1026,47 @@
return HAL_BUSY;
}
}
-
+
/**
* @brief Pauses the DMA Transfer.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
{
+ uint32_t dmarequest = 0x00U;
+
/* Process Locked */
__HAL_LOCK(huart);
-
- if(huart->State == HAL_UART_STATE_BUSY_TX)
+
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+ if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
{
/* Disable the UART DMA Tx request */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
- else if(huart->State == HAL_UART_STATE_BUSY_RX)
+
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+ if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
/* Disable the UART DMA Rx request */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
- else if (huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- /* Disable the UART DMA Tx & Rx requests */
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_ERROR;
- }
-
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
* @brief Resumes the DMA Transfer.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1113,152 +1074,610 @@
{
/* Process Locked */
__HAL_LOCK(huart);
-
- if(huart->State == HAL_UART_STATE_BUSY_TX)
+
+ if(huart->gState == HAL_UART_STATE_BUSY_TX)
{
/* Enable the UART DMA Tx request */
SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
}
- else if(huart->State == HAL_UART_STATE_BUSY_RX)
+
+ if(huart->RxState == HAL_UART_STATE_BUSY_RX)
{
- /* Clear the Overrun flag before resumming the Rx transfer*/
+ /* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_UART_CLEAR_OREFLAG(huart);
+
+ /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
/* Enable the UART DMA Rx request */
SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
- else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- /* Clear the Overrun flag before resumming the Rx transfer*/
- __HAL_UART_CLEAR_OREFLAG(huart);
- /* Enable the UART DMA Tx & Rx request */
- SET_BIT(huart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
- }
- else
- {
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_ERROR;
- }
/* Process Unlocked */
__HAL_UNLOCK(huart);
-
+
return HAL_OK;
}
/**
* @brief Stops the DMA Transfer.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
{
+ uint32_t dmarequest = 0x00U;
/* The Lock is not implemented on this API to allow the user application
to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
*/
+
+ /* Stop UART DMA Tx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+ if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel */
+ if(huart->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+ if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if(huart->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(huart->hdmarx);
+ }
+ UART_EndRxTransfer(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- /* Disable the UART Tx/Rx DMA requests */
- CLEAR_BIT(huart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
-
- /* Abort the UART DMA tx channel */
+ /* Disable the UART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel: use blocking DMA Abort API (no callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+ }
+
+ /* Disable the UART DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel: use blocking DMA Abort API (no callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0x00U;
+ huart->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Restore huart->RxState and huart->gState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the UART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmatx);
+ }
+ }
+
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0x00U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (blocking mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(huart->hdmarx);
+ }
+ }
+
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0x00U;
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfers (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+ uint32_t AbortCplt = 0x01U;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
if(huart->hdmatx != NULL)
{
- HAL_DMA_Abort(huart->hdmatx);
+ /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+ }
+ else
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
}
- /* Abort the UART DMA rx channel */
+ /* DMA Rx Handle is valid */
if(huart->hdmarx != NULL)
{
- HAL_DMA_Abort(huart->hdmarx);
+ /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+ }
+ else
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ }
}
-
- huart->State = HAL_UART_STATE_READY;
-
+
+ /* Disable the UART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at UART level */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* UART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ huart->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* Disable the UART DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* UART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ huart->hdmarx->XferAbortCallback = NULL;
+ AbortCplt = 0x01U;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if(AbortCplt == 0x01U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ huart->TxXferCount = 0x00U;
+ huart->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Transmit transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* Disable the UART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmatx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+ huart->hdmatx->XferAbortCallback(huart->hdmatx);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0x00U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+ }
+ }
+ else
+ {
+ /* Reset Tx transfer counter */
+ huart->TxXferCount = 0x00U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing Receive transfer (Interrupt mode).
+ * @param huart UART handle.
+ * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0x00U;
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+ }
+ }
+ else
+ {
+ /* Reset Rx transfer counter */
+ huart->RxXferCount = 0x00U;
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+ }
+
return HAL_OK;
}
/**
* @brief This function handles UART interrupt request.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
- uint32_t tmp_flag = 0, tmp_it_source = 0;
+ uint32_t isrflags = READ_REG(huart->Instance->SR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
+ uint32_t errorflags = 0x00U;
+ uint32_t dmarequest = 0x00U;
- tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_PE);
- tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE);
- /* UART parity error interrupt occurred ------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- huart->ErrorCode |= HAL_UART_ERROR_PE;
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+ if(errorflags == RESET)
+ {
+ /* UART in mode Receiver -------------------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ UART_Receive_IT(huart);
+ return;
+ }
}
-
- tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_FE);
- tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
- /* UART frame error interrupt occurred -------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- huart->ErrorCode |= HAL_UART_ERROR_FE;
- }
-
- tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_NE);
- /* UART noise error interrupt occurred -------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- huart->ErrorCode |= HAL_UART_ERROR_NE;
- }
-
- tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_ORE);
- /* UART Over-Run interrupt occurred ----------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- huart->ErrorCode |= HAL_UART_ERROR_ORE;
- }
-
- tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE);
- tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE);
- /* UART in mode Receiver ---------------------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- UART_Receive_IT(huart);
- }
-
- tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_TXE);
- tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE);
+
+ /* If some errors occur */
+ if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+ {
+ /* UART parity error interrupt occurred ----------------------------------*/
+ if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART noise error interrupt occurred -----------------------------------*/
+ if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* UART frame error interrupt occurred -----------------------------------*/
+ if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART Over-Run interrupt occurred --------------------------------------*/
+ if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ }
+
+ /* Call UART Error Call back function if need be --------------------------*/
+ if(huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* UART in mode Receiver -----------------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ UART_Receive_IT(huart);
+ }
+
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+ if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
+ {
+ /* Blocking error : transfer is aborted
+ Set the UART state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ UART_EndRxTransfer(huart);
+
+ /* Disable the UART DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the UART DMA Rx channel */
+ if(huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA Abort callback :
+ will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+ huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+ if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_UART_ErrorCallback(huart);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_UART_ErrorCallback(huart);
+ }
+ }
+ else
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+ HAL_UART_ErrorCallback(huart);
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
+ return;
+ } /* End if some error occurs */
+
/* UART in mode Transmitter ------------------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
UART_Transmit_IT(huart);
+ return;
}
-
- tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC);
- tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC);
+
/* UART in mode Transmitter end --------------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
UART_EndTransmit_IT(huart);
- }
-
- if(huart->ErrorCode != HAL_UART_ERROR_NONE)
- {
- /* Clear all the error flag at once */
- __HAL_UART_CLEAR_PEFLAG(huart);
-
- /* Set the UART state ready to be able to start again the process */
- huart->State = HAL_UART_STATE_READY;
-
- HAL_UART_ErrorCallback(huart);
- }
+ return;
+ }
}
/**
* @brief Tx Transfer completed callbacks.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
@@ -1266,14 +1685,14 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_TxCpltCallback can be implemented in the user file
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_UART_TxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Tx Half Transfer completed callbacks.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
@@ -1281,14 +1700,14 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_TxHalfCpltCallback can be implemented in the user file
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_UART_TxHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Transfer completed callbacks.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
@@ -1296,14 +1715,14 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_RxCpltCallback can be implemented in the user file
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_UART_RxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Half Transfer completed callbacks.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
@@ -1311,27 +1730,71 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_RxHalfCpltCallback can be implemented in the user file
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_UART_RxHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief UART error callbacks.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
/* Prevent unused argument(s) compilation warning */
- UNUSED(huart);
- /* NOTE: This function should not be modified, when the callback is needed,
- the HAL_UART_ErrorCallback can be implemented in the user file
+ UNUSED(huart);
+ /* NOTE: This function Should not be modified, when the callback is needed,
+ the HAL_UART_ErrorCallback could be implemented in the user file
*/
}
/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortCpltCallback can be implemented in the user file.
+ */
+}
+/**
+ * @brief UART Abort Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
+ * @brief UART Abort Receive Complete callback.
+ * @param huart UART handle.
+ * @retval None
+ */
+__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+ */
+}
+
+/**
* @}
*/
@@ -1356,7 +1819,7 @@
/**
* @brief Transmits break characters.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1368,12 +1831,12 @@
/* Process Locked */
__HAL_LOCK(huart);
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Send break characters */
SET_BIT(huart->Instance->CR1, USART_CR1_SBK);
- huart->State = HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -1383,7 +1846,7 @@
/**
* @brief Enters the UART in mute mode.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1395,12 +1858,12 @@
/* Process Locked */
__HAL_LOCK(huart);
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Enable the USART mute mode by setting the RWU bit in the CR1 register */
SET_BIT(huart->Instance->CR1, USART_CR1_RWU);
- huart->State = HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -1410,7 +1873,7 @@
/**
* @brief Exits the UART mute mode: wake up software.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1422,12 +1885,12 @@
/* Process Locked */
__HAL_LOCK(huart);
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU);
- huart->State = HAL_UART_STATE_READY;
+ huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -1437,23 +1900,32 @@
/**
* @brief Enables the UART transmitter and disables the UART receiver.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
{
+ uint32_t tmpreg = 0x00U;
+
/* Process Locked */
__HAL_LOCK(huart);
- huart->State = HAL_UART_STATE_BUSY;
+ huart->gState = HAL_UART_STATE_BUSY;
/*-------------------------- USART CR1 Configuration -----------------------*/
+ tmpreg = huart->Instance->CR1;
+
/* Clear TE and RE bits */
+ tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
+
/* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
- MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_TE | USART_CR1_RE), USART_CR1_TE);
-
- huart->State = HAL_UART_STATE_READY;
+ tmpreg |= (uint32_t)USART_CR1_TE;
+
+ /* Write to USART CR1 */
+ WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
+
+ huart->gState = HAL_UART_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -1463,24 +1935,33 @@
/**
* @brief Enables the UART receiver and disables the UART transmitter.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
{
+ uint32_t tmpreg = 0x00U;
+
/* Process Locked */
__HAL_LOCK(huart);
-
- huart->State = HAL_UART_STATE_BUSY;
+
+ huart->gState = HAL_UART_STATE_BUSY;
/*-------------------------- USART CR1 Configuration -----------------------*/
+ tmpreg = huart->Instance->CR1;
+
/* Clear TE and RE bits */
+ tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
+
/* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
- MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_TE | USART_CR1_RE), USART_CR1_RE);
-
- huart->State = HAL_UART_STATE_READY;
-
+ tmpreg |= (uint32_t)USART_CR1_RE;
+
+ /* Write to USART CR1 */
+ WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
+
+ huart->gState = HAL_UART_STATE_READY;
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
@@ -1511,21 +1992,25 @@
/**
* @brief Returns the UART state.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL state
*/
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
{
- return huart->State;
+ uint32_t temp1= 0x00U, temp2 = 0x00U;
+ temp1 = huart->gState;
+ temp2 = huart->RxState;
+
+ return (HAL_UART_StateTypeDef)(temp1 | temp2);
}
/**
-* @brief Return the UART error code
-* @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @brief Return the UART error code
+ * @param huart : pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART.
-* @retval UART Error Code
-*/
+ * @retval UART Error Code
+ */
uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
{
return huart->ErrorCode;
@@ -1536,33 +2021,25 @@
*/
/**
- * @}
- */
-
-/** @defgroup UART_Private_Functions UART Private Functions
- * @brief UART Private functions
- * @{
- */
-/**
* @brief DMA UART transmit process complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma: DMA handle
* @retval None
*/
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* DMA Normal mode*/
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
- huart->TxXferCount = 0;
+ huart->TxXferCount = 0U;
/* Disable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
- /* Enable the UART Transmit Complete Interrupt */
- __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+ /* Enable the UART Transmit Complete Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
}
/* DMA Circular mode */
else
@@ -1573,8 +2050,8 @@
/**
* @brief DMA UART transmit process half complete callback
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1586,135 +2063,274 @@
/**
* @brief DMA UART receive process complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma: DMA handle
* @retval None
*/
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* DMA Normal mode*/
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{
- huart->RxXferCount = 0;
+ huart->RxXferCount = 0U;
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
/* Disable the DMA transfer for the receiver request by setting the DMAR bit
in the UART CR3 register */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- /* Check if a transmit process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX;
- }
- else
- {
- huart->State = HAL_UART_STATE_READY;
- }
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
}
HAL_UART_RxCpltCallback(huart);
}
/**
* @brief DMA UART receive process half complete callback
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
HAL_UART_RxHalfCpltCallback(huart);
}
/**
* @brief DMA UART communication error callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @param hdma: DMA handle
* @retval None
*/
-static void UART_DMAError(DMA_HandleTypeDef *hdma)
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
{
+ uint32_t dmarequest = 0x00U;
UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- huart->RxXferCount = 0;
- huart->TxXferCount = 0;
- huart->State= HAL_UART_STATE_READY;
+
+ /* Stop UART DMA Tx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+ if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+ {
+ huart->TxXferCount = 0U;
+ UART_EndTxTransfer(huart);
+ }
+
+ /* Stop UART DMA Rx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+ if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+ {
+ huart->RxXferCount = 0U;
+ UART_EndRxTransfer(huart);
+ }
+
huart->ErrorCode |= HAL_UART_ERROR_DMA;
HAL_UART_ErrorCallback(huart);
}
/**
* @brief This function handles UART Communication Timeout.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @param Flag: specifies the UART flag to check.
* @param Status: The new Flag status (SET or RESET).
+ * @param Tickstart Tick start value
* @param Timeout: Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
- uint32_t tickstart = 0;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
/* Wait until flag is set */
- if(Status == RESET)
+ while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
{
- while(__HAL_UART_GET_FLAG(huart, Flag) == RESET)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
- huart->State= HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_TIMEOUT;
- }
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(huart);
+
+ return HAL_TIMEOUT;
}
}
}
- else
- {
- while(__HAL_UART_GET_FLAG(huart, Flag) != RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
- __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
- huart->State= HAL_UART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(huart);
-
- return HAL_TIMEOUT;
- }
- }
- }
- }
+
return HAL_OK;
}
/**
+ * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+ * @param huart: UART handle.
+ * @retval None
+ */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* At end of Tx process, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+}
+
+/**
+ * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+ * @param huart: UART handle.
+ * @retval None
+ */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+}
+
+/**
+ * @brief DMA UART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ huart->RxXferCount = 0x00U;
+ huart->TxXferCount = 0x00U;
+
+ HAL_UART_ErrorCallback(huart);
+}
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ huart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(huart->hdmarx != NULL)
+ {
+ if(huart->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0x00U;
+ huart->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(huart->hdmatx != NULL)
+ {
+ if(huart->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ huart->TxXferCount = 0x00U;
+ huart->RxXferCount = 0x00U;
+
+ /* Reset ErrorCode */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+ /* Restore huart->gState and huart->RxState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART Tx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+ * (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+ * and leads to user Tx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ huart->TxXferCount = 0x00U;
+
+ /* Restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortTransmitCpltCallback(huart);
+}
+
+/**
+ * @brief DMA UART Rx communication abort callback, when initiated by user by a call to
+ * HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+ * (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+ * and leads to user Rx Abort Complete callback execution).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ huart->RxXferCount = 0x00U;
+
+ /* Restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_UART_AbortReceiveCpltCallback(huart);
+}
+
+/**
* @brief Sends an amount of data in non blocking mode.
* @param huart: Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
@@ -1723,10 +2339,9 @@
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
{
uint16_t* tmp;
- uint32_t tmp_state = 0;
- tmp_state = huart->State;
- if((tmp_state == HAL_UART_STATE_BUSY_TX) || (tmp_state == HAL_UART_STATE_BUSY_TX_RX))
+ /* Check that a Tx process is ongoing */
+ if(huart->gState == HAL_UART_STATE_BUSY_TX)
{
if(huart->Init.WordLength == UART_WORDLENGTH_9B)
{
@@ -1734,11 +2349,11 @@
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
if(huart->Init.Parity == UART_PARITY_NONE)
{
- huart->pTxBuffPtr += 2;
+ huart->pTxBuffPtr += 2U;
}
else
{
- huart->pTxBuffPtr += 1;
+ huart->pTxBuffPtr += 1U;
}
}
else
@@ -1746,7 +2361,7 @@
huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
}
- if(--huart->TxXferCount == 0)
+ if(--huart->TxXferCount == 0U)
{
/* Disable the UART Transmit Complete Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
@@ -1762,7 +2377,6 @@
}
}
-
/**
* @brief Wraps up transmission in non blocking mode.
* @param huart: pointer to a UART_HandleTypeDef structure that contains
@@ -1774,16 +2388,8 @@
/* Disable the UART Transmit Complete Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
- /* Check if a receive process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_RX;
- }
- else
- {
- huart->State = HAL_UART_STATE_READY;
- }
-
+ /* Tx process is ended, restore huart->gState to Ready */
+ huart->gState = HAL_UART_STATE_READY;
HAL_UART_TxCpltCallback(huart);
return HAL_OK;
@@ -1791,17 +2397,16 @@
/**
* @brief Receives an amount of data in non blocking mode
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
{
uint16_t* tmp;
- uint32_t tmp_state = 0;
- tmp_state = huart->State;
- if((tmp_state == HAL_UART_STATE_BUSY_RX) || (tmp_state == HAL_UART_STATE_BUSY_TX_RX))
+ /* Check that a Rx process is ongoing */
+ if(huart->RxState == HAL_UART_STATE_BUSY_RX)
{
if(huart->Init.WordLength == UART_WORDLENGTH_9B)
{
@@ -1809,12 +2414,12 @@
if(huart->Init.Parity == UART_PARITY_NONE)
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
- huart->pRxBuffPtr += 2;
+ huart->pRxBuffPtr += 2U;
}
else
{
*tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
- huart->pRxBuffPtr += 1;
+ huart->pRxBuffPtr += 1U;
}
}
else
@@ -1829,25 +2434,19 @@
}
}
- if(--huart->RxXferCount == 0)
+ if(--huart->RxXferCount == 0U)
{
+ /* Disable the IRDA Data Register not empty Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
- /* Check if a transmit process is ongoing or not */
- if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
- {
- huart->State = HAL_UART_STATE_BUSY_TX;
- }
- else
- {
- /* Disable the UART Parity Error Interrupt */
- __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-
+ /* Disable the UART Parity Error Interrupt */
+ __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
- huart->State = HAL_UART_STATE_READY;
- }
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
HAL_UART_RxCpltCallback(huart);
return HAL_OK;
@@ -1856,22 +2455,22 @@
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
* @brief Configures the UART peripheral.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart: pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
- uint32_t tmpreg = 0x00;
-
+ uint32_t tmpreg = 0x00U;
+
/* Check the parameters */
- assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
assert_param(IS_UART_PARITY(huart->Init.Parity));
assert_param(IS_UART_MODE(huart->Init.Mode));
@@ -1885,18 +2484,54 @@
/* Configure the UART Word Length, Parity and mode:
Set the M bits according to huart->Init.WordLength value
Set PCE and PS bits according to huart->Init.Parity value
- Set TE and RE bits according to huart->Init.Mode value */
- tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode ;
+ Set TE and RE bits according to huart->Init.Mode value
+ Set OVER8 bit according to huart->Init.OverSampling value */
+
+#if defined(USART_CR1_OVER8)
+ tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
+ MODIFY_REG(huart->Instance->CR1,
+ (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+ tmpreg);
+#else
+ tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode;
MODIFY_REG(huart->Instance->CR1,
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
tmpreg);
-
+#endif /* USART_CR1_OVER8 */
+
/*------- UART-associated USART registers setting : CR3 Configuration ------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
-
- /*------- UART-associated USART registers setting : BRR Configuration ------*/
- if((huart->Instance == USART1))
+
+#if defined(USART_CR1_OVER8)
+ /* Check the Over Sampling */
+ if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ {
+ /*-------------------------- USART BRR Configuration ---------------------*/
+ if(huart->Instance == USART1)
+ {
+ huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+ }
+ else
+ {
+ huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
+ }
+ }
+ else
+ {
+ /*-------------------------- USART BRR Configuration ---------------------*/
+ if(huart->Instance == USART1)
+ {
+ huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
+ }
+ else
+ {
+ huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
+ }
+ }
+#else
+ /*-------------------------- USART BRR Configuration ---------------------*/
+ if(huart->Instance == USART1)
{
huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
}
@@ -1904,7 +2539,9 @@
{
huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
}
+#endif /* USART_CR1_OVER8 */
}
+
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_usart.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_usart.c
index 5460b6b..9057853 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_usart.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_usart.c
@@ -2,15 +2,14 @@
******************************************************************************
* @file stm32f1xx_hal_usart.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief USART HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
- * + Peripheral State and Errors functions
+ * + Peripheral Control functions
@verbatim
==============================================================================
##### How to use this driver #####
@@ -19,7 +18,7 @@
The USART HAL driver can be used as follows:
(#) Declare a USART_HandleTypeDef handle structure.
- (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
+ (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit () API:
(##) Enable the USARTx interface clock.
(##) USART pins configuration:
(+++) Enable the clock for the USART GPIOs.
@@ -34,82 +33,99 @@
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
- (+++) Associate the initilalized DMA handle to the USART DMA Tx/Rx handle.
+ (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA Tx/Rx channel.
(+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
- (used for last byte sending completion detection in DMA non circular mode)
+ (used for last byte sending completion detection in DMA non circular mode)
- (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+ (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
flow control and Mode(Receiver/Transmitter) in the husart Init structure.
(#) Initialize the USART registers by calling the HAL_USART_Init() API:
(++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
- by calling the customed HAL_USART_MspInit(&husart) API.
-
- -@@- The specific USART interrupts (Transmission complete interrupt,
+ by calling the customized HAL_USART_MspInit(&husart) API.
+
+ -@@- The specific USART interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
-
- (#) Three operation modes are available within this driver :
-
+
+ (#) Three operation modes are available within this driver :
+
*** Polling mode IO operation ***
=================================
- [..]
- (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
+ [..]
+ (+) Send an amount of data in blocking mode using HAL_USART_Transmit()
(+) Receive an amount of data in blocking mode using HAL_USART_Receive()
-
- *** Interrupt mode IO operation ***
+
+ *** Interrupt mode IO operation ***
===================================
- [..]
- (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
- (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
+ [..]
+ (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT()
+ (+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
- (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxCpltCallback
- (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
+ (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT()
+ (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_USART_ErrorCallback
-
- *** DMA mode IO operation ***
+
+ *** DMA mode IO operation ***
==============================
- [..]
- (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
- (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
- (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
+ [..]
+ (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA()
+ (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback
+ (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_USART_TxCpltCallback
- (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
- (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
- (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
- add his own code by customization of function pointer HAL_USART_RxCpltCallback
- (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
+ (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA()
+ (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback
+ (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can
+ add his own code by customization of function pointer HAL_USART_RxCpltCallback
+ (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_USART_ErrorCallback
- (+) Pause the DMA Transfer using HAL_USART_DMAPause()
- (+) Resume the DMA Transfer using HAL_USART_DMAResume()
- (+) Stop the DMA Transfer using HAL_USART_DMAStop()
-
+ (+) Pause the DMA Transfer using HAL_USART_DMAPause()
+ (+) Resume the DMA Transfer using HAL_USART_DMAResume()
+ (+) Stop the DMA Transfer using HAL_USART_DMAStop()
+
*** USART HAL driver macros list ***
- =============================================
+ =============================================
[..]
Below the list of most used macros in USART HAL driver.
-
- (+) __HAL_USART_ENABLE: Enable the USART peripheral
- (+) __HAL_USART_DISABLE: Disable the USART peripheral
+
+ (+) __HAL_USART_ENABLE: Enable the USART peripheral
+ (+) __HAL_USART_DISABLE: Disable the USART peripheral
(+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
(+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
(+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
(+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
- (+) __HAL_USART_GET_IT_SOURCE: Check whether the specified USART interrupt has occurred or not
-
- [..]
+
+ [..]
(@) You can refer to the USART HAL driver header file for more useful macros
@endverbatim
+ [..]
+ (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ the possible USART frame formats are as listed in the following table:
+ +-------------------------------------------------------------+
+ | M bit | PCE bit | USART frame |
+ |---------------------|---------------------------------------|
+ | 0 | 0 | | SB | 8 bit data | STB | |
+ |---------|-----------|---------------------------------------|
+ | 0 | 1 | | SB | 7 bit data | PB | STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 0 | | SB | 9 bit data | STB | |
+ |---------|-----------|---------------------------------------|
+ | 1 | 1 | | SB | 8 bit data | PB | STB | |
+ +-------------------------------------------------------------+
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -148,22 +164,26 @@
* @{
*/
#ifdef HAL_USART_MODULE_ENABLED
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup USART_Private_Constants USART Private Constants
+/** @addtogroup USART_Private_Constants
* @{
*/
-#define DUMMY_DATA 0xFFFF
+#define DUMMY_DATA 0xFFFFU
+#define USART_TIMEOUT_VALUE 22000U
/**
* @}
*/
-
-/* Private macros --------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup USART_Private_Functions USART Private Functions
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup USART_Private_Functions
* @{
*/
+static void USART_EndTxTransfer(USART_HandleTypeDef *husart);
+static void USART_EndRxTransfer(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
@@ -173,70 +193,57 @@
static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static void USART_DMAError(DMA_HandleTypeDef *hdma);
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
/**
* @}
*/
-/* Exported functions ---------------------------------------------------------*/
-
-
+/* Exported functions --------------------------------------------------------*/
/** @defgroup USART_Exported_Functions USART Exported Functions
* @{
*/
-/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
- ##### Initialization and Configuration functions #####
+ ##### Initialization and Configuration functions #####
==============================================================================
[..]
- This subsection provides a set of functions allowing to initialize the USART
+ This subsection provides a set of functions allowing to initialize the USART
in asynchronous and in synchronous modes.
- (+) For the asynchronous mode only these parameters can be configured:
+ (+) For the asynchronous mode only these parameters can be configured:
(++) Baud Rate
- (++) Word Length
+ (++) Word Length
(++) Stop Bit
- (++) Parity
+ (++) Parity: If the parity is enabled, then the MSB bit of the data written
+ in the data register is transmitted but is changed by the parity bit.
+ Depending on the frame length defined by the M bit (8-bits or 9-bits),
+ please refer to Reference manual for possible USART frame formats.
(++) USART polarity
(++) USART phase
(++) USART LastBit
(++) Receiver/transmitter modes
[..]
- The HAL_USART_Init() function follows the USART synchronous configuration
+ The HAL_USART_Init() function follows the USART synchronous configuration
procedure (details for the procedure are available in reference manuals
(RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)).
@endverbatim
* @{
*/
-
-/*
- Additionnal remark: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible USART frame formats are as listed in the following table:
- +-------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
-*/
/**
* @brief Initializes the USART mode according to the specified
* parameters in the USART_InitTypeDef and create the associated handle.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -255,7 +262,7 @@
{
/* Allocate lock resource and initialize it */
husart->Lock = HAL_UNLOCKED;
-
+
/* Init the low level hardware */
HAL_USART_MspInit(husart);
}
@@ -265,11 +272,11 @@
/* Set the USART Communication parameters */
USART_SetConfig(husart);
- /* In USART mode, the following bits must be kept cleared:
+ /* In USART mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register
- HDSEL, SCEN and IREN bits in the USART_CR3 register */
CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN);
- CLEAR_BIT(husart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
/* Enable the Peripheral */
__HAL_USART_ENABLE(husart);
@@ -283,13 +290,13 @@
/**
* @brief DeInitializes the USART peripheral.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
{
- /* Check the USART handle allocation */
+ /* Check the USART handle allocation */
if(husart == NULL)
{
return HAL_ERROR;
@@ -300,9 +307,6 @@
husart->State = HAL_USART_STATE_BUSY;
- /* Disable the Peripheral */
- __HAL_USART_DISABLE(husart);
-
/* DeInit the low level hardware */
HAL_USART_MspDeInit(husart);
@@ -317,66 +321,66 @@
/**
* @brief USART MSP Init.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
- __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
+__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_MspInit can be implemented in the user file
- */
+ the HAL_USART_MspInit could be implemented in the user file
+ */
}
/**
* @brief USART MSP DeInit.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
- __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
+__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_MspDeInit can be implemented in the user file
- */
+ the HAL_USART_MspDeInit could be implemented in the user file
+ */
}
/**
* @}
*/
-/** @defgroup USART_Exported_Functions_Group2 IO operation functions
- * @brief USART Transmit and Receive functions
+/** @defgroup USART_Exported_Functions_Group2 IO operation functions
+ * @brief USART Transmit and Receive functions
*
@verbatim
==============================================================================
- ##### IO operation functions #####
+ ##### IO operation functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to manage the USART synchronous
data transfers.
-
- [..]
+
+ [..]
The USART supports master mode only: it cannot receive or send data related to an input
clock (SCLK is always an output).
(#) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
- The HAL status of all data processing is returned by the same function
- after finishing transfer.
- (++) No-Blocking mode: The communication is performed using Interrupts
+ (++) Blocking mode: The communication is performed in polling mode.
+ The HAL status of all data processing is returned by the same function
+ after finishing transfer.
+ (++) No-Blocking mode: The communication is performed using Interrupts
or DMA, These API's return the HAL status.
- The end of the data processing will be indicated through the
- dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
+ The end of the data processing will be indicated through the
+ dedicated USART IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
- The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
- user callbacks
+ The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback()
+ user callbacks
will be executed respectively at the end of the transmit or Receive process
- The HAL_USART_ErrorCallback() user callback will be executed when a communication
+ The HAL_USART_ErrorCallback() user callback will be executed when a communication
error is detected
(#) Blocking mode APIs are :
@@ -411,8 +415,8 @@
*/
/**
- * @brief Simplex Send an amount of data in blocking mode.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @brief Simplex Send an amount of data in blocking mode.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pTxData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -421,11 +425,12 @@
*/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp=0;
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -436,15 +441,18 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
+
husart->TxXferSize = Size;
husart->TxXferCount = Size;
- while(husart->TxXferCount > 0)
+ while(husart->TxXferCount > 0U)
{
husart->TxXferCount--;
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
/* Wait for TC flag in order to write data in DR */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -452,16 +460,16 @@
WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF));
if(husart->Init.Parity == USART_PARITY_NONE)
{
- pTxData += 2;
+ pTxData += 2U;
}
else
{
- pTxData += 1;
+ pTxData += 1U;
}
}
else
{
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -469,8 +477,8 @@
}
}
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
- {
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
}
@@ -488,8 +496,8 @@
}
/**
- * @brief Full-Duplex Receive an amount of data in blocking mode.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @brief Full-Duplex Receive an amount of data in blocking mode.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pRxData: Pointer to data buffer
* @param Size: Amount of data to be received
@@ -498,59 +506,62 @@
*/
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp=0;
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
if(husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0))
+ if((pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
-
/* Process Locked */
__HAL_LOCK(husart);
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
+
husart->RxXferSize = Size;
husart->RxXferCount = Size;
/* Check the remain data to be received */
- while(husart->RxXferCount > 0)
+ while(husart->RxXferCount > 0U)
{
husart->RxXferCount--;
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
/* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
}
/* Send dummy byte in order to generate clock */
WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF));
-
+
/* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
- {
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
}
tmp = (uint16_t*) pRxData ;
if(husart->Init.Parity == USART_PARITY_NONE)
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
- pRxData +=2;
+ pRxData +=2U;
}
else
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
- pRxData +=1;
+ pRxData +=1U;
}
}
else
{
/* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
- {
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ {
return HAL_TIMEOUT;
}
@@ -558,7 +569,7 @@
WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF));
/* Wait until RXNE flag is set to receive the byte */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -590,22 +601,23 @@
}
/**
- * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pTxData: Pointer to data transmitted buffer
- * @param pRxData: Pointer to data received buffer
+ * @param pRxData: Pointer to data received buffer
* @param Size: Amount of data to be sent
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
{
- uint16_t* tmp=0;
+ uint16_t* tmp;
+ uint32_t tickstart = 0U;
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -615,20 +627,23 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
+ /* Init tickstart for timeout managment */
+ tickstart = HAL_GetTick();
+
husart->RxXferSize = Size;
husart->TxXferSize = Size;
husart->TxXferCount = Size;
husart->RxXferCount = Size;
/* Check the remain data to be received */
- while(husart->TxXferCount > 0)
+ while(husart->TxXferCount > 0U)
{
husart->TxXferCount--;
husart->RxXferCount--;
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
{
/* Wait for TC flag in order to write data in DR */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -636,15 +651,15 @@
WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF));
if(husart->Init.Parity == USART_PARITY_NONE)
{
- pTxData += 2;
+ pTxData += 2U;
}
else
{
- pTxData += 1;
+ pTxData += 1U;
}
-
+
/* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -652,25 +667,25 @@
if(husart->Init.Parity == USART_PARITY_NONE)
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
- pRxData += 2;
+ pRxData += 2U;
}
else
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
- pRxData += 1;
+ pRxData += 1U;
}
- }
+ }
else
{
/* Wait for TC flag in order to write data in DR */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
WRITE_REG(husart->Instance->DR, (*pTxData++ & (uint8_t)0x00FF));
/* Wait for RXNE Flag */
- if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
+ if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -701,8 +716,8 @@
}
/**
- * @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @brief Simplex Send an amount of data in non-blocking mode.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pTxData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -711,13 +726,13 @@
*/
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
{
+ /* Check that a Tx process is not already ongoing */
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
-
/* Process Locked */
__HAL_LOCK(husart);
@@ -728,7 +743,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
- /* The USART Error Interrupts: (Frame error, Noise error, Overrun error)
+ /* The USART Error Interrupts: (Frame error, Noise error, Overrun error)
are not managed by the USART transmit process to avoid the overrun interrupt
when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
to benefit for the frame error and noise interrupts the USART mode should be
@@ -751,9 +766,9 @@
}
/**
- * @brief Simplex Receive an amount of data in non-blocking mode.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
+ * @brief Simplex Receive an amount of data in non-blocking mode.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @param pRxData: Pointer to data buffer
* @param Size: Amount of data to be received
* @retval HAL status
@@ -762,7 +777,7 @@
{
if(husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0))
+ if((pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -800,11 +815,11 @@
}
/**
- * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pTxData: Pointer to data transmitted buffer
- * @param pRxData: Pointer to data received buffer
+ * @param pRxData: Pointer to data received buffer
* @param Size: Amount of data to be received
* @retval HAL status
*/
@@ -812,7 +827,7 @@
{
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -848,13 +863,13 @@
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @brief Simplex Send an amount of data in non-blocking mode.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pTxData: Pointer to data buffer
* @param Size: Amount of data to be sent
@@ -862,16 +877,16 @@
*/
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
{
- uint32_t *tmp=0;
+ uint32_t *tmp;
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
- __HAL_LOCK(husart);
+ __HAL_LOCK(husart);
husart->pTxBuffPtr = pTxData;
husart->TxXferSize = Size;
@@ -889,6 +904,9 @@
/* Set the DMA error callback */
husart->hdmatx->XferErrorCallback = USART_DMAError;
+ /* Set the DMA abort callback */
+ husart->hdmatx->XferAbortCallback = NULL;
+
/* Enable the USART transmit DMA channel */
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
@@ -896,13 +914,13 @@
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
- /* Enable the DMA transfer for transmit request by setting the DMAT bit
- in the USART CR3 register */
- SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
/* Process Unlocked */
__HAL_UNLOCK(husart);
+ /* Enable the DMA transfer for transmit request by setting the DMAT bit
+ in the USART CR3 register */
+ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
return HAL_OK;
}
else
@@ -912,8 +930,8 @@
}
/**
- * @brief Full-Duplex Receive an amount of data in non-blocking mode.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @brief Full-Duplex Receive an amount of data in non-blocking mode.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pRxData: Pointer to data buffer
* @param Size: Amount of data to be received
@@ -923,11 +941,11 @@
*/
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
{
- uint32_t *tmp=0;
-
+ uint32_t *tmp;
+
if(husart->State == HAL_USART_STATE_READY)
{
- if((pRxData == NULL) || (Size == 0))
+ if((pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -952,20 +970,42 @@
/* Set the USART DMA Rx transfer error callback */
husart->hdmarx->XferErrorCallback = USART_DMAError;
+ /* Set the DMA abort callback */
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ /* Set the USART Tx DMA transfer complete callback as NULL because the communication closing
+ is performed in DMA reception complete callback */
+ husart->hdmatx->XferHalfCpltCallback = NULL;
+ husart->hdmatx->XferCpltCallback = NULL;
+
+ /* Set the DMA error callback */
+ husart->hdmatx->XferErrorCallback = USART_DMAError;
+
+ /* Set the DMA AbortCpltCallback */
+ husart->hdmatx->XferAbortCallback = NULL;
+
/* Enable the USART receive DMA channel */
tmp = (uint32_t*)&pRxData;
HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
/* Enable the USART transmit DMA channel: the transmit channel is used in order
- to generate in the non-blocking mode the clock to the slave device,
+ to generate in the non-blocking mode the clock to the slave device,
this mode isn't a simplex receive mode but a full-duplex receive one */
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
- /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer
- when using the USART in circular mode */
+ /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer */
__HAL_USART_CLEAR_OREFLAG(husart);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the USART CR3 register */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
@@ -973,9 +1013,6 @@
in the USART CR3 register */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
return HAL_OK;
}
else
@@ -985,22 +1022,22 @@
}
/**
- * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param pTxData: Pointer to data transmitted buffer
- * @param pRxData: Pointer to data received buffer
+ * @param pRxData: Pointer to data received buffer
* @param Size: Amount of data to be received
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
{
- uint32_t *tmp=0;
+ uint32_t *tmp;
if(husart->State == HAL_USART_STATE_READY)
{
- if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
+ if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1033,6 +1070,9 @@
/* Set the USART DMA Rx transfer error callback */
husart->hdmarx->XferErrorCallback = USART_DMAError;
+ /* Set the DMA abort callback */
+ husart->hdmarx->XferAbortCallback = NULL;
+
/* Enable the USART receive DMA channel */
tmp = (uint32_t*)&pRxData;
HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
@@ -1040,14 +1080,23 @@
/* Enable the USART transmit DMA channel */
tmp = (uint32_t*)&pTxData;
HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
-
+
/* Clear the TC flag in the SR register by writing 0 to it */
__HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC);
/* Clear the Overrun flag: mandatory for the second transfer in circular mode */
__HAL_USART_CLEAR_OREFLAG(husart);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
+
+ /* Enable the USART Parity Error Interrupt */
+ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
in the USART CR3 register */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
@@ -1055,9 +1104,6 @@
in the USART CR3 register */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
return HAL_OK;
}
else
@@ -1068,7 +1114,7 @@
/**
* @brief Pauses the DMA Transfer.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -1076,19 +1122,19 @@
{
/* Process Locked */
__HAL_LOCK(husart);
-
+
/* Disable the USART DMA Tx request */
- CLEAR_BIT(husart->Instance->CR3, (uint32_t)(USART_CR3_DMAT));
-
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Resumes the DMA Transfer.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -1096,10 +1142,10 @@
{
/* Process Locked */
__HAL_LOCK(husart);
-
+
/* Enable the USART DMA Tx request */
SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
+
/* Process Unlocked */
__HAL_UNLOCK(husart);
@@ -1108,107 +1154,364 @@
/**
* @brief Stops the DMA Transfer.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
{
+ uint32_t dmarequest = 0x00U;
/* The Lock is not implemented on this API to allow the user application
to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback():
when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback()
*/
- /* Abort the USART DMA Tx channel */
+ /* Stop USART DMA Tx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
+ if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
+ {
+ USART_EndTxTransfer(husart);
+
+ /* Abort the USART DMA Tx channel */
+ if(husart->hdmatx != NULL)
+ {
+ HAL_DMA_Abort(husart->hdmatx);
+ }
+
+ /* Disable the USART Tx DMA request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+ }
+
+ /* Stop USART DMA Rx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
+ if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
+ {
+ USART_EndRxTransfer(husart);
+
+ /* Abort the USART DMA Rx channel */
+ if(husart->hdmarx != NULL)
+ {
+ HAL_DMA_Abort(husart->hdmarx);
+ }
+
+ /* Disable the USART Rx DMA request */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfer (blocking mode).
+ * @param husart USART handle.
+ * @note This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
+ * as described by TransferType parameter) started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
+{
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the USART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
+ if(husart->hdmatx != NULL)
+ {
+ /* Set the USART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(husart->hdmatx);
+ }
+ }
+
+ /* Disable the USART DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
+ if(husart->hdmarx != NULL)
+ {
+ /* Set the USART DMA Abort callback to Null.
+ No call back execution at end of DMA abort procedure */
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ HAL_DMA_Abort(husart->hdmarx);
+ }
+ }
+
+ /* Reset Tx and Rx transfer counters */
+ husart->TxXferCount = 0x00U;
+ husart->RxXferCount = 0x00U;
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Reset Handle ErrorCode to No Error */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Abort ongoing transfer (Interrupt mode).
+ * @param husart USART handle.
+ * @note This procedure could be used for aborting any ongoing transfer (either Tx or Rx,
+ * as described by TransferType parameter) started in Interrupt or DMA mode.
+ * This procedure performs following operations :
+ * - Disable PPP Interrupts (depending of transfer direction)
+ * - Disable the DMA transfer in the peripheral register (if enabled)
+ * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+ * - Set handle State to READY
+ * - At abort completion, call user abort complete callback
+ * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
+ * considered as completed only when user abort complete callback is executed (not when exiting function).
+ * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
+{
+ uint32_t AbortCplt = 0x01U;
+
+ /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised
+ before any call to DMA Abort functions */
+ /* DMA Tx Handle is valid */
if(husart->hdmatx != NULL)
{
- HAL_DMA_Abort(husart->hdmatx);
+ /* Set DMA Abort Complete callback if USART DMA Tx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback;
+ }
+ else
+ {
+ husart->hdmatx->XferAbortCallback = NULL;
+ }
}
- /* Abort the USART DMA Rx channel */
+ /* DMA Rx Handle is valid */
if(husart->hdmarx != NULL)
- {
- HAL_DMA_Abort(husart->hdmarx);
+ {
+ /* Set DMA Abort Complete callback if USART DMA Rx request if enabled.
+ Otherwise, set it to NULL */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback;
+ }
+ else
+ {
+ husart->hdmarx->XferAbortCallback = NULL;
+ }
}
- /* Disable the USART Tx/Rx DMA requests */
- CLEAR_BIT(husart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
+ /* Disable the USART DMA Tx request if enabled */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
+ {
+ /* Disable DMA Tx at USART level */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- husart->State = HAL_USART_STATE_READY;
+ /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */
+ if(husart->hdmatx != NULL)
+ {
+ /* USART Tx DMA Abort callback has already been initialised :
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA TX */
+ if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK)
+ {
+ husart->hdmatx->XferAbortCallback = NULL;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* Disable the USART DMA Rx request if enabled */
+ if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
+ if(husart->hdmarx != NULL)
+ {
+ /* USART Rx DMA Abort callback has already been initialised :
+ will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */
+
+ /* Abort DMA RX */
+ if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ {
+ husart->hdmarx->XferAbortCallback = NULL;
+ AbortCplt = 0x01U;
+ }
+ else
+ {
+ AbortCplt = 0x00U;
+ }
+ }
+ }
+
+ /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+ if(AbortCplt == 0x01U)
+ {
+ /* Reset Tx and Rx transfer counters */
+ husart->TxXferCount = 0x00U;
+ husart->RxXferCount = 0x00U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* As no DMA to be aborted, call directly user Abort complete callback */
+ HAL_USART_AbortCpltCallback(husart);
+ }
return HAL_OK;
}
/**
* @brief This function handles USART interrupt request.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
- * the configuration information for the specified USART module.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * the configuration information for the specified USART module.
* @retval None
*/
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
{
- uint32_t tmp_flag = 0, tmp_it_source = 0;
-
- tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_PE);
- tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE);
- /* USART parity error interrupt occurred -----------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- husart->ErrorCode |= HAL_USART_ERROR_PE;
- }
+ uint32_t isrflags = READ_REG(husart->Instance->SR);
+ uint32_t cr1its = READ_REG(husart->Instance->CR1);
+ uint32_t cr3its = READ_REG(husart->Instance->CR3);
+ uint32_t errorflags = 0x00U;
+ uint32_t dmarequest = 0x00U;
- tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_FE);
- tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
- /* USART frame error interrupt occurred ------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ /* If no error occurs */
+ errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+ if(errorflags == RESET)
{
- husart->ErrorCode |= HAL_USART_ERROR_FE;
- }
-
- tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_NE);
- /* USART noise error interrupt occurred ------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- husart->ErrorCode |= HAL_USART_ERROR_NE;
- }
-
- tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_ORE);
- /* USART Over-Run interrupt occurred ---------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- husart->ErrorCode |= HAL_USART_ERROR_ORE;
- }
-
- if(husart->ErrorCode != HAL_USART_ERROR_NONE)
- {
- /* Clear all the error flag at once */
- __HAL_USART_CLEAR_PEFLAG(husart);
-
- /* Set the USART state ready to be able to start again the process */
- husart->State = HAL_USART_STATE_READY;
-
- HAL_USART_ErrorCallback(husart);
- }
-
- tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE);
- tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE);
- /* USART in mode Receiver --------------------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
- {
- if(husart->State == HAL_USART_STATE_BUSY_RX)
+ /* USART in mode Receiver -------------------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
{
- USART_Receive_IT(husart);
- }
- else
- {
- USART_TransmitReceive_IT(husart);
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ USART_Receive_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ return;
}
}
+ /* If some errors occur */
+ if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+ {
+ /* USART parity error interrupt occurred ----------------------------------*/
+ if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+ {
+ husart->ErrorCode |= HAL_USART_ERROR_PE;
+ }
- tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_TXE);
- tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE);
+ /* USART noise error interrupt occurred --------------------------------*/
+ if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ husart->ErrorCode |= HAL_USART_ERROR_NE;
+ }
+
+ /* USART frame error interrupt occurred --------------------------------*/
+ if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ husart->ErrorCode |= HAL_USART_ERROR_FE;
+ }
+
+ /* USART Over-Run interrupt occurred -----------------------------------*/
+ if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+ {
+ husart->ErrorCode |= HAL_USART_ERROR_ORE;
+ }
+
+ if(husart->ErrorCode != HAL_USART_ERROR_NONE)
+ {
+ /* USART in mode Receiver -----------------------------------------------*/
+ if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+ {
+ if(husart->State == HAL_USART_STATE_BUSY_RX)
+ {
+ USART_Receive_IT(husart);
+ }
+ else
+ {
+ USART_TransmitReceive_IT(husart);
+ }
+ }
+ /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+ consider error as blocking */
+ dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
+ if(((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || dmarequest)
+ {
+ /* Set the USART state ready to be able to start again the process,
+ Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+ USART_EndRxTransfer(husart);
+
+ /* Disable the USART DMA Rx request if enabled */
+ if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
+ {
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+
+ /* Abort the USART DMA Rx channel */
+ if(husart->hdmarx != NULL)
+ {
+ /* Set the USART DMA Abort callback :
+ will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */
+ husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError;
+
+ if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK)
+ {
+ /* Call Directly XferAbortCallback function in case of error */
+ husart->hdmarx->XferAbortCallback(husart->hdmarx);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_USART_ErrorCallback(husart);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_USART_ErrorCallback(husart);
+ }
+ }
+ else
+ {
+ /* Call user error callback */
+ HAL_USART_ErrorCallback(husart);
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+ }
+ }
+ return;
+ }
+
/* USART in mode Transmitter -----------------------------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
+ if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
{
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
@@ -1218,52 +1521,50 @@
{
USART_TransmitReceive_IT(husart);
}
+ return;
}
-
- tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC);
- tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC);
- /* USART in mode Transmitter (transmission end) -----------------------------*/
- if((tmp_flag != RESET) && (tmp_it_source != RESET))
+
+ /* USART in mode Transmitter (transmission end) ----------------------------*/
+ if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
{
USART_EndTransmit_IT(husart);
- }
-
+ return;
+ }
}
-
/**
* @brief Tx Transfer completed callbacks.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
- __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
+__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_TxCpltCallback can be implemented in the user file
+ the HAL_USART_TxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Tx Half Transfer completed callbacks.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
- __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
+__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_TxHalfCpltCallback can be implemented in the user file
+ the HAL_USART_TxHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Transfer completed callbacks.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -1272,13 +1573,13 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_RxCpltCallback can be implemented in the user file
+ the HAL_USART_RxCpltCallback could be implemented in the user file
*/
}
/**
* @brief Rx Half Transfer completed callbacks.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -1287,13 +1588,13 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_RxHalfCpltCallback can be implemented in the user file
+ the HAL_USART_RxHalfCpltCallback could be implemented in the user file
*/
}
/**
* @brief Tx/Rx Transfers completed callback for the non-blocking process.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -1302,51 +1603,66 @@
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_TxRxCpltCallback can be implemented in the user file
+ the HAL_USART_TxRxCpltCallback could be implemented in the user file
*/
}
/**
* @brief USART error callbacks.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
- __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
+__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(husart);
/* NOTE: This function should not be modified, when the callback is needed,
- the HAL_USART_ErrorCallback can be implemented in the user file
- */
+ the HAL_USART_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief USART Abort Complete callback.
+ * @param husart USART handle.
+ * @retval None
+ */
+__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(husart);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_USART_AbortCpltCallback can be implemented in the user file.
+ */
}
/**
* @}
*/
-/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief USART State and Errors functions
+/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions
+ * @brief USART State and Errors functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral State and Errors functions #####
- ==============================================================================
+ ==============================================================================
[..]
- This subsection provides a set of functions allowing to return the State of
+ This subsection provides a set of functions allowing to return the State of
USART communication
process, return Peripheral Errors occurred during communication process
- (+) HAL_USART_GetState() API can be helpful to check in run-time the state
+ (+) HAL_USART_GetState() API can be helpful to check in run-time the state
of the USART peripheral.
- (+) HAL_USART_GetError() check in run-time errors that could be occurred during
- communication.
+ (+) HAL_USART_GetError() check in run-time errors that could be occurred during
+ communication.
@endverbatim
* @{
*/
/**
* @brief Returns the USART state.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL state
*/
@@ -1379,7 +1695,8 @@
* @{
*/
/**
- * @brief DMA USART transmit process complete callback.
+ * @brief DMA USART transmit process complete callback.
+ * @param hdma: DMA handle
* @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
@@ -1387,19 +1704,17 @@
static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
/* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
{
- husart->TxXferCount = 0;
-
+ husart->TxXferCount = 0U;
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
/* Disable the DMA transfer for transmit request by resetting the DMAT bit
in the USART CR3 register */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
- /* Enable the USART Transmit Complete Interrupt */
+ /* Enable the USART Transmit Complete Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_TC);
}
}
@@ -1414,8 +1729,8 @@
}
/**
- * @brief DMA USART transmit process half complete callback
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * @brief DMA USART transmit process half complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1427,32 +1742,35 @@
}
/**
- * @brief DMA USART receive process complete callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief DMA USART receive process complete callback.
+ * @param hdma: DMA handle
* @retval None
*/
static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
/* DMA Normal mode */
- if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) )
+ if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
{
- husart->RxXferCount = 0;
+ husart->RxXferCount = 0x00U;
+
+ /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
if(husart->State == HAL_USART_STATE_BUSY_RX)
{
- /* Disable the DMA transfer for the receiver requests by setting the DMAR bit
+ /* Disable the DMA transfer for the Transmit/Receiver requests by setting the DMAT/DMAR bit
in the USART CR3 register */
CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
husart->State= HAL_USART_STATE_READY;
HAL_USART_RxCpltCallback(husart);
}
- /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
else
{
- /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
+ /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
in the USART CR3 register */
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR));
@@ -1467,7 +1785,7 @@
{
HAL_USART_RxCpltCallback(husart);
}
- /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/
+ /* The USART state is HAL_USART_STATE_BUSY_TX_RX */
else
{
HAL_USART_TxRxCpltCallback(husart);
@@ -1476,8 +1794,8 @@
}
/**
- * @brief DMA USART receive process half complete callback
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * @brief DMA USART receive process half complete callback
+ * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1485,91 +1803,73 @@
{
USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
- HAL_USART_RxHalfCpltCallback(husart);
+ HAL_USART_RxHalfCpltCallback(husart);
}
/**
- * @brief DMA USART communication error callback.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
- * the configuration information for the specified DMA module.
+ * @brief DMA USART communication error callback.
+ * @param hdma: DMA handle
* @retval None
*/
-static void USART_DMAError(DMA_HandleTypeDef *hdma)
+static void USART_DMAError(DMA_HandleTypeDef *hdma)
{
+ uint32_t dmarequest = 0x00U;
USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ husart->RxXferCount = 0x00U;
+ husart->TxXferCount = 0x00U;
- husart->RxXferCount = 0;
- husart->TxXferCount = 0;
+ /* Stop USART DMA Tx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT);
+ if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest)
+ {
+ USART_EndTxTransfer(husart);
+ }
+
+ /* Stop USART DMA Rx request if ongoing */
+ dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR);
+ if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest)
+ {
+ USART_EndRxTransfer(husart);
+ }
+
husart->ErrorCode |= HAL_USART_ERROR_DMA;
husart->State= HAL_USART_STATE_READY;
-
+
HAL_USART_ErrorCallback(husart);
}
/**
* @brief This function handles USART Communication Timeout.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @param Flag: specifies the USART flag to check.
* @param Status: The new Flag status (SET or RESET).
- * @param Timeout: Timeout duration
+ * @param Tickstart: Tick start value.
+ * @param Timeout: Timeout duration.
* @retval HAL status
*/
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
{
- uint32_t tickstart = 0;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
/* Wait until flag is set */
- if(Status == RESET)
+ while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status)
{
- while(__HAL_USART_GET_FLAG(husart, Flag) == RESET)
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
__HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
__HAL_USART_DISABLE_IT(husart, USART_IT_PE);
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
- husart->State= HAL_USART_STATE_READY;
+ husart->State= HAL_USART_STATE_READY;
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
+ /* Process Unlocked */
+ __HAL_UNLOCK(husart);
- return HAL_TIMEOUT;
- }
- }
- }
- }
- else
- {
- while(__HAL_USART_GET_FLAG(husart, Flag) != RESET)
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
- __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
- __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
- __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
- __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
- husart->State= HAL_USART_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(husart);
-
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
}
}
@@ -1577,16 +1877,134 @@
}
/**
- * @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @brief End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).
+ * @param husart: USART handle.
+ * @retval None
+ */
+static void USART_EndTxTransfer(USART_HandleTypeDef *husart)
+{
+ /* Disable TXEIE and TCIE interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+ /* At end of Tx process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+}
+
+/**
+ * @brief End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).
+ * @param husart: USART handle.
+ * @retval None
+ */
+static void USART_EndRxTransfer(USART_HandleTypeDef *husart)
+{
+ /* Disable RXNE, PE and ERR interrupts */
+ CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+
+ /* At end of Rx process, restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+}
+
+/**
+ * @brief DMA USART communication abort callback, when initiated by HAL services on Error
+ * (To be called at end of DMA Abort procedure following error occurrence).
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ husart->RxXferCount = 0x00U;
+ husart->TxXferCount = 0x00U;
+
+ HAL_USART_ErrorCallback(husart);
+}
+
+/**
+ * @brief DMA USART Tx communication abort callback, when initiated by user
+ * (To be called at end of DMA Tx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Rx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ husart->hdmatx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(husart->hdmarx != NULL)
+ {
+ if(husart->hdmarx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ husart->TxXferCount = 0x00U;
+ husart->RxXferCount = 0x00U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_USART_AbortCpltCallback(husart);
+}
+
+/**
+ * @brief DMA USART Rx communication abort callback, when initiated by user
+ * (To be called at end of DMA Rx Abort procedure following user abort request).
+ * @note When this callback is executed, User Abort complete call back is called only if no
+ * Abort still ongoing for Tx DMA Handle.
+ * @param hdma DMA handle.
+ * @retval None
+ */
+static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+ USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+ husart->hdmarx->XferAbortCallback = NULL;
+
+ /* Check if an Abort process is still ongoing */
+ if(husart->hdmatx != NULL)
+ {
+ if(husart->hdmatx->XferAbortCallback != NULL)
+ {
+ return;
+ }
+ }
+
+ /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+ husart->TxXferCount = 0x00U;
+ husart->RxXferCount = 0x00U;
+
+ /* Reset errorCode */
+ husart->ErrorCode = HAL_USART_ERROR_NONE;
+
+ /* Restore husart->State to Ready */
+ husart->State = HAL_USART_STATE_READY;
+
+ /* Call user Abort complete callback */
+ HAL_USART_AbortCpltCallback(husart);
+}
+
+/**
+ * @brief Simplex Send an amount of data in non-blocking mode.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
* @note The USART errors are not managed to avoid the overrun error.
*/
static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
{
- uint16_t* tmp=0;
-
+ uint16_t* tmp;
+
if(husart->State == HAL_USART_STATE_BUSY_TX)
{
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
@@ -1595,24 +2013,24 @@
WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF));
if(husart->Init.Parity == USART_PARITY_NONE)
{
- husart->pTxBuffPtr += 2;
+ husart->pTxBuffPtr += 2U;
}
else
{
- husart->pTxBuffPtr += 1;
+ husart->pTxBuffPtr += 1U;
}
- }
+ }
else
- {
+ {
WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF));
}
-
- if(--husart->TxXferCount == 0)
+
+ if(--husart->TxXferCount == 0U)
{
/* Disable the USART Transmit data register empty Interrupt */
__HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
- /* Enable the USART Transmit Complete Interrupt */
+ /* Enable the USART Transmit Complete Interrupt */
__HAL_USART_ENABLE_IT(husart, USART_IT_TC);
}
return HAL_OK;
@@ -1623,7 +2041,6 @@
}
}
-
/**
* @brief Wraps up transmission in non blocking mode.
* @param husart: pointer to a USART_HandleTypeDef structure that contains
@@ -1632,29 +2049,28 @@
*/
static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
{
- /* Disable the USART Transmit Complete Interrupt */
+ /* Disable the USART Transmit Complete Interrupt */
__HAL_USART_DISABLE_IT(husart, USART_IT_TC);
-
+
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
+
husart->State = HAL_USART_STATE_READY;
-
+
HAL_USART_TxCpltCallback(husart);
-
+
return HAL_OK;
}
-
/**
- * @brief Simplex Receive an amount of data in non-blocking mode.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @brief Simplex Receive an amount of data in non-blocking mode.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
{
- uint16_t* tmp=0;
+ uint16_t* tmp;
if(husart->State == HAL_USART_STATE_BUSY_RX)
{
if(husart->Init.WordLength == USART_WORDLENGTH_9B)
@@ -1663,19 +2079,19 @@
if(husart->Init.Parity == USART_PARITY_NONE)
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
- husart->pRxBuffPtr += 2;
+ husart->pRxBuffPtr += 2U;
}
else
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
- husart->pRxBuffPtr += 1;
+ husart->pRxBuffPtr += 1U;
}
- if(--husart->RxXferCount != 0x00)
+ if(--husart->RxXferCount != 0x00U)
{
/* Send dummy byte in order to generate the clock for the slave to send the next data */
WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF));
}
- }
+ }
else
{
if(husart->Init.Parity == USART_PARITY_NONE)
@@ -1687,50 +2103,50 @@
*husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
}
- if(--husart->RxXferCount != 0x00)
+ if(--husart->RxXferCount != 0x00U)
{
/* Send dummy byte in order to generate the clock for the slave to send the next data */
WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF));
}
}
- if(husart->RxXferCount == 0)
+ if(husart->RxXferCount == 0U)
{
/* Disable the USART RXNE Interrupt */
- __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
/* Disable the USART Parity Error Interrupt */
- __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
husart->State = HAL_USART_STATE_READY;
HAL_USART_RxCpltCallback(husart);
-
+
return HAL_OK;
}
return HAL_OK;
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
{
- uint16_t* tmp=0;
+ uint16_t* tmp;
if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
{
- if(husart->TxXferCount != 0x00)
+ if(husart->TxXferCount != 0x00U)
{
if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
{
@@ -1740,13 +2156,13 @@
WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF));
if(husart->Init.Parity == USART_PARITY_NONE)
{
- husart->pTxBuffPtr += 2;
+ husart->pTxBuffPtr += 2U;
}
else
{
- husart->pTxBuffPtr += 1;
+ husart->pTxBuffPtr += 1U;
}
- }
+ }
else
{
WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF));
@@ -1754,14 +2170,14 @@
husart->TxXferCount--;
/* Check the latest data transmitted */
- if(husart->TxXferCount == 0)
+ if(husart->TxXferCount == 0U)
{
- __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE);
}
}
}
- if(husart->RxXferCount != 0x00)
+ if(husart->RxXferCount != 0x00U)
{
if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
{
@@ -1771,14 +2187,14 @@
if(husart->Init.Parity == USART_PARITY_NONE)
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
- husart->pRxBuffPtr += 2;
+ husart->pRxBuffPtr += 2U;
}
else
{
*tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
- husart->pRxBuffPtr += 1;
+ husart->pRxBuffPtr += 1U;
}
- }
+ }
else
{
if(husart->Init.Parity == USART_PARITY_NONE)
@@ -1795,15 +2211,16 @@
}
/* Check the latest data received */
- if(husart->RxXferCount == 0)
+ if(husart->RxXferCount == 0U)
{
- __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
+ /* Disable the USART RXNE Interrupt */
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE);
/* Disable the USART Parity Error Interrupt */
- __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
+ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
/* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
- __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
husart->State = HAL_USART_STATE_READY;
@@ -1816,13 +2233,13 @@
}
else
{
- return HAL_BUSY;
+ return HAL_BUSY;
}
}
/**
- * @brief Configures the USART peripheral.
- * @param husart: Pointer to a USART_HandleTypeDef structure that contains
+ * @brief Configures the USART pferipheral.
+ * @param husart: pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_wwdg.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_wwdg.c
index 162161a..bac78ac 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_wwdg.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_hal_wwdg.c
@@ -2,22 +2,21 @@
******************************************************************************
* @file stm32f1xx_hal_wwdg.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral State functions
- *
+ * + Peripheral State functions
@verbatim
==============================================================================
##### WWDG specific features #####
==============================================================================
[..]
Once enabled the WWDG generates a system reset on expiry of a programmed
- time period, unless the program refreshes the Counter (T[6;0] downcounter)
+ time period, unless the program refreshes the counter (downcounter)
before reaching 0x3F value (i.e. a reset is generated when the counter
value rolls over from 0x40 to 0x3F).
@@ -29,43 +28,63 @@
reset occurs.
(+) The WWDG counter input clock is derived from the APB clock divided
by a programmable prescaler.
- (+) WWDG clock (Hz) = PCLK / (4096 * Prescaler)
- (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock
- where T[5;0] are the lowest 6 bits of Counter.
+ (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
+ (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
(+) WWDG Counter refresh is allowed between the following limits :
- (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
- (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
+ (++) min time (mS) = 1000 * (Counter _ Window) / WWDG clock
+ (++) max time (mS) = 1000 * (Counter _ 0x40) / WWDG clock
- (+) Min-max timeout value @48 MHz(PCLK): ~85,3us / ~5,46 ms
+ (+) Min-max timeout value at 36 MHz(PCLK1): 910 us / 58.25 ms
+
+ (+) The Early Wakeup Interrupt (EWI) can be used if specific safety
+ operations or data logging must be performed before the actual reset is
+ generated. When the downcounter reaches the value 0x40, an EWI interrupt
+ is generated and the corresponding interrupt service routine (ISR) can
+ be used to trigger specific actions (such as communications or data
+ logging), before resetting the device.
+ In some applications, the EWI interrupt can be used to manage a software
+ system check and/or system recovery/graceful degradation, without
+ generating a WWDG reset. In this case, the corresponding interrupt
+ service routine (ISR) should reload the WWDG counter to avoid the WWDG
+ reset, then trigger the required actions.
+ Note:When the EWI interrupt cannot be served, e.g. due to a system lock
+ in a higher priority task, the WWDG reset will eventually be generated.
+
+ (+) Debug mode : When the microcontroller enters debug mode (core halted),
+ the WWDG counter either continues to work normally or stops, depending
+ on DBG_WWDG_STOP configuration bit in DBG module, accessible through
+ __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
##### How to use this driver #####
==============================================================================
[..]
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
- (+) Set the WWDG prescaler, refresh window and counter value
- using HAL_WWDG_Init() function.
- (+) Start the WWDG using HAL_WWDG_Start() function.
- When the WWDG is enabled the counter value should be configured to
- a value greater than 0x40 to prevent generating an immediate reset.
- (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
- generated when the counter reaches 0x40, and then start the WWDG using
- HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
- add his own code by customization of function pointer HAL_WWDG_WakeupCallback
- Once enabled, EWI interrupt cannot be disabled except by a system reset.
- (+) Then the application program must refresh the WWDG counter at regular
- intervals during normal operation to prevent an MCU reset, using
+
+ (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
+ Interrupt mode using using HAL_WWDG_Init() function.
+ This enables WWDG peripheral and the downcounter starts downcounting
+ from given counter value.
+ Init function can be called again to modify all watchdog parameters,
+ however if EWI mode has been set once, it can't be clear until next
+ reset.
+
+ (+) The application program must refresh the WWDG counter at regular
+ intervals during normal operation to prevent an MCU reset using
HAL_WWDG_Refresh() function. This operation must occur only when
- the counter is lower than the refresh window value already programmed.
-
+ the counter is lower than the window value already programmed.
+
+ (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
+ the counter reaches 0x40. User can add his own code in weak function
+ HAL_WWDG_EarlyWakeupCallback().
+
*** WWDG HAL driver macros list ***
==================================
[..]
Below the list of most used macros in WWDG HAL driver.
-
- (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
- (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
- (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
- (+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wakeup interrupt
+
+ (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
+ (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
+ (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
@endverbatim
******************************************************************************
@@ -96,7 +115,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
@@ -105,13 +124,12 @@
* @{
*/
+#ifdef HAL_WWDG_MODULE_ENABLED
/** @defgroup WWDG WWDG
* @brief WWDG HAL module driver.
* @{
*/
-#ifdef HAL_WWDG_MODULE_ENABLED
-
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -123,30 +141,28 @@
* @{
*/
-/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions.
- *
-@verbatim
+/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions.
+ *
+@verbatim
==============================================================================
- ##### Initialization and de-initialization functions #####
+ ##### Initialization and Configuration functions #####
==============================================================================
[..]
This section provides functions allowing to:
- (+) Initialize the WWDG according to the specified parameters
- in the WWDG_InitTypeDef and create the associated handle
- (+) DeInitialize the WWDG peripheral
- (+) Initialize the WWDG MSP
- (+) DeInitialize the WWDG MSP
-
+ (+) Initialize and start the WWDG according to the specified parameters
+ in the WWDG_InitTypeDef of associated handle.
+ (+) Initialize the WWDG MSP.
+
@endverbatim
* @{
*/
/**
- * @brief Initializes the WWDG according to the specified
- * parameters in the WWDG_InitTypeDef and creates the associated handle.
- * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
+ * @brief Initialize the WWDG according to the specified.
+ * parameters in the WWDG_InitTypeDef of associated handle.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
@@ -160,257 +176,121 @@
/* Check the parameters */
assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
- assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
- assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
-
- if(hwwdg->State == HAL_WWDG_STATE_RESET)
- {
- /* Allocate lock resource and initialize it */
- hwwdg->Lock = HAL_UNLOCKED;
-
- /* Init the low level hardware */
- HAL_WWDG_MspInit(hwwdg);
- }
-
- /* Change WWDG peripheral state */
- hwwdg->State = HAL_WWDG_STATE_BUSY;
+ assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
+ assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
+ assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
+
+ /* Init the low level hardware */
+ HAL_WWDG_MspInit(hwwdg);
+
+ /* Set WWDG Counter */
+ WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
/* Set WWDG Prescaler and Window */
- MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window));
-
- /* Set WWDG Counter */
- MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter);
-
- /* Change WWDG peripheral state */
- hwwdg->State = HAL_WWDG_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief DeInitializes the WWDG peripheral.
- * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
-{
- /* Check the WWDG handle allocation */
- if(hwwdg == NULL)
- {
- return HAL_ERROR;
- }
-
- /* Check the parameters */
- assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
-
- /* Change WWDG peripheral state */
- hwwdg->State = HAL_WWDG_STATE_BUSY;
-
- /* DeInit the low level hardware */
- HAL_WWDG_MspDeInit(hwwdg);
-
- /* Reset WWDG Control register */
- hwwdg->Instance->CR = (uint32_t)0x0000007F;
-
- /* Reset WWDG Configuration register */
- hwwdg->Instance->CFR = (uint32_t)0x0000007F;
-
- /* Reset WWDG Status register */
- hwwdg->Instance->SR = 0;
-
- /* Change WWDG peripheral state */
- hwwdg->State = HAL_WWDG_STATE_RESET;
-
- /* Release Lock */
- __HAL_UNLOCK(hwwdg);
+ WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
/* Return function status */
return HAL_OK;
}
/**
- * @brief Initializes the WWDG MSP.
- * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
+ * @brief Initialize the WWDG MSP.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
+ * @note When rewriting this function in user file, mechanism may be added
+ * to avoid multiple initialize when HAL_WWDG_Init function is called
+ * again to change parameters.
* @retval None
*/
__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hwwdg);
- /* NOTE: This function Should not be modified, when the callback is needed,
+
+ /* NOTE: This function should not be modified, when the callback is needed,
the HAL_WWDG_MspInit could be implemented in the user file
*/
}
/**
- * @brief DeInitializes the WWDG MSP.
- * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval None
- */
-__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
-{
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hwwdg);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_WWDG_MspDeInit could be implemented in the user file
- */
-}
-
-/**
* @}
*/
-/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
+/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
*
-@verbatim
+@verbatim
==============================================================================
- ##### IO operation functions #####
+ ##### IO operation functions #####
==============================================================================
- [..]
+ [..]
This section provides functions allowing to:
- (+) Start the WWDG.
(+) Refresh the WWDG.
- (+) Handle WWDG interrupt request.
+ (+) Handle WWDG interrupt request and associated function callback.
@endverbatim
* @{
*/
/**
- * @brief Starts the WWDG.
- * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
+ * @brief Refresh the WWDG.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg)
+HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
{
- /* Process Locked */
- __HAL_LOCK(hwwdg);
-
- /* Change WWDG peripheral state */
- hwwdg->State = HAL_WWDG_STATE_BUSY;
-
- /* Enable the peripheral */
- __HAL_WWDG_ENABLE(hwwdg);
-
- /* Change WWDG peripheral state */
- hwwdg->State = HAL_WWDG_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hwwdg);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Starts the WWDG with interrupt enabled.
- * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)
-{
- /* Process Locked */
- __HAL_LOCK(hwwdg);
-
- /* Change WWDG peripheral state */
- hwwdg->State = HAL_WWDG_STATE_BUSY;
-
- /* Enable the Early Wakeup Interrupt */
- __HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI);
-
- /* Enable the peripheral */
- __HAL_WWDG_ENABLE(hwwdg);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Refreshes the WWDG.
- * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @param Counter: value of counter to put in WWDG counter
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
-{
- /* Process Locked */
- __HAL_LOCK(hwwdg);
-
- /* Change WWDG peripheral state */
- hwwdg->State = HAL_WWDG_STATE_BUSY;
-
- /* Check the parameters */
- assert_param(IS_WWDG_COUNTER(Counter));
-
/* Write to WWDG CR the WWDG Counter value to refresh with */
- MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter);
-
- /* Change WWDG peripheral state */
- hwwdg->State = HAL_WWDG_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hwwdg);
-
+ WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
+
/* Return function status */
return HAL_OK;
}
/**
- * @brief Handles WWDG interrupt request.
- * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
- * or data logging must be performed before the actual reset is generated.
- * The EWI interrupt is enabled when calling HAL_WWDG_Start_IT function.
- * When the downcounter reaches the value 0x40, and EWI interrupt is
- * generated and the corresponding Interrupt Service Routine (ISR) can
- * be used to trigger specific actions (such as communications or data
- * logging), before resetting the device.
- * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
+ * @brief Handle WWDG interrupt request.
+ * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
+ * or data logging must be performed before the actual reset is generated.
+ * The EWI interrupt is enabled by calling HAL_WWDG_Init function with
+ * EWIMode set to WWDG_EWI_ENABLE.
+ * When the downcounter reaches the value 0x40, and EWI interrupt is
+ * generated and the corresponding Interrupt Service Routine (ISR) can
+ * be used to trigger specific actions (such as communications or data
+ * logging), before resetting the device.
+ * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
* @retval None
*/
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
-{
+{
/* Check if Early Wakeup Interrupt is enable */
if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
{
- /* Wheck if WWDG Early Wakeup Interrupt occurred */
- if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
- {
- /* Early Wakeup callback */
- HAL_WWDG_WakeupCallback(hwwdg);
-
- /* Change WWDG peripheral state */
- hwwdg->State = HAL_WWDG_STATE_READY;
-
+ /* Check if WWDG Early Wakeup Interrupt occurred */
+ if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
+ {
/* Clear the WWDG Early Wakeup flag */
- __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
-
- /* Process Unlocked */
- __HAL_UNLOCK(hwwdg);
+ __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
+
+ /* Early Wakeup callback */
+ HAL_WWDG_EarlyWakeupCallback(hwwdg);
+ }
}
-}
}
/**
- * @brief Early Wakeup WWDG callback.
- * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
+ * @brief WWDG Early Wakeup callback.
+ * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains
+ * the configuration information for the specified WWDG module.
* @retval None
*/
-__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
+__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hwwdg);
- /* NOTE: This function Should not be modified, when the callback is needed,
- the HAL_WWDG_WakeupCallback could be implemented in the user file
+
+ /* NOTE: This function should not be modified, when the callback is needed,
+ the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
*/
}
@@ -418,36 +298,6 @@
* @}
*/
-/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions
- * @brief Peripheral State functions.
- *
-@verbatim
- ==============================================================================
- ##### Peripheral State functions #####
- ==============================================================================
- [..]
- This subsection permits to get in run-time the status of the peripheral
- and the data flow.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the WWDG state.
- * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
- * the configuration information for the specified WWDG module.
- * @retval HAL state
- */
-HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg)
-{
- return hwwdg->State;
-}
-
-/**
- * @}
- */
-
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_adc.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_adc.c
new file mode 100644
index 0000000..24ff8f3
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_adc.c
@@ -0,0 +1,903 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_adc.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief ADC LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_adc.h"
+#include "stm32f1xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC3)
+
+/** @addtogroup ADC_LL ADC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+ * @{
+ */
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* common to several ADC instances. */
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC instance. */
+#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
+ ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
+ || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
+ )
+
+#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
+ ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
+ || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
+ )
+
+#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
+ ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
+ || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group regular */
+#if defined(ADC3)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
+ ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
+ ) \
+ : \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \
+ ) \
+ )
+#else
+#if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
+ )
+#else
+#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
+ ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
+ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
+ )
+#endif
+#endif
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
+ ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
+ || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
+ )
+
+#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
+ ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
+ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
+ ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
+ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
+ )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
+ ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
+ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
+ )
+
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* ADC group injected */
+#if defined(ADC3)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
+ ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
+ ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
+ ) \
+ : \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \
+ ) \
+ )
+#else
+#if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
+ )
+#else
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
+ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
+ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
+ )
+#endif
+#endif
+#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
+ ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
+ || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
+ )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
+ ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
+ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
+ )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
+ ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
+ || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
+ )
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* Check of parameters for configuration of ADC hierarchical scope: */
+/* multimode. */
+#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
+ ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_FAST) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_SLOW) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM) \
+ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM) \
+ )
+
+#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
+ ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
+ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
+ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
+ )
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ADC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of all ADC instances belonging to
+ * the same ADC common instance to their default reset values.
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
+{
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+
+ /* Force reset of ADC clock (core clock) */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1);
+
+ /* Release reset of ADC clock (core clock) */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize some features of ADC common parameters
+ * (all ADC instances belonging to the same ADC common instance)
+ * and multimode (for devices with several ADC instances available).
+ * @note The setting of ADC common parameters is conditioned to
+ * ADC instances state:
+ * All ADC instances belonging to the same ADC common instance
+ * must be disabled.
+ * @param ADCxy_COMMON ADC common instance
+ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+ * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC common registers are initialized
+ * - ERROR: ADC common registers are not initialized
+ */
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+#if defined(ADC_MULTIMODE_SUPPORT)
+ assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+ /* Note: Hardware constraint (refer to description of functions */
+ /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
+ /* On this STM32 serie, setting of these features is conditioned to */
+ /* ADC state: */
+ /* All ADC instances of the ADC common group must be disabled. */
+ if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - common to several ADC */
+ /* (all ADC instances belonging to the same ADC common instance) */
+ /* - multimode (if several ADC instances available on the */
+ /* selected device) */
+ /* - Set ADC multimode configuration */
+ /* - Set ADC multimode DMA transfer */
+ /* - Set ADC multimode: delay between 2 sampling phases */
+#if defined(ADC_MULTIMODE_SUPPORT)
+ if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+ {
+ MODIFY_REG(ADCxy_COMMON->CR1,
+ ADC_CR1_DUALMOD,
+ ADC_CommonInitStruct->Multimode
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCxy_COMMON->CR1,
+ ADC_CR1_DUALMOD,
+ LL_ADC_MULTI_INDEPENDENT
+ );
+ }
+#endif
+ }
+ else
+ {
+ /* Initialization error: One or several ADC instances belonging to */
+ /* the same ADC common instance are not disabled. */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
+ * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+{
+ /* Set ADC_CommonInitStruct fields to default values */
+ /* Set fields of ADC common */
+ /* (all ADC instances belonging to the same ADC common instance) */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+ /* Set fields of ADC multimode */
+ ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
+#endif /* ADC_MULTIMODE_SUPPORT */
+}
+
+/**
+ * @brief De-initialize registers of the selected ADC instance
+ * to their default reset values.
+ * @note To reset all ADC instances quickly (perform a hard reset),
+ * use function @ref LL_ADC_CommonDeInit().
+ * @param ADCx ADC instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are de-initialized
+ * - ERROR: ADC registers are not de-initialized
+ */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ /* Disable ADC instance if not already disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 1U)
+ {
+ /* Set ADC group regular trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
+
+ /* Set ADC group injected trigger source to SW start to ensure to not */
+ /* have an external trigger event occurring during the conversion stop */
+ /* ADC disable process. */
+ LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
+
+ /* Disable the ADC instance */
+ LL_ADC_Disable(ADCx);
+ }
+
+ /* Check whether ADC state is compliant with expected state */
+ /* (hardware requirements of bits state to reset registers below) */
+ if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
+ {
+ /* ========== Reset ADC registers ========== */
+ /* Reset register SR */
+ CLEAR_BIT(ADCx->SR,
+ ( LL_ADC_FLAG_STRT
+ | LL_ADC_FLAG_JSTRT
+ | LL_ADC_FLAG_EOS
+ | LL_ADC_FLAG_JEOS
+ | LL_ADC_FLAG_AWD1 )
+ );
+
+ /* Reset register CR1 */
+ #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
+
+ CLEAR_BIT(ADCx->CR1,
+ ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DUALMOD
+ | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
+ | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
+ | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
+ | ADC_CR1_AWDCH )
+ );
+ #else
+
+ CLEAR_BIT(ADCx->CR1,
+ ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM
+ | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO
+ | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE
+ | ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH )
+ );
+ #endif
+
+ /* Reset register CR2 */
+ CLEAR_BIT(ADCx->CR2,
+ ( ADC_CR2_TSVREFE
+ | ADC_CR2_SWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL
+ | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL
+ | ADC_CR2_ALIGN | ADC_CR2_DMA
+ | ADC_CR2_RSTCAL | ADC_CR2_CAL
+ | ADC_CR2_CONT | ADC_CR2_ADON )
+ );
+
+ /* Reset register SMPR1 */
+ CLEAR_BIT(ADCx->SMPR1,
+ ( ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
+ | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
+ | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
+ );
+
+ /* Reset register SMPR2 */
+ CLEAR_BIT(ADCx->SMPR2,
+ ( ADC_SMPR2_SMP9
+ | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
+ | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
+ | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
+ );
+
+ /* Reset register JOFR1 */
+ CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
+ /* Reset register JOFR2 */
+ CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
+ /* Reset register JOFR3 */
+ CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
+ /* Reset register JOFR4 */
+ CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
+
+ /* Reset register HTR */
+ SET_BIT(ADCx->HTR, ADC_HTR_HT);
+ /* Reset register LTR */
+ CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
+
+ /* Reset register SQR1 */
+ CLEAR_BIT(ADCx->SQR1,
+ ( ADC_SQR1_L
+ | ADC_SQR1_SQ16
+ | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
+ );
+
+ /* Reset register SQR2 */
+ CLEAR_BIT(ADCx->SQR2,
+ ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
+ | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
+ );
+
+
+ /* Reset register JSQR */
+ CLEAR_BIT(ADCx->JSQR,
+ ( ADC_JSQR_JL
+ | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
+ | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
+ );
+
+ /* Reset register DR */
+ /* bits in access mode read only, no direct reset applicable */
+
+ /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+ /* bits in access mode read only, no direct reset applicable */
+
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize some features of ADC instance.
+ * @note These parameters have an impact on ADC scope: ADC instance.
+ * Affects both group regular and group injected (availability
+ * of ADC group injected depends on STM32 families).
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Instance .
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, some other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+ assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
+ assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC instance */
+ /* - Set ADC conversion data alignment */
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_SCAN
+ ,
+ ADC_InitStruct->SequencersScanMode
+ );
+
+ MODIFY_REG(ADCx->CR2,
+ ADC_CR2_ALIGN
+ ,
+ ADC_InitStruct->DataAlignment
+ );
+
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
+ * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
+{
+ /* Set ADC_InitStruct fields to default values */
+ /* Set fields of ADC instance */
+ ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+
+ /* Enable scan mode to have a generic behavior with ADC of other */
+ /* STM32 families, without this setting available: */
+ /* ADC group regular sequencer and ADC group injected sequencer depend */
+ /* only of their own configuration. */
+ ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
+
+}
+
+/**
+ * @brief Initialize some features of ADC group regular.
+ * @note These parameters have an impact on ADC scope: ADC group regular.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "REG").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group regular or group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+#if defined(ADC3)
+ assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
+#else
+ assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
+#endif
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
+ if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
+ assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group regular */
+ /* - Set ADC group regular trigger source */
+ /* - Set ADC group regular sequencer length */
+ /* - Set ADC group regular sequencer discontinuous mode */
+ /* - Set ADC group regular continuous mode */
+ /* - Set ADC group regular conversion data transfer: no transfer or */
+ /* transfer by DMA, and DMA requests mode */
+ /* Note: On this STM32 serie, ADC trigger edge is set when starting */
+ /* ADC conversion. */
+ /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
+ if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_DISCEN
+ | ADC_CR1_DISCNUM
+ ,
+ ADC_REG_InitStruct->SequencerLength
+ | ADC_REG_InitStruct->SequencerDiscont
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_DISCEN
+ | ADC_CR1_DISCNUM
+ ,
+ ADC_REG_InitStruct->SequencerLength
+ | LL_ADC_REG_SEQ_DISCONT_DISABLE
+ );
+ }
+
+ MODIFY_REG(ADCx->CR2,
+ ADC_CR2_EXTSEL
+ | ADC_CR2_CONT
+ | ADC_CR2_DMA
+ ,
+ ADC_REG_InitStruct->TriggerSource
+ | ADC_REG_InitStruct->ContinuousMode
+ | ADC_REG_InitStruct->DMATransfer
+ );
+
+ /* Set ADC group regular sequencer length and scan direction */
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* Note: If ADC instance feature scan mode is disabled */
+ /* (refer to ADC instance initialization structure */
+ /* parameter @ref SequencersScanMode */
+ /* or function @ref LL_ADC_SetSequencersScanMode() ), */
+ /* this parameter is discarded. */
+ LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+ * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+{
+ /* Set ADC_REG_InitStruct fields to default values */
+ /* Set fields of ADC group regular */
+ /* Note: On this STM32 serie, ADC trigger edge is set when starting */
+ /* ADC conversion. */
+ /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
+ ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
+ ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
+ ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+ ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
+ ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
+}
+
+/**
+ * @brief Initialize some features of ADC group injected.
+ * @note These parameters have an impact on ADC scope: ADC group injected.
+ * Refer to corresponding unitary functions into
+ * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+ * (functions with prefix "INJ").
+ * @note The setting of these parameters by function @ref LL_ADC_Init()
+ * is conditioned to ADC state:
+ * ADC instance must be disabled.
+ * This condition is applied to all ADC features, for efficiency
+ * and compatibility over all STM32 families. However, the different
+ * features can be set under different ADC state conditions
+ * (setting possible with ADC enabled without conversion on going,
+ * ADC enabled with conversion on going, ...)
+ * Each feature can be updated afterwards with a unitary function
+ * and potentially with ADC in a different state than disabled,
+ * refer to description of each function for setting
+ * conditioned to ADC state.
+ * @note After using this function, other features must be configured
+ * using LL unitary functions.
+ * The minimum configuration remaining to be done is:
+ * - Set ADC group injected sequencer:
+ * map channel on the selected sequencer rank.
+ * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
+ * - Set ADC channel sampling time
+ * Refer to function LL_ADC_SetChannelSamplingTime();
+ * @param ADCx ADC instance
+ * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ADC registers are initialized
+ * - ERROR: ADC registers are not initialized
+ */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+#if defined(ADC3)
+ assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
+#else
+ assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
+#endif
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
+ if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
+ {
+ assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
+ }
+ assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* ADC instance must be disabled. */
+ if(LL_ADC_IsEnabled(ADCx) == 0U)
+ {
+ /* Configuration of ADC hierarchical scope: */
+ /* - ADC group injected */
+ /* - Set ADC group injected trigger source */
+ /* - Set ADC group injected sequencer length */
+ /* - Set ADC group injected sequencer discontinuous mode */
+ /* - Set ADC group injected conversion trigger: independent or */
+ /* from ADC group regular */
+ /* Note: On this STM32 serie, ADC trigger edge is set when starting */
+ /* ADC conversion. */
+ /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
+ if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_JDISCEN
+ | ADC_CR1_JAUTO
+ ,
+ ADC_INJ_InitStruct->SequencerDiscont
+ | ADC_INJ_InitStruct->TrigAuto
+ );
+ }
+ else
+ {
+ MODIFY_REG(ADCx->CR1,
+ ADC_CR1_JDISCEN
+ | ADC_CR1_JAUTO
+ ,
+ LL_ADC_REG_SEQ_DISCONT_DISABLE
+ | ADC_INJ_InitStruct->TrigAuto
+ );
+ }
+
+ MODIFY_REG(ADCx->CR2,
+ ADC_CR2_JEXTSEL
+ ,
+ ADC_INJ_InitStruct->TriggerSource
+ );
+
+ /* Note: Hardware constraint (refer to description of this function): */
+ /* Note: If ADC instance feature scan mode is disabled */
+ /* (refer to ADC instance initialization structure */
+ /* parameter @ref SequencersScanMode */
+ /* or function @ref LL_ADC_SetSequencersScanMode() ), */
+ /* this parameter is discarded. */
+ LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
+ }
+ else
+ {
+ /* Initialization error: ADC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
+ * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+{
+ /* Set ADC_INJ_InitStruct fields to default values */
+ /* Set fields of ADC group injected */
+ ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
+ ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
+ ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
+ ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* ADC1 || ADC2 || ADC3 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_crc.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_crc.c
new file mode 100644
index 0000000..7d07f8f
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_crc.c
@@ -0,0 +1,126 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_crc.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief CRC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_crc.h"
+#include "stm32f1xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (CRC)
+
+/** @addtogroup CRC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CRC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CRC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize CRC registers (Registers restored to their default values).
+ * @param CRCx CRC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: CRC registers are de-initialized
+ * - ERROR: CRC registers are not de-initialized
+ */
+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_CRC_ALL_INSTANCE(CRCx));
+
+ if (CRCx == CRC)
+ {
+
+ /* Reset the CRC calculation unit */
+ LL_CRC_ResetCRCCalculationUnit(CRCx);
+
+ /* Reset IDR register */
+ LL_CRC_Write_IDR(CRCx, 0x00U);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (CRC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_dac.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_dac.c
new file mode 100644
index 0000000..60b8730
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_dac.c
@@ -0,0 +1,274 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_dac.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief DAC LL module driver
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_dac.h"
+#include "stm32f1xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (DAC)
+
+/** @addtogroup DAC_LL DAC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup DAC_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
+ ( \
+ ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
+ || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
+ )
+
+#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
+ ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \
+ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
+ )
+#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
+ ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
+ || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+ )
+
+#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \
+ ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
+ || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \
+ )
+
+#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
+ ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
+ || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
+ )
+
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DAC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DAC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize registers of the selected DAC instance
+ * to their default reset values.
+ * @param DACx DAC instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DAC registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(DACx));
+
+ /* Force reset of DAC1 clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
+
+ /* Release reset of DAC1 clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize some features of DAC instance.
+ * @note The setting of these parameters by function @ref LL_DAC_Init()
+ * is conditioned to DAC state:
+ * DAC instance must be disabled.
+ * @param DACx DAC instance
+ * @param DAC_Channel This parameter can be one of the following values:
+ * @arg @ref LL_DAC_CHANNEL_1
+ * @arg @ref LL_DAC_CHANNEL_2
+ * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DAC registers are initialized
+ * - ERROR: DAC registers are not initialized
+ */
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_INSTANCE(DACx));
+ assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
+ assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
+ assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
+ assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
+ if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+ {
+ assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
+ }
+
+ /* Note: Hardware constraint (refer to description of this function) */
+ /* DAC instance must be disabled. */
+ if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
+ {
+ /* Configuration of DAC channel: */
+ /* - TriggerSource */
+ /* - WaveAutoGeneration */
+ /* - OutputBuffer */
+ if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
+ {
+ MODIFY_REG(DACx->CR,
+ ( DAC_CR_TSEL1
+ | DAC_CR_WAVE1
+ | DAC_CR_MAMP1
+ | DAC_CR_BOFF1
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ ,
+ ( DAC_InitStruct->TriggerSource
+ | DAC_InitStruct->WaveAutoGeneration
+ | DAC_InitStruct->WaveAutoGenerationConfig
+ | DAC_InitStruct->OutputBuffer
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+ }
+ else
+ {
+ MODIFY_REG(DACx->CR,
+ ( DAC_CR_TSEL1
+ | DAC_CR_WAVE1
+ | DAC_CR_BOFF1
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ ,
+ ( DAC_InitStruct->TriggerSource
+ | LL_DAC_WAVE_AUTO_GENERATION_NONE
+ | DAC_InitStruct->OutputBuffer
+ ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+ );
+ }
+ }
+ else
+ {
+ /* Initialization error: DAC instance is not disabled. */
+ status = ERROR;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_DAC_InitTypeDef field to default value.
+ * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
+{
+ /* Set DAC_InitStruct fields to default values */
+ DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE;
+ DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE;
+ /* Note: Parameter discarded if wave auto generation is disabled, */
+ /* set anyway to its default value. */
+ DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
+ DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DAC */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_dma.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_dma.c
new file mode 100644
index 0000000..d90bfa0
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_dma.c
@@ -0,0 +1,331 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_dma.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief DMA LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_dma.h"
+#include "stm32f1xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup DMA_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
+ ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
+
+#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
+ ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
+
+#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+
+#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+ ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+
+#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+
+#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
+ ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+
+#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
+
+#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
+ ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+
+#if defined (DMA2)
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
+ (((INSTANCE) == DMA2) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5))))
+#else
+#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
+ (((CHANNEL) == LL_DMA_CHANNEL_1) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_2) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_3) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_4) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_5) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_6) || \
+ ((CHANNEL) == LL_DMA_CHANNEL_7))))
+#endif
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DMA_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup DMA_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the DMA registers to their default reset values.
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA registers are de-initialized
+ * - ERROR: DMA registers are not de-initialized
+ */
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
+{
+ DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
+ ErrorStatus status = SUCCESS;
+
+ /* Check the DMA Instance DMAx and Channel parameters*/
+ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+ tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
+
+ /* Disable the selected DMAx_Channely */
+ CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
+
+ /* Reset DMAx_Channely control register */
+ LL_DMA_WriteReg(tmp, CCR, 0U);
+
+ /* Reset DMAx_Channely remaining bytes register */
+ LL_DMA_WriteReg(tmp, CNDTR, 0U);
+
+ /* Reset DMAx_Channely peripheral address register */
+ LL_DMA_WriteReg(tmp, CPAR, 0U);
+
+ /* Reset DMAx_Channely memory address register */
+ LL_DMA_WriteReg(tmp, CMAR, 0U);
+
+ if (Channel == LL_DMA_CHANNEL_1)
+ {
+ /* Reset interrupt pending bits for DMAx Channel1 */
+ LL_DMA_ClearFlag_GI1(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_2)
+ {
+ /* Reset interrupt pending bits for DMAx Channel2 */
+ LL_DMA_ClearFlag_GI2(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_3)
+ {
+ /* Reset interrupt pending bits for DMAx Channel3 */
+ LL_DMA_ClearFlag_GI3(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_4)
+ {
+ /* Reset interrupt pending bits for DMAx Channel4 */
+ LL_DMA_ClearFlag_GI4(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_5)
+ {
+ /* Reset interrupt pending bits for DMAx Channel5 */
+ LL_DMA_ClearFlag_GI5(DMAx);
+ }
+
+ else if (Channel == LL_DMA_CHANNEL_6)
+ {
+ /* Reset interrupt pending bits for DMAx Channel6 */
+ LL_DMA_ClearFlag_GI6(DMAx);
+ }
+ else if (Channel == LL_DMA_CHANNEL_7)
+ {
+ /* Reset interrupt pending bits for DMAx Channel7 */
+ LL_DMA_ClearFlag_GI7(DMAx);
+ }
+ else
+ {
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
+ * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
+ * @arg @ref __LL_DMA_GET_INSTANCE
+ * @arg @ref __LL_DMA_GET_CHANNEL
+ * @param DMAx DMAx Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_DMA_CHANNEL_1
+ * @arg @ref LL_DMA_CHANNEL_2
+ * @arg @ref LL_DMA_CHANNEL_3
+ * @arg @ref LL_DMA_CHANNEL_4
+ * @arg @ref LL_DMA_CHANNEL_5
+ * @arg @ref LL_DMA_CHANNEL_6
+ * @arg @ref LL_DMA_CHANNEL_7
+ * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: DMA registers are initialized
+ * - ERROR: Not applicable
+ */
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Check the DMA Instance DMAx and Channel parameters*/
+ assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
+
+ /* Check the DMA parameters from DMA_InitStruct */
+ assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
+ assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
+ assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
+ assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
+ assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
+ assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
+ assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
+ assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
+
+ /*---------------------------- DMAx CCR Configuration ------------------------
+ * Configure DMAx_Channely: data transfer direction, data transfer mode,
+ * peripheral and memory increment mode,
+ * data size alignment and priority level with parameters :
+ * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
+ * - Mode: DMA_CCR_CIRC bit
+ * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
+ * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
+ * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
+ * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
+ * - Priority: DMA_CCR_PL[1:0] bits
+ */
+ LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
+ DMA_InitStruct->Mode | \
+ DMA_InitStruct->PeriphOrM2MSrcIncMode | \
+ DMA_InitStruct->MemoryOrM2MDstIncMode | \
+ DMA_InitStruct->PeriphOrM2MSrcDataSize | \
+ DMA_InitStruct->MemoryOrM2MDstDataSize | \
+ DMA_InitStruct->Priority);
+
+ /*-------------------------- DMAx CMAR Configuration -------------------------
+ * Configure the memory or destination base address with parameter :
+ * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
+ */
+ LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
+
+ /*-------------------------- DMAx CPAR Configuration -------------------------
+ * Configure the peripheral or source base address with parameter :
+ * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
+ */
+ LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
+
+ /*--------------------------- DMAx CNDTR Configuration -----------------------
+ * Configure the peripheral base address with parameter :
+ * - NbData: DMA_CNDTR_NDT[15:0] bits
+ */
+ LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
+ * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
+ * @retval None
+ */
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
+{
+ /* Set DMA_InitStruct fields to default values */
+ DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
+ DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
+ DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+ DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
+ DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
+ DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
+ DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
+ DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
+ DMA_InitStruct->NbData = 0x00000000U;
+ DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_exti.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_exti.c
new file mode 100644
index 0000000..c3d094a
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_exti.c
@@ -0,0 +1,232 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_exti.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief EXTI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_exti.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
+
+#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
+ || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
+ || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+
+
+#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup EXTI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup EXTI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the EXTI registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: EXTI registers are de-initialized
+ * - ERROR: not applicable
+ */
+uint32_t LL_EXTI_DeInit(void)
+{
+ /* Interrupt mask register set to default reset values */
+ LL_EXTI_WriteReg(IMR, 0x00000000U);
+ /* Event mask register set to default reset values */
+ LL_EXTI_WriteReg(EMR, 0x00000000U);
+ /* Rising Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(RTSR, 0x00000000U);
+ /* Falling Trigger selection register set to default reset values */
+ LL_EXTI_WriteReg(FTSR, 0x00000000U);
+ /* Software interrupt event register set to default reset values */
+ LL_EXTI_WriteReg(SWIER, 0x00000000U);
+ /* Pending register clear */
+ LL_EXTI_WriteReg(PR, 0x000FFFFFU);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
+ * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: EXTI registers are initialized
+ * - ERROR: not applicable
+ */
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ /* Check the parameters */
+ assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
+ assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
+
+ /* ENABLE LineCommand */
+ if (EXTI_InitStruct->LineCommand != DISABLE)
+ {
+ assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
+
+ /* Configure EXTI Lines in range from 0 to 31 */
+ if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
+ {
+ switch (EXTI_InitStruct->Mode)
+ {
+ case LL_EXTI_MODE_IT:
+ /* First Disable Event on provided Lines */
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable IT on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_EVENT:
+ /* First Disable IT on provided Lines */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Event on provided Lines */
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_MODE_IT_EVENT:
+ /* Directly Enable IT & Event on provided Lines */
+ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
+ {
+ switch (EXTI_InitStruct->Trigger)
+ {
+ case LL_EXTI_TRIGGER_RISING:
+ /* First Disable Falling Trigger on provided Lines */
+ LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Rising Trigger on provided Lines */
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_FALLING:
+ /* First Disable Rising Trigger on provided Lines */
+ LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ /* Then Enable Falling Trigger on provided Lines */
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ case LL_EXTI_TRIGGER_RISING_FALLING:
+ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
+ break;
+ default:
+ status = ERROR;
+ break;
+ }
+ }
+ }
+ }
+ /* DISABLE LineCommand */
+ else
+ {
+ /* De-configure EXTI Lines in range from 0 to 31 */
+ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
+ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
+ * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
+ * @retval None
+ */
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
+{
+ EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
+ EXTI_InitStruct->LineCommand = DISABLE;
+ EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
+ EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (EXTI) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_fsmc.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_fsmc.c
index fbb9368..0f23c77 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_fsmc.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_fsmc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_ll_fsmc.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief FSMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -35,17 +35,17 @@
(++) Static random access memory (SRAM).
(++) NOR Flash memory.
(++) PSRAM (4 memory banks).
- (++) 16-bit PC Card compatible devices
+ (++) 16-bit PC Card compatible devices.
(++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
- data
- (+) Independent Chip Select control for each memory bank
- (+) Independent configuration for each memory bank
-
+ data.
+ (+) Independent Chip Select control for each memory bank.
+ (+) Independent configuration for each memory bank.
+
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -79,10 +79,10 @@
* @{
*/
-#if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
-
#if defined(FSMC_BANK1)
+#if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
+
/** @defgroup FSMC_LL FSMC Low Layer
* @brief FSMC driver modules
* @{
@@ -90,78 +90,7 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
- * @{
- */
-
-/* ----------------------- FSMC registers bit mask --------------------------- */
-/* --- PCR Register ---*/
-/* PCR register clear mask */
-#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN | \
- FSMC_PCRx_PTYP | FSMC_PCRx_PWID | \
- FSMC_PCRx_ECCEN | FSMC_PCRx_TCLR | \
- FSMC_PCRx_TAR | FSMC_PCRx_ECCPS))
-
-/* --- SR Register ---*/
-/* SR register clear mask */
-#define SR_CLEAR_MASK ((uint32_t)(FSMC_SRx_IRS | FSMC_SRx_ILS | FSMC_SRx_IFS | \
- FSMC_SRx_IREN | FSMC_SRx_ILEN | FSMC_SRx_IFEN))
-
-/* --- PMEM Register ---*/
-/* PMEM register clear mask */
-#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEMx_MEMSETx | FSMC_PMEMx_MEMWAITx |\
- FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx))
-
-/* --- PATT Register ---*/
-/* PATT register clear mask */
-#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATTx_ATTSETx | FSMC_PATTx_ATTWAITx |\
- FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx))
-
-/* --- BCR Register ---*/
-/* BCR register clear mask */
-#define BCR_CLEAR_MASK ((uint32_t)(FSMC_BCRx_FACCEN | FSMC_BCRx_MUXEN | \
- FSMC_BCRx_MTYP | FSMC_BCRx_MWID | \
- FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL | \
- FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \
- FSMC_BCRx_WREN | FSMC_BCRx_WAITEN | \
- FSMC_BCRx_EXTMOD | FSMC_BCRx_ASYNCWAIT | \
- FSMC_BCRx_CBURSTRW))
-/* --- BTR Register ---*/
-/* BTR register clear mask */
-#define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD |\
- FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
- FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT |\
- FSMC_BTRx_ACCMOD))
-
-/* --- BWTR Register ---*/
-/* BWTR register clear mask */
-#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
-#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \
- FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \
- FSMC_BWTRx_BUSTURN))
-#else
-#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \
- FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \
- FSMC_BWTRx_CLKDIV | FSMC_BWTRx_DATLAT))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-
-/* --- PIO4 Register ---*/
-/* PIO4 register clear mask */
-#define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | \
- FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
-/**
- * @}
- */
-
/* Private macro -------------------------------------------------------------*/
-/** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
@@ -190,13 +119,12 @@
(+) FSMC NORSRAM bank enable/disable write operation using the functions
FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
-
@endverbatim
* @{
*/
-
-/** @defgroup FSMC_NORSRAM_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
+
+/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
+ * @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
@@ -281,12 +209,11 @@
return HAL_OK;
}
-
/**
- * @brief DeInitialize the FSMC_NORSRAM peripheral
+ * @brief DeInitialize the FSMC_NORSRAM peripheral
* @param Device: Pointer to NORSRAM device instance
* @param ExDevice: Pointer to NORSRAM extended mode device instance
- * @param Bank: NORSRAM bank number
+ * @param Bank: NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
@@ -301,19 +228,19 @@
/* De-initialize the FSMC_NORSRAM device */
/* FSMC_NORSRAM_BANK1 */
- if (Bank == FSMC_NORSRAM_BANK1)
+ if(Bank == FSMC_NORSRAM_BANK1)
{
- Device->BTCR[Bank] = 0x000030DB;
+ Device->BTCR[Bank] = 0x000030DBU;
}
/* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
else
- {
- Device->BTCR[Bank] = 0x000030D2;
+ {
+ Device->BTCR[Bank] = 0x000030D2U;
}
-
- Device->BTCR[Bank + 1] = 0x0FFFFFFF;
- ExDevice->BWTR[Bank] = 0x0FFFFFFF;
-
+
+ Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
+ ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
+
return HAL_OK;
}
@@ -340,14 +267,14 @@
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
/* Set FSMC_NORSRAM device timing parameters */
- MODIFY_REG(Device->BTCR[Bank + 1], \
- BTR_CLEAR_MASK, \
- (uint32_t)(Timing->AddressSetupTime | \
- ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BTRx_ADDHLD)) | \
- ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BTRx_DATAST)) | \
- ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BTRx_BUSTURN)) | \
- (((Timing->CLKDivision) - 1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) | \
- (((Timing->DataLatency) - 2) << POSITION_VAL(FSMC_BTRx_DATLAT)) | \
+ MODIFY_REG(Device->BTCR[Bank + 1U], \
+ BTR_CLEAR_MASK, \
+ (uint32_t)(Timing->AddressSetupTime | \
+ ((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) | \
+ ((Timing->DataSetupTime) << FSMC_BTRx_DATAST_Pos) | \
+ ((Timing->BusTurnAroundDuration) << FSMC_BTRx_BUSTURN_Pos) | \
+ (((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) | \
+ (((Timing->DataLatency) - 2U) << FSMC_BTRx_DATLAT_Pos) | \
(Timing->AccessMode)));
return HAL_OK;
@@ -359,7 +286,7 @@
* @param Device: Pointer to NORSRAM device instance
* @param Timing: Pointer to NORSRAM Timing structure
* @param Bank: NORSRAM bank number
- * @param ExtendedMode: FSMC Extended Mode
+ * @param ExtendedMode FSMC Extended Mode
* This parameter can be one of the following values:
* @arg FSMC_EXTENDED_MODE_DISABLE
* @arg FSMC_EXTENDED_MODE_ENABLE
@@ -371,14 +298,14 @@
assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
- if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
+ if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
{
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
-#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
#else
assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
@@ -388,42 +315,39 @@
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
-#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
- MODIFY_REG(Device->BWTR[Bank], \
- BWTR_CLEAR_MASK, \
- (uint32_t)(Timing->AddressSetupTime | \
- ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) | \
- ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) | \
- Timing->AccessMode | \
- ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BWTRx_BUSTURN))));
+#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
+ MODIFY_REG(Device->BWTR[Bank], \
+ BWTR_CLEAR_MASK, \
+ (uint32_t)(Timing->AddressSetupTime | \
+ ((Timing->AddressHoldTime) << FSMC_BWTRx_ADDHLD_Pos) | \
+ ((Timing->DataSetupTime) << FSMC_BWTRx_DATAST_Pos) | \
+ Timing->AccessMode | \
+ ((Timing->BusTurnAroundDuration) << FSMC_BWTRx_BUSTURN_Pos)));
#else
- MODIFY_REG(Device->BWTR[Bank], \
- BWTR_CLEAR_MASK, \
- (uint32_t)(Timing->AddressSetupTime | \
- ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) | \
- ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) | \
- Timing->AccessMode | \
- (((Timing->CLKDivision) - 1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) | \
- (((Timing->DataLatency) - 2) << POSITION_VAL(FSMC_BWTRx_DATLAT))));
+ MODIFY_REG(Device->BWTR[Bank], \
+ BWTR_CLEAR_MASK, \
+ (uint32_t)(Timing->AddressSetupTime | \
+ ((Timing->AddressHoldTime) << FSMC_BWTRx_ADDHLD_Pos) | \
+ ((Timing->DataSetupTime) << FSMC_BWTRx_DATAST_Pos) | \
+ Timing->AccessMode | \
+ (((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) | \
+ (((Timing->DataLatency) - 2U) << FSMC_BWTRx_DATLAT_Pos)));
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
}
else
{
- Device->BWTR[Bank] = 0x0FFFFFFF;
+ Device->BWTR[Bank] = 0x0FFFFFFFU;
}
return HAL_OK;
}
-
-
/**
* @}
*/
-
/** @defgroup FSMC_NORSRAM_Group2 Control functions
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### FSMC_NORSRAM Control functions #####
@@ -471,7 +395,6 @@
return HAL_OK;
}
-
/**
* @}
*/
@@ -479,6 +402,7 @@
/**
* @}
*/
+
#if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
/** @defgroup FSMC_NAND FSMC NAND Controller functions
* @brief NAND Controller functions
@@ -506,8 +430,8 @@
*/
/** @defgroup FSMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
@@ -545,28 +469,27 @@
if (Init->NandBank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
- MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature | \
- FSMC_PCR_MEMORY_TYPE_NAND | \
- Init->MemoryDataWidth | \
- Init->EccComputation | \
- Init->ECCPageSize | \
- ((Init->TCLRSetupTime) << POSITION_VAL(FSMC_PCRx_TCLR)) | \
- ((Init->TARSetupTime) << POSITION_VAL(FSMC_PCRx_TAR))));
+ MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
+ FSMC_PCR_MEMORY_TYPE_NAND |
+ Init->MemoryDataWidth |
+ Init->EccComputation |
+ Init->ECCPageSize |
+ ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) |
+ ((Init->TARSetupTime) << FSMC_PCRx_TAR_Pos)));
}
else
{
/* NAND bank 3 registers configuration */
- MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature | \
- FSMC_PCR_MEMORY_TYPE_NAND | \
- Init->MemoryDataWidth | \
- Init->EccComputation | \
- Init->ECCPageSize | \
- ((Init->TCLRSetupTime) << POSITION_VAL(FSMC_PCRx_TCLR)) | \
- ((Init->TARSetupTime) << POSITION_VAL(FSMC_PCRx_TAR))));
+ MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
+ FSMC_PCR_MEMORY_TYPE_NAND |
+ Init->MemoryDataWidth |
+ Init->EccComputation |
+ Init->ECCPageSize |
+ ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) |
+ ((Init->TARSetupTime) << FSMC_PCRx_TAR_Pos)));
}
return HAL_OK;
-
}
/**
@@ -588,21 +511,21 @@
assert_param(IS_FSMC_NAND_BANK(Bank));
/* Set FMC_NAND device timing parameters */
- if (Bank == FSMC_NAND_BANK2)
+ if(Bank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
- MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx)) | \
- ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx)) | \
- ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx))));
+ MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) | \
+ ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) | \
+ ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
}
else
{
/* NAND bank 3 registers configuration */
- MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx)) | \
- ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx)) | \
- ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx))));
+ MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) | \
+ ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) | \
+ ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
}
return HAL_OK;
@@ -627,21 +550,21 @@
assert_param(IS_FSMC_NAND_BANK(Bank));
/* Set FMC_NAND device timing parameters */
- if (Bank == FSMC_NAND_BANK2)
+ if(Bank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
- MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx)) | \
- ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx)) | \
- ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx))));
+ MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | \
+ ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | \
+ ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos)));
}
else
{
/* NAND bank 3 registers configuration */
- MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx)) | \
- ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx)) | \
- ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx))));
+ MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | \
+ ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | \
+ ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos)));
}
return HAL_OK;
@@ -649,7 +572,7 @@
/**
- * @brief DeInitializes the FSMC_NAND device
+ * @brief DeInitializes the FSMC_NAND device
* @param Device: Pointer to NAND device instance
* @param Bank: NAND bank number
* @retval HAL status
@@ -664,22 +587,22 @@
__FSMC_NAND_DISABLE(Device, Bank);
/* De-initialize the NAND Bank */
- if (Bank == FSMC_NAND_BANK2)
+ if(Bank == FSMC_NAND_BANK2)
{
/* Set the FSMC_NAND_BANK2 registers to their reset values */
- WRITE_REG(Device->PCR2, 0x00000018);
- WRITE_REG(Device->SR2, 0x00000040);
- WRITE_REG(Device->PMEM2, 0xFCFCFCFC);
- WRITE_REG(Device->PATT2, 0xFCFCFCFC);
+ WRITE_REG(Device->PCR2, 0x00000018U);
+ WRITE_REG(Device->SR2, 0x00000040U);
+ WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
+ WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
}
/* FSMC_Bank3_NAND */
else
{
/* Set the FSMC_NAND_BANK3 registers to their reset values */
- WRITE_REG(Device->PCR3, 0x00000018);
- WRITE_REG(Device->SR3, 0x00000040);
- WRITE_REG(Device->PMEM3, 0xFCFCFCFC);
- WRITE_REG(Device->PATT3, 0xFCFCFCFC);
+ WRITE_REG(Device->PCR3, 0x00000018U);
+ WRITE_REG(Device->SR3, 0x00000040U);
+ WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
+ WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
}
return HAL_OK;
@@ -691,8 +614,8 @@
/** @defgroup FSMC_NAND_Exported_Functions_Group2 Peripheral Control functions
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### FSMC_NAND Control functions #####
@@ -705,7 +628,6 @@
* @{
*/
-
/**
* @brief Enables dynamically FSMC_NAND ECC feature.
* @param Device: Pointer to NAND device instance
@@ -719,7 +641,7 @@
assert_param(IS_FSMC_NAND_BANK(Bank));
/* Enable ECC feature */
- if (Bank == FSMC_NAND_BANK2)
+ if(Bank == FSMC_NAND_BANK2)
{
SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
}
@@ -731,7 +653,6 @@
return HAL_OK;
}
-
/**
* @brief Disables dynamically FSMC_NAND ECC feature.
* @param Device: Pointer to NAND device instance
@@ -745,7 +666,7 @@
assert_param(IS_FSMC_NAND_BANK(Bank));
/* Disable ECC feature */
- if (Bank == FSMC_NAND_BANK2)
+ if(Bank == FSMC_NAND_BANK2)
{
CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
}
@@ -762,13 +683,13 @@
* @param Device: Pointer to NAND device instance
* @param ECCval: Pointer to ECC value
* @param Bank: NAND bank number
- * @param Timeout: Timeout wait value
+ * @param Timeout: Timeout wait value
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
{
- uint32_t tickstart = 0;
-
+ uint32_t tickstart = 0U;
+
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
assert_param(IS_FSMC_NAND_BANK(Bank));
@@ -776,20 +697,20 @@
/* Get tick */
tickstart = HAL_GetTick();
- /* Wait untill FIFO is empty */
- while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
+ /* Wait until FIFO is empty */
+ while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
{
/* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
+ if(Timeout != HAL_MAX_DELAY)
{
- if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
return HAL_TIMEOUT;
}
}
}
- if (Bank == FSMC_NAND_BANK2)
+ if(Bank == FSMC_NAND_BANK2)
{
/* Get the ECCR2 register value */
*ECCval = (uint32_t)Device->ECCR2;
@@ -811,8 +732,6 @@
* @}
*/
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-#if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
/** @defgroup FSMC_PCCARD FSMC PCCARD Controller functions
* @brief PCCARD Controller functions
*
@@ -833,14 +752,13 @@
(+) FSMC PCCARD bank IO space timing configuration using the function
FSMC_PCCARD_IOSpace_Timing_Init()
-
@endverbatim
* @{
*/
/** @defgroup FSMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
@@ -871,14 +789,14 @@
assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
/* Set FSMC_PCCARD device control parameters */
- MODIFY_REG(Device->PCR4, \
+ MODIFY_REG(Device->PCR4,
(FSMC_PCRx_PTYP | FSMC_PCRx_PWAITEN | FSMC_PCRx_PWID |
- FSMC_PCRx_TCLR | FSMC_PCRx_TAR), \
- (FSMC_PCR_MEMORY_TYPE_PCCARD | \
- Init->Waitfeature | \
- FSMC_NAND_PCC_MEM_BUS_WIDTH_16 | \
- (Init->TCLRSetupTime << POSITION_VAL(FSMC_PCRx_TCLR)) | \
- (Init->TARSetupTime << POSITION_VAL(FSMC_PCRx_TAR))));
+ FSMC_PCRx_TCLR | FSMC_PCRx_TAR),
+ (FSMC_PCR_MEMORY_TYPE_PCCARD |
+ Init->Waitfeature |
+ FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |
+ (Init->TCLRSetupTime << FSMC_PCRx_TCLR_Pos) |
+ (Init->TARSetupTime << FSMC_PCRx_TAR_Pos)));
return HAL_OK;
@@ -901,11 +819,11 @@
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
/* Set PCCARD timing parameters */
- MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK, \
- (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx)) | \
- ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx)) | \
- ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx))));
+ MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
+ (Timing->SetupTime |
+ ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
+ ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
+ ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
return HAL_OK;
}
@@ -928,10 +846,10 @@
/* Set PCCARD timing parameters */
MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK, \
- (Timing->SetupTime | \
- ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx)) | \
- ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx)) | \
- ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx))));
+ (Timing->SetupTime | \
+ ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | \
+ ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | \
+ ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos)));
return HAL_OK;
}
@@ -953,11 +871,11 @@
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
/* Set FSMC_PCCARD device timing parameters */
- MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, \
- (Timing->SetupTime | \
- (Timing->WaitSetupTime << POSITION_VAL(FSMC_PIO4_IOWAIT4)) | \
- (Timing->HoldSetupTime << POSITION_VAL(FSMC_PIO4_IOHOLD4)) | \
- (Timing->HiZSetupTime << POSITION_VAL(FSMC_PIO4_IOHIZ4))));
+ MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, \
+ (Timing->SetupTime | \
+ (Timing->WaitSetupTime << FSMC_PIO4_IOWAIT4_Pos) | \
+ (Timing->HoldSetupTime << FSMC_PIO4_IOHOLD4_Pos) | \
+ (Timing->HiZSetupTime << FSMC_PIO4_IOHIZ4_Pos)));
return HAL_OK;
}
@@ -976,11 +894,11 @@
__FSMC_PCCARD_DISABLE(Device);
/* De-initialize the FSMC_PCCARD device */
- WRITE_REG(Device->PCR4, 0x00000018);
- WRITE_REG(Device->SR4, 0x00000040);
- WRITE_REG(Device->PMEM4, 0xFCFCFCFC);
- WRITE_REG(Device->PATT4, 0xFCFCFCFC);
- WRITE_REG(Device->PIO4, 0xFCFCFCFC);
+ WRITE_REG(Device->PCR4, 0x00000018U);
+ WRITE_REG(Device->SR4, 0x00000040U);
+ WRITE_REG(Device->PMEM4, 0xFCFCFCFCU);
+ WRITE_REG(Device->PATT4, 0xFCFCFCFCU);
+ WRITE_REG(Device->PIO4, 0xFCFCFCFCU);
return HAL_OK;
}
@@ -1002,9 +920,9 @@
* @}
*/
-#endif /* FSMC_BANK1 */
+#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
-#endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) */
+#endif /* FSMC_BANK1 */
/**
* @}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_gpio.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_gpio.c
new file mode 100644
index 0000000..43360fa
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_gpio.c
@@ -0,0 +1,265 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_gpio.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief GPIO LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_gpio.h"
+#include "stm32f1xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
+
+/** @addtogroup GPIO_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_GPIO_PIN(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+
+#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_ANALOG) ||\
+ ((__VALUE__) == LL_GPIO_MODE_FLOATING) ||\
+ ((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
+ ((__VALUE__) == LL_GPIO_MODE_ALTERNATE))
+
+#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
+ ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))
+
+#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
+ ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
+
+#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_DOWN) ||\
+ ((__VALUE__) == LL_GPIO_PULL_UP))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup GPIO_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize GPIO registers (Registers restored to their default values).
+ * @param GPIOx GPIO Port
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are de-initialized
+ * - ERROR: Wrong GPIO Port
+ */
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+
+ /* Force and Release reset on clock of GPIOx Port */
+ if (GPIOx == GPIOA)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOA);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOA);
+ }
+ else if (GPIOx == GPIOB)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOB);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOB);
+ }
+ else if (GPIOx == GPIOC)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOC);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOC);
+ }
+ else if (GPIOx == GPIOD)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOD);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOD);
+ }
+#if defined(GPIOE)
+ else if (GPIOx == GPIOE)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOE);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOE);
+ }
+#endif
+#if defined(GPIOF)
+ else if (GPIOx == GPIOF)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOF);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOF);
+ }
+#endif
+#if defined(GPIOG)
+ else if (GPIOx == GPIOG)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOG);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOG);
+ }
+#endif
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
+ * @param GPIOx GPIO Port
+ * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+ * that contains the configuration information for the specified GPIO peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ uint32_t pinpos = 0x00000000U;
+ uint32_t currentpin = 0x00000000U;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+ assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
+ assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
+ assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
+
+ /* ------------------------- Configure the port pins ---------------- */
+ /* Initialize pinpos on first pin set */
+ pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
+
+ /* Configure the port pins */
+ while ((((GPIO_InitStruct->Pin) & 0x0000FFFFU) >> pinpos) != 0x00000000U)
+ {
+ /* Get current io position */
+ if(pinpos <8 )
+ {
+ currentpin = (GPIO_InitStruct->Pin) & (0x00000101U << pinpos);
+ }
+ else
+ {
+ currentpin = (GPIO_InitStruct->Pin) & ((0x00010001U << (pinpos-8)) | 0x04000000U);
+ }
+
+ if (currentpin)
+ {
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+
+ /* Pull-up Pull down resistor configuration*/
+ LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
+
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_FLOATING))
+ {
+ /* Speed mode configuration */
+ LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
+ }
+ }
+ pinpos++;
+ }
+
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_FLOATING))
+ {
+ /* Check Output mode parameters */
+ assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
+
+ /* Output mode configuration*/
+ LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
+ }
+ return (SUCCESS);
+}
+
+/**
+ * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
+ * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
+ GPIO_InitStruct->Mode = LL_GPIO_MODE_FLOATING;
+ GPIO_InitStruct->Speed = 0x00000000U;
+ GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
+ GPIO_InitStruct->Pull = LL_GPIO_PULL_DOWN;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_i2c.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_i2c.c
new file mode 100644
index 0000000..0a882f7
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_i2c.c
@@ -0,0 +1,239 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_i2c.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief I2C LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_i2c.h"
+#include "stm32f1xx_ll_bus.h"
+#include "stm32f1xx_ll_rcc.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (I2C1) || defined (I2C2)
+
+/** @defgroup I2C_LL I2C
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
+ ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
+
+#define IS_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
+
+#define IS_I2C_DUTY_CYCLE(__VALUE__) (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \
+ ((__VALUE__) == LL_I2C_DUTYCYCLE_16_9))
+
+#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
+
+#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
+ ((__VALUE__) == LL_I2C_NACK))
+
+#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
+ ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2C_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the I2C registers to their default reset values.
+ * @param I2Cx I2C Instance.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2C registers are de-initialized
+ * - ERROR: I2C registers are not de-initialized
+ */
+uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the I2C Instance I2Cx */
+ assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+ if (I2Cx == I2C1)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
+ }
+#if defined(I2C2)
+ else if (I2Cx == I2C2)
+ {
+ /* Force reset of I2C clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+ /* Release reset of I2C clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
+
+ }
+#endif /* I2C2 */
+ else
+ {
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
+ * @param I2Cx I2C Instance.
+ * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2C registers are initialized
+ * - ERROR: Not applicable
+ */
+uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+ LL_RCC_ClocksTypeDef rcc_clocks;
+
+ /* Check the I2C Instance I2Cx */
+ assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
+
+ /* Check the I2C parameters from I2C_InitStruct */
+ assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
+ assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->ClockSpeed));
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->DutyCycle));
+ assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
+ assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
+ assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
+
+ /* Disable the selected I2Cx Peripheral */
+ LL_I2C_Disable(I2Cx);
+
+ /* Retrieve Clock frequencies */
+ LL_RCC_GetSystemClocksFreq(&rcc_clocks);
+
+ /*---------------------------- I2Cx SCL Clock Speed Configuration ------------
+ * Configure the SCL speed :
+ * - ClockSpeed: I2C_CR2_FREQ[5:0], I2C_TRISE_TRISE[5:0], I2C_CCR_FS,
+ * and I2C_CCR_CCR[11:0] bits
+ * - DutyCycle: I2C_CCR_DUTY[7:0] bits
+ */
+ LL_I2C_ConfigSpeed(I2Cx, rcc_clocks.PCLK1_Frequency, I2C_InitStruct->ClockSpeed, I2C_InitStruct->DutyCycle);
+
+ /*---------------------------- I2Cx OAR1 Configuration -----------------------
+ * Disable, Configure and Enable I2Cx device own address 1 with parameters :
+ * - OwnAddress1: I2C_OAR1_ADD[9:8], I2C_OAR1_ADD[7:1] and I2C_OAR1_ADD0 bits
+ * - OwnAddrSize: I2C_OAR1_ADDMODE bit
+ */
+ LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
+
+ /*---------------------------- I2Cx MODE Configuration -----------------------
+ * Configure I2Cx peripheral mode with parameter :
+ * - PeripheralMode: I2C_CR1_SMBUS, I2C_CR1_SMBTYPE and I2C_CR1_ENARP bits
+ */
+ LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
+
+ /* Enable the selected I2Cx Peripheral */
+ LL_I2C_Enable(I2Cx);
+
+ /*---------------------------- I2Cx CR2 Configuration ------------------------
+ * Configure the ACKnowledge or Non ACKnowledge condition
+ * after the address receive match code or next received byte with parameter :
+ * - TypeAcknowledge: I2C_CR2_NACK bit
+ */
+ LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set each @ref LL_I2C_InitTypeDef field to default value.
+ * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
+ * @retval None
+ */
+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+ /* Set I2C_InitStruct fields to default values */
+ I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C;
+ I2C_InitStruct->ClockSpeed = 5000U;
+ I2C_InitStruct->DutyCycle = LL_I2C_DUTYCYCLE_2;
+ I2C_InitStruct->OwnAddress1 = 0U;
+ I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
+ I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* I2C1 || I2C2 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_pwr.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_pwr.c
new file mode 100644
index 0000000..947d47a
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_pwr.c
@@ -0,0 +1,103 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_pwr.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief PWR LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_pwr.h"
+#include "stm32f1xx_ll_bus.h"
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup PWR_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the PWR registers to their default reset values.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: PWR registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_PWR_DeInit(void)
+{
+ /* Force reset of PWR clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
+
+ /* Release reset of PWR clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
+
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* defined(PWR) */
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_rcc.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_rcc.c
new file mode 100644
index 0000000..d931ff9
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_rcc.c
@@ -0,0 +1,507 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_rcc.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief RCC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_rcc.h"
+#ifdef USE_FULL_ASSERT
+ #include "stm32_assert.h"
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Macros
+ * @{
+ */
+#if defined(RCC_PLLI2S_SUPPORT)
+#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S2_CLKSOURCE) \
+ || ((__VALUE__) == LL_RCC_I2S3_CLKSOURCE))
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(USB) || defined(USB_OTG_FS)
+#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
+#endif /* USB */
+
+#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup RCC_LL_Private_Functions RCC Private functions
+ * @{
+ */
+uint32_t RCC_GetSystemClockFreq(void);
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
+uint32_t RCC_PLL_GetFreqDomain_SYS(void);
+#if defined(RCC_PLLI2S_SUPPORT)
+uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
+#endif /* RCC_PLLI2S_SUPPORT */
+#if defined(RCC_PLL2_SUPPORT)
+uint32_t RCC_PLL2_GetFreqClockFreq(void);
+#endif /* RCC_PLL2_SUPPORT */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RCC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Reset the RCC clock configuration to the default reset state.
+ * @note The default reset state of the clock configuration is given below:
+ * - HSI ON and used as system clock source
+ * - HSE PLL, PLL2, PLL3 OFF
+ * - AHB, APB1 and APB2 prescaler set to 1.
+ * - CSS, MCO OFF
+ * - All interrupts disabled
+ * @note This function doesn't modify the configuration of the
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RCC registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_RCC_DeInit(void)
+{
+ uint32_t vl_mask = 0U;
+
+ /* Set HSION bit */
+ LL_RCC_HSI_Enable();
+
+ /* Reset SW, HPRE, PPRE, MCOSEL, PLLXTPRE, PLLSRC and ADCPRE bits */
+ vl_mask = 0xFFFFFFFFU;
+ CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL |\
+ RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_ADCPRE));
+
+#if defined(USB)
+ /* Reset USBPRE bit */
+ CLEAR_BIT(vl_mask, RCC_CFGR_USBPRE);
+#elif defined(USB_OTG_FS)
+ /* Reset OTGFSPRE bit */
+ CLEAR_BIT(vl_mask, RCC_CFGR_OTGFSPRE);
+#endif /* USB */
+
+#if defined(RCC_CFGR_PLLMULL2)
+ /* Set PLL multiplication factor to 2 */
+ vl_mask |= RCC_CFGR_PLLMULL2;
+#else
+ /* Set PLL multiplication factor to 4 */
+ vl_mask |= RCC_CFGR_PLLMULL4;
+#endif /* RCC_CFGR_PLLMULL2 */
+
+ LL_RCC_WriteReg(CFGR, vl_mask);
+
+ /* Reset HSEON, HSEBYP, CSSON, PLLON bits */
+ vl_mask = 0xFFFFFFFFU;
+ CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP));
+
+#if defined(RCC_CR_PLL2ON)
+ /* Reset PLL2ON bit */
+ CLEAR_BIT(vl_mask, RCC_CR_PLL2ON);
+#endif /* RCC_CR_PLL2ON */
+
+#if defined(RCC_CR_PLL3ON)
+ /* Reset PLL3ON bit */
+ CLEAR_BIT(vl_mask, RCC_CR_PLL3ON);
+#endif /* RCC_CR_PLL3ON */
+
+ LL_RCC_WriteReg(CR, vl_mask);
+
+ /* Set HSITRIM bits to the reset value */
+ LL_RCC_HSI_SetCalibTrimming(0x10U);
+
+#if defined(RCC_CFGR2_PREDIV1)
+ /* Reset CFGR2 register */
+ vl_mask = 0x00000000U;
+
+#if defined(RCC_PLL2_SUPPORT)
+ /* Set PLL2 multiplication factor to 8 */
+ vl_mask |= RCC_CFGR2_PLL2MUL8;
+#endif /* RCC_PLL2_SUPPORT */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+ /* Set PLL3 multiplication factor to 8 */
+ vl_mask |= RCC_CFGR2_PLL3MUL8;
+#endif /* RCC_PLLI2S_SUPPORT */
+
+ LL_RCC_WriteReg(CFGR2, vl_mask);
+#endif /* RCC_CFGR2_PREDIV1 */
+
+ /* Disable all interrupts */
+ LL_RCC_WriteReg(CIR, 0x00000000U);
+
+ return SUCCESS;
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_EF_Get_Freq
+ * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
+ * and different peripheral clocks available on the device.
+ * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
+ * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
+ * @note If SYSCLK source is PLL, function returns values based on
+ * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+ * @note (**) HSI_VALUE is a defined constant but the real value may vary
+ * depending on the variations in voltage and temperature.
+ * @note (***) HSE_VALUE is a defined constant, user has to ensure that
+ * HSE_VALUE is same as the real frequency of the crystal used.
+ * Otherwise, this function may have wrong result.
+ * @note The result of this function could be incorrect when using fractional
+ * value for HSE crystal.
+ * @note This function can be used by the user application to compute the
+ * baud-rate for the communication peripherals or configure other parameters.
+ * @{
+ */
+
+/**
+ * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
+ * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
+ * must be called to update structure fields. Otherwise, any
+ * configuration based on this function will be incorrect.
+ * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
+ * @retval None
+ */
+void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
+{
+ /* Get SYSCLK frequency */
+ RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
+
+ /* HCLK clock frequency */
+ RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
+
+ /* PCLK1 clock frequency */
+ RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
+
+ /* PCLK2 clock frequency */
+ RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
+}
+
+#if defined(RCC_CFGR2_I2S2SRC)
+/**
+ * @brief Return I2Sx clock frequency
+ * @param I2SxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_I2S2_CLKSOURCE
+ * @arg @ref LL_RCC_I2S3_CLKSOURCE
+ * @retval I2S clock frequency (in Hz)
+ */
+uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
+{
+ uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
+
+ /* I2S1CLK clock frequency */
+ switch (LL_RCC_GetI2SClockSource(I2SxSource))
+ {
+ case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
+ case LL_RCC_I2S3_CLKSOURCE_SYSCLK:
+ i2s_frequency = RCC_GetSystemClockFreq();
+ break;
+
+ case LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO: /*!< PLLI2S oscillator clock selected as I2S clock source */
+ case LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO:
+ default:
+ i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2U;
+ break;
+ }
+
+ return i2s_frequency;
+}
+#endif /* RCC_CFGR2_I2S2SRC */
+
+#if defined(USB) || defined(USB_OTG_FS)
+/**
+ * @brief Return USBx clock frequency
+ * @param USBxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_USB_CLKSOURCE
+ * @retval USB clock frequency (in Hz)
+ * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready
+ */
+uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
+{
+ uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
+
+ /* USBCLK clock frequency */
+ switch (LL_RCC_GetUSBClockSource(USBxSource))
+ {
+#if defined(RCC_CFGR_USBPRE)
+ case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
+ if (LL_RCC_PLL_IsReady())
+ {
+ usb_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ break;
+
+ case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock divided by 1.5 used as USB clock source */
+ default:
+ if (LL_RCC_PLL_IsReady())
+ {
+ usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
+ }
+ break;
+#endif /* RCC_CFGR_USBPRE */
+#if defined(RCC_CFGR_OTGFSPRE)
+ /* USBCLK = PLLVCO/2
+ = (2 x PLLCLK) / 2
+ = PLLCLK */
+ case LL_RCC_USB_CLKSOURCE_PLL_DIV_2: /* PLL clock used as USB clock source */
+ if (LL_RCC_PLL_IsReady())
+ {
+ usb_frequency = RCC_PLL_GetFreqDomain_SYS();
+ }
+ break;
+
+ /* USBCLK = PLLVCO/3
+ = (2 x PLLCLK) / 3 */
+ case LL_RCC_USB_CLKSOURCE_PLL_DIV_3: /* PLL clock divided by 3 used as USB clock source */
+ default:
+ if (LL_RCC_PLL_IsReady())
+ {
+ usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2U) / 3U;
+ }
+ break;
+#endif /* RCC_CFGR_OTGFSPRE */
+ }
+
+ return usb_frequency;
+}
+#endif /* USB */
+
+/**
+ * @brief Return ADCx clock frequency
+ * @param ADCxSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_ADC_CLKSOURCE
+ * @retval ADC clock frequency (in Hz)
+ */
+uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
+{
+ uint32_t adc_prescaler = 0U;
+ uint32_t adc_frequency = 0U;
+
+ /* Check parameter */
+ assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
+
+ /* Get ADC prescaler */
+ adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
+
+ /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
+ adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
+ / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
+
+ return adc_frequency;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup RCC_LL_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Return SYSTEM clock frequency
+ * @retval SYSTEM clock frequency (in Hz)
+ */
+uint32_t RCC_GetSystemClockFreq(void)
+{
+ uint32_t frequency = 0U;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (LL_RCC_GetSysClkSource())
+ {
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
+ frequency = HSI_VALUE;
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
+ frequency = HSE_VALUE;
+ break;
+
+ case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
+ frequency = RCC_PLL_GetFreqDomain_SYS();
+ break;
+
+ default:
+ frequency = HSI_VALUE;
+ break;
+ }
+
+ return frequency;
+}
+
+/**
+ * @brief Return HCLK clock frequency
+ * @param SYSCLK_Frequency SYSCLK clock frequency
+ * @retval HCLK clock frequency (in Hz)
+ */
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+ /* HCLK clock frequency */
+ return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+}
+
+/**
+ * @brief Return PCLK1 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK1 clock frequency */
+ return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+}
+
+/**
+ * @brief Return PCLK2 clock frequency
+ * @param HCLK_Frequency HCLK clock frequency
+ * @retval PCLK2 clock frequency (in Hz)
+ */
+uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK2 clock frequency */
+ return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
+}
+
+/**
+ * @brief Return PLL clock frequency used for system domain
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLL_GetFreqDomain_SYS(void)
+{
+ uint32_t pllinputfreq = 0U, pllsource = 0U;
+
+ /* PLL_VCO = (HSE_VALUE, HSI_VALUE or PLL2 / PLL Predivider) * PLL Multiplicator */
+
+ /* Get PLL source */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ {
+ case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
+ pllinputfreq = HSI_VALUE / 2U;
+ break;
+
+ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1U);
+ break;
+
+#if defined(RCC_PLL2_SUPPORT)
+ case LL_RCC_PLLSOURCE_PLL2: /* PLL2 used as PLL clock source */
+ pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1U);
+ break;
+#endif /* RCC_PLL2_SUPPORT */
+
+ default:
+ pllinputfreq = HSI_VALUE / 2U;
+ break;
+ }
+ return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator());
+}
+
+#if defined(RCC_PLL2_SUPPORT)
+/**
+ * @brief Return PLL clock frequency used for system domain
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLL2_GetFreqClockFreq(void)
+{
+ return __LL_RCC_CALC_PLL2CLK_FREQ(HSE_VALUE, LL_RCC_PLL2_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
+}
+#endif /* RCC_PLL2_SUPPORT */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Return PLL clock frequency used for system domain
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
+{
+ return __LL_RCC_CALC_PLLI2SCLK_FREQ(HSE_VALUE, LL_RCC_PLLI2S_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RCC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_rtc.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_rtc.c
new file mode 100644
index 0000000..48510d2
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_rtc.c
@@ -0,0 +1,558 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_rtc.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief RTC LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_rtc.h"
+#include "stm32f1xx_ll_cortex.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined(RTC)
+
+/** @addtogroup RTC_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Constants
+ * @{
+ */
+/* Default values used for prescaler */
+#define RTC_ASYNCH_PRESC_DEFAULT 0x00007FFFU
+
+/* Values used for timeout */
+#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
+#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RTC_LL_Private_Macros
+ * @{
+ */
+
+#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0xFFFFFU)
+
+#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
+ || ((__VALUE__) == LL_RTC_FORMAT_BCD))
+
+#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
+#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
+#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
+#define IS_LL_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_NONE) || \
+ ((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_RTCCLOCK) || \
+ ((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_ALARM) || \
+ ((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_SECOND))
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup RTC_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-Initializes the RTC registers to their default reset values.
+ * @note This function doesn't reset the RTC Clock source and RTC Backup Data
+ * registers.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are de-initialized
+ * - ERROR: RTC registers are not de-initialized
+ */
+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ LL_RTC_WriteReg(RTCx,CNTL, 0x0000);
+ LL_RTC_WriteReg(RTCx,CNTH, 0x0000);
+ LL_RTC_WriteReg(RTCx,PRLH, 0x0000);
+ LL_RTC_WriteReg(RTCx,PRLL, 0x8000);
+ LL_RTC_WriteReg(RTCx,CRH, 0x0000);
+ LL_RTC_WriteReg(RTCx,CRL, 0x0020);
+
+ /* Reset Tamper and alternate functions configuration register */
+ LL_RTC_WriteReg(BKP,RTCCR, 0x00000000U);
+ LL_RTC_WriteReg(BKP,CR, 0x00000000U);
+ LL_RTC_WriteReg(BKP,CSR, 0x00000000U);
+
+ /* Exit Initialization Mode */
+ if(LL_RTC_ExitInitMode(RTCx) == ERROR)
+ {
+ return ERROR;
+ }
+
+ /* Wait till the RTC RSF flag is set */
+ status = LL_RTC_WaitForSynchro(RTCx);
+
+ /* Clear RSF Flag */
+ LL_RTC_ClearFlag_RS(RTCx);
+ }
+
+ /* Enable the write protection for RTC registers */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Initializes the RTC registers according to the specified parameters
+ * in RTC_InitStruct.
+ * @param RTCx RTC Instance
+ * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
+ * the configuration information for the RTC peripheral.
+ * @note The RTC Prescaler register is write protected and can be written in
+ * initialization mode only.
+ * @note the user should call LL_RTC_StructInit() or the structure of Prescaler
+ * need to be initialized before RTC init()
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are initialized
+ * - ERROR: RTC registers are not initialized
+ */
+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
+ assert_param(IS_LL_RTC_CALIB_OUTPUT(RTC_InitStruct->OutPutSource));
+ /* Waiting for synchro */
+ if(LL_RTC_WaitForSynchro(RTCx) != ERROR)
+ {
+ /* Set Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Clear Flag Bits */
+ LL_RTC_ClearFlag_ALR(RTCx);
+ LL_RTC_ClearFlag_OW(RTCx);
+ LL_RTC_ClearFlag_SEC(RTCx);
+
+ if(RTC_InitStruct->OutPutSource != LL_RTC_CALIB_OUTPUT_NONE)
+ {
+ /* Disable the selected Tamper Pin */
+ LL_RTC_TAMPER_Disable(BKP);
+ }
+ /* Set the signal which will be routed to RTC Tamper Pin */
+ LL_RTC_SetOutputSource(BKP, RTC_InitStruct->OutPutSource);
+
+ /* Configure Synchronous and Asynchronous prescaler factor */
+ LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
+
+ /* Exit Initialization Mode */
+ LL_RTC_ExitInitMode(RTCx);
+
+ status = SUCCESS;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_InitTypeDef field to default value.
+ * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
+{
+ /* Set RTC_InitStruct fields to default values */
+ RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
+ RTC_InitStruct->OutPutSource = LL_RTC_CALIB_OUTPUT_NONE;
+}
+
+/**
+ * @brief Set the RTC current time.
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
+ * the time configuration information for the RTC.
+ * @note The user should call LL_RTC_TIME_StructInit() or the structure
+ * of time need to be initialized before time init()
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Time register is configured
+ * - ERROR: RTC Time register is not configured
+ */
+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+ ErrorStatus status = ERROR;
+ uint32_t counter_time = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
+ assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
+ }
+
+ /* Enter Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Check the input parameters format */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ counter_time = (uint32_t)(((uint32_t)RTC_TimeStruct->Hours * 3600U) + \
+ ((uint32_t)RTC_TimeStruct->Minutes * 60U) + \
+ ((uint32_t)RTC_TimeStruct->Seconds));
+ LL_RTC_TIME_Set(RTCx, counter_time);
+ }
+ else
+ {
+ counter_time = (((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)) * 3600U) + \
+ ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)) * 60U) + \
+ ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds))));
+ LL_RTC_TIME_Set(RTCx, counter_time);
+ }
+ status = SUCCESS;
+ }
+ /* Exit Initialization mode */
+ LL_RTC_ExitInitMode(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
+ * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
+{
+ /* Time = 00h:00min:00sec */
+ RTC_TimeStruct->Hours = 0U;
+ RTC_TimeStruct->Minutes = 0U;
+ RTC_TimeStruct->Seconds = 0U;
+}
+
+/**
+ * @brief Set the RTC Alarm.
+ * @param RTCx RTC Instance
+ * @param RTC_Format This parameter can be one of the following values:
+ * @arg @ref LL_RTC_FORMAT_BIN
+ * @arg @ref LL_RTC_FORMAT_BCD
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
+ * contains the alarm configuration parameters.
+ * @note the user should call LL_RTC_ALARM_StructInit() or the structure
+ * of Alarm need to be initialized before Alarm init()
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: ALARM registers are configured
+ * - ERROR: ALARM registers are not configured
+ */
+ErrorStatus LL_RTC_ALARM_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ ErrorStatus status = ERROR;
+ uint32_t counter_alarm = 0U;
+ /* Check the parameters */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+ assert_param(IS_LL_RTC_FORMAT(RTC_Format));
+
+ if (RTC_Format == LL_RTC_FORMAT_BIN)
+ {
+ assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
+ assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
+ assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
+ }
+ else
+ {
+ assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
+ assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
+ assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
+ }
+
+ /* Enter Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ /* Check the input parameters format */
+ if (RTC_Format != LL_RTC_FORMAT_BIN)
+ {
+ counter_alarm = (uint32_t)(((uint32_t)RTC_AlarmStruct->AlarmTime.Hours * 3600U) + \
+ ((uint32_t)RTC_AlarmStruct->AlarmTime.Minutes * 60U) + \
+ ((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds));
+ LL_RTC_ALARM_Set(RTCx, counter_alarm);
+ }
+ else
+ {
+ counter_alarm = (((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)) * 3600U) + \
+ ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)) * 60U) + \
+ ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))));
+ LL_RTC_ALARM_Set(RTCx, counter_alarm);
+ }
+ status = SUCCESS;
+ }
+ /* Exit Initialization mode */
+ LL_RTC_ExitInitMode(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARM field to default value (Time = 00h:00mn:00sec /
+ * Day = 1st day of the month/Mask = all fields are masked).
+ * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
+ * @retval None
+ */
+void LL_RTC_ALARM_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
+{
+ /* Alarm Time Settings : Time = 00h:00mn:00sec */
+ RTC_AlarmStruct->AlarmTime.Hours = 0U;
+ RTC_AlarmStruct->AlarmTime.Minutes = 0U;
+ RTC_AlarmStruct->AlarmTime.Seconds = 0U;
+}
+
+/**
+ * @brief Enters the RTC Initialization mode.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC is in Init mode
+ * - ERROR: RTC is not in Init mode
+ */
+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
+{
+ __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
+ ErrorStatus status = SUCCESS;
+ uint32_t tmp = 0U;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
+ while ((timeout != 0U) && (tmp != 1U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout --;
+ }
+ tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+
+ /* Disable the write protection for RTC registers */
+ LL_RTC_DisableWriteProtection(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Exit the RTC Initialization mode.
+ * @note When the initialization sequence is complete, the calendar restarts
+ * counting after 4 RTCCLK cycles.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC exited from in Init mode
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
+{
+ __IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
+ ErrorStatus status = SUCCESS;
+ uint32_t tmp = 0U;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Disable initialization mode */
+ LL_RTC_EnableWriteProtection(RTCx);
+
+ /* Wait till RTC is in INIT state and if Time out is reached exit */
+ tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
+ while ((timeout != 0U) && (tmp != 1U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout --;
+ }
+ tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+ return status;
+}
+
+/**
+ * @brief Set the Time Counter
+ * @param RTCx RTC Instance
+ * @param TimeCounter this value can be from 0 to 0xFFFFFFFF
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC Counter register configured
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_RTC_TIME_SetCounter(RTC_TypeDef *RTCx, uint32_t TimeCounter)
+{
+ ErrorStatus status = ERROR;
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Enter Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ LL_RTC_TIME_Set(RTCx, TimeCounter);
+ status = SUCCESS;
+ }
+ /* Exit Initialization mode */
+ LL_RTC_ExitInitMode(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Set Alarm Counter.
+ * @param RTCx RTC Instance
+ * @param AlarmCounter this value can be from 0 to 0xFFFFFFFF
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC exited from in Init mode
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_RTC_ALARM_SetCounter(RTC_TypeDef *RTCx, uint32_t AlarmCounter)
+{
+ ErrorStatus status = ERROR;
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Enter Initialization mode */
+ if (LL_RTC_EnterInitMode(RTCx) != ERROR)
+ {
+ LL_RTC_ALARM_Set(RTCx, AlarmCounter);
+ status = SUCCESS;
+ }
+ /* Exit Initialization mode */
+ LL_RTC_ExitInitMode(RTCx);
+
+ return status;
+}
+
+/**
+ * @brief Waits until the RTC registers are synchronized with RTC APB clock.
+ * @note The RTC Resynchronization mode is write protected, use the
+ * @ref LL_RTC_DisableWriteProtection before calling this function.
+ * @param RTCx RTC Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: RTC registers are synchronised
+ * - ERROR: RTC registers are not synchronised
+ */
+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
+{
+ __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
+ ErrorStatus status = SUCCESS;
+ uint32_t tmp = 0U;
+
+ /* Check the parameter */
+ assert_param(IS_RTC_ALL_INSTANCE(RTCx));
+
+ /* Clear RSF flag */
+ LL_RTC_ClearFlag_RS(RTCx);
+
+ /* Wait the registers to be synchronised */
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ while ((timeout != 0U) && (tmp != 0U))
+ {
+ if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
+ {
+ timeout--;
+ }
+ tmp = LL_RTC_IsActiveFlag_RS(RTCx);
+ if (timeout == 0U)
+ {
+ status = ERROR;
+ }
+ }
+
+ return (status);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* defined(RTC) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_sdmmc.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_sdmmc.c
index a07d887..4c008d1 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_sdmmc.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_sdmmc.c
@@ -2,12 +2,12 @@
******************************************************************************
* @file stm32f1xx_ll_sdmmc.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
- * @brief SDMMC Low Layer HAL module driver.
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief SDIO Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
- * functionalities of the SDMMC peripheral:
+ * functionalities of the SDIO peripheral:
* + Initialization/de-initialization functions
* + I/O operation functions
* + Peripheral Control functions
@@ -17,11 +17,11 @@
==============================================================================
##### SDMMC peripheral features #####
==============================================================================
- [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2
- peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA
+ [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2
+ peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
devices.
-
- [..] The SDIO features include the following:
+
+ [..] The SDMMC features include the following:
(+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
for three different databus modes: 1-bit (default), 4-bit and 8-bit
(+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
@@ -38,9 +38,9 @@
==============================================================================
[..]
This driver is a considered as a driver of service for external devices drivers
- that interfaces with the SDIO peripheral.
- According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs
- is used in the device's driver to perform SDIO operations and functionalities.
+ that interfaces with the SDMMC peripheral.
+ According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs
+ is used in the device's driver to perform SDMMC operations and functionalities.
This driver is almost transparent for the final user, it is only used to implement other
functionalities of the external device.
@@ -50,10 +50,10 @@
(++) SDIO adapter clock (SDIOCLK = HCLK)
(++) AHB bus clock (HCLK/2)
- -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:
- Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
+ -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
+ Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))
- (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO
+ (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
peripheral.
(+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx)
@@ -84,11 +84,11 @@
-@@- To check if the command is well received, read the SDIO_CMDRESP
register using the SDIO_GetCommandResponse().
- The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
+ The SDMMC responses registers (SDIO_RESP1 to SDIO_RESP2), use the
SDIO_GetResponse() function.
(+) To control the DPSM (Data Path State Machine) and send/receive
- data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
+ data to/from the card use the SDIO_ConfigData(), SDIO_GetDataCounter(),
SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
*** Read Operations ***
@@ -100,14 +100,14 @@
(++) Data TimeOut
(++) Data Length
(++) Data Block size
- (++) Data Transfer direction: should be from card (To SDIO)
+ (++) Data Transfer direction: should be from card (To SDMMC)
(++) Data Transfer mode
(++) DPSM Status (Enable or Disable)
- (#) Configure the SDIO resources to receive the data from the card
- according to selected transfer mode.
+ (#) Configure the SDMMC resources to receive the data from the card
+ according to selected transfer mode (Refer to Step 8, 9 and 10).
- (#) Send the selected Read command.
+ (#) Send the selected Read command (refer to step 11).
(#) Use the SDIO flags/interrupts to check the transfer status.
@@ -124,18 +124,27 @@
(++) Data Transfer mode
(++) DPSM Status (Enable or Disable)
- (#) Configure the SDIO resources to send the data to the card according to
+ (#) Configure the SDMMC resources to send the data to the card according to
selected transfer mode.
(#) Send the selected Write command.
(#) Use the SDIO flags/interrupts to check the transfer status.
+
+ *** Command management operations ***
+ =====================================
+ [..]
+ (#) The commands used for Read/Write//Erase operations are managed in
+ separate functions.
+ Each function allows to send the needed command with the related argument,
+ then check the response.
+ By the same approach, you could implement a command and check the response.
@endverbatim
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -165,7 +174,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
-#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
#if defined(STM32F103xE) || defined(STM32F103xG)
@@ -174,22 +182,30 @@
*/
/** @defgroup SDMMC_LL SDMMC Low Layer
- * @brief Low layer module for SD and MMC driver
+ * @brief Low layer module for SD
* @{
*/
+#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx);
+static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout);
+static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx);
+static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx);
+static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx);
+static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA);
-/** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
* @{
*/
-/** @defgroup HAL_SDMMC_LL_Group1 Initialization and de-initialization functions
+/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
@@ -203,14 +219,16 @@
*/
/**
- * @brief Initializes the SDIO according to the specified
- * parameters in the SDIO_InitTypeDef and create the associated handle.
- * @param SDIOx: Pointer to SDIO register base
- * @param Init: SDIO initialization structure
+ * @brief Initializes the SDMMC according to the specified
+ * parameters in the SDMMC_InitTypeDef and create the associated handle.
+ * @param SDIOx: Pointer to SDMMC register base
+ * @param Init: SDMMC initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
{
+ uint32_t tmpreg = 0U;
+
/* Check the parameters */
assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge));
@@ -220,18 +238,22 @@
assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
- /* Set SDIO configuration parameters */
- /* Write to SDIO CLKCR */
- MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, Init.ClockEdge |\
- Init.ClockBypass |\
- Init.ClockPowerSave |\
- Init.BusWide |\
- Init.HardwareFlowControl |\
- Init.ClockDiv);
+ /* Set SDMMC configuration parameters */
+ tmpreg |= (Init.ClockEdge |\
+ Init.ClockBypass |\
+ Init.ClockPowerSave |\
+ Init.BusWide |\
+ Init.HardwareFlowControl |\
+ Init.ClockDiv
+ );
+
+ /* Write to SDMMC CLKCR */
+ MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
return HAL_OK;
}
+
/**
* @}
*/
@@ -241,10 +263,10 @@
*
@verbatim
===============================================================================
- ##### IO operation functions #####
- ===============================================================================
+ ##### I/O operation functions #####
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to manage the SDIO data
+ This subsection provides a set of functions allowing to manage the SDMMC data
transfers.
@endverbatim
@@ -253,7 +275,7 @@
/**
* @brief Read data (word) from Rx FIFO in blocking mode (polling)
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
@@ -264,7 +286,7 @@
/**
* @brief Write data (word) to Tx FIFO in blocking mode (polling)
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDMMC register base
* @param pWriteData: pointer to data to write
* @retval HAL status
*/
@@ -288,7 +310,7 @@
##### Peripheral Control functions #####
===============================================================================
[..]
- This subsection provides a set of functions allowing to control the SDIO data
+ This subsection provides a set of functions allowing to control the SDMMC data
transfers.
@endverbatim
@@ -296,8 +318,8 @@
*/
/**
- * @brief Set SDIO Power state to ON.
- * @param SDIOx: Pointer to SDIO register base
+ * @brief Set SDMMC Power state to ON.
+ * @param SDIOx: Pointer to SDMMC register base
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
@@ -305,25 +327,25 @@
/* Set power state to ON */
SDIOx->POWER = SDIO_POWER_PWRCTRL;
- return HAL_OK;
+ return HAL_OK;
}
/**
- * @brief Set SDIO Power state to OFF.
- * @param SDIOx: Pointer to SDIO register base
+ * @brief Set SDMMC Power state to OFF.
+ * @param SDIOx: Pointer to SDMMC register base
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
{
/* Set power state to OFF */
- SDIOx->POWER = (uint32_t)0x00000000;
+ SDIOx->POWER = 0x00000000U;
return HAL_OK;
}
/**
- * @brief Get SDIO Power state.
- * @param SDIOx: Pointer to SDIO register base
+ * @brief Get SDMMC Power state.
+ * @param SDIOx: Pointer to SDMMC register base
* @retval Power status of the controller. The returned value can be one of the
* following values:
* - 0x00: Power OFF
@@ -336,37 +358,41 @@
}
/**
- * @brief Configure the SDIO command path according to the specified parameters in
+ * @brief Configure the SDMMC command path according to the specified parameters in
* SDIO_CmdInitTypeDef structure and send the command
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDMMC register base
* @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains
- * the configuration information for the SDIO command
+ * the configuration information for the SDMMC command
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command)
{
+ uint32_t tmpreg = 0U;
+
/* Check the parameters */
assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex));
assert_param(IS_SDIO_RESPONSE(Command->Response));
assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt));
assert_param(IS_SDIO_CPSM(Command->CPSM));
- /* Set the SDIO Argument value */
+ /* Set the SDMMC Argument value */
SDIOx->ARG = Command->Argument;
- /* Set SDIO command parameters */
- /* Write to SDIO CMD register */
- MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, Command->CmdIndex |\
- Command->Response |\
- Command->WaitForInterrupt |\
- Command->CPSM);
+ /* Set SDMMC command parameters */
+ tmpreg |= (uint32_t)(Command->CmdIndex |\
+ Command->Response |\
+ Command->WaitForInterrupt |\
+ Command->CPSM);
+
+ /* Write to SDMMC CMD register */
+ MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg);
return HAL_OK;
}
/**
* @brief Return the command index of last command for which response received
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDMMC register base
* @retval Command index of the last command response received
*/
uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
@@ -377,7 +403,8 @@
/**
* @brief Return the response received from the card for the last command
- * @param SDIO_RESP: Specifies the SDIO response register.
+ * @param SDIOx: Pointer to SDMMC register base
+ * @param Response: Specifies the SDMMC response register.
* This parameter can be one of the following values:
* @arg SDIO_RESP1: Response Register 1
* @arg SDIO_RESP2: Response Register 2
@@ -387,27 +414,29 @@
*/
uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response)
{
- __IO uint32_t tmp = 0;
+ __IO uint32_t tmp = 0U;
/* Check the parameters */
assert_param(IS_SDIO_RESP(Response));
/* Get the response */
- tmp = SDIO_RESP_ADDR + Response;
+ tmp = (uint32_t)&(SDIOx->RESP1) + Response;
return (*(__IO uint32_t *) tmp);
}
/**
- * @brief Configure the SDIO data path according to the specified
+ * @brief Configure the SDMMC data path according to the specified
* parameters in the SDIO_DataInitTypeDef.
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDMMC register base
* @param Data : pointer to a SDIO_DataInitTypeDef structure
- * that contains the configuration information for the SDIO data.
+ * that contains the configuration information for the SDMMC data.
* @retval HAL status
*/
-HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data)
+HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data)
{
+ uint32_t tmpreg = 0U;
+
/* Check the parameters */
assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength));
assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize));
@@ -415,18 +444,20 @@
assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode));
assert_param(IS_SDIO_DPSM(Data->DPSM));
- /* Set the SDIO Data TimeOut value */
+ /* Set the SDMMC Data TimeOut value */
SDIOx->DTIMER = Data->DataTimeOut;
- /* Set the SDIO DataLength value */
+ /* Set the SDMMC DataLength value */
SDIOx->DLEN = Data->DataLength;
- /* Set the SDIO data configuration parameters */
- /* Write to SDIO DCTRL */
- MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, Data->DataBlockSize |\
- Data->TransferDir |\
- Data->TransferMode |\
- Data->DPSM);
+ /* Set the SDMMC data configuration parameters */
+ tmpreg |= (uint32_t)(Data->DataBlockSize |\
+ Data->TransferDir |\
+ Data->TransferMode |\
+ Data->DPSM);
+
+ /* Write to SDMMC DCTRL */
+ MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
return HAL_OK;
@@ -434,7 +465,7 @@
/**
* @brief Returns number of remaining data bytes to be transferred.
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDMMC register base
* @retval Number of remaining data bytes to be transferred
*/
uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
@@ -444,7 +475,7 @@
/**
* @brief Get the FIFO data
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx: Pointer to SDMMC register base
* @retval Data received
*/
uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
@@ -452,26 +483,1001 @@
return (SDIOx->FIFO);
}
-
/**
* @brief Sets one of the two options of inserting read wait interval.
- * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
+ * @param SDIOx: Pointer to SDMMC register base
+ * @param SDIO_ReadWaitMode: SDMMC Read Wait operation mode.
* This parameter can be:
- * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK
- * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2
+ * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
+ * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
* @retval None
*/
-HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode)
+HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode)
{
/* Check the parameters */
assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
-
- /* Set SDIO read wait mode */
- MODIFY_REG(SDIO->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode);
+
+ /* Set SDMMC read wait mode */
+ MODIFY_REG(SDIOx->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode);
return HAL_OK;
}
+/**
+ * @}
+ */
+
+
+/** @defgroup HAL_SDMMC_LL_Group4 Command management functions
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Commands management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the needed commands.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Send the Data Block Lenght command and check the response
+ * @param SDIOx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)BlockSize;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Read Single Block command and check the response
+ * @param SDIOx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Read Multi Block command and check the response
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)ReadAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Write Single Block command and check the response
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Write Multi Block command and check the response
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)WriteAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Start Address Erase command for SD and check the response
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the End Address Erase command for SD and check the response
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Start Address Erase command and check the response
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)StartAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_START, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the End Address Erase command and check the response
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = (uint32_t)EndAdd;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_END, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Erase command and check the response
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Set Block Size for Card */
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE, SDIO_MAXERASETIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Stop Transfer command and check the response.
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Send CMD12 STOP_TRANSMISSION */
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, 100000000U);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Select Deselect command and check the response.
+ * @param SDIOx: Pointer to SDIO register base
+ * @param addr: Address of the card to be selected
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Send CMD7 SDMMC_SEL_DESEL_CARD */
+ sdmmc_cmdinit.Argument = (uint32_t)Addr;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Go Idle State command and check the response.
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_NO;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdError(SDIOx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Operating Condition command and check the response.
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Send CMD8 to verify SD card interface operating condition */
+ /* Argument: - [31:12]: Reserved (shall be set to '0')
+ - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
+ - [7:0]: Check Pattern (recommended 0xAA) */
+ /* CMD Response: R7 */
+ sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp7(SDIOx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Application command to verify that that the next command
+ * is an application specific com-mand rather than a standard command
+ * and check the response.
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = (uint32_t)Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ /* If there is a HAL_ERROR, it is a MMC card, else
+ it is a SD card: SD card 2.0 (voltage range mismatch)
+ or SD card 1.x */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the command asking the accessed card to send its operating
+ * condition register (OCR)
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | SdType;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp3(SDIOx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Bus Width command and check the response.
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = (uint32_t)BusWidth;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Send SCR command and check the response.
+ * @param SDIOx: Pointer to SDMMC register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Send CMD51 SD_APP_SEND_SCR */
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Send CID command and check the response.
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Send CMD2 ALL_SEND_CID */
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp2(SDIOx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Send CSD command and check the response.
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Send CMD9 SEND_CSD */
+ sdmmc_cmdinit.Argument = (uint32_t)Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp2(SDIOx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Send CSD command and check the response.
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ /* Send CMD3 SD_CMD_SET_REL_ADDR */
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Status command and check the response.
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = (uint32_t)Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Send the Status register command and check the response.
+ * @param SDIOx: Pointer to SDIO register base
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = 0U;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_STATUS, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @brief Sends host capacity support information and activates the card's
+ * initialization process. Send SDMMC_CMD_SEND_OP_COND command
+ * @param SDIOx: Pointer to SDIO register base
+ * @parame Argument: Argument used for the command
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp3(SDIOx);
+
+ return errorstate;
+}
+
+/**
+ * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
+ * @param SDIOx: Pointer to SDIO register base
+ * @parame Argument: Argument used for the command
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument)
+{
+ SDIO_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate = SDMMC_ERROR_NONE;
+
+ sdmmc_cmdinit.Argument = Argument;
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH;
+ sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE;
+ SDIO_SendCommand(SDIOx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SWITCH, SDIO_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
+ * @}
+ */
+
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Checks for error conditions for CMD0.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx)
+{
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDMMC_CMDTIMEOUT is expressed in ms */
+ register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+
+ }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT));
+
+ /* Clear all the static flags */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @brief Checks for error conditions for R1 response.
+ * @param hsd: SD handle
+ * @param SD_CMD: The sent command index
+ * @retval SD Card error state
+ */
+static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout)
+{
+ uint32_t response_r1;
+
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The Timeout is expressed in ms */
+ register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+
+ }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
+
+ if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+ {
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+
+ return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ }
+ else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
+ {
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
+
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+
+ /* Check response received is of desired command */
+ if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
+ {
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+
+ /* Clear all the static flags */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
+
+ /* We have received response, retrieve it for analysis */
+ response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
+
+ if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO)
+ {
+ return SDMMC_ERROR_NONE;
+ }
+ else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE)
+ {
+ return SDMMC_ERROR_ADDR_OUT_OF_RANGE;
+ }
+ else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED)
+ {
+ return SDMMC_ERROR_ADDR_MISALIGNED;
+ }
+ else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR)
+ {
+ return SDMMC_ERROR_BLOCK_LEN_ERR;
+ }
+ else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR)
+ {
+ return SDMMC_ERROR_ERASE_SEQ_ERR;
+ }
+ else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM)
+ {
+ return SDMMC_ERROR_BAD_ERASE_PARAM;
+ }
+ else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION)
+ {
+ return SDMMC_ERROR_WRITE_PROT_VIOLATION;
+ }
+ else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED)
+ {
+ return SDMMC_ERROR_LOCK_UNLOCK_FAILED;
+ }
+ else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED)
+ {
+ return SDMMC_ERROR_COM_CRC_FAILED;
+ }
+ else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD)
+ {
+ return SDMMC_ERROR_ILLEGAL_CMD;
+ }
+ else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED)
+ {
+ return SDMMC_ERROR_CARD_ECC_FAILED;
+ }
+ else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR)
+ {
+ return SDMMC_ERROR_CC_ERR;
+ }
+ else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN)
+ {
+ return SDMMC_ERROR_STREAM_READ_UNDERRUN;
+ }
+ else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN)
+ {
+ return SDMMC_ERROR_STREAM_WRITE_OVERRUN;
+ }
+ else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE)
+ {
+ return SDMMC_ERROR_CID_CSD_OVERWRITE;
+ }
+ else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP)
+ {
+ return SDMMC_ERROR_WP_ERASE_SKIP;
+ }
+ else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED)
+ {
+ return SDMMC_ERROR_CARD_ECC_DISABLED;
+ }
+ else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET)
+ {
+ return SDMMC_ERROR_ERASE_RESET;
+ }
+ else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR)
+ {
+ return SDMMC_ERROR_AKE_SEQ_ERR;
+ }
+ else
+ {
+ return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+}
+
+/**
+ * @brief Checks for error conditions for R2 (CID or CSD) response.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx)
+{
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDMMC_CMDTIMEOUT is expressed in ms */
+ register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+
+ }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
+
+ if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+ {
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+
+ return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ }
+ else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
+ {
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
+
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+ else
+ {
+ /* No error flag set */
+ /* Clear all the static flags */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
+ }
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @brief Checks for error conditions for R3 (OCR) response.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx)
+{
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDMMC_CMDTIMEOUT is expressed in ms */
+ register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+
+ }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
+
+ if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+ {
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+
+ return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ }
+ else
+
+ {
+ /* Clear all the static flags */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
+ }
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @brief Checks for error conditions for R6 (RCA) response.
+ * @param hsd: SD handle
+ * @param SD_CMD: The sent command index
+ * @param pRCA: Pointer to the variable that will contain the SD card relative
+ * address RCA
+ * @retval SD Card error state
+ */
+static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA)
+{
+ uint32_t response_r1;
+
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDMMC_CMDTIMEOUT is expressed in ms */
+ register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+
+ }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
+
+ if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+ {
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT);
+
+ return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ }
+ else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL))
+ {
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL);
+
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+
+ /* Check response received is of desired command */
+ if(SDIO_GetCommandResponse(SDIOx) != SD_CMD)
+ {
+ return SDMMC_ERROR_CMD_CRC_FAIL;
+ }
+
+ /* Clear all the static flags */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS);
+
+ /* We have received response, retrieve it. */
+ response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1);
+
+ if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO)
+ {
+ *pRCA = (uint16_t) (response_r1 >> 16);
+
+ return SDMMC_ERROR_NONE;
+ }
+ else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD)
+ {
+ return SDMMC_ERROR_ILLEGAL_CMD;
+ }
+ else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED)
+ {
+ return SDMMC_ERROR_COM_CRC_FAILED;
+ }
+ else
+ {
+ return SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+}
+
+/**
+ * @brief Checks for error conditions for R7 response.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx)
+{
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDIO_CMDTIMEOUT is expressed in ms */
+ register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+
+ }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT));
+
+ if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT))
+ {
+ /* Card is SD V2.0 compliant */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND);
+
+ return SDMMC_ERROR_CMD_RSP_TIMEOUT;
+ }
+
+ if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND))
+ {
+ /* Card is SD V2.0 compliant */
+ __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND);
+ }
+
+ return SDMMC_ERROR_NONE;
+
+}
/**
* @}
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_spi.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_spi.c
new file mode 100644
index 0000000..67262c9
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_spi.c
@@ -0,0 +1,562 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_spi.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief SPI LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_spi.h"
+#include "stm32f1xx_ll_bus.h"
+#include "stm32f1xx_ll_rcc.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (SPI1) || defined (SPI2) || defined (SPI3)
+
+/** @addtogroup SPI_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Constants SPI Private Constants
+ * @{
+ */
+/* SPI registers Masks */
+#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
+ SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
+ SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \
+ SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
+ SPI_CR1_BIDIMODE)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SPI_LL_Private_Macros SPI Private Macros
+ * @{
+ */
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
+ || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
+ || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+
+#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
+ || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+
+#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
+ || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
+
+#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
+ || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+
+#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
+ || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+
+#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
+ || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+
+#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
+ || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+
+#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
+ || ((__VALUE__) == LL_SPI_MSB_FIRST))
+
+#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
+ || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+
+#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup SPI_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the SPI registers to their default reset values.
+ * @param SPIx SPI Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are de-initialized
+ * - ERROR: SPI registers are not de-initialized
+ */
+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the parameters */
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+#if defined(SPI1)
+ if (SPIx == SPI1)
+ {
+ /* Force reset of SPI clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ /* Release reset of SPI clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
+
+ status = SUCCESS;
+ }
+#endif /* SPI1 */
+#if defined(SPI2)
+ if (SPIx == SPI2)
+ {
+ /* Force reset of SPI clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ /* Release reset of SPI clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
+
+ status = SUCCESS;
+ }
+#endif /* SPI2 */
+#if defined(SPI3)
+ if (SPIx == SPI3)
+ {
+ /* Force reset of SPI clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+ /* Release reset of SPI clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
+
+ status = SUCCESS;
+ }
+#endif /* SPI3 */
+
+ return status;
+}
+
+/**
+ * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+ * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param SPIx SPI Instance
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
+ */
+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ ErrorStatus status = ERROR;
+
+ /* Check the SPI Instance SPIx*/
+ assert_param(IS_SPI_ALL_INSTANCE(SPIx));
+
+ /* Check the SPI parameters from SPI_InitStruct*/
+ assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
+ assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
+ assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
+ assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
+ assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
+ assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
+ assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
+ assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
+ assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
+
+ if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
+ {
+ /*---------------------------- SPIx CR1 Configuration ------------------------
+ * Configure SPIx CR1 with parameters:
+ * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
+ * - Master/Slave Mode: SPI_CR1_MSTR bit
+ * - DataWidth: SPI_CR1_DFF bit
+ * - ClockPolarity: SPI_CR1_CPOL bit
+ * - ClockPhase: SPI_CR1_CPHA bit
+ * - NSS management: SPI_CR1_SSM bit
+ * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
+ * - BitOrder: SPI_CR1_LSBFIRST bit
+ * - CRCCalculation: SPI_CR1_CRCEN bit
+ */
+ MODIFY_REG(SPIx->CR1,
+ SPI_CR1_CLEAR_MASK,
+ SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
+ SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
+ SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
+ SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
+
+ /*---------------------------- SPIx CR2 Configuration ------------------------
+ * Configure SPIx CR2 with parameters:
+ * - NSS management: SSOE bit
+ */
+ MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
+
+ /*---------------------------- SPIx CRCPR Configuration ----------------------
+ * Configure SPIx CRCPR with parameters:
+ * - CRCPoly: CRCPOLY[15:0] bits
+ */
+ if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
+ {
+ assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
+ LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
+ }
+ status = SUCCESS;
+ }
+
+#if defined (SPI_I2S_SUPPORT)
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+ CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
+#endif /* SPI_I2S_SUPPORT */
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
+ * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
+{
+ /* Set SPI_InitStruct fields to default values */
+ SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
+ SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
+ SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
+ SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
+ SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
+ SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
+ SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
+ SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
+ SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
+ SPI_InitStruct->CRCPoly = 7U;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#if defined(SPI_I2S_SUPPORT)
+/** @addtogroup I2S_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Constants I2S Private Constants
+ * @{
+ */
+/* I2S registers Masks */
+#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
+ SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
+ SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
+
+#define I2S_I2SPR_CLEAR_MASK 0x0002U
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2S_LL_Private_Macros I2S Private Macros
+ * @{
+ */
+
+#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
+ || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+
+#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
+ || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+
+#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
+ || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
+ || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+
+#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
+ || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
+
+#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
+ || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+
+#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
+ && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
+ || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+
+#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
+
+#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
+ || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2S_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup I2S_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize the SPI/I2S registers to their default reset values.
+ * @param SPIx SPI Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are de-initialized
+ * - ERROR: SPI registers are not de-initialized
+ */
+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+{
+ return LL_SPI_DeInit(SPIx);
+}
+
+/**
+ * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
+ * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
+ * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param SPIx SPI Instance
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: SPI registers are Initialized
+ * - ERROR: SPI registers are not Initialized
+ */
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
+ uint32_t tmp = 0U;
+ uint32_t sourceclock = 0U;
+#if defined(I2S2_I2S3_CLOCK_FEATURE)
+#else
+ LL_RCC_ClocksTypeDef rcc_clocks;
+#endif /* I2S2_I2S3_CLOCK_FEATURE */
+ ErrorStatus status = ERROR;
+
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
+ assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
+ assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
+ assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
+ assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
+ assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
+
+ if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
+ {
+ /*---------------------------- SPIx I2SCFGR Configuration --------------------
+ * Configure SPIx I2SCFGR with parameters:
+ * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
+ * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
+ * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
+ * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
+ */
+
+ /* Write to SPIx I2SCFGR */
+ MODIFY_REG(SPIx->I2SCFGR,
+ I2S_I2SCFGR_CLEAR_MASK,
+ I2S_InitStruct->Mode | I2S_InitStruct->Standard |
+ I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
+ SPI_I2SCFGR_I2SMOD);
+
+ /*---------------------------- SPIx I2SPR Configuration ----------------------
+ * Configure SPIx I2SPR with parameters:
+ * - MCLKOutput: SPI_I2SPR_MCKOE bit
+ * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
+ */
+
+ /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
+ * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
+ */
+ if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
+ {
+ /* Check the frame length (For the Prescaler computing)
+ * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
+ */
+ if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
+ {
+ /* Packet length is 32 bits */
+ packetlength = 2U;
+ }
+#if defined(I2S2_I2S3_CLOCK_FEATURE)
+ /* If an external I2S clock has to be used, the specific define should be set
+ in the project configuration or in the stm32f1xx_ll_rcc.h file */
+ if(SPIx == SPI2)
+ {
+ /* Get the I2S source clock value */
+ sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
+ }
+ else /* SPI3 */
+ {
+ /* Get the I2S source clock value */
+ sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S3_CLKSOURCE);
+ }
+#else
+ /* I2S Clock source is System clock: Get System Clock frequency */
+ LL_RCC_GetSystemClocksFreq(&rcc_clocks);
+
+ /* Get the source clock value: based on System Clock value */
+ sourceclock = rcc_clocks.SYSCLK_Frequency;
+#endif /* I2S2_I2S3_CLOCK_FEATURE */
+ /* Compute the Real divider depending on the MCLK output state with a floating point */
+ if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
+ {
+ /* MCLK output is enabled */
+ tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ }
+ else
+ {
+ /* MCLK output is disabled */
+ tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
+ }
+
+ /* Remove the floating point */
+ tmp = tmp / 10U;
+
+ /* Check the parity of the divider */
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
+
+ /* Compute the i2sdiv prescaler */
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
+
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+ i2sodd = (uint16_t)(i2sodd << 8U);
+ }
+
+ /* Test if the divider is 1 or 0 or greater than 0xFF */
+ if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
+ {
+ /* Set the default values */
+ i2sdiv = 2U;
+ i2sodd = 0U;
+ }
+
+ /* Write to SPIx I2SPR register the computed value */
+ WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
+
+ status = SUCCESS;
+ }
+ return status;
+}
+
+/**
+ * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
+ * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
+{
+ /*--------------- Reset I2S init structure parameters values -----------------*/
+ I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
+ I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
+ I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
+ I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
+ I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
+ I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
+}
+
+/**
+ * @brief Set linear and parity prescaler.
+ * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
+ * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
+ * @param SPIx SPI Instance
+ * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
+ * @param PrescalerParity This parameter can be one of the following values:
+ * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
+ * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
+ * @retval None
+ */
+void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
+{
+ /* Check the I2S parameters */
+ assert_param(IS_I2S_ALL_INSTANCE(SPIx));
+ assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
+ assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
+
+ /* Write to SPIx I2SPR */
+ MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+#endif /* SPI_I2S_SUPPORT */
+
+#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_tim.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_tim.c
new file mode 100644
index 0000000..ef5edc8
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_tim.c
@@ -0,0 +1,1216 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_tim.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief TIM LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_tim.h"
+#include "stm32f1xx_ll_bus.h"
+
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
+
+/** @addtogroup TIM_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup TIM_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
+ || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
+
+#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
+ || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
+
+#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
+ || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
+ || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
+
+#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
+
+#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
+ || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
+
+#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
+ || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
+
+#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
+ || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
+
+#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
+ || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
+
+#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
+ || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
+
+#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+
+#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
+ || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
+
+#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
+ || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
+
+#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
+
+#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
+ || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
+
+#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
+ || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
+
+#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
+ || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
+
+#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
+ || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
+
+#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
+ || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
+/**
+ * @}
+ */
+
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup TIM_LL_Private_Functions TIM Private Functions
+ * @{
+ */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIM_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup TIM_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief Set TIMx registers to their reset values.
+ * @param TIMx Timer instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: invalid TIMx instance
+ */
+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
+{
+ ErrorStatus result = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(TIMx));
+
+ if (TIMx == TIM2)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
+ }
+#if defined(TIM1)
+ else if (TIMx == TIM1)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
+ }
+#endif
+#if defined(TIM3)
+ else if (TIMx == TIM3)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
+ }
+#endif
+#if defined(TIM4)
+ else if (TIMx == TIM4)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
+ }
+#endif
+#if defined(TIM5)
+ else if (TIMx == TIM5)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
+ }
+#endif
+#if defined(TIM6)
+ else if (TIMx == TIM6)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
+ }
+#endif
+#if defined (TIM7)
+ else if (TIMx == TIM7)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
+ }
+#endif
+#if defined(TIM8)
+ else if (TIMx == TIM8)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
+ }
+#endif
+#if defined(TIM9)
+ else if (TIMx == TIM9)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
+ }
+#endif
+#if defined(TIM10)
+ else if (TIMx == TIM10)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
+ }
+#endif
+#if defined(TIM11)
+ else if (TIMx == TIM11)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
+ }
+#endif
+#if defined(TIM12)
+ else if (TIMx == TIM12)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
+ }
+#endif
+#if defined(TIM13)
+ else if (TIMx == TIM13)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
+ }
+#endif
+#if defined(TIM14)
+ else if (TIMx == TIM14)
+ {
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
+ }
+#endif
+#if defined(TIM15)
+ else if (TIMx == TIM15)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
+ }
+#endif
+#if defined(TIM16)
+ else if (TIMx == TIM16)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
+ }
+#endif
+#if defined(TIM17)
+ else if (TIMx == TIM17)
+ {
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
+ }
+#endif
+ else
+ {
+ result = ERROR;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Set the fields of the time base unit configuration data structure
+ * to their default values.
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
+ * @retval None
+ */
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+ /* Set the default configuration */
+ TIM_InitStruct->Prescaler = (uint16_t)0x0000;
+ TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
+ TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
+ TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
+ TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
+}
+
+/**
+ * @brief Configure the TIMx time base unit.
+ * @param TIMx Timer Instance
+ * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
+{
+ uint32_t tmpcr1 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
+ assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
+
+ tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
+
+ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ {
+ /* Select the Counter Mode */
+ MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
+ }
+
+ if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ {
+ /* Set the clock division */
+ MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
+ }
+
+ /* Write to TIMx CR1 */
+ LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
+
+ /* Set the Autoreload value */
+ LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
+
+ /* Set the Prescaler value */
+ LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
+
+ if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ {
+ /* Set the Repetition Counter value */
+ LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
+ }
+
+ /* Generate an update event to reload the Prescaler
+ and the repetition counter value (if applicable) immediately */
+ LL_TIM_GenerateEvent_UPDATE(TIMx);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the TIMx output channel configuration data
+ * structure to their default values.
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
+ * @retval None
+ */
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+ /* Set the default configuration */
+ TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
+ TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
+ TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
+ TIM_OC_InitStruct->CompareValue = 0x00000000U;
+ TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
+ TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
+ TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
+ TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
+}
+
+/**
+ * @brief Configure the TIMx output channel.
+ * @param TIMx Timer Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx output channel is initialized
+ * - ERROR: TIMx output channel is not initialized
+ */
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+{
+ ErrorStatus result = ERROR;
+
+ switch (Channel)
+ {
+ case LL_TIM_CHANNEL_CH1:
+ result = OC1Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH2:
+ result = OC2Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH3:
+ result = OC3Config(TIMx, TIM_OC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH4:
+ result = OC4Config(TIMx, TIM_OC_InitStruct);
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Set the fields of the TIMx input channel configuration data
+ * structure to their default values.
+ * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
+ * @retval None
+ */
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Set the default configuration */
+ TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
+ TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+ * @brief Configure the TIMx input channel.
+ * @param TIMx Timer Instance
+ * @param Channel This parameter can be one of the following values:
+ * @arg @ref LL_TIM_CHANNEL_CH1
+ * @arg @ref LL_TIM_CHANNEL_CH2
+ * @arg @ref LL_TIM_CHANNEL_CH3
+ * @arg @ref LL_TIM_CHANNEL_CH4
+ * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx output channel is initialized
+ * - ERROR: TIMx output channel is not initialized
+ */
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
+{
+ ErrorStatus result = ERROR;
+
+ switch (Channel)
+ {
+ case LL_TIM_CHANNEL_CH1:
+ result = IC1Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH2:
+ result = IC2Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH3:
+ result = IC3Config(TIMx, TIM_IC_InitStruct);
+ break;
+ case LL_TIM_CHANNEL_CH4:
+ result = IC4Config(TIMx, TIM_IC_InitStruct);
+ break;
+ default:
+ break;
+ }
+
+ return result;
+}
+
+/**
+ * @brief Fills each TIM_EncoderInitStruct field with its default value
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
+ * @retval None
+ */
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+ /* Set the default configuration */
+ TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
+ TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
+ TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
+ TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
+}
+
+/**
+ * @brief Configure the encoder interface of the timer instance.
+ * @param TIMx Timer Instance
+ * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
+
+ /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Configure TI1 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
+
+ /* Configure TI2 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
+ tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
+
+ /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
+ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
+ tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
+ tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Set encoder mode */
+ LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the TIMx Hall sensor interface configuration data
+ * structure to their default values.
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
+ * @retval None
+ */
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+ /* Set the default configuration */
+ TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
+ TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
+ TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
+ TIM_HallSensorInitStruct->CommutationDelay = 0U;
+}
+
+/**
+ * @brief Configure the Hall sensor interface of the timer instance.
+ * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
+ * to the TI1 input channel
+ * @note TIMx slave mode controller is configured in reset mode.
+ Selected internal trigger is TI1F_ED.
+ * @note Channel 1 is configured as input, IC1 is mapped on TRC.
+ * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
+ * between 2 changes on the inputs. It gives information about motor speed.
+ * @note Channel 2 is configured in output PWM 2 mode.
+ * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
+ * @note OC2REF is selected as trigger output on TRGO.
+ * @param TIMx Timer Instance
+ * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+{
+ uint32_t tmpcr2 = 0U;
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpsmcr = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
+ assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
+
+ /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
+ TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx SMCR register value */
+ tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
+
+ /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
+ tmpcr2 |= TIM_CR2_TI1S;
+
+ /* OC2REF signal is used as trigger output (TRGO) */
+ tmpcr2 |= LL_TIM_TRGO_OC2REF;
+
+ /* Configure the slave mode controller */
+ tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
+ tmpsmcr |= LL_TIM_TS_TI1F_ED;
+ tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
+
+ /* Configure input channel 1 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
+ tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
+ tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
+
+ /* Configure input channel 2 */
+ tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
+ tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
+
+ /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
+ tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
+ tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx SMCR */
+ LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ /* Write to TIMx CCR2 */
+ LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Set the fields of the Break and Dead Time configuration data structure
+ * to their default values.
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
+ * @retval None
+ */
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+ /* Set the default configuration */
+ TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
+ TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
+ TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
+ TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
+ TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
+ TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
+ TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
+}
+
+/**
+ * @brief Configure the Break and Dead Time feature of the timer instance.
+ * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
+ * depending on the LOCK configuration, it can be necessary to configure all of
+ * them during the first write access to the TIMx_BDTR register.
+ * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+ * a timer instance provides a break input.
+ * @param TIMx Timer Instance
+ * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Break and Dead Time is initialized
+ * - ERROR: not applicable
+ */
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+{
+ uint32_t tmpbdtr = 0;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
+ assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
+ assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
+ assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
+ assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
+ assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+
+ /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */
+
+ /* Set the BDTR bits */
+ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
+
+ /* Set TIMx_BDTR */
+ LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
+
+ return SUCCESS;
+}
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
+ * @brief Private functions
+ * @{
+ */
+/**
+ * @brief Configure the TIMx output channel 1.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
+
+ /* Set the Output Compare Mode */
+ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 2.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr1 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR1 register value */
+ tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR1 */
+ LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 3.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the complementary output Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
+
+ /* Set the complementary output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
+
+ /* Set the complementary output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR2 */
+ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx output channel 4.
+ * @param TIMx Timer Instance
+ * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+{
+ uint32_t tmpccmr2 = 0U;
+ uint32_t tmpccer = 0U;
+ uint32_t tmpcr2 = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
+ assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+ assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
+
+ /* Get the TIMx CCER register value */
+ tmpccer = LL_TIM_ReadReg(TIMx, CCER);
+
+ /* Get the TIMx CR2 register value */
+ tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
+
+ /* Get the TIMx CCMR2 register value */
+ tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
+
+ /* Reset Capture/Compare selection Bits */
+ CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
+
+ /* Select the Output Compare Mode */
+ MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
+
+ /* Set the Output Compare Polarity */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
+
+ /* Set the Output State */
+ MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
+
+ if (IS_TIM_BREAK_INSTANCE(TIMx))
+ {
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
+ assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+
+ /* Set the Output Idle state */
+ MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
+ }
+
+ /* Write to TIMx CR2 */
+ LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
+
+ /* Write to TIMx CCMR2 */
+ LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
+
+ /* Set the Capture Compare Register value */
+ LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
+
+ /* Write to TIMx CCER */
+ LL_TIM_WriteReg(TIMx, CCER, tmpccer);
+
+ return SUCCESS;
+}
+
+
+/**
+ * @brief Configure the TIMx input channel 1.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 1: Reset the CC1E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR1,
+ (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+ /* Select the Polarity and set the CC1E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC1P | TIM_CCER_CC1NP),
+ (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 2.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC2_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 2: Reset the CC2E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR1,
+ (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+ /* Select the Polarity and set the CC2E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC2P | TIM_CCER_CC2NP),
+ ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 3.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC3_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 3: Reset the CC3E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR2,
+ (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
+
+ /* Select the Polarity and set the CC3E Bit */
+ MODIFY_REG(TIMx->CCER,
+ (TIM_CCER_CC3P | TIM_CCER_CC3NP),
+ ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
+
+ return SUCCESS;
+}
+
+/**
+ * @brief Configure the TIMx input channel 4.
+ * @param TIMx Timer Instance
+ * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: TIMx registers are de-initialized
+ * - ERROR: not applicable
+ */
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_CC4_INSTANCE(TIMx));
+ assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
+ assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
+ assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
+ assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
+
+ /* Disable the Channel 4: Reset the CC4E Bit */
+ TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
+
+ /* Select the Input and set the filter and the prescaler value */
+ MODIFY_REG(TIMx->CCMR2,
+ (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
+ (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
+
+ /* Select the Polarity and set the CC4E Bit */
+ MODIFY_REG(TIMx->CCER,
+ TIM_CCER_CC4P,
+ ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
+
+ return SUCCESS;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_usart.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_usart.c
new file mode 100644
index 0000000..04b047a
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_usart.c
@@ -0,0 +1,451 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_usart.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief USART LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_usart.h"
+#include "stm32f1xx_ll_rcc.h"
+#include "stm32f1xx_ll_bus.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
+
+/** @addtogroup USART_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Macros
+ * @{
+ */
+
+/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
+ * divided by the smallest oversampling used on the USART (i.e. 8) */
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
+
+#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
+ || ((__VALUE__) == LL_USART_DIRECTION_RX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX) \
+ || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
+
+#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
+ || ((__VALUE__) == LL_USART_PARITY_EVEN) \
+ || ((__VALUE__) == LL_USART_PARITY_ODD))
+
+#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
+ || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
+
+#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
+ || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
+
+#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
+ || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
+
+#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
+ || ((__VALUE__) == LL_USART_PHASE_2EDGE))
+
+#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
+ || ((__VALUE__) == LL_USART_POLARITY_HIGH))
+
+#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
+ || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
+
+#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1) \
+ || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
+ || ((__VALUE__) == LL_USART_STOPBITS_2))
+
+#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
+ || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
+
+/**
+ * @}
+ */
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup USART_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup USART_LL_EF_Init
+ * @{
+ */
+
+/**
+ * @brief De-initialize USART registers (Registers restored to their default values).
+ * @param USARTx USART Instance
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers are de-initialized
+ * - ERROR: USART registers are not de-initialized
+ */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+
+ if (USARTx == USART1)
+ {
+ /* Force reset of USART clock */
+ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
+
+ /* Release reset of USART clock */
+ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
+ }
+ else if (USARTx == USART2)
+ {
+ /* Force reset of USART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
+
+ /* Release reset of USART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
+ }
+#if defined(USART3)
+ else if (USARTx == USART3)
+ {
+ /* Force reset of USART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
+
+ /* Release reset of USART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
+ }
+#endif /* USART3 */
+#if defined(UART4)
+ else if (USARTx == UART4)
+ {
+ /* Force reset of UART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
+
+ /* Release reset of UART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
+ }
+#endif /* UART4 */
+#if defined(UART5)
+ else if (USARTx == UART5)
+ {
+ /* Force reset of UART clock */
+ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
+
+ /* Release reset of UART clock */
+ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
+ }
+#endif /* UART5 */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Initialize USART registers according to the specified
+ * parameters in USART_InitStruct.
+ * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+ * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
+ * @param USARTx USART Instance
+ * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
+ * that contains the configuration information for the specified USART peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers are initialized according to USART_InitStruct content
+ * - ERROR: Problem occurred during USART Registers initialization
+ */
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
+{
+ ErrorStatus status = ERROR;
+ uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
+ LL_RCC_ClocksTypeDef rcc_clocks;
+
+ /* Check the parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+ assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
+ assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
+ assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
+ assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
+ assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
+ assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
+#if defined(USART_CR1_OVER8)
+ assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
+#endif /* USART_OverSampling_Feature */
+
+ /* USART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers */
+ if (LL_USART_IsEnabled(USARTx) == 0U)
+ {
+ /*---------------------------- USART CR1 Configuration -----------------------
+ * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
+ * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
+ * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
+ * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
+ * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
+ */
+#if defined(USART_CR1_OVER8)
+ MODIFY_REG(USARTx->CR1,
+ (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+ USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+ (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+ USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
+#else
+ MODIFY_REG(USARTx->CR1,
+ (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
+ USART_CR1_TE | USART_CR1_RE),
+ (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
+ USART_InitStruct->TransferDirection));
+#endif /* USART_OverSampling_Feature */
+
+ /*---------------------------- USART CR2 Configuration -----------------------
+ * Configure USARTx CR2 (Stop bits) with parameters:
+ * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
+ * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
+ */
+ LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
+
+ /*---------------------------- USART CR3 Configuration -----------------------
+ * Configure USARTx CR3 (Hardware Flow Control) with parameters:
+ * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
+ */
+ LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
+
+ /*---------------------------- USART BRR Configuration -----------------------
+ * Retrieve Clock frequency used for USART Peripheral
+ */
+ LL_RCC_GetSystemClocksFreq(&rcc_clocks);
+ if (USARTx == USART1)
+ {
+ periphclk = rcc_clocks.PCLK2_Frequency;
+ }
+ else if (USARTx == USART2)
+ {
+ periphclk = rcc_clocks.PCLK1_Frequency;
+ }
+#if defined(USART3)
+ else if (USARTx == USART3)
+ {
+ periphclk = rcc_clocks.PCLK1_Frequency;
+ }
+#endif /* USART3 */
+#if defined(UART4)
+ else if (USARTx == UART4)
+ {
+ periphclk = rcc_clocks.PCLK1_Frequency;
+ }
+#endif /* UART4 */
+#if defined(UART5)
+ else if (USARTx == UART5)
+ {
+ periphclk = rcc_clocks.PCLK1_Frequency;
+ }
+#endif /* UART5 */
+ else
+ {
+ /* Nothing to do, as error code is already assigned to ERROR value */
+ }
+
+ /* Configure the USART Baud Rate :
+ - valid baud rate value (different from 0) is required
+ - Peripheral clock as returned by RCC service, should be valid (different from 0).
+ */
+ if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+ && (USART_InitStruct->BaudRate != 0U))
+ {
+ status = SUCCESS;
+#if defined(USART_CR1_OVER8)
+ LL_USART_SetBaudRate(USARTx,
+ periphclk,
+ USART_InitStruct->OverSampling,
+ USART_InitStruct->BaudRate);
+#else
+ LL_USART_SetBaudRate(USARTx,
+ periphclk,
+ USART_InitStruct->BaudRate);
+#endif /* USART_OverSampling_Feature */
+ }
+ }
+ /* Endif (=> USART not in Disabled state => return ERROR) */
+
+ return (status);
+}
+
+/**
+ * @brief Set each @ref LL_USART_InitTypeDef field to default value.
+ * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+
+void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
+{
+ /* Set USART_InitStruct fields to default values */
+ USART_InitStruct->BaudRate = 9600U;
+ USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
+ USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
+ USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
+ USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
+ USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
+#if defined(USART_CR1_OVER8)
+ USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
+#endif /* USART_OverSampling_Feature */
+}
+
+/**
+ * @brief Initialize USART Clock related settings according to the
+ * specified parameters in the USART_ClockInitStruct.
+ * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
+ * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @param USARTx USART Instance
+ * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * that contains the Clock configuration information for the specified USART peripheral.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
+ * - ERROR: Problem occurred during USART Registers initialization
+ */
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check USART Instance and Clock signal output parameters */
+ assert_param(IS_UART_INSTANCE(USARTx));
+ assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
+
+ /* USART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers */
+ if (LL_USART_IsEnabled(USARTx) == 0U)
+ {
+ /*---------------------------- USART CR2 Configuration -----------------------*/
+ /* If Clock signal has to be output */
+ if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
+ {
+ /* Deactivate Clock signal delivery :
+ * - Disable Clock Output: USART_CR2_CLKEN cleared
+ */
+ LL_USART_DisableSCLKOutput(USARTx);
+ }
+ else
+ {
+ /* Ensure USART instance is USART capable */
+ assert_param(IS_USART_INSTANCE(USARTx));
+
+ /* Check clock related parameters */
+ assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
+ assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
+ assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
+
+ /*---------------------------- USART CR2 Configuration -----------------------
+ * Configure USARTx CR2 (Clock signal related bits) with parameters:
+ * - Enable Clock Output: USART_CR2_CLKEN set
+ * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
+ * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
+ * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
+ */
+ MODIFY_REG(USARTx->CR2,
+ USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
+ USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
+ USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
+ }
+ }
+ /* Else (USART not in Disabled state => return ERROR */
+ else
+ {
+ status = ERROR;
+ }
+
+ return (status);
+}
+
+/**
+ * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
+ * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * whose fields will be set to default values.
+ * @retval None
+ */
+void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+ /* Set LL_USART_ClockInitStruct fields with default values */
+ USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
+ USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
+
+/**
+ * @}
+ */
+
+#endif /* USE_FULL_LL_DRIVER */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_usb.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_usb.c
index 4aee962..2603268 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_usb.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_usb.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_ll_usb.c
* @author MCD Application Team
- * @version V1.0.4
- * @date 29-April-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief USB Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -123,6 +123,9 @@
*/
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(cfg);
+
/* Select FS Embedded PHY */
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
@@ -177,7 +180,7 @@
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
}
- else if ( mode == USB_DEVICE_MODE)
+ else if (mode == USB_DEVICE_MODE)
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
}
@@ -276,7 +279,7 @@
{
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
}
-
+
if (cfg.vbus_sensing_enable == ENABLE)
{
USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
@@ -297,7 +300,7 @@
{
uint32_t count = 0;
- USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6));
+ USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)(num << 6));
do
{
@@ -346,6 +349,9 @@
*/
HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
USBx_DEVICE->DCFG |= speed;
return HAL_OK;
}
@@ -361,7 +367,9 @@
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
{
uint8_t speed = 0;
-
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||
((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
{
@@ -383,6 +391,9 @@
*/
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
if (ep->is_in)
{
/* Assign a Tx FIFO */
@@ -397,7 +408,7 @@
if (ep->is_in == 1)
{
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
-
+
if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
{
USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
@@ -426,6 +437,9 @@
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
/* Read DEPCTLn register */
if (ep->is_in == 1)
{
@@ -451,7 +465,9 @@
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
{
uint16_t pktcnt = 0;
-
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
/* IN endpoint */
if (ep->is_in == 1)
{
@@ -557,6 +573,9 @@
*/
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
/* IN endpoint */
if (ep->is_in == 1)
{
@@ -630,7 +649,9 @@
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
{
uint32_t count32b = 0 , index = 0;
-
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
count32b = (len + 3) / 4;
for (index = 0; index < count32b; index++, src += 4)
{
@@ -651,7 +672,9 @@
{
uint32_t index = 0;
uint32_t count32b = (len + 3) / 4;
-
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
for ( index = 0; index < count32b; index++, dest += 4 )
{
*(__packed uint32_t *)dest = USBx_DFIFO(0);
@@ -668,6 +691,9 @@
*/
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
if (ep->is_in == 1)
{
if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)
@@ -695,6 +721,9 @@
*/
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
if (ep->is_in == 1)
{
USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
@@ -752,6 +781,9 @@
*/
HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(address);
USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD;
@@ -765,6 +797,9 @@
*/
HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
HAL_Delay(3);
@@ -778,6 +813,9 @@
*/
HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
HAL_Delay(3);
@@ -806,6 +844,9 @@
uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
{
uint32_t tmpreg = 0;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
tmpreg = USBx_DEVICE->DAINT;
tmpreg &= USBx_DEVICE->DAINTMSK;
return ((tmpreg & 0xffff0000) >> 16);
@@ -819,6 +860,9 @@
uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
{
uint32_t tmpreg = 0;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
tmpreg = USBx_DEVICE->DAINT;
tmpreg &= USBx_DEVICE->DAINTMSK;
return ((tmpreg & 0xFFFF));
@@ -833,6 +877,9 @@
*/
uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
uint32_t tmpreg = 0;
tmpreg = USBx_OUTEP(epnum)->DOEPINT;
tmpreg &= USBx_DEVICE->DOEPMSK;
@@ -849,7 +896,9 @@
uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
{
uint32_t tmpreg = 0, msk = 0, emp = 0;
-
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
msk = USBx_DEVICE->DIEPMSK;
emp = USBx_DEVICE->DIEPEMPMSK;
msk |= ((emp >> epnum) & 0x1) << 7;
@@ -878,6 +927,9 @@
*/
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
return ((USBx->GINTSTS ) & 0x1);
}
@@ -888,6 +940,8 @@
*/
HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
/* Set the MPS of the IN EP based on the enumeration speed */
USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
@@ -908,6 +962,9 @@
*/
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(psetup);
USBx_OUTEP(0)->DOEPTSIZ = 0;
USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));
USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);
@@ -999,6 +1056,9 @@
*/
HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
@@ -1023,7 +1083,9 @@
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
{
__IO uint32_t hprt0 = 0;
-
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
hprt0 = USBx_HPRT0;
hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
@@ -1046,7 +1108,9 @@
HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
{
__IO uint32_t hprt0 = 0;
-
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
hprt0 = USBx_HPRT0;
hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
@@ -1073,7 +1137,9 @@
uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
{
__IO uint32_t hprt0 = 0;
-
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
hprt0 = USBx_HPRT0;
return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
}
@@ -1085,6 +1151,9 @@
*/
uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
}
@@ -1292,6 +1361,9 @@
*/
uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
return ((USBx_HOST->HAINT) & 0xFFFF);
}
@@ -1305,9 +1377,12 @@
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
{
uint32_t count = 0;
-
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
/* Check for space in the request queue to issue the halt. */
- if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18)))
+ if (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_CTRL) ||
+ (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_BULK)))
{
USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
@@ -1368,7 +1443,9 @@
{
uint8_t num_packets = 1;
uint32_t tmpreg = 0;
-
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+
USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
USB_OTG_HCTSIZ_DOPING;
@@ -1442,6 +1519,8 @@
*/
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
/* active Remote wakeup signalling */
@@ -1457,6 +1536,8 @@
*/
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
/* active Remote wakeup signalling */
USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
return HAL_OK;
@@ -1477,6 +1558,9 @@
*/
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(cfg);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
@@ -1496,7 +1580,7 @@
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
- | USB_CNTR_ESOFM | USB_CNTR_RESETM;
+ | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
/* Set interrupt mask */
USBx->CNTR |= winterruptmask;
@@ -1534,6 +1618,9 @@
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(mode);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
@@ -1550,7 +1637,10 @@
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg)
-{
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(cfg);
+
/* Init Device */
/*CNTR_FRES = 1*/
USBx->CNTR = USB_CNTR_FRES;
@@ -1563,6 +1653,9 @@
/*Set Btable Address*/
USBx->BTABLE = BTABLE_ADDRESS;
+
+ /* Enable USB Device Interrupt mask */
+ USB_EnableGlobalInt(USBx);
return HAL_OK;
}
@@ -1575,8 +1668,11 @@
15 means Flush all Tx FIFOs
* @retval HAL status
*/
-HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num )
+HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(num);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
@@ -1591,6 +1687,8 @@
*/
HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
@@ -1832,6 +1930,11 @@
*/
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(src);
+ UNUSED(ch_ep_num);
+ UNUSED(len);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
@@ -1849,6 +1952,10 @@
*/
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(dest);
+ UNUSED(len);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
@@ -1948,6 +2055,8 @@
*/
HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
@@ -1962,6 +2071,8 @@
*/
HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
@@ -1989,6 +2100,8 @@
*/
uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
@@ -2003,6 +2116,8 @@
*/
uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
@@ -2019,6 +2134,9 @@
*/
uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(epnum);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
@@ -2035,6 +2153,9 @@
*/
uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(epnum);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
@@ -2050,6 +2171,9 @@
*/
void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(interrupt);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
@@ -2064,6 +2188,9 @@
*/
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(USBx);
+ UNUSED(psetup);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
diff --git a/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_utils.c b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_utils.c
new file mode 100644
index 0000000..91e071a
--- /dev/null
+++ b/ext/hal/st/stm32cube/stm32f1xx/drivers/src/stm32f1xx_ll_utils.c
@@ -0,0 +1,623 @@
+/**
+ ******************************************************************************
+ * @file stm32f1xx_ll_utils.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 14-April-2017
+ * @brief UTILS LL module driver.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f1xx_ll_rcc.h"
+#include "stm32f1xx_ll_utils.h"
+#include "stm32f1xx_ll_system.h"
+#ifdef USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif
+
+/** @addtogroup STM32F1xx_LL_Driver
+ * @{
+ */
+
+/** @addtogroup UTILS_LL
+ * @{
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Constants
+ * @{
+ */
+
+/* Defines used for PLL range */
+#define UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY /*!< Frequency max for PLL output, in Hz */
+
+/* Defines used for HSE range */
+#define UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN /*!< Frequency min for HSE frequency, in Hz */
+#define UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX /*!< Frequency max for HSE frequency, in Hz */
+
+/* Defines used for FLASH latency according to HCLK Frequency */
+#if defined(FLASH_ACR_LATENCY)
+#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */
+#define UTILS_LATENCY2_FREQ 48000000U /*!< SYSCLK frequency to set FLASH latency 2 */
+#else
+ /*!< No Latency Configuration in this device */
+#endif
+/**
+ * @}
+ */
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Private_Macros
+ * @{
+ */
+#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
+ || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
+
+#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB1_DIV_16))
+
+#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
+ || ((__VALUE__) == LL_RCC_APB2_DIV_16))
+
+#if defined(RCC_CFGR_PLLMULL6_5)
+#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_4) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_6_5))
+#else
+#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_3) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_10) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_11) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_13) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_14) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_15) \
+ || ((__VALUE__) == LL_RCC_PLL_MUL_16))
+#endif /* RCC_CFGR_PLLMULL6_5 */
+
+#if defined(RCC_CFGR2_PREDIV1)
+#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \
+ ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
+#else
+#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
+#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/
+
+#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
+
+
+#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
+ || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
+
+#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+/**
+ * @}
+ */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
+ * @{
+ */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+#if defined(FLASH_ACR_LATENCY)
+static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
+#endif /* FLASH_ACR_LATENCY */
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+static ErrorStatus UTILS_PLL_IsBusy(void);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UTILS_LL_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup UTILS_LL_EF_DELAY
+ * @{
+ */
+
+/**
+ * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
+ * @note When a RTOS is used, it is recommended to avoid changing the Systick
+ * configuration by calling this function, for a delay use rather osDelay RTOS service.
+ * @param HCLKFrequency HCLK frequency in Hz
+ * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
+ * @retval None
+ */
+void LL_Init1msTick(uint32_t HCLKFrequency)
+{
+ /* Use frequency provided in argument */
+ LL_InitTick(HCLKFrequency, 1000U);
+}
+
+/**
+ * @brief This function provides accurate delay (in milliseconds) based
+ * on SysTick counter flag
+ * @note When a RTOS is used, it is recommended to avoid using blocking delay
+ * and use rather osDelay service.
+ * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
+ * will configure Systick to 1ms
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+void LL_mDelay(uint32_t Delay)
+{
+ __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
+ /* Add this code to indicate that local variable is not used */
+ ((void)tmp);
+
+ /* Add a period to guaranty minimum wait */
+ if (Delay < LL_MAX_DELAY)
+ {
+ Delay++;
+ }
+
+ while (Delay)
+ {
+ if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+ {
+ Delay--;
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_EF_SYSTEM
+ * @brief System Configuration functions
+ *
+ @verbatim
+ ===============================================================================
+ ##### System Configuration functions #####
+ ===============================================================================
+ [..]
+ System, AHB and APB buses clocks configuration
+
+ (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz.
+ @endverbatim
+ @internal
+ Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
+ (++) +-----------------------------------------------+
+ (++) | Latency | SYSCLK clock frequency (MHz) |
+ (++) |---------------|-------------------------------|
+ (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
+ (++) |---------------|-------------------------------|
+ (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
+ (++) |---------------|-------------------------------|
+ (++) |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
+ (++) +-----------------------------------------------+
+ @endinternal
+ * @{
+ */
+
+/**
+ * @brief This function sets directly SystemCoreClock CMSIS variable.
+ * @note Variable can be calculated also through SystemCoreClockUpdate function.
+ * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+ * @retval None
+ */
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
+{
+ /* HCLK clock frequency */
+ SystemCoreClock = HCLKFrequency;
+}
+
+/**
+ * @brief This function configures system clock with HSI as clock source of the PLL
+ * @note The application need to ensure that PLL is disabled.
+ * @note Function is based on the following formula:
+ * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
+ * - PREDIV: Set to 2 for few devices
+ * - PLLMUL: The application software must set correctly the PLL multiplication factor to
+ * not exceed 72MHz
+ * @note FLASH latency can be modified through this function.
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+ LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t pllfreq = 0U;
+
+ /* Check if one of the PLL is enabled */
+ if (UTILS_PLL_IsBusy() == SUCCESS)
+ {
+#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
+ /* Check PREDIV value */
+ assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
+#else
+ /* Force PREDIV value to 2 */
+ UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
+#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
+
+ /* Enable HSI if not enabled */
+ if (LL_RCC_HSI_IsReady() != 1U)
+ {
+ LL_RCC_HSI_Enable();
+ while (LL_RCC_HSI_IsReady() != 1U)
+ {
+ /* Wait for HSI ready */
+ }
+ }
+
+ /* Configure PLL */
+ LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
+
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @brief This function configures system clock with HSE as clock source of the PLL
+ * @note The application need to ensure that PLL is disabled.
+ * @note Function is based on the following formula:
+ * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
+ * - PREDIV: Set to 2 for few devices
+ * - PLLMUL: The application software must set correctly the PLL multiplication factor to
+ * not exceed @ref UTILS_PLL_OUTPUT_MAX
+ * @note FLASH latency can be modified through this function.
+ * @param HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
+ * @param HSEBypass This parameter can be one of the following values:
+ * @arg @ref LL_UTILS_HSEBYPASS_ON
+ * @arg @ref LL_UTILS_HSEBYPASS_OFF
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Max frequency configuration done
+ * - ERROR: Max frequency configuration not done
+ */
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+ LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+ uint32_t pllfreq = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
+ assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
+
+ /* Check if one of the PLL is enabled */
+ if (UTILS_PLL_IsBusy() == SUCCESS)
+ {
+ assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
+
+ /* Calculate the new PLL output frequency */
+ pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
+
+ /* Enable HSE if not enabled */
+ if (LL_RCC_HSE_IsReady() != 1U)
+ {
+ /* Check if need to enable HSE bypass feature or not */
+ if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
+ {
+ LL_RCC_HSE_EnableBypass();
+ }
+ else
+ {
+ LL_RCC_HSE_DisableBypass();
+ }
+
+ /* Enable HSE */
+ LL_RCC_HSE_Enable();
+ while (LL_RCC_HSE_IsReady() != 1U)
+ {
+ /* Wait for HSE ready */
+ }
+ }
+
+ /* Configure PLL */
+ LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
+
+ /* Enable PLL and switch system clock to PLL */
+ status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
+ }
+ else
+ {
+ /* Current PLL configuration cannot be modified */
+ status = ERROR;
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup UTILS_LL_Private_Functions
+ * @{
+ */
+/**
+ * @brief Update number of Flash wait states in line with new frequency and current
+ voltage range.
+ * @param Frequency SYSCLK frequency
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: Latency has been modified
+ * - ERROR: Latency cannot be modified
+ */
+#if defined(FLASH_ACR_LATENCY)
+static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
+{
+ ErrorStatus status = SUCCESS;
+
+ uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
+
+ /* Frequency cannot be equal to 0 */
+ if (Frequency == 0U)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ if (Frequency > UTILS_LATENCY2_FREQ)
+ {
+ /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
+ latency = LL_FLASH_LATENCY_2;
+ }
+ else
+ {
+ if (Frequency > UTILS_LATENCY1_FREQ)
+ {
+ /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
+ latency = LL_FLASH_LATENCY_1;
+ }
+ /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
+ }
+
+ LL_FLASH_SetLatency(latency);
+
+ /* Check that the new number of wait states is taken into account to access the Flash
+ memory by reading the FLASH_ACR register */
+ if (LL_FLASH_GetLatency() != latency)
+ {
+ status = ERROR;
+ }
+ }
+ return status;
+}
+#endif /* FLASH_ACR_LATENCY */
+
+/**
+ * @brief Function to check that PLL can be modified
+ * @param PLL_InputFrequency PLL input frequency (in Hz)
+ * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
+ * the configuration information for the PLL.
+ * @retval PLL output frequency (in Hz)
+ */
+static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
+{
+ uint32_t pllfreq = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
+
+ /* Check different PLL parameters according to RM */
+#if defined (RCC_CFGR2_PREDIV1)
+ pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
+#elif defined(RCC_CFGR2_PREDIV1SRC)
+ pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
+#else
+ pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul);
+#endif /*RCC_CFGR2_PREDIV1SRC*/
+ assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
+
+ return pllfreq;
+}
+
+/**
+ * @brief Function to check that PLL can be modified
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: PLL modification can be done
+ * - ERROR: PLL is busy
+ */
+static ErrorStatus UTILS_PLL_IsBusy(void)
+{
+ ErrorStatus status = SUCCESS;
+
+ /* Check if PLL is busy*/
+ if (LL_RCC_PLL_IsReady() != 0U)
+ {
+ /* PLL configuration cannot be modified */
+ status = ERROR;
+ }
+#if defined(RCC_PLL2_SUPPORT)
+ /* Check if PLL2 is busy*/
+ if (LL_RCC_PLL2_IsReady() != 0U)
+ {
+ /* PLL2 configuration cannot be modified */
+ status = ERROR;
+ }
+#endif /* RCC_PLL2_SUPPORT */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+ /* Check if PLLI2S is busy*/
+ if (LL_RCC_PLLI2S_IsReady() != 0U)
+ {
+ /* PLLI2S configuration cannot be modified */
+ status = ERROR;
+ }
+#endif /* RCC_PLLI2S_SUPPORT */
+
+ return status;
+}
+
+/**
+ * @brief Function to enable PLL and switch system clock to PLL
+ * @param SYSCLK_Frequency SYSCLK frequency
+ * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
+ * the configuration information for the BUS prescalers.
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: No problem to switch system to PLL
+ * - ERROR: Problem to switch system to PLL
+ */
+static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
+{
+ ErrorStatus status = SUCCESS;
+#if defined(FLASH_ACR_LATENCY)
+ uint32_t sysclk_frequency_current = 0U;
+#endif /* FLASH_ACR_LATENCY */
+
+ assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
+ assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
+ assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
+
+#if defined(FLASH_ACR_LATENCY)
+ /* Calculate current SYSCLK frequency */
+ sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_CFGR_HPRE_Pos]);
+#endif /* FLASH_ACR_LATENCY */
+
+ /* Increasing the number of wait states because of higher CPU frequency */
+#if defined (FLASH_ACR_LATENCY)
+ if (sysclk_frequency_current < SYSCLK_Frequency)
+ {
+ /* Set FLASH latency to highest latency */
+ status = UTILS_SetFlashLatency(SYSCLK_Frequency);
+ }
+#endif /* FLASH_ACR_LATENCY */
+
+ /* Update system clock configuration */
+ if (status == SUCCESS)
+ {
+#if defined(RCC_PLL2_SUPPORT)
+ /* Enable PLL2 */
+ LL_RCC_PLL2_Enable();
+ while (LL_RCC_PLL2_IsReady() != 1U)
+ {
+ /* Wait for PLL2 ready */
+ }
+
+#endif /* RCC_PLL2_SUPPORT */
+ /* Enable PLL */
+ LL_RCC_PLL_Enable();
+ while (LL_RCC_PLL_IsReady() != 1U)
+ {
+ /* Wait for PLL ready */
+ }
+
+ /* Sysclk activation on the main PLL */
+ LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+ while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
+ {
+ /* Wait for system clock switch to PLL */
+ }
+
+ /* Set APB1 & APB2 prescaler*/
+ LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
+ LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
+ }
+
+ /* Decreasing the number of wait states because of lower CPU frequency */
+#if defined (FLASH_ACR_LATENCY)
+ if (sysclk_frequency_current > SYSCLK_Frequency)
+ {
+ /* Set FLASH latency to lowest latency */
+ status = UTILS_SetFlashLatency(SYSCLK_Frequency);
+ }
+#endif /* FLASH_ACR_LATENCY */
+
+ /* Update SystemCoreClock variable */
+ if (status == SUCCESS)
+ {
+ LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
+ }
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f100xb.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f100xb.h
index dd0027b..495a164 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f100xb.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f100xb.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f100xb.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
-#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
+ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
@@ -141,7 +141,6 @@
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
} IRQn_Type;
-
/**
* @}
*/
@@ -555,73 +554,73 @@
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */
+#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
-#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
-#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
-#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
+#define CEC_BASE (APB1PERIPH_BASE + 0x00007800U)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000U)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400U)
+#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800U)
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
+#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
-#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
+#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
+#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
@@ -633,52 +632,53 @@
* @{
*/
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define CEC ((CEC_TypeDef *) CEC_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
+#define TIM6 ((TIM_TypeDef *)TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *)TIM7_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
+#define USART2 ((USART_TypeDef *)USART2_BASE)
+#define USART3 ((USART_TypeDef *)USART3_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
+#define BKP ((BKP_TypeDef *)BKP_BASE)
+#define PWR ((PWR_TypeDef *)PWR_BASE)
+#define DAC1 ((DAC_TypeDef *)DAC_BASE)
+#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */
+#define CEC ((CEC_TypeDef *)CEC_BASE)
+#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
+#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
+#define USART1 ((USART_TypeDef *)USART1_BASE)
+#define TIM15 ((TIM_TypeDef *)TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *)TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *)TIM17_BASE)
+#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *)RCC_BASE)
+#define CRC ((CRC_TypeDef *)CRC_BASE)
+#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB ((OB_TypeDef *)OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/**
@@ -749,14 +749,24 @@
#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
+
+/* Legacy defines */
+#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
+#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
+#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
+#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
+#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
+#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
+#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
+#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
@@ -921,9 +931,9 @@
#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
@@ -932,9 +942,9 @@
#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
@@ -945,15 +955,15 @@
#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
@@ -963,11 +973,11 @@
#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
@@ -977,11 +987,11 @@
#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
@@ -990,10 +1000,10 @@
#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
@@ -1012,10 +1022,10 @@
#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+#define RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U /*!< PREDIV1 clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U /*!< PREDIV1 clock divided by 2 for PLL entry */
-#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMULL3_Pos (18U)
#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
@@ -1067,22 +1077,22 @@
#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
/* Reference defines */
- #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
- #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
- #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
- #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
- #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
- #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
- #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
- #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
- #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
/*!<****************** Bit definition for RCC_CIR register ********************/
#define RCC_CIR_LSIRDYF_Pos (0U)
@@ -1381,10 +1391,10 @@
#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@@ -1433,7 +1443,7 @@
#define RCC_CFGR2_PREDIV1_2 (0x4U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */
#define RCC_CFGR2_PREDIV1_3 (0x8U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */
-#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+#define RCC_CFGR2_PREDIV1_DIV1 0x00000000U /*!< PREDIV1 input clock not divided */
#define RCC_CFGR2_PREDIV1_DIV2_Pos (0U)
#define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */
#define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */
@@ -2010,7 +2020,7 @@
#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos (0U)
#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
@@ -2065,7 +2075,7 @@
#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
@@ -2104,7 +2114,7 @@
#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
@@ -2119,7 +2129,7 @@
#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
@@ -2134,7 +2144,7 @@
#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
@@ -2152,7 +2162,7 @@
#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -2177,7 +2187,7 @@
#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
@@ -2204,7 +2214,7 @@
#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
@@ -2225,7 +2235,7 @@
#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
@@ -2246,7 +2256,7 @@
#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
@@ -2267,7 +2277,7 @@
#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
@@ -2302,7 +2312,7 @@
#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
@@ -2323,7 +2333,7 @@
#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
@@ -2344,7 +2354,7 @@
#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
@@ -2365,7 +2375,7 @@
#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
@@ -2400,7 +2410,7 @@
#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
@@ -2421,7 +2431,7 @@
#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
@@ -2442,7 +2452,7 @@
#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
@@ -2463,7 +2473,7 @@
#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
@@ -2498,7 +2508,7 @@
#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
@@ -2519,7 +2529,7 @@
#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
@@ -2540,7 +2550,7 @@
#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
@@ -2561,7 +2571,7 @@
#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
@@ -2605,440 +2615,6 @@
/******************************************************************************/
/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA_Pos (0U)
-#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA_Pos (0U)
-#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND_Pos (0U)
-#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND_Pos (0U)
-#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE_Pos (0U)
-#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos (0U)
-#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos (8U)
-#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos (16U)
-#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos (24U)
-#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos (0U)
-#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos (1U)
-#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos (3U)
-#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos (4U)
-#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos (7U)
-#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos (8U)
-#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos (9U)
-#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos (10U)
-#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos (11U)
-#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos (12U)
-#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
-#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos (15U)
-#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos (16U)
-#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos (17U)
-#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos (18U)
-#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
-#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos (19U)
-#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
-#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos (24U)
-#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos (25U)
-#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS_Pos (0U)
-#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS_Pos (0U)
-#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF_Pos (0U)
-#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
@@ -3098,12 +2674,6 @@
#define EXTI_IMR_MR17_Pos (17U)
#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos (18U)
-#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
-#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos (19U)
-#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -3124,9 +2694,8 @@
#define EXTI_IMR_IM15 EXTI_IMR_MR15
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
-#define EXTI_IMR_IM18 EXTI_IMR_MR18
-#define EXTI_IMR_IM19 EXTI_IMR_MR19
-
+#define EXTI_IMR_IM 0x0003FFFFU /*!< Interrupt Mask All */
+
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0_Pos (0U)
#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
@@ -3182,12 +2751,6 @@
#define EXTI_EMR_MR17_Pos (17U)
#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos (18U)
-#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
-#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos (19U)
-#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -3208,8 +2771,6 @@
#define EXTI_EMR_EM15 EXTI_EMR_MR15
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
-#define EXTI_EMR_EM18 EXTI_EMR_MR18
-#define EXTI_EMR_EM19 EXTI_EMR_MR19
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -3266,12 +2827,6 @@
#define EXTI_RTSR_TR17_Pos (17U)
#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos (18U)
-#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
-#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos (19U)
-#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -3292,8 +2847,6 @@
#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -3350,12 +2903,6 @@
#define EXTI_FTSR_TR17_Pos (17U)
#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos (18U)
-#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
-#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos (19U)
-#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -3376,8 +2923,6 @@
#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -3434,12 +2979,6 @@
#define EXTI_SWIER_SWIER17_Pos (17U)
#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos (18U)
-#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos (19U)
-#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -3460,8 +2999,6 @@
#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -3518,12 +3055,6 @@
#define EXTI_PR_PR17_Pos (17U)
#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos (18U)
-#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
-#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos (19U)
-#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
-#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -3544,8 +3075,6 @@
#define EXTI_PR_PIF15 EXTI_PR_PR15
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
-#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
/******************************************************************************/
/* */
@@ -4648,10 +4177,6 @@
#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-#define TIM_SMCR_OCCS_Pos (3U)
-#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
-#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
-
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
@@ -4996,9 +4521,6 @@
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos (15U)
-#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
-#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT_Pos (0U)
@@ -5102,8 +4624,6 @@
#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-/******************* Bit definition for TIM_OR register ********************/
-
/******************************************************************************/
/* */
/* Real-Time Clock */
@@ -5845,8 +5365,8 @@
#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
@@ -5891,6 +5411,11 @@
#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
+
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
@@ -6071,6 +5596,9 @@
#define USART_CR1_UE_Pos (13U)
#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< USART Oversmapling 8-bits */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_ADD_Pos (0U)
@@ -6139,6 +5667,9 @@
#define USART_CR3_CTSIE_Pos (10U)
#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One Bit method */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC_Pos (0U)
@@ -6452,7 +5983,7 @@
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
@@ -6480,6 +6011,9 @@
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@@ -6500,6 +6034,8 @@
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
@@ -6700,6 +6236,18 @@
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
+
/****************************** END TIM Instances *****************************/
@@ -6757,10 +6305,14 @@
+#define RCC_HSE_MIN 4000000U
+#define RCC_HSE_MAX 26000000U
+
+#define RCC_MAX_FREQUENCY 24000000U
/**
* @}
-*/
+ */
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
@@ -6771,33 +6323,33 @@
/* Aliases for __IRQn */
#define ADC1_2_IRQn ADC1_IRQn
-#define USBWakeUp_IRQn CEC_IRQn
#define OTG_FS_WKUP_IRQn CEC_IRQn
-#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
+#define USBWakeUp_IRQn CEC_IRQn
#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
-#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
-#define TIM10_IRQn TIM1_UP_TIM16_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
+#define TIM10_IRQn TIM1_UP_TIM16_IRQn
+#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
#define TIM6_IRQn TIM6_DAC_IRQn
/* Aliases for __IRQHandler */
#define ADC1_2_IRQHandler ADC1_IRQHandler
-#define USBWakeUp_IRQHandler CEC_IRQHandler
#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
-#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define USBWakeUp_IRQHandler CEC_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
-#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
-#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f100xe.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f100xe.h
index 68012d3..3b87d3a 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f100xe.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f100xe.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f100xe.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
-#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
+ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
@@ -156,7 +156,6 @@
the AFIO_MAPR2 register is set) */
} IRQn_Type;
-
/**
* @}
*/
@@ -621,99 +620,99 @@
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END 0x0807FFFFU /*!< FLASH END address of bank1 */
+#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
-#define FSMC_BASE ((uint32_t)0x60000000) /*!< FSMC base address */
-#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+#define FSMC_BASE 0x60000000U /*!< FSMC base address */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x00001800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x00001C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x00002000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
-#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
-#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
-#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
-#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
-#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
+#define CEC_BASE (APB1PERIPH_BASE + 0x00007800U)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00U)
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x00002000U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000U)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400U)
+#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800U)
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
+#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
-#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
-#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
-#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
-#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
-#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400U)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408U)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CU)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430U)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458U)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
-#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
+#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
+#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
#define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */
#define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */
-#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */
-#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */
-#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */
+#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000U) /*!< FSMC Bank1_2 base address */
+#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000U) /*!< FSMC Bank1_3 base address */
+#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000U) /*!< FSMC Bank1_4 base address */
-#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
-#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x00000000U) /*!< FSMC Bank1 registers base address */
+#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x00000104U) /*!< FSMC Bank1E registers base address */
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
@@ -725,69 +724,70 @@
* @{
*/
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define CEC ((CEC_TypeDef *) CEC_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
-#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *)TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *)TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *)TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *)TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *)TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *)TIM14_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *)SPI3_BASE)
+#define USART2 ((USART_TypeDef *)USART2_BASE)
+#define USART3 ((USART_TypeDef *)USART3_BASE)
+#define UART4 ((USART_TypeDef *)UART4_BASE)
+#define UART5 ((USART_TypeDef *)UART5_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
+#define BKP ((BKP_TypeDef *)BKP_BASE)
+#define PWR ((PWR_TypeDef *)PWR_BASE)
+#define DAC1 ((DAC_TypeDef *)DAC_BASE)
+#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */
+#define CEC ((CEC_TypeDef *)CEC_BASE)
+#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE)
+#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
+#define USART1 ((USART_TypeDef *)USART1_BASE)
+#define TIM15 ((TIM_TypeDef *)TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *)TIM16_BASE)
+#define TIM17 ((TIM_TypeDef *)TIM17_BASE)
+#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *)DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *)RCC_BASE)
+#define CRC ((CRC_TypeDef *)CRC_BASE)
+#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB ((OB_TypeDef *)OB_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/**
@@ -858,14 +858,24 @@
#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
+
+/* Legacy defines */
+#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
+#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
+#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
+#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
+#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
+#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
+#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
+#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
@@ -1190,9 +1200,9 @@
#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
@@ -1201,9 +1211,9 @@
#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
@@ -1214,15 +1224,15 @@
#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
@@ -1232,11 +1242,11 @@
#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
@@ -1246,11 +1256,11 @@
#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
@@ -1259,10 +1269,10 @@
#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
@@ -1281,10 +1291,10 @@
#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+#define RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U /*!< PREDIV1 clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U /*!< PREDIV1 clock divided by 2 for PLL entry */
-#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMULL3_Pos (18U)
#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
@@ -1336,22 +1346,22 @@
#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
/* Reference defines */
- #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
- #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
- #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
- #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
- #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
- #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
- #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
- #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
- #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
+ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
+ #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
+ #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
+ #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
+ #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
+ #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
+ #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
+ #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
+ #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
/*!<****************** Bit definition for RCC_CIR register ********************/
#define RCC_CIR_LSIRDYF_Pos (0U)
@@ -1710,10 +1720,10 @@
#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@@ -1762,7 +1772,7 @@
#define RCC_CFGR2_PREDIV1_2 (0x4U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */
#define RCC_CFGR2_PREDIV1_3 (0x8U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */
-#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+#define RCC_CFGR2_PREDIV1_DIV1 0x00000000U /*!< PREDIV1 input clock not divided */
#define RCC_CFGR2_PREDIV1_DIV2_Pos (0U)
#define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */
#define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */
@@ -2339,7 +2349,7 @@
#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos (0U)
#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
@@ -2394,7 +2404,7 @@
#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
@@ -2433,7 +2443,7 @@
#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
@@ -2448,7 +2458,7 @@
#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
@@ -2463,7 +2473,7 @@
#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
@@ -2481,7 +2491,7 @@
#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -2509,7 +2519,7 @@
#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
@@ -2536,7 +2546,7 @@
#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
@@ -2557,7 +2567,7 @@
#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
@@ -2578,7 +2588,7 @@
#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
@@ -2599,7 +2609,7 @@
#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
@@ -2634,7 +2644,7 @@
#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
@@ -2655,7 +2665,7 @@
#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
@@ -2676,7 +2686,7 @@
#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
@@ -2697,7 +2707,7 @@
#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
@@ -2732,7 +2742,7 @@
#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
@@ -2753,7 +2763,7 @@
#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
@@ -2774,7 +2784,7 @@
#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
@@ -2795,7 +2805,7 @@
#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
@@ -2830,7 +2840,7 @@
#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
@@ -2851,7 +2861,7 @@
#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
@@ -2872,7 +2882,7 @@
#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
@@ -2893,7 +2903,7 @@
#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
@@ -2952,440 +2962,6 @@
/******************************************************************************/
/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA_Pos (0U)
-#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA_Pos (0U)
-#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND_Pos (0U)
-#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND_Pos (0U)
-#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE_Pos (0U)
-#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos (0U)
-#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos (8U)
-#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos (16U)
-#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos (24U)
-#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos (0U)
-#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos (1U)
-#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos (3U)
-#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos (4U)
-#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos (7U)
-#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos (8U)
-#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos (9U)
-#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos (10U)
-#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos (11U)
-#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos (12U)
-#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
-#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos (15U)
-#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos (16U)
-#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos (17U)
-#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos (18U)
-#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
-#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos (19U)
-#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
-#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos (24U)
-#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos (25U)
-#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS_Pos (0U)
-#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS_Pos (0U)
-#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF_Pos (0U)
-#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
@@ -3445,12 +3021,6 @@
#define EXTI_IMR_MR17_Pos (17U)
#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos (18U)
-#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
-#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos (19U)
-#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -3471,9 +3041,8 @@
#define EXTI_IMR_IM15 EXTI_IMR_MR15
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
-#define EXTI_IMR_IM18 EXTI_IMR_MR18
-#define EXTI_IMR_IM19 EXTI_IMR_MR19
-
+#define EXTI_IMR_IM 0x0003FFFFU /*!< Interrupt Mask All */
+
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0_Pos (0U)
#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
@@ -3529,12 +3098,6 @@
#define EXTI_EMR_MR17_Pos (17U)
#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos (18U)
-#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
-#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos (19U)
-#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -3555,8 +3118,6 @@
#define EXTI_EMR_EM15 EXTI_EMR_MR15
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
-#define EXTI_EMR_EM18 EXTI_EMR_MR18
-#define EXTI_EMR_EM19 EXTI_EMR_MR19
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -3613,12 +3174,6 @@
#define EXTI_RTSR_TR17_Pos (17U)
#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos (18U)
-#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
-#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos (19U)
-#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -3639,8 +3194,6 @@
#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -3697,12 +3250,6 @@
#define EXTI_FTSR_TR17_Pos (17U)
#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos (18U)
-#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
-#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos (19U)
-#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -3723,8 +3270,6 @@
#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -3781,12 +3326,6 @@
#define EXTI_SWIER_SWIER17_Pos (17U)
#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos (18U)
-#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos (19U)
-#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -3807,8 +3346,6 @@
#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -3865,12 +3402,6 @@
#define EXTI_PR_PR17_Pos (17U)
#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos (18U)
-#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
-#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos (19U)
-#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
-#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -3891,8 +3422,6 @@
#define EXTI_PR_PIF15 EXTI_PR_PR15
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
-#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
/******************************************************************************/
/* */
@@ -4995,10 +4524,6 @@
#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-#define TIM_SMCR_OCCS_Pos (3U)
-#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
-#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
-
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
@@ -5343,9 +4868,6 @@
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos (15U)
-#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
-#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT_Pos (0U)
@@ -5449,8 +4971,6 @@
#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-/******************* Bit definition for TIM_OR register ********************/
-
/******************************************************************************/
/* */
/* Real-Time Clock */
@@ -6359,8 +5879,8 @@
#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
@@ -6405,6 +5925,11 @@
#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
+
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
@@ -6585,6 +6110,9 @@
#define USART_CR1_UE_Pos (13U)
#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
+#define USART_CR1_OVER8_Pos (15U)
+#define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< USART Oversmapling 8-bits */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_ADD_Pos (0U)
@@ -6653,6 +6181,9 @@
#define USART_CR3_CTSIE_Pos (10U)
#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos (11U)
+#define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One Bit method */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC_Pos (0U)
@@ -6984,7 +6515,7 @@
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
@@ -7019,6 +6550,9 @@
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@@ -7044,6 +6578,8 @@
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
@@ -7289,6 +6825,20 @@
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
+
/****************************** END TIM Instances *****************************/
@@ -7358,10 +6908,14 @@
+#define RCC_HSE_MIN 4000000U
+#define RCC_HSE_MAX 26000000U
+
+#define RCC_MAX_FREQUENCY 24000000U
/**
* @}
-*/
+ */
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
@@ -7372,45 +6926,45 @@
/* Aliases for __IRQn */
#define ADC1_2_IRQn ADC1_IRQn
-#define USBWakeUp_IRQn CEC_IRQn
#define OTG_FS_WKUP_IRQn CEC_IRQn
+#define USBWakeUp_IRQn CEC_IRQn
#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
#define TIM8_BRK_IRQn TIM12_IRQn
#define TIM8_UP_IRQn TIM13_IRQn
#define TIM8_UP_TIM13_IRQn TIM13_IRQn
#define TIM8_TRG_COM_IRQn TIM14_IRQn
#define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn
-#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
#define TIM9_IRQn TIM1_BRK_TIM15_IRQn
+#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn
-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
-#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
#define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
-#define TIM10_IRQn TIM1_UP_TIM16_IRQn
+#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn
#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn
+#define TIM10_IRQn TIM1_UP_TIM16_IRQn
#define TIM6_IRQn TIM6_DAC_IRQn
/* Aliases for __IRQHandler */
#define ADC1_2_IRQHandler ADC1_IRQHandler
-#define USBWakeUp_IRQHandler CEC_IRQHandler
#define OTG_FS_WKUP_IRQHandler CEC_IRQHandler
+#define USBWakeUp_IRQHandler CEC_IRQHandler
#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
#define TIM8_BRK_IRQHandler TIM12_IRQHandler
#define TIM8_UP_IRQHandler TIM13_IRQHandler
#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
#define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler
-#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
+#define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler
-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
-#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
-#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
#define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler
#define TIM6_IRQHandler TIM6_DAC_IRQHandler
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101x6.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101x6.h
index 92b413d..9e279b1 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101x6.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101x6.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f101x6.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
-#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
+ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
@@ -129,7 +129,6 @@
RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
} IRQn_Type;
-
/**
* @}
*/
@@ -507,60 +506,60 @@
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x08007FFF) /*!< FLASH END address of bank1 */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END 0x08007FFFU /*!< FLASH END address of bank1 */
+#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
+#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
+#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
-#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
+#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
+#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
@@ -572,39 +571,39 @@
* @{
*/
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
+#define USART2 ((USART_TypeDef *)USART2_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define BKP ((BKP_TypeDef *)BKP_BASE)
+#define PWR ((PWR_TypeDef *)PWR_BASE)
+#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
+#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
+#define USART1 ((USART_TypeDef *)USART1_BASE)
+#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *)RCC_BASE)
+#define CRC ((CRC_TypeDef *)CRC_BASE)
+#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB ((OB_TypeDef *)OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/**
@@ -675,14 +674,24 @@
#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
+
+/* Legacy defines */
+#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
+#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
+#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
+#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
+#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
+#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
+#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
+#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
@@ -847,9 +856,9 @@
#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
@@ -858,9 +867,9 @@
#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
@@ -871,15 +880,15 @@
#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
@@ -889,11 +898,11 @@
#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
@@ -903,11 +912,11 @@
#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
@@ -916,10 +925,10 @@
#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
@@ -938,10 +947,10 @@
#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
-#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMULL3_Pos (18U)
#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
@@ -993,11 +1002,11 @@
#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
/* Reference defines */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
@@ -1235,10 +1244,10 @@
#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@@ -1808,7 +1817,7 @@
#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos (0U)
#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
@@ -1863,7 +1872,7 @@
#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
@@ -1903,7 +1912,7 @@
#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
@@ -1918,7 +1927,7 @@
#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
@@ -1936,7 +1945,7 @@
#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -1958,7 +1967,7 @@
#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
@@ -1985,7 +1994,7 @@
#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
@@ -2006,7 +2015,7 @@
#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
@@ -2027,7 +2036,7 @@
#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
@@ -2048,7 +2057,7 @@
#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
@@ -2083,7 +2092,7 @@
#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
@@ -2104,7 +2113,7 @@
#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
@@ -2125,7 +2134,7 @@
#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
@@ -2146,7 +2155,7 @@
#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
@@ -2181,7 +2190,7 @@
#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
@@ -2202,7 +2211,7 @@
#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
@@ -2223,7 +2232,7 @@
#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
@@ -2244,7 +2253,7 @@
#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
@@ -2279,7 +2288,7 @@
#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
@@ -2300,7 +2309,7 @@
#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
@@ -2321,7 +2330,7 @@
#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
@@ -2342,7 +2351,7 @@
#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
@@ -2368,440 +2377,6 @@
/******************************************************************************/
/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA_Pos (0U)
-#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA_Pos (0U)
-#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND_Pos (0U)
-#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND_Pos (0U)
-#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE_Pos (0U)
-#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos (0U)
-#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos (8U)
-#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos (16U)
-#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos (24U)
-#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos (0U)
-#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos (1U)
-#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos (3U)
-#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos (4U)
-#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos (7U)
-#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos (8U)
-#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos (9U)
-#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos (10U)
-#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos (11U)
-#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos (12U)
-#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
-#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos (15U)
-#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos (16U)
-#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos (17U)
-#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos (18U)
-#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
-#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos (19U)
-#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
-#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos (24U)
-#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos (25U)
-#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS_Pos (0U)
-#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS_Pos (0U)
-#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF_Pos (0U)
-#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
@@ -2864,9 +2439,6 @@
#define EXTI_IMR_MR18_Pos (18U)
#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos (19U)
-#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -2888,8 +2460,8 @@
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
-#define EXTI_IMR_IM19 EXTI_IMR_MR19
-
+#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
+
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0_Pos (0U)
#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
@@ -2948,9 +2520,6 @@
#define EXTI_EMR_MR18_Pos (18U)
#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos (19U)
-#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -2972,7 +2541,6 @@
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#define EXTI_EMR_EM18 EXTI_EMR_MR18
-#define EXTI_EMR_EM19 EXTI_EMR_MR19
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -3032,9 +2600,6 @@
#define EXTI_RTSR_TR18_Pos (18U)
#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos (19U)
-#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -3056,7 +2621,6 @@
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -3116,9 +2680,6 @@
#define EXTI_FTSR_TR18_Pos (18U)
#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos (19U)
-#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -3140,7 +2701,6 @@
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -3200,9 +2760,6 @@
#define EXTI_SWIER_SWIER18_Pos (18U)
#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos (19U)
-#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -3224,7 +2781,6 @@
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -3284,9 +2840,6 @@
#define EXTI_PR_PR18_Pos (18U)
#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos (19U)
-#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
-#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -3308,7 +2861,6 @@
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
/******************************************************************************/
/* */
@@ -4158,10 +3710,6 @@
#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-#define TIM_SMCR_OCCS_Pos (3U)
-#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
-#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
-
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
@@ -4506,9 +4054,6 @@
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos (15U)
-#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
-#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT_Pos (0U)
@@ -4612,8 +4157,6 @@
#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-/******************* Bit definition for TIM_OR register ********************/
-
/******************************************************************************/
/* */
/* Real-Time Clock */
@@ -5359,8 +4902,8 @@
#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
@@ -5405,6 +4948,11 @@
#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
+
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
@@ -5959,6 +5507,9 @@
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@@ -5971,6 +5522,8 @@
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) 0U
+
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
@@ -6027,7 +5580,7 @@
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
-#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) 0U
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM2) && \
@@ -6042,13 +5595,13 @@
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))))
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) 0U
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) 0U
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
@@ -6062,7 +5615,15 @@
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) 0U
+
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
/****************************** END TIM Instances *****************************/
@@ -6101,7 +5662,7 @@
/***************** UART Instances : DMA mode available **********************/
#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) )
+ ((INSTANCE) == USART2))
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@@ -6112,10 +5673,14 @@
+#define RCC_HSE_MIN 4000000U
+#define RCC_HSE_MAX 16000000U
+
+#define RCC_MAX_FREQUENCY 72000000U
/**
* @}
-*/
+ */
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xb.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xb.h
index 2909876..4e0ddf2 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xb.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xb.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f101xb.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
-#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
+ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
@@ -134,7 +134,6 @@
RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
} IRQn_Type;
-
/**
* @}
*/
@@ -512,65 +511,65 @@
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */
+#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
+#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
-#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
+#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
+#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
@@ -582,44 +581,44 @@
* @{
*/
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
+#define USART2 ((USART_TypeDef *)USART2_BASE)
+#define USART3 ((USART_TypeDef *)USART3_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
+#define BKP ((BKP_TypeDef *)BKP_BASE)
+#define PWR ((PWR_TypeDef *)PWR_BASE)
+#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
+#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
+#define USART1 ((USART_TypeDef *)USART1_BASE)
+#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *)RCC_BASE)
+#define CRC ((CRC_TypeDef *)CRC_BASE)
+#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB ((OB_TypeDef *)OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/**
@@ -690,14 +689,24 @@
#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
+
+/* Legacy defines */
+#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
+#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
+#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
+#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
+#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
+#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
+#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
+#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
@@ -862,9 +871,9 @@
#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
@@ -873,9 +882,9 @@
#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
@@ -886,15 +895,15 @@
#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
@@ -904,11 +913,11 @@
#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
@@ -918,11 +927,11 @@
#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
@@ -931,10 +940,10 @@
#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
@@ -953,10 +962,10 @@
#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
-#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMULL3_Pos (18U)
#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
@@ -1008,11 +1017,11 @@
#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
/* Reference defines */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
@@ -1280,10 +1289,10 @@
#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@@ -1853,7 +1862,7 @@
#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos (0U)
#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
@@ -1908,7 +1917,7 @@
#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
@@ -1947,7 +1956,7 @@
#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
@@ -1962,7 +1971,7 @@
#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
@@ -1977,7 +1986,7 @@
#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
@@ -1995,7 +2004,7 @@
#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -2020,7 +2029,7 @@
#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
@@ -2047,7 +2056,7 @@
#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
@@ -2068,7 +2077,7 @@
#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
@@ -2089,7 +2098,7 @@
#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
@@ -2110,7 +2119,7 @@
#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
@@ -2145,7 +2154,7 @@
#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
@@ -2166,7 +2175,7 @@
#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
@@ -2187,7 +2196,7 @@
#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
@@ -2208,7 +2217,7 @@
#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
@@ -2243,7 +2252,7 @@
#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
@@ -2264,7 +2273,7 @@
#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
@@ -2285,7 +2294,7 @@
#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
@@ -2306,7 +2315,7 @@
#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
@@ -2341,7 +2350,7 @@
#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
@@ -2362,7 +2371,7 @@
#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
@@ -2383,7 +2392,7 @@
#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
@@ -2404,7 +2413,7 @@
#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
@@ -2430,440 +2439,6 @@
/******************************************************************************/
/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA_Pos (0U)
-#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA_Pos (0U)
-#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND_Pos (0U)
-#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND_Pos (0U)
-#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE_Pos (0U)
-#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos (0U)
-#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos (8U)
-#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos (16U)
-#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos (24U)
-#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos (0U)
-#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos (1U)
-#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos (3U)
-#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos (4U)
-#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos (7U)
-#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos (8U)
-#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos (9U)
-#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos (10U)
-#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos (11U)
-#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos (12U)
-#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
-#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos (15U)
-#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos (16U)
-#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos (17U)
-#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos (18U)
-#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
-#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos (19U)
-#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
-#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos (24U)
-#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos (25U)
-#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS_Pos (0U)
-#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS_Pos (0U)
-#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF_Pos (0U)
-#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
@@ -2926,9 +2501,6 @@
#define EXTI_IMR_MR18_Pos (18U)
#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos (19U)
-#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -2950,8 +2522,8 @@
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
-#define EXTI_IMR_IM19 EXTI_IMR_MR19
-
+#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
+
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0_Pos (0U)
#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
@@ -3010,9 +2582,6 @@
#define EXTI_EMR_MR18_Pos (18U)
#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos (19U)
-#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -3034,7 +2603,6 @@
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#define EXTI_EMR_EM18 EXTI_EMR_MR18
-#define EXTI_EMR_EM19 EXTI_EMR_MR19
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -3094,9 +2662,6 @@
#define EXTI_RTSR_TR18_Pos (18U)
#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos (19U)
-#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -3118,7 +2683,6 @@
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -3178,9 +2742,6 @@
#define EXTI_FTSR_TR18_Pos (18U)
#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos (19U)
-#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -3202,7 +2763,6 @@
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -3262,9 +2822,6 @@
#define EXTI_SWIER_SWIER18_Pos (18U)
#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos (19U)
-#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -3286,7 +2843,6 @@
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -3346,9 +2902,6 @@
#define EXTI_PR_PR18_Pos (18U)
#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos (19U)
-#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
-#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -3370,7 +2923,6 @@
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
/******************************************************************************/
/* */
@@ -4220,10 +3772,6 @@
#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-#define TIM_SMCR_OCCS_Pos (3U)
-#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
-#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
-
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
@@ -4568,9 +4116,6 @@
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos (15U)
-#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
-#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT_Pos (0U)
@@ -4674,8 +4219,6 @@
#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-/******************* Bit definition for TIM_OR register ********************/
-
/******************************************************************************/
/* */
/* Real-Time Clock */
@@ -5421,8 +4964,8 @@
#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
@@ -5467,6 +5010,11 @@
#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
+
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
@@ -6053,6 +5601,9 @@
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@@ -6067,6 +5618,8 @@
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) 0U
+
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
@@ -6137,7 +5690,7 @@
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
-#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) 0U
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM2) && \
@@ -6158,14 +5711,14 @@
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))))
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) 0U
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) 0U
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
@@ -6182,7 +5735,17 @@
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) 0U
+
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
/****************************** END TIM Instances *****************************/
@@ -6241,10 +5804,14 @@
+#define RCC_HSE_MIN 4000000U
+#define RCC_HSE_MAX 16000000U
+
+#define RCC_MAX_FREQUENCY 72000000U
/**
* @}
-*/
+ */
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xe.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xe.h
index bc0fdee..f128174 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xe.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xe.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f101xe.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
-#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
+ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
@@ -145,7 +145,6 @@
DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
} IRQn_Type;
-
/**
* @}
*/
@@ -629,96 +628,96 @@
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END 0x0807FFFFU /*!< FLASH END address of bank1 */
+#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
-#define FSMC_BASE ((uint32_t)0x60000000) /*!< FSMC base address */
-#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+#define FSMC_BASE 0x60000000U /*!< FSMC base address */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
-#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
-#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00U)
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x00002000U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
+#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
-#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
-#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
-#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
-#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
-#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400U)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408U)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CU)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430U)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458U)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
-#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
+#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
+#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
#define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */
#define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */
-#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */
-#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */
-#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */
+#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000U) /*!< FSMC Bank1_2 base address */
+#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000U) /*!< FSMC Bank1_3 base address */
+#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000U) /*!< FSMC Bank1_4 base address */
-#define FSMC_BANK2 (FSMC_BASE + 0x10000000) /*!< FSMC Bank2 base address */
-#define FSMC_BANK3 (FSMC_BASE + 0x20000000) /*!< FSMC Bank3 base address */
-#define FSMC_BANK4 (FSMC_BASE + 0x30000000) /*!< FSMC Bank4 base address */
+#define FSMC_BANK2 (FSMC_BASE + 0x10000000U) /*!< FSMC Bank2 base address */
+#define FSMC_BANK3 (FSMC_BASE + 0x20000000U) /*!< FSMC Bank3 base address */
+#define FSMC_BANK4 (FSMC_BASE + 0x30000000U) /*!< FSMC Bank4 base address */
-#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
-#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
-#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2/Bank3 registers base address */
-#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
+#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x00000000U) /*!< FSMC Bank1 registers base address */
+#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x00000104U) /*!< FSMC Bank1E registers base address */
+#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x00000060U) /*!< FSMC Bank2/Bank3 registers base address */
+#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x000000A0U) /*!< FSMC Bank4 registers base address */
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
@@ -730,63 +729,64 @@
* @{
*/
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
-#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
-#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_BANK2_3_R_BASE)
-#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_BANK4_R_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *)TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *)TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *)TIM7_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *)SPI3_BASE)
+#define USART2 ((USART_TypeDef *)USART2_BASE)
+#define USART3 ((USART_TypeDef *)USART3_BASE)
+#define UART4 ((USART_TypeDef *)UART4_BASE)
+#define UART5 ((USART_TypeDef *)UART5_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
+#define BKP ((BKP_TypeDef *)BKP_BASE)
+#define PWR ((PWR_TypeDef *)PWR_BASE)
+#define DAC1 ((DAC_TypeDef *)DAC_BASE)
+#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */
+#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE)
+#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
+#define USART1 ((USART_TypeDef *)USART1_BASE)
+#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *)DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *)RCC_BASE)
+#define CRC ((CRC_TypeDef *)CRC_BASE)
+#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB ((OB_TypeDef *)OB_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)
+#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *)FSMC_BANK2_3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *)FSMC_BANK4_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/**
@@ -857,14 +857,24 @@
#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
+
+/* Legacy defines */
+#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
+#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
+#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
+#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
+#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
+#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
+#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
+#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
@@ -1189,9 +1199,9 @@
#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
@@ -1200,9 +1210,9 @@
#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
@@ -1213,15 +1223,15 @@
#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
@@ -1231,11 +1241,11 @@
#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
@@ -1245,11 +1255,11 @@
#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
@@ -1258,10 +1268,10 @@
#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
@@ -1280,10 +1290,10 @@
#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
-#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMULL3_Pos (18U)
#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
@@ -1335,11 +1345,11 @@
#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
/* Reference defines */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
@@ -1667,10 +1677,10 @@
#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@@ -2240,7 +2250,7 @@
#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos (0U)
#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
@@ -2295,7 +2305,7 @@
#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
@@ -2334,7 +2344,7 @@
#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
@@ -2349,7 +2359,7 @@
#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
@@ -2364,7 +2374,7 @@
#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
@@ -2382,7 +2392,7 @@
#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -2410,7 +2420,7 @@
#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
@@ -2437,7 +2447,7 @@
#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
@@ -2458,7 +2468,7 @@
#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
@@ -2479,7 +2489,7 @@
#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
@@ -2500,7 +2510,7 @@
#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
@@ -2535,7 +2545,7 @@
#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
@@ -2556,7 +2566,7 @@
#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
@@ -2577,7 +2587,7 @@
#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
@@ -2598,7 +2608,7 @@
#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
@@ -2633,7 +2643,7 @@
#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
@@ -2654,7 +2664,7 @@
#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
@@ -2675,7 +2685,7 @@
#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
@@ -2696,7 +2706,7 @@
#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
@@ -2731,7 +2741,7 @@
#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
@@ -2752,7 +2762,7 @@
#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
@@ -2773,7 +2783,7 @@
#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
@@ -2794,7 +2804,7 @@
#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
@@ -2823,440 +2833,6 @@
/******************************************************************************/
/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA_Pos (0U)
-#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA_Pos (0U)
-#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND_Pos (0U)
-#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND_Pos (0U)
-#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE_Pos (0U)
-#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos (0U)
-#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos (8U)
-#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos (16U)
-#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos (24U)
-#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos (0U)
-#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos (1U)
-#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos (3U)
-#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos (4U)
-#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos (7U)
-#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos (8U)
-#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos (9U)
-#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos (10U)
-#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos (11U)
-#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos (12U)
-#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
-#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos (15U)
-#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos (16U)
-#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos (17U)
-#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos (18U)
-#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
-#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos (19U)
-#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
-#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos (24U)
-#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos (25U)
-#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS_Pos (0U)
-#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS_Pos (0U)
-#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF_Pos (0U)
-#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
@@ -3319,9 +2895,6 @@
#define EXTI_IMR_MR18_Pos (18U)
#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos (19U)
-#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -3343,8 +2916,8 @@
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
-#define EXTI_IMR_IM19 EXTI_IMR_MR19
-
+#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
+
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0_Pos (0U)
#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
@@ -3403,9 +2976,6 @@
#define EXTI_EMR_MR18_Pos (18U)
#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos (19U)
-#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -3427,7 +2997,6 @@
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#define EXTI_EMR_EM18 EXTI_EMR_MR18
-#define EXTI_EMR_EM19 EXTI_EMR_MR19
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -3487,9 +3056,6 @@
#define EXTI_RTSR_TR18_Pos (18U)
#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos (19U)
-#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -3511,7 +3077,6 @@
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -3571,9 +3136,6 @@
#define EXTI_FTSR_TR18_Pos (18U)
#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos (19U)
-#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -3595,7 +3157,6 @@
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -3655,9 +3216,6 @@
#define EXTI_SWIER_SWIER18_Pos (18U)
#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos (19U)
-#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -3679,7 +3237,6 @@
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -3739,9 +3296,6 @@
#define EXTI_PR_PR18_Pos (18U)
#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos (19U)
-#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
-#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -3763,7 +3317,6 @@
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
/******************************************************************************/
/* */
@@ -4762,10 +4315,6 @@
#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-#define TIM_SMCR_OCCS_Pos (3U)
-#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
-#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
-
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
@@ -5110,9 +4659,6 @@
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos (15U)
-#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
-#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT_Pos (0U)
@@ -5216,8 +4762,6 @@
#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-/******************* Bit definition for TIM_OR register ********************/
-
/******************************************************************************/
/* */
/* Real-Time Clock */
@@ -5640,14 +5184,14 @@
#define FSMC_PMEMx_MEMWAITx_Pos (8U)
#define FSMC_PMEMx_MEMWAITx_Msk (0xFFU << FSMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */
#define FSMC_PMEMx_MEMWAITx FSMC_PMEMx_MEMWAITx_Msk /*!< MEMWAITx[7:0] bits (Common memory x wait time) */
-#define FSMC_PMEMx_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) /*!< Bit 4 */
-#define FSMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) /*!< Bit 5 */
-#define FSMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) /*!< Bit 6 */
-#define FSMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+#define FSMC_PMEMx_MEMWAIT2_0 0x00000100U /*!< Bit 0 */
+#define FSMC_PMEMx_MEMWAITx_1 0x00000200U /*!< Bit 1 */
+#define FSMC_PMEMx_MEMWAITx_2 0x00000400U /*!< Bit 2 */
+#define FSMC_PMEMx_MEMWAITx_3 0x00000800U /*!< Bit 3 */
+#define FSMC_PMEMx_MEMWAITx_4 0x00001000U /*!< Bit 4 */
+#define FSMC_PMEMx_MEMWAITx_5 0x00002000U /*!< Bit 5 */
+#define FSMC_PMEMx_MEMWAITx_6 0x00004000U /*!< Bit 6 */
+#define FSMC_PMEMx_MEMWAITx_7 0x00008000U /*!< Bit 7 */
#define FSMC_PMEMx_MEMHOLDx_Pos (16U)
#define FSMC_PMEMx_MEMHOLDx_Msk (0xFFU << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */
@@ -6345,8 +5889,8 @@
#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
@@ -6391,6 +5935,11 @@
#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
+
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
@@ -6971,7 +6520,7 @@
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
@@ -7006,6 +6555,9 @@
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@@ -7024,6 +6576,8 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7))
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) 0U
+
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
@@ -7110,7 +6664,7 @@
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
-#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) 0U
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM2) && \
@@ -7137,7 +6691,7 @@
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))))
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) 0U
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
@@ -7145,7 +6699,7 @@
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) 0U
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
@@ -7167,7 +6721,19 @@
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) 0U
+
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
/****************************** END TIM Instances *****************************/
@@ -7237,10 +6803,14 @@
+#define RCC_HSE_MIN 4000000U
+#define RCC_HSE_MAX 16000000U
+
+#define RCC_MAX_FREQUENCY 72000000U
/**
* @}
-*/
+ */
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xg.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xg.h
index 768a002..d434eb0 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xg.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f101xg.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f101xg.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
- #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
-#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
+ #define __MPU_PRESENT 1U /*!< STM32 XL-density devices provide an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
@@ -116,7 +116,7 @@
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM9_IRQn = 24, /*!< TIM9 global Interrupt */
TIM10_IRQn = 25, /*!< TIM10 global Interrupt */
@@ -151,7 +151,6 @@
DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
} IRQn_Type;
-
/**
* @}
*/
@@ -641,104 +640,103 @@
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */
-#define FLASH_BANK2_END ((uint32_t)0x080FFFFF) /*!< FLASH END address of bank2 */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END 0x0807FFFFU /*!< FLASH END address of bank1 */
+#define FLASH_BANK2_END 0x080FFFFFU /*!< FLASH END address of bank2 */
+#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
-#define FSMC_BASE ((uint32_t)0x60000000) /*!< FSMC base address */
-#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+#define FSMC_BASE 0x60000000U /*!< FSMC base address */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x00001800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x00001C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x00002000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
-#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
-#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
-#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
-#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
-#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
+#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00U)
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x00002000U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x00004C00U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x00005000U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x00005400U)
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
+#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
-#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
-#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
-#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
-#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
-#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400U)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408U)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CU)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430U)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458U)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
-#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
+#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
+#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
#define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */
#define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */
-#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */
-#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */
-#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */
+#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000U) /*!< FSMC Bank1_2 base address */
+#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000U) /*!< FSMC Bank1_3 base address */
+#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000U) /*!< FSMC Bank1_4 base address */
-#define FSMC_BANK2 (FSMC_BASE + 0x10000000) /*!< FSMC Bank2 base address */
-#define FSMC_BANK3 (FSMC_BASE + 0x20000000) /*!< FSMC Bank3 base address */
-#define FSMC_BANK4 (FSMC_BASE + 0x30000000) /*!< FSMC Bank4 base address */
+#define FSMC_BANK2 (FSMC_BASE + 0x10000000U) /*!< FSMC Bank2 base address */
+#define FSMC_BANK3 (FSMC_BASE + 0x20000000U) /*!< FSMC Bank3 base address */
+#define FSMC_BANK4 (FSMC_BASE + 0x30000000U) /*!< FSMC Bank4 base address */
-#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
-#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
-#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2/Bank3 registers base address */
-#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
+#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x00000000U) /*!< FSMC Bank1 registers base address */
+#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x00000104U) /*!< FSMC Bank1E registers base address */
+#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x00000060U) /*!< FSMC Bank2/Bank3 registers base address */
+#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x000000A0U) /*!< FSMC Bank4 registers base address */
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
@@ -750,70 +748,70 @@
* @{
*/
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
-#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
-#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_BANK2_3_R_BASE)
-#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_BANK4_R_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *)TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *)TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *)TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *)TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *)TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *)TIM14_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *)SPI3_BASE)
+#define USART2 ((USART_TypeDef *)USART2_BASE)
+#define USART3 ((USART_TypeDef *)USART3_BASE)
+#define UART4 ((USART_TypeDef *)UART4_BASE)
+#define UART5 ((USART_TypeDef *)UART5_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
+#define BKP ((BKP_TypeDef *)BKP_BASE)
+#define PWR ((PWR_TypeDef *)PWR_BASE)
+#define DAC1 ((DAC_TypeDef *)DAC_BASE)
+#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */
+#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE)
+#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
+#define USART1 ((USART_TypeDef *)USART1_BASE)
+#define TIM9 ((TIM_TypeDef *)TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *)TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *)TIM11_BASE)
+#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *)DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *)RCC_BASE)
+#define CRC ((CRC_TypeDef *)CRC_BASE)
+#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB ((OB_TypeDef *)OB_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)
+#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *)FSMC_BANK2_3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *)FSMC_BANK4_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/**
@@ -884,14 +882,24 @@
#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
+
+/* Legacy defines */
+#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
+#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
+#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
+#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
+#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
+#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
+#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
+#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
@@ -1216,9 +1224,9 @@
#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
@@ -1227,9 +1235,9 @@
#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
@@ -1240,15 +1248,15 @@
#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
@@ -1258,11 +1266,11 @@
#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
@@ -1272,11 +1280,11 @@
#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
@@ -1285,10 +1293,10 @@
#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
@@ -1307,10 +1315,10 @@
#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
-#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMULL3_Pos (18U)
#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
@@ -1362,11 +1370,11 @@
#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
/* Reference defines */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
@@ -1453,9 +1461,6 @@
#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
-#define RCC_APB2RSTR_ADC2RST_Pos (10U)
-#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
-#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
#define RCC_APB2RSTR_TIM1RST_Pos (11U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
@@ -1607,9 +1612,6 @@
#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
-#define RCC_APB2ENR_ADC2EN_Pos (10U)
-#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
-#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
#define RCC_APB2ENR_TIM1EN_Pos (11U)
#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
@@ -1736,10 +1738,10 @@
#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@@ -2309,7 +2311,7 @@
#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos (0U)
#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
@@ -2364,7 +2366,7 @@
#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
@@ -2403,7 +2405,7 @@
#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
@@ -2418,7 +2420,7 @@
#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
@@ -2433,7 +2435,7 @@
#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
@@ -2451,7 +2453,7 @@
#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -2479,7 +2481,7 @@
#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
@@ -2506,7 +2508,7 @@
#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
@@ -2527,7 +2529,7 @@
#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
@@ -2548,7 +2550,7 @@
#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
@@ -2569,7 +2571,7 @@
#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
@@ -2604,7 +2606,7 @@
#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
@@ -2625,7 +2627,7 @@
#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
@@ -2646,7 +2648,7 @@
#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
@@ -2667,7 +2669,7 @@
#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
@@ -2702,7 +2704,7 @@
#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
@@ -2723,7 +2725,7 @@
#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
@@ -2744,7 +2746,7 @@
#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
@@ -2765,7 +2767,7 @@
#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
@@ -2800,7 +2802,7 @@
#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
@@ -2821,7 +2823,7 @@
#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
@@ -2842,7 +2844,7 @@
#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
@@ -2863,7 +2865,7 @@
#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
@@ -2907,440 +2909,6 @@
/******************************************************************************/
/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA_Pos (0U)
-#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA_Pos (0U)
-#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND_Pos (0U)
-#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND_Pos (0U)
-#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE_Pos (0U)
-#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos (0U)
-#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos (8U)
-#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos (16U)
-#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos (24U)
-#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos (0U)
-#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos (1U)
-#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos (3U)
-#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos (4U)
-#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos (7U)
-#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos (8U)
-#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos (9U)
-#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos (10U)
-#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos (11U)
-#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos (12U)
-#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
-#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos (15U)
-#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos (16U)
-#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos (17U)
-#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos (18U)
-#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
-#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos (19U)
-#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
-#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos (24U)
-#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos (25U)
-#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS_Pos (0U)
-#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS_Pos (0U)
-#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF_Pos (0U)
-#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
@@ -3403,9 +2971,6 @@
#define EXTI_IMR_MR18_Pos (18U)
#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos (19U)
-#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -3427,8 +2992,8 @@
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
-#define EXTI_IMR_IM19 EXTI_IMR_MR19
-
+#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
+
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0_Pos (0U)
#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
@@ -3487,9 +3052,6 @@
#define EXTI_EMR_MR18_Pos (18U)
#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos (19U)
-#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -3511,7 +3073,6 @@
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#define EXTI_EMR_EM18 EXTI_EMR_MR18
-#define EXTI_EMR_EM19 EXTI_EMR_MR19
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -3571,9 +3132,6 @@
#define EXTI_RTSR_TR18_Pos (18U)
#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos (19U)
-#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -3595,7 +3153,6 @@
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -3655,9 +3212,6 @@
#define EXTI_FTSR_TR18_Pos (18U)
#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos (19U)
-#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -3679,7 +3233,6 @@
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -3739,9 +3292,6 @@
#define EXTI_SWIER_SWIER18_Pos (18U)
#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos (19U)
-#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -3763,7 +3313,6 @@
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -3823,9 +3372,6 @@
#define EXTI_PR_PR18_Pos (18U)
#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos (19U)
-#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
-#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -3847,7 +3393,6 @@
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
/******************************************************************************/
/* */
@@ -4099,7 +3644,6 @@
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
*/
-#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
/******************** Bit definition for ADC_SR register ********************/
#define ADC_SR_AWD_Pos (0U)
@@ -4164,14 +3708,6 @@
#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
-#define ADC_CR1_DUALMOD_Pos (16U)
-#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
-#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
-#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
-#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
-#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
-#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
-
#define ADC_CR1_JAWDEN_Pos (22U)
#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
@@ -4614,9 +4150,6 @@
#define ADC_DR_DATA_Pos (0U)
#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
-#define ADC_DR_ADC2DATA_Pos (16U)
-#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
-#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
/******************************************************************************/
/* */
/* Digital to Analog Converter */
@@ -4857,10 +4390,6 @@
#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-#define TIM_SMCR_OCCS_Pos (3U)
-#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
-#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
-
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
@@ -5205,9 +4734,6 @@
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos (15U)
-#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
-#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT_Pos (0U)
@@ -5311,8 +4837,6 @@
#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-/******************* Bit definition for TIM_OR register ********************/
-
/******************************************************************************/
/* */
/* Real-Time Clock */
@@ -5735,14 +5259,14 @@
#define FSMC_PMEMx_MEMWAITx_Pos (8U)
#define FSMC_PMEMx_MEMWAITx_Msk (0xFFU << FSMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */
#define FSMC_PMEMx_MEMWAITx FSMC_PMEMx_MEMWAITx_Msk /*!< MEMWAITx[7:0] bits (Common memory x wait time) */
-#define FSMC_PMEMx_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) /*!< Bit 4 */
-#define FSMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) /*!< Bit 5 */
-#define FSMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) /*!< Bit 6 */
-#define FSMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+#define FSMC_PMEMx_MEMWAIT2_0 0x00000100U /*!< Bit 0 */
+#define FSMC_PMEMx_MEMWAITx_1 0x00000200U /*!< Bit 1 */
+#define FSMC_PMEMx_MEMWAITx_2 0x00000400U /*!< Bit 2 */
+#define FSMC_PMEMx_MEMWAITx_3 0x00000800U /*!< Bit 3 */
+#define FSMC_PMEMx_MEMWAITx_4 0x00001000U /*!< Bit 4 */
+#define FSMC_PMEMx_MEMWAITx_5 0x00002000U /*!< Bit 5 */
+#define FSMC_PMEMx_MEMWAITx_6 0x00004000U /*!< Bit 6 */
+#define FSMC_PMEMx_MEMWAITx_7 0x00008000U /*!< Bit 7 */
#define FSMC_PMEMx_MEMHOLDx_Pos (16U)
#define FSMC_PMEMx_MEMHOLDx_Msk (0xFFU << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */
@@ -6440,8 +5964,8 @@
#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
@@ -6486,6 +6010,11 @@
#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
+
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
@@ -7115,12 +6644,9 @@
*/
/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
- ((INSTANCE) == ADC2))
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
-
-#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
@@ -7128,7 +6654,7 @@
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
@@ -7163,6 +6689,9 @@
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@@ -7187,6 +6716,8 @@
((INSTANCE) == TIM13) || \
((INSTANCE) == TIM14))
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) 0U
+
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
@@ -7287,7 +6818,7 @@
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
-#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) 0U
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM2) && \
@@ -7334,7 +6865,7 @@
(((INSTANCE) == TIM14) && \
(((CHANNEL) == TIM_CHANNEL_1))))
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) 0U
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
@@ -7342,7 +6873,7 @@
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) 0U
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
@@ -7370,7 +6901,19 @@
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5))
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) 0U
+
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
/****************************** END TIM Instances *****************************/
@@ -7440,10 +6983,14 @@
+#define RCC_HSE_MIN 4000000U
+#define RCC_HSE_MAX 16000000U
+
+#define RCC_MAX_FREQUENCY 72000000U
/**
* @}
-*/
+ */
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
@@ -7453,20 +7000,20 @@
/******************************************************************************/
/* Aliases for __IRQn */
-#define ADC1_IRQn ADC1_2_IRQn
+#define ADC1_2_IRQn ADC1_IRQn
#define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn
+#define TIM1_UP_TIM10_IRQn TIM10_IRQn
#define TIM1_UP_TIM16_IRQn TIM10_IRQn
#define TIM1_UP_IRQn TIM10_IRQn
-#define TIM1_UP_TIM10_IRQn TIM10_IRQn
+#define TIM1_TRG_COM_IRQn TIM11_IRQn
#define TIM1_TRG_COM_TIM11_IRQn TIM11_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM11_IRQn
-#define TIM1_TRG_COM_IRQn TIM11_IRQn
-#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
#define TIM8_BRK_IRQn TIM12_IRQn
-#define TIM8_UP_IRQn TIM13_IRQn
+#define TIM8_BRK_TIM12_IRQn TIM12_IRQn
#define TIM8_UP_TIM13_IRQn TIM13_IRQn
-#define TIM8_TRG_COM_IRQn TIM14_IRQn
+#define TIM8_UP_IRQn TIM13_IRQn
#define TIM8_TRG_COM_TIM14_IRQn TIM14_IRQn
+#define TIM8_TRG_COM_IRQn TIM14_IRQn
#define TIM6_DAC_IRQn TIM6_IRQn
#define TIM1_BRK_TIM15_IRQn TIM9_IRQn
#define TIM1_BRK_IRQn TIM9_IRQn
@@ -7474,20 +7021,20 @@
/* Aliases for __IRQHandler */
-#define ADC1_IRQHandler ADC1_2_IRQHandler
+#define ADC1_2_IRQHandler ADC1_IRQHandler
#define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler
+#define TIM1_UP_TIM10_IRQHandler TIM10_IRQHandler
#define TIM1_UP_TIM16_IRQHandler TIM10_IRQHandler
#define TIM1_UP_IRQHandler TIM10_IRQHandler
-#define TIM1_UP_TIM10_IRQHandler TIM10_IRQHandler
+#define TIM1_TRG_COM_IRQHandler TIM11_IRQHandler
#define TIM1_TRG_COM_TIM11_IRQHandler TIM11_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM11_IRQHandler
-#define TIM1_TRG_COM_IRQHandler TIM11_IRQHandler
-#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
#define TIM8_BRK_IRQHandler TIM12_IRQHandler
-#define TIM8_UP_IRQHandler TIM13_IRQHandler
+#define TIM8_BRK_TIM12_IRQHandler TIM12_IRQHandler
#define TIM8_UP_TIM13_IRQHandler TIM13_IRQHandler
-#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
+#define TIM8_UP_IRQHandler TIM13_IRQHandler
#define TIM8_TRG_COM_TIM14_IRQHandler TIM14_IRQHandler
+#define TIM8_TRG_COM_IRQHandler TIM14_IRQHandler
#define TIM6_DAC_IRQHandler TIM6_IRQHandler
#define TIM1_BRK_TIM15_IRQHandler TIM9_IRQHandler
#define TIM1_BRK_IRQHandler TIM9_IRQHandler
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f102x6.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f102x6.h
index 4fb02af..67202c7 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f102x6.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f102x6.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f102x6.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
-#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
+ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
@@ -132,7 +132,6 @@
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
} IRQn_Type;
-
/**
* @}
*/
@@ -543,64 +542,64 @@
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x08007FFF) /*!< FLASH END address of bank1 */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END 0x08007FFFU /*!< FLASH END address of bank1 */
+#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
+#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
+#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
-#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
+#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
+#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
/* USB device FS */
-#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
/**
@@ -611,40 +610,40 @@
* @{
*/
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define USB ((USB_TypeDef *) USB_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
+#define USART2 ((USART_TypeDef *)USART2_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define USB ((USB_TypeDef *)USB_BASE)
+#define BKP ((BKP_TypeDef *)BKP_BASE)
+#define PWR ((PWR_TypeDef *)PWR_BASE)
+#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
+#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
+#define USART1 ((USART_TypeDef *)USART1_BASE)
+#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *)RCC_BASE)
+#define CRC ((CRC_TypeDef *)CRC_BASE)
+#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB ((OB_TypeDef *)OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/**
@@ -715,14 +714,24 @@
#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
+
+/* Legacy defines */
+#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
+#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
+#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
+#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
+#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
+#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
+#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
+#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
@@ -887,9 +896,9 @@
#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
@@ -898,9 +907,9 @@
#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
@@ -911,15 +920,15 @@
#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
@@ -929,11 +938,11 @@
#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
@@ -943,11 +952,11 @@
#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
@@ -956,10 +965,10 @@
#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
@@ -978,10 +987,10 @@
#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
-#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMULL3_Pos (18U)
#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
@@ -1036,11 +1045,11 @@
#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
/* Reference defines */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
@@ -1284,10 +1293,10 @@
#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@@ -1857,7 +1866,7 @@
#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos (0U)
#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
@@ -1912,7 +1921,7 @@
#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
@@ -1952,7 +1961,7 @@
#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
@@ -1967,7 +1976,7 @@
#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
@@ -1985,7 +1994,7 @@
#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -2007,7 +2016,7 @@
#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
@@ -2034,7 +2043,7 @@
#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
@@ -2055,7 +2064,7 @@
#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
@@ -2076,7 +2085,7 @@
#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
@@ -2097,7 +2106,7 @@
#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
@@ -2132,7 +2141,7 @@
#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
@@ -2153,7 +2162,7 @@
#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
@@ -2174,7 +2183,7 @@
#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
@@ -2195,7 +2204,7 @@
#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
@@ -2230,7 +2239,7 @@
#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
@@ -2251,7 +2260,7 @@
#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
@@ -2272,7 +2281,7 @@
#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
@@ -2293,7 +2302,7 @@
#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
@@ -2328,7 +2337,7 @@
#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
@@ -2349,7 +2358,7 @@
#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
@@ -2370,7 +2379,7 @@
#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
@@ -2391,7 +2400,7 @@
#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
@@ -2417,440 +2426,6 @@
/******************************************************************************/
/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA_Pos (0U)
-#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA_Pos (0U)
-#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND_Pos (0U)
-#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND_Pos (0U)
-#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE_Pos (0U)
-#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos (0U)
-#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos (8U)
-#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos (16U)
-#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos (24U)
-#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos (0U)
-#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos (1U)
-#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos (3U)
-#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos (4U)
-#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos (7U)
-#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos (8U)
-#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos (9U)
-#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos (10U)
-#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos (11U)
-#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos (12U)
-#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
-#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos (15U)
-#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos (16U)
-#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos (17U)
-#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos (18U)
-#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
-#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos (19U)
-#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
-#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos (24U)
-#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos (25U)
-#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS_Pos (0U)
-#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS_Pos (0U)
-#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF_Pos (0U)
-#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
@@ -2913,9 +2488,6 @@
#define EXTI_IMR_MR18_Pos (18U)
#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos (19U)
-#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -2937,8 +2509,8 @@
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
-#define EXTI_IMR_IM19 EXTI_IMR_MR19
-
+#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
+
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0_Pos (0U)
#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
@@ -2997,9 +2569,6 @@
#define EXTI_EMR_MR18_Pos (18U)
#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos (19U)
-#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -3021,7 +2590,6 @@
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#define EXTI_EMR_EM18 EXTI_EMR_MR18
-#define EXTI_EMR_EM19 EXTI_EMR_MR19
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -3081,9 +2649,6 @@
#define EXTI_RTSR_TR18_Pos (18U)
#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos (19U)
-#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -3105,7 +2670,6 @@
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -3165,9 +2729,6 @@
#define EXTI_FTSR_TR18_Pos (18U)
#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos (19U)
-#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -3189,7 +2750,6 @@
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -3249,9 +2809,6 @@
#define EXTI_SWIER_SWIER18_Pos (18U)
#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos (19U)
-#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -3273,7 +2830,6 @@
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -3333,9 +2889,6 @@
#define EXTI_PR_PR18_Pos (18U)
#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos (19U)
-#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
-#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -3357,7 +2910,6 @@
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
/******************************************************************************/
/* */
@@ -4207,10 +3759,6 @@
#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-#define TIM_SMCR_OCCS_Pos (3U)
-#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
-#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
-
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
@@ -4555,9 +4103,6 @@
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos (15U)
-#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
-#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT_Pos (0U)
@@ -4661,8 +4206,6 @@
#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-/******************* Bit definition for TIM_OR register ********************/
-
/******************************************************************************/
/* */
/* Real-Time Clock */
@@ -5255,28 +4798,28 @@
#define USB_EP_TYPE_MASK_Pos (9U)
#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
-#define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
-
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
- /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */
+#define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
- /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************* Bit definition for USB_EP0R register *******************/
@@ -5843,52 +5386,52 @@
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+#define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+#define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+#define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+#define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+#define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+#define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+#define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+#define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+#define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+#define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+#define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+#define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+#define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+#define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+#define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+#define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */
/*----------------------------------------------------------------------------*/
@@ -6081,196 +5624,196 @@
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/******************************************************************************/
@@ -6478,8 +6021,8 @@
#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
@@ -6524,6 +6067,11 @@
#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
+
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
@@ -7078,6 +6626,9 @@
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@@ -7090,6 +6641,8 @@
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) 0U
+
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
@@ -7146,7 +6699,7 @@
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
-#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) 0U
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM2) && \
@@ -7161,13 +6714,13 @@
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))))
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) 0U
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) 0U
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
@@ -7181,7 +6734,15 @@
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) 0U
+
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
/****************************** END TIM Instances *****************************/
@@ -7220,7 +6781,7 @@
/***************** UART Instances : DMA mode available **********************/
#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) )
+ ((INSTANCE) == USART2))
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@@ -7233,10 +6794,14 @@
+#define RCC_HSE_MIN 4000000U
+#define RCC_HSE_MAX 16000000U
+
+#define RCC_MAX_FREQUENCY 72000000U
/**
* @}
-*/
+ */
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
@@ -7247,22 +6812,22 @@
/* Aliases for __IRQn */
#define ADC1_2_IRQn ADC1_IRQn
-#define CEC_IRQn USBWakeUp_IRQn
#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
-#define USB_HP_CAN1_TX_IRQn USB_HP_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
#define CAN1_TX_IRQn USB_HP_IRQn
-#define USB_LP_CAN1_RX0_IRQn USB_LP_IRQn
+#define USB_HP_CAN1_TX_IRQn USB_HP_IRQn
#define CAN1_RX0_IRQn USB_LP_IRQn
+#define USB_LP_CAN1_RX0_IRQn USB_LP_IRQn
/* Aliases for __IRQHandler */
#define ADC1_2_IRQHandler ADC1_IRQHandler
-#define CEC_IRQHandler USBWakeUp_IRQHandler
#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
-#define USB_HP_CAN1_TX_IRQHandler USB_HP_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
#define CAN1_TX_IRQHandler USB_HP_IRQHandler
-#define USB_LP_CAN1_RX0_IRQHandler USB_LP_IRQHandler
+#define USB_HP_CAN1_TX_IRQHandler USB_HP_IRQHandler
#define CAN1_RX0_IRQHandler USB_LP_IRQHandler
+#define USB_LP_CAN1_RX0_IRQHandler USB_LP_IRQHandler
/**
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f102xb.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f102xb.h
index 63a3945..75ccf6c 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f102xb.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f102xb.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f102xb.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
-#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
+ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
@@ -137,7 +137,6 @@
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
} IRQn_Type;
-
/**
* @}
*/
@@ -548,68 +547,68 @@
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */
+#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
+#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
-#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
+#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
+#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
/* USB device FS */
-#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
/**
@@ -620,44 +619,44 @@
* @{
*/
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define USB ((USB_TypeDef *) USB_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
+#define USART2 ((USART_TypeDef *)USART2_BASE)
+#define USART3 ((USART_TypeDef *)USART3_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
+#define USB ((USB_TypeDef *)USB_BASE)
+#define BKP ((BKP_TypeDef *)BKP_BASE)
+#define PWR ((PWR_TypeDef *)PWR_BASE)
+#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
+#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
+#define USART1 ((USART_TypeDef *)USART1_BASE)
+#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *)RCC_BASE)
+#define CRC ((CRC_TypeDef *)CRC_BASE)
+#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB ((OB_TypeDef *)OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/**
@@ -728,14 +727,24 @@
#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
+
+/* Legacy defines */
+#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
+#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
+#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
+#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
+#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
+#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
+#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
+#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
@@ -900,9 +909,9 @@
#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
@@ -911,9 +920,9 @@
#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
@@ -924,15 +933,15 @@
#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
@@ -942,11 +951,11 @@
#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
@@ -956,11 +965,11 @@
#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
@@ -969,10 +978,10 @@
#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
@@ -991,10 +1000,10 @@
#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
-#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMULL3_Pos (18U)
#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
@@ -1049,11 +1058,11 @@
#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
/* Reference defines */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
@@ -1321,10 +1330,10 @@
#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@@ -1894,7 +1903,7 @@
#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos (0U)
#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
@@ -1949,7 +1958,7 @@
#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
@@ -1988,7 +1997,7 @@
#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
@@ -2003,7 +2012,7 @@
#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
@@ -2018,7 +2027,7 @@
#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
@@ -2036,7 +2045,7 @@
#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -2061,7 +2070,7 @@
#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
@@ -2088,7 +2097,7 @@
#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
@@ -2109,7 +2118,7 @@
#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
@@ -2130,7 +2139,7 @@
#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
@@ -2151,7 +2160,7 @@
#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
@@ -2186,7 +2195,7 @@
#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
@@ -2207,7 +2216,7 @@
#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
@@ -2228,7 +2237,7 @@
#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
@@ -2249,7 +2258,7 @@
#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
@@ -2284,7 +2293,7 @@
#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
@@ -2305,7 +2314,7 @@
#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
@@ -2326,7 +2335,7 @@
#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
@@ -2347,7 +2356,7 @@
#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
@@ -2382,7 +2391,7 @@
#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
@@ -2403,7 +2412,7 @@
#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
@@ -2424,7 +2433,7 @@
#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
@@ -2445,7 +2454,7 @@
#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
@@ -2471,440 +2480,6 @@
/******************************************************************************/
/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA_Pos (0U)
-#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA_Pos (0U)
-#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND_Pos (0U)
-#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND_Pos (0U)
-#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE_Pos (0U)
-#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos (0U)
-#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos (8U)
-#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos (16U)
-#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos (24U)
-#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos (0U)
-#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos (1U)
-#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos (3U)
-#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos (4U)
-#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos (7U)
-#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos (8U)
-#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos (9U)
-#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos (10U)
-#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos (11U)
-#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos (12U)
-#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
-#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos (15U)
-#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos (16U)
-#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos (17U)
-#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos (18U)
-#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
-#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos (19U)
-#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
-#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos (24U)
-#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos (25U)
-#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS_Pos (0U)
-#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS_Pos (0U)
-#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF_Pos (0U)
-#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
@@ -2967,9 +2542,6 @@
#define EXTI_IMR_MR18_Pos (18U)
#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos (19U)
-#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -2991,8 +2563,8 @@
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
-#define EXTI_IMR_IM19 EXTI_IMR_MR19
-
+#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
+
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0_Pos (0U)
#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
@@ -3051,9 +2623,6 @@
#define EXTI_EMR_MR18_Pos (18U)
#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos (19U)
-#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -3075,7 +2644,6 @@
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#define EXTI_EMR_EM18 EXTI_EMR_MR18
-#define EXTI_EMR_EM19 EXTI_EMR_MR19
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -3135,9 +2703,6 @@
#define EXTI_RTSR_TR18_Pos (18U)
#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos (19U)
-#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -3159,7 +2724,6 @@
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -3219,9 +2783,6 @@
#define EXTI_FTSR_TR18_Pos (18U)
#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos (19U)
-#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -3243,7 +2804,6 @@
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -3303,9 +2863,6 @@
#define EXTI_SWIER_SWIER18_Pos (18U)
#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos (19U)
-#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -3327,7 +2884,6 @@
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -3387,9 +2943,6 @@
#define EXTI_PR_PR18_Pos (18U)
#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos (19U)
-#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
-#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -3411,7 +2964,6 @@
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
/******************************************************************************/
/* */
@@ -4261,10 +3813,6 @@
#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-#define TIM_SMCR_OCCS_Pos (3U)
-#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
-#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
-
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
@@ -4609,9 +4157,6 @@
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos (15U)
-#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
-#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT_Pos (0U)
@@ -4715,8 +4260,6 @@
#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-/******************* Bit definition for TIM_OR register ********************/
-
/******************************************************************************/
/* */
/* Real-Time Clock */
@@ -5309,28 +4852,28 @@
#define USB_EP_TYPE_MASK_Pos (9U)
#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
-#define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
-
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
- /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */
+#define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
- /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************* Bit definition for USB_EP0R register *******************/
@@ -5897,52 +5440,52 @@
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+#define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+#define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+#define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+#define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+#define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+#define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+#define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+#define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+#define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+#define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+#define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+#define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+#define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+#define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+#define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+#define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */
/*----------------------------------------------------------------------------*/
@@ -6135,196 +5678,196 @@
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/******************************************************************************/
@@ -6532,8 +6075,8 @@
#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
@@ -6578,6 +6121,11 @@
#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
+
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
@@ -7163,6 +6711,9 @@
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@@ -7177,6 +6728,8 @@
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) 0U
+
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
@@ -7247,7 +6800,7 @@
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
-#define IS_TIM_BREAK_INSTANCE(INSTANCE) (0)
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) 0U
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM2) && \
@@ -7268,14 +6821,14 @@
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))))
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) (0)
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) 0U
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (0)
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) 0U
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM2) || \
@@ -7292,7 +6845,17 @@
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (0)
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) 0U
+
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
/****************************** END TIM Instances *****************************/
@@ -7353,10 +6916,14 @@
+#define RCC_HSE_MIN 4000000U
+#define RCC_HSE_MAX 16000000U
+
+#define RCC_MAX_FREQUENCY 72000000U
/**
* @}
-*/
+ */
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103x6.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103x6.h
index 78c09d1..d311634 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103x6.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103x6.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f103x6.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
-#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
+ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
@@ -138,7 +138,6 @@
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
} IRQn_Type;
-
/**
* @}
*/
@@ -612,67 +611,67 @@
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x08007FFF) /*!< FLASH END address of bank1 */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END 0x08007FFFU /*!< FLASH END address of bank1 */
+#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
-#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
+#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
+#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
-#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
+#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
+#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
/* USB device FS */
-#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
/**
@@ -683,43 +682,43 @@
* @{
*/
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define USB ((USB_TypeDef *) USB_BASE)
-#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
+#define USART2 ((USART_TypeDef *)USART2_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define USB ((USB_TypeDef *)USB_BASE)
+#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
+#define BKP ((BKP_TypeDef *)BKP_BASE)
+#define PWR ((PWR_TypeDef *)PWR_BASE)
+#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
+#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *)ADC2_BASE)
+#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
+#define USART1 ((USART_TypeDef *)USART1_BASE)
+#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *)RCC_BASE)
+#define CRC ((CRC_TypeDef *)CRC_BASE)
+#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB ((OB_TypeDef *)OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/**
@@ -790,14 +789,24 @@
#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
+
+/* Legacy defines */
+#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
+#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
+#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
+#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
+#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
+#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
+#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
+#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
@@ -962,9 +971,9 @@
#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
@@ -973,9 +982,9 @@
#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
@@ -986,15 +995,15 @@
#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
@@ -1004,11 +1013,11 @@
#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
@@ -1018,11 +1027,11 @@
#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
@@ -1031,10 +1040,10 @@
#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
@@ -1053,10 +1062,10 @@
#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
-#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMULL3_Pos (18U)
#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
@@ -1111,11 +1120,11 @@
#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
/* Reference defines */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
@@ -1371,10 +1380,10 @@
#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@@ -1944,7 +1953,7 @@
#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos (0U)
#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
@@ -1999,7 +2008,7 @@
#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
@@ -2039,7 +2048,7 @@
#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
@@ -2054,7 +2063,7 @@
#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
@@ -2072,7 +2081,7 @@
#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -2088,7 +2097,7 @@
#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
/*!< CAN_REMAP configuration */
-#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
@@ -2108,7 +2117,7 @@
#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
@@ -2135,7 +2144,7 @@
#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
@@ -2156,7 +2165,7 @@
#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
@@ -2177,7 +2186,7 @@
#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
@@ -2198,7 +2207,7 @@
#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
@@ -2233,7 +2242,7 @@
#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
@@ -2254,7 +2263,7 @@
#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
@@ -2275,7 +2284,7 @@
#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
@@ -2296,7 +2305,7 @@
#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
@@ -2331,7 +2340,7 @@
#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
@@ -2352,7 +2361,7 @@
#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
@@ -2373,7 +2382,7 @@
#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
@@ -2394,7 +2403,7 @@
#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
@@ -2429,7 +2438,7 @@
#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
@@ -2450,7 +2459,7 @@
#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
@@ -2471,7 +2480,7 @@
#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
@@ -2492,7 +2501,7 @@
#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
@@ -2518,440 +2527,6 @@
/******************************************************************************/
/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA_Pos (0U)
-#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA_Pos (0U)
-#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND_Pos (0U)
-#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND_Pos (0U)
-#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE_Pos (0U)
-#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos (0U)
-#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos (8U)
-#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos (16U)
-#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos (24U)
-#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos (0U)
-#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos (1U)
-#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos (3U)
-#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos (4U)
-#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos (7U)
-#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos (8U)
-#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos (9U)
-#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos (10U)
-#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos (11U)
-#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos (12U)
-#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
-#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos (15U)
-#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos (16U)
-#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos (17U)
-#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos (18U)
-#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
-#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos (19U)
-#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
-#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos (24U)
-#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos (25U)
-#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS_Pos (0U)
-#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS_Pos (0U)
-#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF_Pos (0U)
-#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
@@ -3014,9 +2589,6 @@
#define EXTI_IMR_MR18_Pos (18U)
#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos (19U)
-#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -3038,8 +2610,8 @@
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
-#define EXTI_IMR_IM19 EXTI_IMR_MR19
-
+#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
+
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0_Pos (0U)
#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
@@ -3098,9 +2670,6 @@
#define EXTI_EMR_MR18_Pos (18U)
#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos (19U)
-#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -3122,7 +2691,6 @@
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#define EXTI_EMR_EM18 EXTI_EMR_MR18
-#define EXTI_EMR_EM19 EXTI_EMR_MR19
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -3182,9 +2750,6 @@
#define EXTI_RTSR_TR18_Pos (18U)
#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos (19U)
-#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -3206,7 +2771,6 @@
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -3266,9 +2830,6 @@
#define EXTI_FTSR_TR18_Pos (18U)
#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos (19U)
-#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -3290,7 +2851,6 @@
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -3350,9 +2910,6 @@
#define EXTI_SWIER_SWIER18_Pos (18U)
#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos (19U)
-#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -3374,7 +2931,6 @@
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -3434,9 +2990,6 @@
#define EXTI_PR_PR18_Pos (18U)
#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos (19U)
-#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
-#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -3458,7 +3011,6 @@
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
/******************************************************************************/
/* */
@@ -4319,10 +3871,6 @@
#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-#define TIM_SMCR_OCCS_Pos (3U)
-#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
-#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
-
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
@@ -4667,9 +4215,6 @@
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos (15U)
-#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
-#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT_Pos (0U)
@@ -4773,8 +4318,6 @@
#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-/******************* Bit definition for TIM_OR register ********************/
-
/******************************************************************************/
/* */
/* Real-Time Clock */
@@ -5367,28 +4910,28 @@
#define USB_EP_TYPE_MASK_Pos (9U)
#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
-#define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
-
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
- /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */
+#define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
- /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************* Bit definition for USB_EP0R register *******************/
@@ -5955,52 +5498,52 @@
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+#define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+#define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+#define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+#define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+#define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+#define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+#define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+#define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+#define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+#define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+#define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+#define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+#define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+#define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+#define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+#define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */
/*----------------------------------------------------------------------------*/
@@ -6193,196 +5736,196 @@
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/******************************************************************************/
/* */
@@ -10075,8 +9618,8 @@
#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
@@ -10121,6 +9664,11 @@
#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
+
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
@@ -10687,6 +10235,9 @@
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@@ -10700,6 +10251,8 @@
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3))
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
@@ -10824,6 +10377,16 @@
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
+
/****************************** END TIM Instances *****************************/
@@ -10861,7 +10424,7 @@
/***************** UART Instances : DMA mode available **********************/
#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) )
+ ((INSTANCE) == USART2))
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
@@ -10874,10 +10437,14 @@
+#define RCC_HSE_MIN 4000000U
+#define RCC_HSE_MAX 16000000U
+
+#define RCC_MAX_FREQUENCY 72000000U
/**
* @}
-*/
+ */
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
@@ -10888,40 +10455,40 @@
/* Aliases for __IRQn */
#define ADC1_IRQn ADC1_2_IRQn
-#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
-#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
#define TIM9_IRQn TIM1_BRK_IRQn
-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM11_IRQn TIM1_TRG_COM_IRQn
-#define TIM10_IRQn TIM1_UP_IRQn
-#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
-#define CEC_IRQn USBWakeUp_IRQn
+#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
+#define TIM10_IRQn TIM1_UP_IRQn
#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
-#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
-#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
+#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
+#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
/* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler
-#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
-#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM10_IRQHandler TIM1_UP_IRQHandler
-#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
-#define CEC_IRQHandler USBWakeUp_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_IRQHandler
#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
-#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
-#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
/**
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xb.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xb.h
index 77cbd679..2714731 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xb.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xb.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f103xb.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
-#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
+ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
@@ -143,7 +143,6 @@
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
} IRQn_Type;
-
/**
* @}
*/
@@ -617,72 +616,72 @@
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */
+#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
-#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
+#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
+#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
-#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
+#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
+#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
/* USB device FS */
-#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
/**
@@ -693,48 +692,48 @@
* @{
*/
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define USB ((USB_TypeDef *) USB_BASE)
-#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
+#define USART2 ((USART_TypeDef *)USART2_BASE)
+#define USART3 ((USART_TypeDef *)USART3_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
+#define USB ((USB_TypeDef *)USB_BASE)
+#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
+#define BKP ((BKP_TypeDef *)BKP_BASE)
+#define PWR ((PWR_TypeDef *)PWR_BASE)
+#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
+#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *)ADC2_BASE)
+#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
+#define USART1 ((USART_TypeDef *)USART1_BASE)
+#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define RCC ((RCC_TypeDef *)RCC_BASE)
+#define CRC ((CRC_TypeDef *)CRC_BASE)
+#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB ((OB_TypeDef *)OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/**
@@ -805,14 +804,24 @@
#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
+
+/* Legacy defines */
+#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
+#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
+#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
+#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
+#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
+#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
+#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
+#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
@@ -977,9 +986,9 @@
#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
@@ -988,9 +997,9 @@
#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
@@ -1001,15 +1010,15 @@
#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
@@ -1019,11 +1028,11 @@
#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
@@ -1033,11 +1042,11 @@
#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
@@ -1046,10 +1055,10 @@
#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
@@ -1068,10 +1077,10 @@
#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
-#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMULL3_Pos (18U)
#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
@@ -1126,11 +1135,11 @@
#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
/* Reference defines */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
@@ -1416,10 +1425,10 @@
#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@@ -1989,7 +1998,7 @@
#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos (0U)
#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
@@ -2044,7 +2053,7 @@
#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
@@ -2083,7 +2092,7 @@
#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
@@ -2098,7 +2107,7 @@
#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
@@ -2113,7 +2122,7 @@
#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
@@ -2131,7 +2140,7 @@
#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -2150,7 +2159,7 @@
#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
/*!< CAN_REMAP configuration */
-#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
@@ -2170,7 +2179,7 @@
#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
@@ -2197,7 +2206,7 @@
#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
@@ -2218,7 +2227,7 @@
#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
@@ -2239,7 +2248,7 @@
#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
@@ -2260,7 +2269,7 @@
#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
@@ -2295,7 +2304,7 @@
#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
@@ -2316,7 +2325,7 @@
#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
@@ -2337,7 +2346,7 @@
#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
@@ -2358,7 +2367,7 @@
#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
@@ -2393,7 +2402,7 @@
#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
@@ -2414,7 +2423,7 @@
#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
@@ -2435,7 +2444,7 @@
#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
@@ -2456,7 +2465,7 @@
#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
@@ -2491,7 +2500,7 @@
#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
@@ -2512,7 +2521,7 @@
#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
@@ -2533,7 +2542,7 @@
#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
@@ -2554,7 +2563,7 @@
#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
@@ -2580,440 +2589,6 @@
/******************************************************************************/
/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA_Pos (0U)
-#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA_Pos (0U)
-#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND_Pos (0U)
-#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND_Pos (0U)
-#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE_Pos (0U)
-#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos (0U)
-#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos (8U)
-#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos (16U)
-#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos (24U)
-#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos (0U)
-#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos (1U)
-#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos (3U)
-#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos (4U)
-#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos (7U)
-#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos (8U)
-#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos (9U)
-#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos (10U)
-#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos (11U)
-#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos (12U)
-#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
-#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos (15U)
-#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos (16U)
-#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos (17U)
-#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos (18U)
-#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
-#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos (19U)
-#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
-#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos (24U)
-#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos (25U)
-#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS_Pos (0U)
-#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS_Pos (0U)
-#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF_Pos (0U)
-#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
@@ -3076,9 +2651,6 @@
#define EXTI_IMR_MR18_Pos (18U)
#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos (19U)
-#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -3100,8 +2672,8 @@
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
-#define EXTI_IMR_IM19 EXTI_IMR_MR19
-
+#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
+
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0_Pos (0U)
#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
@@ -3160,9 +2732,6 @@
#define EXTI_EMR_MR18_Pos (18U)
#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos (19U)
-#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -3184,7 +2753,6 @@
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#define EXTI_EMR_EM18 EXTI_EMR_MR18
-#define EXTI_EMR_EM19 EXTI_EMR_MR19
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -3244,9 +2812,6 @@
#define EXTI_RTSR_TR18_Pos (18U)
#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos (19U)
-#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -3268,7 +2833,6 @@
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -3328,9 +2892,6 @@
#define EXTI_FTSR_TR18_Pos (18U)
#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos (19U)
-#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -3352,7 +2913,6 @@
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -3412,9 +2972,6 @@
#define EXTI_SWIER_SWIER18_Pos (18U)
#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos (19U)
-#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -3436,7 +2993,6 @@
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -3496,9 +3052,6 @@
#define EXTI_PR_PR18_Pos (18U)
#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos (19U)
-#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
-#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -3520,7 +3073,6 @@
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
/******************************************************************************/
/* */
@@ -4381,10 +3933,6 @@
#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-#define TIM_SMCR_OCCS_Pos (3U)
-#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
-#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
-
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
@@ -4729,9 +4277,6 @@
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos (15U)
-#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
-#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT_Pos (0U)
@@ -4835,8 +4380,6 @@
#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-/******************* Bit definition for TIM_OR register ********************/
-
/******************************************************************************/
/* */
/* Real-Time Clock */
@@ -5429,28 +4972,28 @@
#define USB_EP_TYPE_MASK_Pos (9U)
#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
-#define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
-
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
- /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */
+#define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
- /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************* Bit definition for USB_EP0R register *******************/
@@ -6017,52 +5560,52 @@
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+#define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+#define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+#define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+#define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+#define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+#define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+#define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+#define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+#define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+#define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+#define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+#define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+#define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+#define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+#define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+#define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */
/*----------------------------------------------------------------------------*/
@@ -6255,196 +5798,196 @@
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/******************************************************************************/
/* */
@@ -10137,8 +9680,8 @@
#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
@@ -10183,6 +9726,11 @@
#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
+
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
@@ -10781,6 +10329,9 @@
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@@ -10796,6 +10347,8 @@
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4))
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
@@ -10944,6 +10497,18 @@
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
+
/****************************** END TIM Instances *****************************/
@@ -11003,10 +10568,14 @@
+#define RCC_HSE_MIN 4000000U
+#define RCC_HSE_MAX 16000000U
+
+#define RCC_MAX_FREQUENCY 72000000U
/**
* @}
-*/
+ */
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
@@ -11017,40 +10586,40 @@
/* Aliases for __IRQn */
#define ADC1_IRQn ADC1_2_IRQn
-#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
-#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
#define TIM9_IRQn TIM1_BRK_IRQn
-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM11_IRQn TIM1_TRG_COM_IRQn
-#define TIM10_IRQn TIM1_UP_IRQn
-#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
-#define CEC_IRQn USBWakeUp_IRQn
+#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
+#define TIM10_IRQn TIM1_UP_IRQn
#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
-#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
+#define CEC_IRQn USBWakeUp_IRQn
#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
-#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
+#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
+#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
/* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler
-#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
-#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM10_IRQHandler TIM1_UP_IRQHandler
-#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
-#define CEC_IRQHandler USBWakeUp_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
+#define TIM10_IRQHandler TIM1_UP_IRQHandler
#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
-#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
+#define CEC_IRQHandler USBWakeUp_IRQHandler
#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
-#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
+#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
/**
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xe.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xe.h
index 464e82c..c97aecc 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xe.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xe.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f103xe.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
-#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
+ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
@@ -160,7 +160,6 @@
DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
} IRQn_Type;
-
/**
* @}
*/
@@ -741,105 +740,105 @@
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END 0x0807FFFFU /*!< FLASH END address of bank1 */
+#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
-#define FSMC_BASE ((uint32_t)0x60000000) /*!< FSMC base address */
-#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+#define FSMC_BASE 0x60000000U /*!< FSMC base address */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
-#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
-#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
-#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
-#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
+#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00U)
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x00002000U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x00003C00U)
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
+#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
-#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
-#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
-#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
-#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
-#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400U)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408U)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CU)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430U)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458U)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
-#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
+#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
+#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
#define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */
#define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */
-#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */
-#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */
-#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */
+#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000U) /*!< FSMC Bank1_2 base address */
+#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000U) /*!< FSMC Bank1_3 base address */
+#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000U) /*!< FSMC Bank1_4 base address */
-#define FSMC_BANK2 (FSMC_BASE + 0x10000000) /*!< FSMC Bank2 base address */
-#define FSMC_BANK3 (FSMC_BASE + 0x20000000) /*!< FSMC Bank3 base address */
-#define FSMC_BANK4 (FSMC_BASE + 0x30000000) /*!< FSMC Bank4 base address */
+#define FSMC_BANK2 (FSMC_BASE + 0x10000000U) /*!< FSMC Bank2 base address */
+#define FSMC_BANK3 (FSMC_BASE + 0x20000000U) /*!< FSMC Bank3 base address */
+#define FSMC_BANK4 (FSMC_BASE + 0x30000000U) /*!< FSMC Bank4 base address */
-#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
-#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
-#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2/Bank3 registers base address */
-#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
+#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x00000000U) /*!< FSMC Bank1 registers base address */
+#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x00000104U) /*!< FSMC Bank1E registers base address */
+#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x00000060U) /*!< FSMC Bank2/Bank3 registers base address */
+#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x000000A0U) /*!< FSMC Bank4 registers base address */
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
/* USB device FS */
-#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
/**
@@ -850,69 +849,70 @@
* @{
*/
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define USB ((USB_TypeDef *) USB_BASE)
-#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
-#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
-#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
-#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_BANK2_3_R_BASE)
-#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_BANK4_R_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *)TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *)TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *)TIM7_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *)SPI3_BASE)
+#define USART2 ((USART_TypeDef *)USART2_BASE)
+#define USART3 ((USART_TypeDef *)USART3_BASE)
+#define UART4 ((USART_TypeDef *)UART4_BASE)
+#define UART5 ((USART_TypeDef *)UART5_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
+#define USB ((USB_TypeDef *)USB_BASE)
+#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
+#define BKP ((BKP_TypeDef *)BKP_BASE)
+#define PWR ((PWR_TypeDef *)PWR_BASE)
+#define DAC1 ((DAC_TypeDef *)DAC_BASE)
+#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */
+#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE)
+#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *)ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *)ADC3_BASE)
+#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
+#define TIM8 ((TIM_TypeDef *)TIM8_BASE)
+#define USART1 ((USART_TypeDef *)USART1_BASE)
+#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *)DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *)RCC_BASE)
+#define CRC ((CRC_TypeDef *)CRC_BASE)
+#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB ((OB_TypeDef *)OB_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)
+#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *)FSMC_BANK2_3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *)FSMC_BANK4_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/**
@@ -983,14 +983,24 @@
#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
+
+/* Legacy defines */
+#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
+#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
+#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
+#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
+#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
+#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
+#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
+#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
@@ -1315,9 +1325,9 @@
#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
@@ -1326,9 +1336,9 @@
#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
@@ -1339,15 +1349,15 @@
#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
@@ -1357,11 +1367,11 @@
#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
@@ -1371,11 +1381,11 @@
#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
@@ -1384,10 +1394,10 @@
#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
@@ -1406,10 +1416,10 @@
#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
-#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMULL3_Pos (18U)
#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
@@ -1464,11 +1474,11 @@
#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
/* Reference defines */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
@@ -1829,10 +1839,10 @@
#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@@ -2402,7 +2412,7 @@
#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos (0U)
#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
@@ -2457,7 +2467,7 @@
#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
@@ -2496,7 +2506,7 @@
#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
@@ -2511,7 +2521,7 @@
#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
@@ -2526,7 +2536,7 @@
#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
@@ -2544,7 +2554,7 @@
#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -2563,7 +2573,7 @@
#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
/*!< CAN_REMAP configuration */
-#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
@@ -2598,7 +2608,7 @@
#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
@@ -2625,7 +2635,7 @@
#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
@@ -2646,7 +2656,7 @@
#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
@@ -2667,7 +2677,7 @@
#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
@@ -2688,7 +2698,7 @@
#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
@@ -2723,7 +2733,7 @@
#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
@@ -2744,7 +2754,7 @@
#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
@@ -2765,7 +2775,7 @@
#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
@@ -2786,7 +2796,7 @@
#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
@@ -2821,7 +2831,7 @@
#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
@@ -2842,7 +2852,7 @@
#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
@@ -2863,7 +2873,7 @@
#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
@@ -2884,7 +2894,7 @@
#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
@@ -2919,7 +2929,7 @@
#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
@@ -2940,7 +2950,7 @@
#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
@@ -2961,7 +2971,7 @@
#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
@@ -2982,7 +2992,7 @@
#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
@@ -3011,440 +3021,6 @@
/******************************************************************************/
/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA_Pos (0U)
-#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA_Pos (0U)
-#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND_Pos (0U)
-#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND_Pos (0U)
-#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE_Pos (0U)
-#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos (0U)
-#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos (8U)
-#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos (16U)
-#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos (24U)
-#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos (0U)
-#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos (1U)
-#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos (3U)
-#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos (4U)
-#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos (7U)
-#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos (8U)
-#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos (9U)
-#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos (10U)
-#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos (11U)
-#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos (12U)
-#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
-#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos (15U)
-#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos (16U)
-#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos (17U)
-#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos (18U)
-#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
-#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos (19U)
-#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
-#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos (24U)
-#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos (25U)
-#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS_Pos (0U)
-#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS_Pos (0U)
-#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF_Pos (0U)
-#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
@@ -3507,9 +3083,6 @@
#define EXTI_IMR_MR18_Pos (18U)
#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos (19U)
-#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -3531,8 +3104,8 @@
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
-#define EXTI_IMR_IM19 EXTI_IMR_MR19
-
+#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
+
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0_Pos (0U)
#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
@@ -3591,9 +3164,6 @@
#define EXTI_EMR_MR18_Pos (18U)
#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos (19U)
-#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -3615,7 +3185,6 @@
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#define EXTI_EMR_EM18 EXTI_EMR_MR18
-#define EXTI_EMR_EM19 EXTI_EMR_MR19
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -3675,9 +3244,6 @@
#define EXTI_RTSR_TR18_Pos (18U)
#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos (19U)
-#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -3699,7 +3265,6 @@
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -3759,9 +3324,6 @@
#define EXTI_FTSR_TR18_Pos (18U)
#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos (19U)
-#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -3783,7 +3345,6 @@
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -3843,9 +3404,6 @@
#define EXTI_SWIER_SWIER18_Pos (18U)
#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos (19U)
-#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -3867,7 +3425,6 @@
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -3927,9 +3484,6 @@
#define EXTI_PR_PR18_Pos (18U)
#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos (19U)
-#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
-#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -3951,7 +3505,6 @@
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
/******************************************************************************/
/* */
@@ -4961,10 +4514,6 @@
#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-#define TIM_SMCR_OCCS_Pos (3U)
-#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
-#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
-
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
@@ -5309,9 +4858,6 @@
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos (15U)
-#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
-#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT_Pos (0U)
@@ -5415,8 +4961,6 @@
#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-/******************* Bit definition for TIM_OR register ********************/
-
/******************************************************************************/
/* */
/* Real-Time Clock */
@@ -5839,14 +5383,14 @@
#define FSMC_PMEMx_MEMWAITx_Pos (8U)
#define FSMC_PMEMx_MEMWAITx_Msk (0xFFU << FSMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */
#define FSMC_PMEMx_MEMWAITx FSMC_PMEMx_MEMWAITx_Msk /*!< MEMWAITx[7:0] bits (Common memory x wait time) */
-#define FSMC_PMEMx_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) /*!< Bit 4 */
-#define FSMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) /*!< Bit 5 */
-#define FSMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) /*!< Bit 6 */
-#define FSMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+#define FSMC_PMEMx_MEMWAIT2_0 0x00000100U /*!< Bit 0 */
+#define FSMC_PMEMx_MEMWAITx_1 0x00000200U /*!< Bit 1 */
+#define FSMC_PMEMx_MEMWAITx_2 0x00000400U /*!< Bit 2 */
+#define FSMC_PMEMx_MEMWAITx_3 0x00000800U /*!< Bit 3 */
+#define FSMC_PMEMx_MEMWAITx_4 0x00001000U /*!< Bit 4 */
+#define FSMC_PMEMx_MEMWAITx_5 0x00002000U /*!< Bit 5 */
+#define FSMC_PMEMx_MEMWAITx_6 0x00004000U /*!< Bit 6 */
+#define FSMC_PMEMx_MEMWAITx_7 0x00008000U /*!< Bit 7 */
#define FSMC_PMEMx_MEMHOLDx_Pos (16U)
#define FSMC_PMEMx_MEMHOLDx_Msk (0xFFU << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */
@@ -6391,28 +5935,28 @@
#define USB_EP_TYPE_MASK_Pos (9U)
#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
-#define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
-
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
- /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */
+#define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
- /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************* Bit definition for USB_EP0R register *******************/
@@ -6979,52 +6523,52 @@
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+#define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+#define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+#define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+#define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+#define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+#define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+#define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+#define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+#define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+#define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+#define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+#define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+#define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+#define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+#define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+#define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */
/*----------------------------------------------------------------------------*/
@@ -7217,196 +6761,196 @@
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/******************************************************************************/
/* */
@@ -10899,7 +10443,10 @@
/* Serial Peripheral Interface */
/* */
/******************************************************************************/
-
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_CPHA_Pos (0U)
#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
@@ -11142,8 +10689,8 @@
#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
@@ -11188,6 +10735,11 @@
#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
+
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
@@ -11773,7 +11325,7 @@
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
@@ -11808,6 +11360,9 @@
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
@@ -11835,6 +11390,10 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7))
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
@@ -12043,6 +11602,22 @@
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
+
/****************************** END TIM Instances *****************************/
@@ -12113,10 +11688,14 @@
+#define RCC_HSE_MIN 4000000U
+#define RCC_HSE_MAX 16000000U
+
+#define RCC_MAX_FREQUENCY 72000000U
/**
* @}
-*/
+ */
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
@@ -12128,26 +11707,26 @@
/* Aliases for __IRQn */
#define ADC1_IRQn ADC1_2_IRQn
#define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn
-#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
#define TIM9_IRQn TIM1_BRK_IRQn
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
-#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
#define TIM11_IRQn TIM1_TRG_COM_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
#define TIM10_IRQn TIM1_UP_IRQn
-#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
+#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
#define TIM6_DAC_IRQn TIM6_IRQn
#define TIM12_IRQn TIM8_BRK_IRQn
#define TIM8_BRK_TIM12_IRQn TIM8_BRK_IRQn
-#define TIM14_IRQn TIM8_TRG_COM_IRQn
#define TIM8_TRG_COM_TIM14_IRQn TIM8_TRG_COM_IRQn
+#define TIM14_IRQn TIM8_TRG_COM_IRQn
#define TIM8_UP_TIM13_IRQn TIM8_UP_IRQn
#define TIM13_IRQn TIM8_UP_IRQn
#define CEC_IRQn USBWakeUp_IRQn
#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
-#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
+#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
@@ -12155,30 +11734,29 @@
/* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler
#define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler
-#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM10_IRQHandler TIM1_UP_IRQHandler
-#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
+#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
#define TIM6_DAC_IRQHandler TIM6_IRQHandler
#define TIM12_IRQHandler TIM8_BRK_IRQHandler
#define TIM8_BRK_TIM12_IRQHandler TIM8_BRK_IRQHandler
-#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
#define TIM8_TRG_COM_TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
+#define TIM14_IRQHandler TIM8_TRG_COM_IRQHandler
#define TIM8_UP_TIM13_IRQHandler TIM8_UP_IRQHandler
#define TIM13_IRQHandler TIM8_UP_IRQHandler
#define CEC_IRQHandler USBWakeUp_IRQHandler
#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
-#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
+#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
-
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xg.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xg.h
index 1d30f78..f725e56 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xg.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f103xg.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f103xg.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
- #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
-#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
+ #define __MPU_PRESENT 1U /*!< STM32 XL-density devices provide an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
@@ -160,7 +160,6 @@
DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
} IRQn_Type;
-
/**
* @}
*/
@@ -747,112 +746,112 @@
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x0807FFFF) /*!< FLASH END address of bank1 */
-#define FLASH_BANK2_END ((uint32_t)0x080FFFFF) /*!< FLASH END address of bank2 */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END 0x0807FFFFU /*!< FLASH END address of bank1 */
+#define FLASH_BANK2_END 0x080FFFFFU /*!< FLASH END address of bank2 */
+#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
-#define FSMC_BASE ((uint32_t)0x60000000) /*!< FSMC base address */
-#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+#define FSMC_BASE 0x60000000U /*!< FSMC base address */
+#define FSMC_R_BASE 0xA0000000U /*!< FSMC registers base address */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
-#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
-#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x00001800U)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x00001C00U)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x00002000U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
-#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
-#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
-#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
-#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
-#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
-#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
-#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
+#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
+#define GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00U)
+#define GPIOG_BASE (APB2PERIPH_BASE + 0x00002000U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
+#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
+#define ADC3_BASE (APB2PERIPH_BASE + 0x00003C00U)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x00004C00U)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x00005000U)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x00005400U)
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
+#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
-#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
-#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
-#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
-#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
-#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400U)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408U)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CU)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430U)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458U)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
-#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
+#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
+#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
#define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */
#define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */
-#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000) /*!< FSMC Bank1_2 base address */
-#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000) /*!< FSMC Bank1_3 base address */
-#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000) /*!< FSMC Bank1_4 base address */
+#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000U) /*!< FSMC Bank1_2 base address */
+#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000U) /*!< FSMC Bank1_3 base address */
+#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000U) /*!< FSMC Bank1_4 base address */
-#define FSMC_BANK2 (FSMC_BASE + 0x10000000) /*!< FSMC Bank2 base address */
-#define FSMC_BANK3 (FSMC_BASE + 0x20000000) /*!< FSMC Bank3 base address */
-#define FSMC_BANK4 (FSMC_BASE + 0x30000000) /*!< FSMC Bank4 base address */
+#define FSMC_BANK2 (FSMC_BASE + 0x10000000U) /*!< FSMC Bank2 base address */
+#define FSMC_BANK3 (FSMC_BASE + 0x20000000U) /*!< FSMC Bank3 base address */
+#define FSMC_BANK4 (FSMC_BASE + 0x30000000U) /*!< FSMC Bank4 base address */
-#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
-#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
-#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2/Bank3 registers base address */
-#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */
+#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x00000000U) /*!< FSMC Bank1 registers base address */
+#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x00000104U) /*!< FSMC Bank1E registers base address */
+#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x00000060U) /*!< FSMC Bank2/Bank3 registers base address */
+#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x000000A0U) /*!< FSMC Bank4 registers base address */
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
/* USB device FS */
-#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
+#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
/**
@@ -863,75 +862,76 @@
* @{
*/
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define USB ((USB_TypeDef *) USB_BASE)
-#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
-#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_BANK1_R_BASE)
-#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_BANK1E_R_BASE)
-#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_BANK2_3_R_BASE)
-#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_BANK4_R_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *)TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *)TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *)TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *)TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *)TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *)TIM14_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *)SPI3_BASE)
+#define USART2 ((USART_TypeDef *)USART2_BASE)
+#define USART3 ((USART_TypeDef *)USART3_BASE)
+#define UART4 ((USART_TypeDef *)UART4_BASE)
+#define UART5 ((USART_TypeDef *)UART5_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
+#define USB ((USB_TypeDef *)USB_BASE)
+#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
+#define BKP ((BKP_TypeDef *)BKP_BASE)
+#define PWR ((PWR_TypeDef *)PWR_BASE)
+#define DAC1 ((DAC_TypeDef *)DAC_BASE)
+#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */
+#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
+#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE)
+#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *)ADC2_BASE)
+#define ADC3 ((ADC_TypeDef *)ADC3_BASE)
+#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
+#define TIM8 ((TIM_TypeDef *)TIM8_BASE)
+#define USART1 ((USART_TypeDef *)USART1_BASE)
+#define TIM9 ((TIM_TypeDef *)TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *)TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *)TIM11_BASE)
+#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *)DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *)RCC_BASE)
+#define CRC ((CRC_TypeDef *)CRC_BASE)
+#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB ((OB_TypeDef *)OB_BASE)
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)
+#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *)FSMC_BANK2_3_R_BASE)
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *)FSMC_BANK4_R_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
/**
@@ -1002,14 +1002,24 @@
#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
+
+/* Legacy defines */
+#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
+#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
+#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
+#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
+#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
+#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
+#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
+#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
@@ -1334,9 +1344,9 @@
#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
@@ -1345,9 +1355,9 @@
#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
@@ -1358,15 +1368,15 @@
#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
@@ -1376,11 +1386,11 @@
#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
@@ -1390,11 +1400,11 @@
#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
@@ -1403,10 +1413,10 @@
#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
@@ -1425,10 +1435,10 @@
#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
-#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
+#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
#define RCC_CFGR_PLLMULL3_Pos (18U)
#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
@@ -1483,11 +1493,11 @@
#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
/* Reference defines */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
@@ -1884,10 +1894,10 @@
#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@@ -2457,7 +2467,7 @@
#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos (0U)
#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
@@ -2512,7 +2522,7 @@
#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
@@ -2551,7 +2561,7 @@
#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
@@ -2566,7 +2576,7 @@
#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
@@ -2581,7 +2591,7 @@
#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
@@ -2599,7 +2609,7 @@
#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -2618,7 +2628,7 @@
#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
/*!< CAN_REMAP configuration */
-#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
@@ -2653,7 +2663,7 @@
#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
@@ -2680,7 +2690,7 @@
#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
@@ -2701,7 +2711,7 @@
#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
@@ -2722,7 +2732,7 @@
#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
@@ -2743,7 +2753,7 @@
#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
@@ -2778,7 +2788,7 @@
#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
@@ -2799,7 +2809,7 @@
#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
@@ -2820,7 +2830,7 @@
#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
@@ -2841,7 +2851,7 @@
#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
@@ -2876,7 +2886,7 @@
#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
@@ -2897,7 +2907,7 @@
#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
@@ -2918,7 +2928,7 @@
#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
@@ -2939,7 +2949,7 @@
#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
@@ -2974,7 +2984,7 @@
#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
@@ -2995,7 +3005,7 @@
#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
@@ -3016,7 +3026,7 @@
#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
@@ -3037,7 +3047,7 @@
#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
@@ -3081,440 +3091,6 @@
/******************************************************************************/
/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA_Pos (0U)
-#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA_Pos (0U)
-#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND_Pos (0U)
-#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND_Pos (0U)
-#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE_Pos (0U)
-#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos (0U)
-#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos (8U)
-#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos (16U)
-#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos (24U)
-#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos (0U)
-#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos (1U)
-#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos (3U)
-#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos (4U)
-#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos (7U)
-#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos (8U)
-#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos (9U)
-#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos (10U)
-#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos (11U)
-#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos (12U)
-#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
-#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos (15U)
-#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos (16U)
-#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos (17U)
-#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos (18U)
-#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
-#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos (19U)
-#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
-#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos (24U)
-#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos (25U)
-#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS_Pos (0U)
-#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS_Pos (0U)
-#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF_Pos (0U)
-#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
@@ -3577,9 +3153,6 @@
#define EXTI_IMR_MR18_Pos (18U)
#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos (19U)
-#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
/* References Defines */
#define EXTI_IMR_IM0 EXTI_IMR_MR0
@@ -3601,8 +3174,8 @@
#define EXTI_IMR_IM16 EXTI_IMR_MR16
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
-#define EXTI_IMR_IM19 EXTI_IMR_MR19
-
+#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
+
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0_Pos (0U)
#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
@@ -3661,9 +3234,6 @@
#define EXTI_EMR_MR18_Pos (18U)
#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos (19U)
-#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
-#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
/* References Defines */
#define EXTI_EMR_EM0 EXTI_EMR_MR0
@@ -3685,7 +3255,6 @@
#define EXTI_EMR_EM16 EXTI_EMR_MR16
#define EXTI_EMR_EM17 EXTI_EMR_MR17
#define EXTI_EMR_EM18 EXTI_EMR_MR18
-#define EXTI_EMR_EM19 EXTI_EMR_MR19
/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0_Pos (0U)
@@ -3745,9 +3314,6 @@
#define EXTI_RTSR_TR18_Pos (18U)
#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos (19U)
-#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
@@ -3769,7 +3335,6 @@
#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
-#define EXTI_RTSR_RT19 EXTI_RTSR_TR19
/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0_Pos (0U)
@@ -3829,9 +3394,6 @@
#define EXTI_FTSR_TR18_Pos (18U)
#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos (19U)
-#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
-#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
/* References Defines */
#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
@@ -3853,7 +3415,6 @@
#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-#define EXTI_FTSR_FT19 EXTI_FTSR_TR19
/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0_Pos (0U)
@@ -3913,9 +3474,6 @@
#define EXTI_SWIER_SWIER18_Pos (18U)
#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos (19U)
-#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
/* References Defines */
#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
@@ -3937,7 +3495,6 @@
#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0_Pos (0U)
@@ -3997,9 +3554,6 @@
#define EXTI_PR_PR18_Pos (18U)
#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos (19U)
-#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
-#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
/* References Defines */
#define EXTI_PR_PIF0 EXTI_PR_PR0
@@ -4021,7 +3575,6 @@
#define EXTI_PR_PIF16 EXTI_PR_PR16
#define EXTI_PR_PIF17 EXTI_PR_PR17
#define EXTI_PR_PIF18 EXTI_PR_PR18
-#define EXTI_PR_PIF19 EXTI_PR_PR19
/******************************************************************************/
/* */
@@ -5031,10 +4584,6 @@
#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-#define TIM_SMCR_OCCS_Pos (3U)
-#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
-#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
-
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
@@ -5379,9 +4928,6 @@
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos (15U)
-#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
-#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT_Pos (0U)
@@ -5485,8 +5031,6 @@
#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-/******************* Bit definition for TIM_OR register ********************/
-
/******************************************************************************/
/* */
/* Real-Time Clock */
@@ -5909,14 +5453,14 @@
#define FSMC_PMEMx_MEMWAITx_Pos (8U)
#define FSMC_PMEMx_MEMWAITx_Msk (0xFFU << FSMC_PMEMx_MEMWAITx_Pos) /*!< 0x0000FF00 */
#define FSMC_PMEMx_MEMWAITx FSMC_PMEMx_MEMWAITx_Msk /*!< MEMWAITx[7:0] bits (Common memory x wait time) */
-#define FSMC_PMEMx_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define FSMC_PMEMx_MEMWAITx_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define FSMC_PMEMx_MEMWAITx_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define FSMC_PMEMx_MEMWAITx_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-#define FSMC_PMEMx_MEMWAITx_4 ((uint32_t)0x00001000) /*!< Bit 4 */
-#define FSMC_PMEMx_MEMWAITx_5 ((uint32_t)0x00002000) /*!< Bit 5 */
-#define FSMC_PMEMx_MEMWAITx_6 ((uint32_t)0x00004000) /*!< Bit 6 */
-#define FSMC_PMEMx_MEMWAITx_7 ((uint32_t)0x00008000) /*!< Bit 7 */
+#define FSMC_PMEMx_MEMWAIT2_0 0x00000100U /*!< Bit 0 */
+#define FSMC_PMEMx_MEMWAITx_1 0x00000200U /*!< Bit 1 */
+#define FSMC_PMEMx_MEMWAITx_2 0x00000400U /*!< Bit 2 */
+#define FSMC_PMEMx_MEMWAITx_3 0x00000800U /*!< Bit 3 */
+#define FSMC_PMEMx_MEMWAITx_4 0x00001000U /*!< Bit 4 */
+#define FSMC_PMEMx_MEMWAITx_5 0x00002000U /*!< Bit 5 */
+#define FSMC_PMEMx_MEMWAITx_6 0x00004000U /*!< Bit 6 */
+#define FSMC_PMEMx_MEMWAITx_7 0x00008000U /*!< Bit 7 */
#define FSMC_PMEMx_MEMHOLDx_Pos (16U)
#define FSMC_PMEMx_MEMHOLDx_Msk (0xFFU << FSMC_PMEMx_MEMHOLDx_Pos) /*!< 0x00FF0000 */
@@ -6461,28 +6005,28 @@
#define USB_EP_TYPE_MASK_Pos (9U)
#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
-#define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
-
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
- /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
+#define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */
+#define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */
+#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
+ /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
- /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
+ /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************* Bit definition for USB_EP0R register *******************/
@@ -7049,52 +6593,52 @@
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+#define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+#define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+#define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+#define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+#define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+#define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+#define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+#define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+#define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+#define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+#define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+#define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+#define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+#define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+#define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+#define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */
/*----------------------------------------------------------------------------*/
@@ -7287,196 +6831,196 @@
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+#define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+#define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+#define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+#define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
/******************************************************************************/
/* */
@@ -10969,7 +10513,10 @@
/* Serial Peripheral Interface */
/* */
/******************************************************************************/
-
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_CPHA_Pos (0U)
#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
@@ -11212,8 +10759,8 @@
#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
@@ -11258,6 +10805,11 @@
#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
+
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
@@ -11911,7 +11463,7 @@
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
@@ -11946,6 +11498,9 @@
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
@@ -11979,6 +11534,10 @@
((INSTANCE) == TIM13) || \
((INSTANCE) == TIM14))
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM8))
+
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
@@ -12227,6 +11786,22 @@
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5) || \
+ ((INSTANCE) == TIM8))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
+
/****************************** END TIM Instances *****************************/
@@ -12297,10 +11872,14 @@
+#define RCC_HSE_MIN 4000000U
+#define RCC_HSE_MAX 16000000U
+
+#define RCC_MAX_FREQUENCY 72000000U
/**
* @}
-*/
+ */
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
@@ -12312,20 +11891,20 @@
/* Aliases for __IRQn */
#define ADC1_IRQn ADC1_2_IRQn
#define DMA2_Channel4_IRQn DMA2_Channel4_5_IRQn
-#define TIM1_BRK_TIM15_IRQn TIM1_BRK_TIM9_IRQn
#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM1_BRK_TIM9_IRQn
#define TIM9_IRQn TIM1_BRK_TIM9_IRQn
-#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_TIM11_IRQn
-#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn
#define TIM11_IRQn TIM1_TRG_COM_TIM11_IRQn
+#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn
+#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_TIM11_IRQn
#define TIM10_IRQn TIM1_UP_TIM10_IRQn
#define TIM1_UP_TIM16_IRQn TIM1_UP_TIM10_IRQn
#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn
#define TIM6_DAC_IRQn TIM6_IRQn
#define TIM12_IRQn TIM8_BRK_TIM12_IRQn
#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn
-#define TIM14_IRQn TIM8_TRG_COM_TIM14_IRQn
#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn
+#define TIM14_IRQn TIM8_TRG_COM_TIM14_IRQn
#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn
#define TIM13_IRQn TIM8_UP_TIM13_IRQn
#define CEC_IRQn USBWakeUp_IRQn
@@ -12339,20 +11918,20 @@
/* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler
#define DMA2_Channel4_IRQHandler DMA2_Channel4_5_IRQHandler
-#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_TIM9_IRQHandler
#define TIM1_BRK_IRQHandler TIM1_BRK_TIM9_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_TIM9_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_TIM9_IRQHandler
-#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
-#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
#define TIM11_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
+#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
+#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler
#define TIM10_IRQHandler TIM1_UP_TIM10_IRQHandler
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_TIM10_IRQHandler
#define TIM1_UP_IRQHandler TIM1_UP_TIM10_IRQHandler
#define TIM6_DAC_IRQHandler TIM6_IRQHandler
#define TIM12_IRQHandler TIM8_BRK_TIM12_IRQHandler
#define TIM8_BRK_IRQHandler TIM8_BRK_TIM12_IRQHandler
-#define TIM14_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler
#define TIM8_TRG_COM_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler
+#define TIM14_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler
#define TIM8_UP_IRQHandler TIM8_UP_TIM13_IRQHandler
#define TIM13_IRQHandler TIM8_UP_TIM13_IRQHandler
#define CEC_IRQHandler USBWakeUp_IRQHandler
@@ -12362,7 +11941,6 @@
#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
-
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f105xc.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f105xc.h
index 137ebfa..c3dab14 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f105xc.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f105xc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f105xc.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
-#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
+ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
@@ -159,7 +159,6 @@
OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */
} IRQn_Type;
-
/**
* @}
*/
@@ -770,99 +769,99 @@
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x0803FFFF) /*!< FLASH END address of bank1 */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END 0x0803FFFFU /*!< FLASH END address of bank1 */
+#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
-#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x00006800U)
+#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
+#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
-#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
-#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
-#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
-#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
-#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400U)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408U)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CU)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430U)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458U)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
-#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
+#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
+#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
/*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
-#define USB_OTG_GLOBAL_BASE ((uint32_t )0x00000000)
-#define USB_OTG_DEVICE_BASE ((uint32_t )0x00000800)
-#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x00000900)
-#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0x00000B00)
-#define USB_OTG_EP_REG_SIZE ((uint32_t )0x00000020)
-#define USB_OTG_HOST_BASE ((uint32_t )0x00000400)
-#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x00000440)
-#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x00000500)
-#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x00000020)
-#define USB_OTG_PCGCCTL_BASE ((uint32_t )0x00000E00)
-#define USB_OTG_FIFO_BASE ((uint32_t )0x00001000)
-#define USB_OTG_FIFO_SIZE ((uint32_t )0x00001000)
+#define USB_OTG_GLOBAL_BASE 0x00000000U
+#define USB_OTG_DEVICE_BASE 0x00000800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x00000900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00U
+#define USB_OTG_EP_REG_SIZE 0x00000020U
+#define USB_OTG_HOST_BASE 0x00000400U
+#define USB_OTG_HOST_PORT_BASE 0x00000440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x00000500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020U
+#define USB_OTG_PCGCCTL_BASE 0x00000E00U
+#define USB_OTG_FIFO_BASE 0x00001000U
+#define USB_OTG_FIFO_SIZE 0x00001000U
/**
* @}
@@ -872,63 +871,64 @@
* @{
*/
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *)TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *)TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *)TIM7_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *)SPI3_BASE)
+#define USART2 ((USART_TypeDef *)USART2_BASE)
+#define USART3 ((USART_TypeDef *)USART3_BASE)
+#define UART4 ((USART_TypeDef *)UART4_BASE)
+#define UART5 ((USART_TypeDef *)UART5_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
+#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *)CAN2_BASE)
+#define BKP ((BKP_TypeDef *)BKP_BASE)
+#define PWR ((PWR_TypeDef *)PWR_BASE)
+#define DAC1 ((DAC_TypeDef *)DAC_BASE)
+#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */
+#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
+#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *)ADC2_BASE)
+#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
+#define USART1 ((USART_TypeDef *)USART1_BASE)
+#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *)DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *)RCC_BASE)
+#define CRC ((CRC_TypeDef *)CRC_BASE)
+#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB ((OB_TypeDef *)OB_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
-#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *)USB_OTG_FS_PERIPH_BASE)
/**
* @}
@@ -998,14 +998,24 @@
#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
+
+/* Legacy defines */
+#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
+#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
+#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
+#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
+#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
+#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
+#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
+#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
@@ -1321,12 +1331,23 @@
#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
+ */
+#define RCC_PLL2_SUPPORT /*!< Support PLL2 */
+
#define RCC_CR_PLL2ON_Pos (26U)
#define RCC_CR_PLL2ON_Msk (0x1U << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */
#define RCC_CR_PLL2RDY_Pos (27U)
#define RCC_CR_PLL2RDY_Msk (0x1U << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLL3 (PLLI2S)*/
+
#define RCC_CR_PLL3ON_Pos (28U)
#define RCC_CR_PLL3ON_Msk (0x1U << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */
@@ -1342,9 +1363,9 @@
#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
@@ -1353,9 +1374,9 @@
#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
@@ -1366,15 +1387,15 @@
#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
@@ -1384,11 +1405,11 @@
#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
@@ -1398,11 +1419,11 @@
#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
@@ -1411,10 +1432,10 @@
#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
@@ -1433,8 +1454,8 @@
#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+#define RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U /*!< PREDIV1 clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U /*!< PREDIV1 clock divided by 2 for PLL entry */
#define RCC_CFGR_PLLMULL4_Pos (19U)
#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
@@ -1454,7 +1475,7 @@
#define RCC_CFGR_PLLMULL9_Pos (18U)
#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock * 9 */
-#define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */
+#define RCC_CFGR_PLLMULL6_5 0x00340000U /*!< PLL input clock * 6.5 */
#define RCC_CFGR_OTGFSPRE_Pos (22U)
#define RCC_CFGR_OTGFSPRE_Msk (0x1U << RCC_CFGR_OTGFSPRE_Pos) /*!< 0x00400000 */
@@ -1469,15 +1490,15 @@
#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
#define RCC_CFGR_MCO_3 (0x8U << RCC_CFGR_MCO_Pos) /*!< 0x08000000 */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
-#define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/
-#define RCC_CFGR_MCO_PLL3CLK_DIV2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
-#define RCC_CFGR_MCO_EXT_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
-#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */
+#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_PLL2CLK 0x08000000U /*!< PLL2 clock selected as MCO source*/
+#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x09000000U /*!< PLL3 clock divided by 2 selected as MCO source*/
+#define RCC_CFGR_MCO_EXT_HSE 0x0A000000U /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL3CLK 0x0B000000U /*!< PLL3 clock selected as MCO source */
/* Reference defines */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
@@ -1834,10 +1855,10 @@
#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@@ -1890,7 +1911,7 @@
#define RCC_CFGR2_PREDIV1_2 (0x4U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */
#define RCC_CFGR2_PREDIV1_3 (0x8U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */
-#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+#define RCC_CFGR2_PREDIV1_DIV1 0x00000000U /*!< PREDIV1 input clock not divided */
#define RCC_CFGR2_PREDIV1_DIV2_Pos (0U)
#define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */
#define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */
@@ -1946,7 +1967,7 @@
#define RCC_CFGR2_PREDIV2_2 (0x4U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000040 */
#define RCC_CFGR2_PREDIV2_3 (0x8U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000080 */
-#define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */
+#define RCC_CFGR2_PREDIV2_DIV1 0x00000000U /*!< PREDIV2 input clock not divided */
#define RCC_CFGR2_PREDIV2_DIV2_Pos (4U)
#define RCC_CFGR2_PREDIV2_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV2_DIV2_Pos) /*!< 0x00000010 */
#define RCC_CFGR2_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2_Msk /*!< PREDIV2 input clock divided by 2 */
@@ -2073,7 +2094,7 @@
#define RCC_CFGR2_PREDIV1SRC_PLL2_Pos (16U)
#define RCC_CFGR2_PREDIV1SRC_PLL2_Msk (0x1U << RCC_CFGR2_PREDIV1SRC_PLL2_Pos) /*!< 0x00010000 */
#define RCC_CFGR2_PREDIV1SRC_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2_Msk /*!< PLL2 selected as PREDIV1 entry clock source */
-#define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */
+#define RCC_CFGR2_PREDIV1SRC_HSE 0x00000000U /*!< HSE selected as PREDIV1 entry clock source */
#define RCC_CFGR2_I2S2SRC_Pos (17U)
#define RCC_CFGR2_I2S2SRC_Msk (0x1U << RCC_CFGR2_I2S2SRC_Pos) /*!< 0x00020000 */
#define RCC_CFGR2_I2S2SRC RCC_CFGR2_I2S2SRC_Msk /*!< I2S2 entry clock source */
@@ -2612,7 +2633,7 @@
#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos (0U)
#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
@@ -2667,7 +2688,7 @@
#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
@@ -2706,7 +2727,7 @@
#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
@@ -2721,7 +2742,7 @@
#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
@@ -2736,7 +2757,7 @@
#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
@@ -2754,7 +2775,7 @@
#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -2773,7 +2794,7 @@
#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
/*!< CAN_REMAP configuration */
-#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
@@ -2796,7 +2817,7 @@
#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
@@ -2852,7 +2873,7 @@
#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
@@ -2873,7 +2894,7 @@
#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
@@ -2894,7 +2915,7 @@
#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
@@ -2915,7 +2936,7 @@
#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
@@ -2950,7 +2971,7 @@
#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
@@ -2971,7 +2992,7 @@
#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
@@ -2992,7 +3013,7 @@
#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
@@ -3013,7 +3034,7 @@
#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
@@ -3048,7 +3069,7 @@
#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
@@ -3069,7 +3090,7 @@
#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
@@ -3090,7 +3111,7 @@
#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
@@ -3111,7 +3132,7 @@
#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
@@ -3146,7 +3167,7 @@
#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
@@ -3167,7 +3188,7 @@
#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
@@ -3188,7 +3209,7 @@
#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
@@ -3209,7 +3230,7 @@
#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
@@ -3235,440 +3256,6 @@
/******************************************************************************/
/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA_Pos (0U)
-#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA_Pos (0U)
-#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND_Pos (0U)
-#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND_Pos (0U)
-#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE_Pos (0U)
-#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos (0U)
-#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos (8U)
-#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos (16U)
-#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos (24U)
-#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos (0U)
-#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos (1U)
-#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos (3U)
-#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos (4U)
-#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos (7U)
-#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos (8U)
-#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos (9U)
-#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos (10U)
-#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos (11U)
-#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos (12U)
-#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
-#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos (15U)
-#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos (16U)
-#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos (17U)
-#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos (18U)
-#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
-#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos (19U)
-#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
-#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos (24U)
-#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos (25U)
-#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS_Pos (0U)
-#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS_Pos (0U)
-#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF_Pos (0U)
-#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
@@ -3756,7 +3343,8 @@
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
#define EXTI_IMR_IM19 EXTI_IMR_MR19
-
+#define EXTI_IMR_IM 0x000FFFFFU /*!< Interrupt Mask All */
+
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0_Pos (0U)
#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
@@ -5185,10 +4773,6 @@
#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-#define TIM_SMCR_OCCS_Pos (3U)
-#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
-#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
-
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
@@ -5533,9 +5117,6 @@
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos (15U)
-#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
-#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT_Pos (0U)
@@ -5639,8 +5220,6 @@
#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-/******************* Bit definition for TIM_OR register ********************/
-
/******************************************************************************/
/* */
/* Real-Time Clock */
@@ -12583,7 +12162,11 @@
/* Serial Peripheral Interface */
/* */
/******************************************************************************/
-
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
+#define I2S2_I2S3_CLOCK_FEATURE
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_CPHA_Pos (0U)
#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
@@ -12826,8 +12409,8 @@
#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
@@ -12872,6 +12455,11 @@
#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
+
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
@@ -13622,10 +13210,11 @@
#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
@@ -14762,7 +14351,7 @@
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
@@ -14795,6 +14384,9 @@
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
@@ -14818,6 +14410,8 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7))
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
@@ -14994,6 +14588,20 @@
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
+
/****************************** END TIM Instances *****************************/
@@ -15064,10 +14672,14 @@
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
+#define RCC_HSE_MIN 3000000U
+#define RCC_HSE_MAX 25000000U
+
+#define RCC_MAX_FREQUENCY 72000000U
/**
* @}
-*/
+ */
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
@@ -15078,19 +14690,19 @@
/* Aliases for __IRQn */
#define ADC1_IRQn ADC1_2_IRQn
-#define USB_LP_IRQn CAN1_RX0_IRQn
#define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn
+#define USB_LP_IRQn CAN1_RX0_IRQn
#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
#define USB_HP_IRQn CAN1_TX_IRQn
#define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn
#define USBWakeUp_IRQn OTG_FS_WKUP_IRQn
#define CEC_IRQn OTG_FS_WKUP_IRQn
-#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
+#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
#define TIM9_IRQn TIM1_BRK_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
-#define TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM10_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
@@ -15099,25 +14711,24 @@
/* Aliases for __IRQHandler */
#define ADC1_IRQHandler ADC1_2_IRQHandler
-#define USB_LP_IRQHandler CAN1_RX0_IRQHandler
#define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler
+#define USB_LP_IRQHandler CAN1_RX0_IRQHandler
#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
#define USB_HP_IRQHandler CAN1_TX_IRQHandler
#define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler
#define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler
#define CEC_IRQHandler OTG_FS_WKUP_IRQHandler
-#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM6_DAC_IRQHandler TIM6_IRQHandler
-
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f107xc.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f107xc.h
index 542f5aa..7cec10c 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f107xc.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f107xc.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f107xc.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F1xx devices.
@@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -65,10 +65,10 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
- #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
-#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
+ #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
+#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/**
* @}
@@ -161,7 +161,6 @@
OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */
} IRQn_Type;
-
/**
* @}
*/
@@ -844,104 +843,104 @@
*/
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END ((uint32_t)0x0803FFFF) /*!< FLASH END address of bank1 */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
+#define FLASH_BANK1_END 0x0803FFFFU /*!< FLASH END address of bank1 */
+#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
+#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
+#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
+#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
+#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00U)
+#define UART5_BASE (APB1PERIPH_BASE + 0x00005000U)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
-#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
-#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
-#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x00006800U)
+#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
+#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
+#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
+#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
+#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
+#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
+#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
+#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
+#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
-#define SDIO_BASE (PERIPH_BASE + 0x18000)
+#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
-#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
-#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
-#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
-#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
-#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
+#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
+#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400U)
+#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408U)
+#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CU)
+#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430U)
+#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444U)
+#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458U)
+#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
+#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
-#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */
-#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
+#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
+#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
+#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
-#define ETH_BASE (AHBPERIPH_BASE + 0x8000)
+#define ETH_BASE (AHBPERIPH_BASE + 0x00008000U)
#define ETH_MAC_BASE (ETH_BASE)
-#define ETH_MMC_BASE (ETH_BASE + 0x0100)
-#define ETH_PTP_BASE (ETH_BASE + 0x0700)
-#define ETH_DMA_BASE (ETH_BASE + 0x1000)
+#define ETH_MMC_BASE (ETH_BASE + 0x00000100U)
+#define ETH_PTP_BASE (ETH_BASE + 0x00000700U)
+#define ETH_DMA_BASE (ETH_BASE + 0x00001000U)
-#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
/*!< USB registers base address */
-#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
+#define USB_OTG_FS_PERIPH_BASE 0x50000000U
-#define USB_OTG_GLOBAL_BASE ((uint32_t )0x00000000)
-#define USB_OTG_DEVICE_BASE ((uint32_t )0x00000800)
-#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x00000900)
-#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0x00000B00)
-#define USB_OTG_EP_REG_SIZE ((uint32_t )0x00000020)
-#define USB_OTG_HOST_BASE ((uint32_t )0x00000400)
-#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x00000440)
-#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x00000500)
-#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x00000020)
-#define USB_OTG_PCGCCTL_BASE ((uint32_t )0x00000E00)
-#define USB_OTG_FIFO_BASE ((uint32_t )0x00001000)
-#define USB_OTG_FIFO_SIZE ((uint32_t )0x00001000)
+#define USB_OTG_GLOBAL_BASE 0x00000000U
+#define USB_OTG_DEVICE_BASE 0x00000800U
+#define USB_OTG_IN_ENDPOINT_BASE 0x00000900U
+#define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00U
+#define USB_OTG_EP_REG_SIZE 0x00000020U
+#define USB_OTG_HOST_BASE 0x00000400U
+#define USB_OTG_HOST_PORT_BASE 0x00000440U
+#define USB_OTG_HOST_CHANNEL_BASE 0x00000500U
+#define USB_OTG_HOST_CHANNEL_SIZE 0x00000020U
+#define USB_OTG_PCGCCTL_BASE 0x00000E00U
+#define USB_OTG_FIFO_BASE 0x00001000U
+#define USB_OTG_FIFO_SIZE 0x00001000U
/**
* @}
@@ -951,64 +950,65 @@
* @{
*/
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define UART4 ((USART_TypeDef *) UART4_BASE)
-#define UART5 ((USART_TypeDef *) UART5_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
-#define BKP ((BKP_TypeDef *) BKP_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
-#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
+#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *)TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *)TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *)TIM7_BASE)
+#define RTC ((RTC_TypeDef *)RTC_BASE)
+#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *)SPI3_BASE)
+#define USART2 ((USART_TypeDef *)USART2_BASE)
+#define USART3 ((USART_TypeDef *)USART3_BASE)
+#define UART4 ((USART_TypeDef *)UART4_BASE)
+#define UART5 ((USART_TypeDef *)UART5_BASE)
+#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
+#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
+#define CAN2 ((CAN_TypeDef *)CAN2_BASE)
+#define BKP ((BKP_TypeDef *)BKP_BASE)
+#define PWR ((PWR_TypeDef *)PWR_BASE)
+#define DAC1 ((DAC_TypeDef *)DAC_BASE)
+#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */
+#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
+#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
+#define ADC2 ((ADC_TypeDef *)ADC2_BASE)
+#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
+#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
+#define USART1 ((USART_TypeDef *)USART1_BASE)
+#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
+#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *)DMA2_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
+#define RCC ((RCC_TypeDef *)RCC_BASE)
+#define CRC ((CRC_TypeDef *)CRC_BASE)
+#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB ((OB_TypeDef *)OB_BASE)
#define ETH ((ETH_TypeDef *) ETH_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
-#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *)USB_OTG_FS_PERIPH_BASE)
/**
* @}
@@ -1078,14 +1078,24 @@
#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
-#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */
-#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */
-#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */
-#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */
-#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */
-#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */
-#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */
-#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */
+#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
+#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
+#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
+#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
+#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
+#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
+#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
+#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
+
+/* Legacy defines */
+#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
+#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
+#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
+#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
+#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
+#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
+#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
+#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
#define PWR_CR_DBP_Pos (8U)
#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
@@ -1401,12 +1411,23 @@
#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
+ */
+#define RCC_PLL2_SUPPORT /*!< Support PLL2 */
+
#define RCC_CR_PLL2ON_Pos (26U)
#define RCC_CR_PLL2ON_Msk (0x1U << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */
#define RCC_CR_PLL2RDY_Pos (27U)
#define RCC_CR_PLL2RDY_Msk (0x1U << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
+ */
+#define RCC_PLLI2S_SUPPORT /*!< Support PLL3 (PLLI2S)*/
+
#define RCC_CR_PLL3ON_Pos (28U)
#define RCC_CR_PLL3ON_Msk (0x1U << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */
@@ -1422,9 +1443,9 @@
#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
@@ -1433,9 +1454,9 @@
#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
@@ -1446,15 +1467,15 @@
#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
@@ -1464,11 +1485,11 @@
#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
@@ -1478,11 +1499,11 @@
#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
#define RCC_CFGR_ADCPRE_Pos (14U)
@@ -1491,10 +1512,10 @@
#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */
+#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
+#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
+#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
+#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
#define RCC_CFGR_PLLSRC_Pos (16U)
#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
@@ -1513,8 +1534,8 @@
#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
+#define RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U /*!< PREDIV1 clock not divided for PLL entry */
+#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U /*!< PREDIV1 clock divided by 2 for PLL entry */
#define RCC_CFGR_PLLMULL4_Pos (19U)
#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
@@ -1534,7 +1555,7 @@
#define RCC_CFGR_PLLMULL9_Pos (18U)
#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock * 9 */
-#define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */
+#define RCC_CFGR_PLLMULL6_5 0x00340000U /*!< PLL input clock * 6.5 */
#define RCC_CFGR_OTGFSPRE_Pos (22U)
#define RCC_CFGR_OTGFSPRE_Msk (0x1U << RCC_CFGR_OTGFSPRE_Pos) /*!< 0x00400000 */
@@ -1549,15 +1570,15 @@
#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
#define RCC_CFGR_MCO_3 (0x8U << RCC_CFGR_MCO_Pos) /*!< 0x08000000 */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
-#define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/
-#define RCC_CFGR_MCO_PLL3CLK_DIV2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
-#define RCC_CFGR_MCO_EXT_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
-#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */
+#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
+#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
+#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
+#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
+#define RCC_CFGR_MCO_PLL2CLK 0x08000000U /*!< PLL2 clock selected as MCO source*/
+#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x09000000U /*!< PLL3 clock divided by 2 selected as MCO source*/
+#define RCC_CFGR_MCO_EXT_HSE 0x0A000000U /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
+#define RCC_CFGR_MCO_PLL3CLK 0x0B000000U /*!< PLL3 clock selected as MCO source */
/* Reference defines */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCO
@@ -1923,10 +1944,10 @@
#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
+#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
+#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
@@ -1982,7 +2003,7 @@
#define RCC_CFGR2_PREDIV1_2 (0x4U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */
#define RCC_CFGR2_PREDIV1_3 (0x8U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */
-#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
+#define RCC_CFGR2_PREDIV1_DIV1 0x00000000U /*!< PREDIV1 input clock not divided */
#define RCC_CFGR2_PREDIV1_DIV2_Pos (0U)
#define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */
#define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */
@@ -2038,7 +2059,7 @@
#define RCC_CFGR2_PREDIV2_2 (0x4U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000040 */
#define RCC_CFGR2_PREDIV2_3 (0x8U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000080 */
-#define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */
+#define RCC_CFGR2_PREDIV2_DIV1 0x00000000U /*!< PREDIV2 input clock not divided */
#define RCC_CFGR2_PREDIV2_DIV2_Pos (4U)
#define RCC_CFGR2_PREDIV2_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV2_DIV2_Pos) /*!< 0x00000010 */
#define RCC_CFGR2_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2_Msk /*!< PREDIV2 input clock divided by 2 */
@@ -2165,7 +2186,7 @@
#define RCC_CFGR2_PREDIV1SRC_PLL2_Pos (16U)
#define RCC_CFGR2_PREDIV1SRC_PLL2_Msk (0x1U << RCC_CFGR2_PREDIV1SRC_PLL2_Pos) /*!< 0x00010000 */
#define RCC_CFGR2_PREDIV1SRC_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2_Msk /*!< PLL2 selected as PREDIV1 entry clock source */
-#define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */
+#define RCC_CFGR2_PREDIV1SRC_HSE 0x00000000U /*!< HSE selected as PREDIV1 entry clock source */
#define RCC_CFGR2_I2S2SRC_Pos (17U)
#define RCC_CFGR2_I2S2SRC_Msk (0x1U << RCC_CFGR2_I2S2SRC_Pos) /*!< 0x00020000 */
#define RCC_CFGR2_I2S2SRC RCC_CFGR2_I2S2SRC_Msk /*!< I2S2 entry clock source */
@@ -2704,7 +2725,7 @@
#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */
+#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
#define AFIO_EVCR_PIN_PX1_Pos (0U)
#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
@@ -2759,7 +2780,7 @@
#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */
+#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
#define AFIO_EVCR_PORT_PB_Pos (4U)
#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
@@ -2798,7 +2819,7 @@
#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
@@ -2813,7 +2834,7 @@
#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
@@ -2828,7 +2849,7 @@
#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
@@ -2846,7 +2867,7 @@
#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
@@ -2865,7 +2886,7 @@
#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
/*!< CAN_REMAP configuration */
-#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
@@ -2888,7 +2909,7 @@
#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
@@ -2944,7 +2965,7 @@
#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
@@ -2965,7 +2986,7 @@
#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
@@ -2986,7 +3007,7 @@
#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
@@ -3007,7 +3028,7 @@
#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
@@ -3042,7 +3063,7 @@
#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
@@ -3063,7 +3084,7 @@
#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
@@ -3084,7 +3105,7 @@
#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
@@ -3105,7 +3126,7 @@
#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
@@ -3140,7 +3161,7 @@
#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
@@ -3161,7 +3182,7 @@
#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
@@ -3182,7 +3203,7 @@
#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
@@ -3203,7 +3224,7 @@
#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
@@ -3238,7 +3259,7 @@
#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
@@ -3259,7 +3280,7 @@
#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
@@ -3280,7 +3301,7 @@
#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
@@ -3301,7 +3322,7 @@
#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
@@ -3327,440 +3348,6 @@
/******************************************************************************/
/* */
-/* SystemTick */
-/* */
-/******************************************************************************/
-
-/***************** Bit definition for SysTick_CTRL register *****************/
-#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
-#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
-#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
-#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
-
-/***************** Bit definition for SysTick_LOAD register *****************/
-#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/***************** Bit definition for SysTick_VAL register ******************/
-#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
-
-/***************** Bit definition for SysTick_CALIB register ****************/
-#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
-#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
-#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/* */
-/* Nested Vectored Interrupt Controller */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for NVIC_ISER register *******************/
-#define NVIC_ISER_SETENA_Pos (0U)
-#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
-#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
-#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
-#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
-#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
-#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
-#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
-#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
-#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
-#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
-#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
-#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
-#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
-#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
-#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
-#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
-#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
-#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
-#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
-#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
-#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
-#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
-#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
-#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
-#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
-#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
-#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
-#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
-#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
-#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
-#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
-#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
-#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICER register *******************/
-#define NVIC_ICER_CLRENA_Pos (0U)
-#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
-#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
-#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
-#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
-#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
-#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
-#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
-#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
-#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
-#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
-#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
-#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
-#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
-#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
-#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
-#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
-#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
-#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
-#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
-#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
-#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
-#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
-#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
-#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
-#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
-#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
-#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
-#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
-#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
-#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
-#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
-#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
-#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ISPR register *******************/
-#define NVIC_ISPR_SETPEND_Pos (0U)
-#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
-#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_ICPR register *******************/
-#define NVIC_ICPR_CLRPEND_Pos (0U)
-#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
-#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
-#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
-#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
-#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
-#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
-#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
-#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
-#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
-#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
-#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
-#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
-#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
-#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
-#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
-#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
-#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
-#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
-#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
-#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
-#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
-#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
-#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
-#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
-#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
-#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
-#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
-#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
-#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
-#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
-#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
-#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
-#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_IABR register *******************/
-#define NVIC_IABR_ACTIVE_Pos (0U)
-#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
-#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
-#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
-#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
-#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
-#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
-#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
-#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
-#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
-#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
-#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
-#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
-#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
-#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
-#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
-#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
-#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
-#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
-#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
-#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
-#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
-#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
-#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
-#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
-#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
-#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
-#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
-#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
-#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
-#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
-#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
-#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
-#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
-#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for NVIC_PRI0 register *******************/
-#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
-#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
-#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
-#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
-
-/****************** Bit definition for NVIC_PRI1 register *******************/
-#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
-#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
-#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
-#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
-
-/****************** Bit definition for NVIC_PRI2 register *******************/
-#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
-#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
-#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
-#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
-
-/****************** Bit definition for NVIC_PRI3 register *******************/
-#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
-#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
-#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
-#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
-
-/****************** Bit definition for NVIC_PRI4 register *******************/
-#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
-#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
-#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
-#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
-
-/****************** Bit definition for NVIC_PRI5 register *******************/
-#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
-#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
-#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
-#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
-
-/****************** Bit definition for NVIC_PRI6 register *******************/
-#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
-#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
-#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
-#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
-
-/****************** Bit definition for NVIC_PRI7 register *******************/
-#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
-#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
-#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
-#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
-
-/****************** Bit definition for SCB_CPUID register *******************/
-#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
-#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
-#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
-#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
-#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
-
-/******************* Bit definition for SCB_ICSR register *******************/
-#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
-#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
-#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
-#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
-#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
-#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
-#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
-#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
-
-/******************* Bit definition for SCB_VTOR register *******************/
-#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
-#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
-
-/*!<***************** Bit definition for SCB_AIRCR register *******************/
-#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
-#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
-#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
-
-#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
-#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-
-/* prority group configuration */
-#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
-#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/******************* Bit definition for SCB_SCR register ********************/
-#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
-#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
-#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
-
-/******************** Bit definition for SCB_CCR register *******************/
-#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
-#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
-#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
-#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/******************* Bit definition for SCB_SHPR register ********************/
-#define SCB_SHPR_PRI_N_Pos (0U)
-#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
-#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define SCB_SHPR_PRI_N1_Pos (8U)
-#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
-#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define SCB_SHPR_PRI_N2_Pos (16U)
-#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
-#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define SCB_SHPR_PRI_N3_Pos (24U)
-#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
-#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/****************** Bit definition for SCB_SHCSR register *******************/
-#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
-#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
-#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
-#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
-#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
-#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
-#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
-#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
-#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
-#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
-#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
-#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
-#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
-#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
-
-/******************* Bit definition for SCB_CFSR register *******************/
-/*!< MFSR */
-#define SCB_CFSR_IACCVIOL_Pos (0U)
-#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */
-#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
-#define SCB_CFSR_DACCVIOL_Pos (1U)
-#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */
-#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
-#define SCB_CFSR_MUNSTKERR_Pos (3U)
-#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */
-#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_MSTKERR_Pos (4U)
-#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */
-#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_MMARVALID_Pos (7U)
-#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */
-#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define SCB_CFSR_IBUSERR_Pos (8U)
-#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */
-#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
-#define SCB_CFSR_PRECISERR_Pos (9U)
-#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */
-#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
-#define SCB_CFSR_IMPRECISERR_Pos (10U)
-#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */
-#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
-#define SCB_CFSR_UNSTKERR_Pos (11U)
-#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */
-#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
-#define SCB_CFSR_STKERR_Pos (12U)
-#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */
-#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
-#define SCB_CFSR_BFARVALID_Pos (15U)
-#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */
-#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define SCB_CFSR_UNDEFINSTR_Pos (16U)
-#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */
-#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */
-#define SCB_CFSR_INVSTATE_Pos (17U)
-#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */
-#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
-#define SCB_CFSR_INVPC_Pos (18U)
-#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */
-#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
-#define SCB_CFSR_NOCP_Pos (19U)
-#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */
-#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
-#define SCB_CFSR_UNALIGNED_Pos (24U)
-#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */
-#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define SCB_CFSR_DIVBYZERO_Pos (25U)
-#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */
-#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/******************* Bit definition for SCB_HFSR register *******************/
-#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */
-#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
-
-/******************* Bit definition for SCB_DFSR register *******************/
-#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
-#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
-#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
-#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
-#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
-
-/******************* Bit definition for SCB_MMFAR register ******************/
-#define SCB_MMFAR_ADDRESS_Pos (0U)
-#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
-
-/******************* Bit definition for SCB_BFAR register *******************/
-#define SCB_BFAR_ADDRESS_Pos (0U)
-#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
-#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
-
-/******************* Bit definition for SCB_afsr register *******************/
-#define SCB_AFSR_IMPDEF_Pos (0U)
-#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
-#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
-
-/******************************************************************************/
-/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
@@ -3848,7 +3435,8 @@
#define EXTI_IMR_IM17 EXTI_IMR_MR17
#define EXTI_IMR_IM18 EXTI_IMR_MR18
#define EXTI_IMR_IM19 EXTI_IMR_MR19
-
+#define EXTI_IMR_IM 0x000FFFFFU /*!< Interrupt Mask All */
+
/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0_Pos (0U)
#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
@@ -5277,10 +4865,6 @@
#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-#define TIM_SMCR_OCCS_Pos (3U)
-#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
-#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
-
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
@@ -5625,9 +5209,6 @@
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos (15U)
-#define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
-#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
#define TIM_CNT_CNT_Pos (0U)
@@ -5731,8 +5312,6 @@
#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-/******************* Bit definition for TIM_OR register ********************/
-
/******************************************************************************/
/* */
/* Real-Time Clock */
@@ -12675,7 +12254,11 @@
/* Serial Peripheral Interface */
/* */
/******************************************************************************/
-
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie)
+ */
+#define SPI_I2S_SUPPORT /*!< I2S support */
+#define I2S2_I2S3_CLOCK_FEATURE
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_CPHA_Pos (0U)
#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
@@ -12918,8 +12501,8 @@
#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
+#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
#define I2C_OAR1_ADD0_Pos (0U)
#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
@@ -12964,6 +12547,11 @@
#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR_Pos (0U)
+#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
+#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
+
/******************* Bit definition for I2C_SR1 register ********************/
#define I2C_SR1_SB_Pos (0U)
#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
@@ -13538,14 +13126,14 @@
#define ETH_MACCR_IFG_Pos (17U)
#define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
-#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
-#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
-#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
-#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
-#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
-#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
-#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
+#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
+#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
+#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
+#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
+#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
+#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
+#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
#define ETH_MACCR_CSD_Pos (16U)
#define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
@@ -13574,10 +13162,10 @@
#define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
a transmission attempt during retries after a collision: 0 =< r <2^k */
-#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
-#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
-#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
-#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
+#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
+#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
+#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
+#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
#define ETH_MACCR_DC_Pos (4U)
#define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
@@ -13652,7 +13240,7 @@
#define ETH_MACMIIAR_CR_Pos (2U)
#define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
-#define ETH_MACMIIAR_CR_DIV42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
+#define ETH_MACMIIAR_CR_DIV42 0x00000000U /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
#define ETH_MACMIIAR_CR_DIV16_Pos (3U)
#define ETH_MACMIIAR_CR_DIV16_Msk (0x1U << ETH_MACMIIAR_CR_DIV16_Pos) /*!< 0x00000008 */
#define ETH_MACMIIAR_CR_DIV16 ETH_MACMIIAR_CR_DIV16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
@@ -13681,7 +13269,7 @@
#define ETH_MACFCR_PLT_Pos (4U)
#define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
-#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
+#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
#define ETH_MACFCR_PLT_Minus28_Pos (4U)
#define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
@@ -13796,12 +13384,12 @@
#define ETH_MACA1HR_MBC_Pos (24U)
#define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
#define ETH_MACA1HR_MACA1H_Pos (0U)
#define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
@@ -13821,12 +13409,12 @@
#define ETH_MACA2HR_MBC_Pos (24U)
#define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
-#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
#define ETH_MACA2HR_MACA2H_Pos (0U)
#define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
@@ -13846,12 +13434,12 @@
#define ETH_MACA3HR_MBC_Pos (24U)
#define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
-#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
+#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
#define ETH_MACA3HR_MACA3H_Pos (0U)
#define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
@@ -14040,43 +13628,43 @@
#define ETH_DMABMR_RDP_Pos (17U)
#define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
-#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
+#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
#define ETH_DMABMR_FB_Pos (16U)
#define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
#define ETH_DMABMR_RTPR_Pos (14U)
#define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
-#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
-#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
-#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
-#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
#define ETH_DMABMR_PBL_Pos (8U)
#define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
-#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
#define ETH_DMABMR_DSL_Pos (2U)
#define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
@@ -14133,7 +13721,7 @@
#define ETH_DMASR_TPS_Pos (20U)
#define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
-#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
#define ETH_DMASR_TPS_Fetching_Pos (20U)
#define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
@@ -14152,7 +13740,7 @@
#define ETH_DMASR_RPS_Pos (17U)
#define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
-#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
#define ETH_DMASR_RPS_Fetching_Pos (17U)
#define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
@@ -14233,14 +13821,14 @@
#define ETH_DMAOMR_TTC_Pos (14U)
#define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
-#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
#define ETH_DMAOMR_ST_Pos (13U)
#define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
@@ -14253,10 +13841,10 @@
#define ETH_DMAOMR_RTC_Pos (3U)
#define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
-#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
-#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
-#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
-#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
#define ETH_DMAOMR_OSF_Pos (2U)
#define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
@@ -14533,10 +14121,11 @@
#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
-#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
-#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
@@ -15673,7 +15262,7 @@
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
/****************************** DMA Instances *********************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
@@ -15706,6 +15295,9 @@
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
+
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
@@ -15729,6 +15321,8 @@
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7))
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
+
#define IS_TIM_CC1_INSTANCE(INSTANCE)\
(((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
@@ -15905,6 +15499,20 @@
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
((INSTANCE) == TIM1)
+#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+ ((INSTANCE) == TIM2) || \
+ ((INSTANCE) == TIM3) || \
+ ((INSTANCE) == TIM4) || \
+ ((INSTANCE) == TIM5))
+
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
+
/****************************** END TIM Instances *****************************/
@@ -15977,10 +15585,14 @@
/****************************** USB Instances ********************************/
#define IS_ETH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ETH)
+#define RCC_HSE_MIN 3000000U
+#define RCC_HSE_MAX 25000000U
+
+#define RCC_MAX_FREQUENCY 72000000U
/**
* @}
-*/
+ */
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
@@ -15996,14 +15608,14 @@
#define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
#define USB_HP_IRQn CAN1_TX_IRQn
#define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn
-#define USBWakeUp_IRQn OTG_FS_WKUP_IRQn
#define CEC_IRQn OTG_FS_WKUP_IRQn
+#define USBWakeUp_IRQn OTG_FS_WKUP_IRQn
#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
#define TIM9_IRQn TIM1_BRK_IRQn
+#define TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
-#define TIM11_IRQn TIM1_TRG_COM_IRQn
#define TIM10_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
@@ -16017,20 +15629,19 @@
#define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
#define USB_HP_IRQHandler CAN1_TX_IRQHandler
#define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler
-#define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler
#define CEC_IRQHandler OTG_FS_WKUP_IRQHandler
+#define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler
#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
#define TIM9_IRQHandler TIM1_BRK_IRQHandler
+#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
#define TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
#define TIM6_DAC_IRQHandler TIM6_IRQHandler
-
/**
* @}
*/
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f1xx.h b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f1xx.h
index 233d1b3..333095b 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f1xx.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/stm32f1xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -108,10 +108,10 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number
+ * @brief CMSIS Device version number V4.2.0
*/
-#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
-#define __STM32F1_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
+#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/system_stm32f1xx.c b/ext/hal/st/stm32cube/stm32f1xx/soc/system_stm32f1xx.c
index e78886b..789b551 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/system_stm32f1xx.c
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/system_stm32f1xx.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f1xx.c
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@@ -35,7 +35,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -93,12 +93,12 @@
*/
#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+ #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+ #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
@@ -110,7 +110,7 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
@@ -134,13 +134,13 @@
* Clock Definitions
*******************************************************************************/
#if defined(STM32F100xB) ||defined(STM32F100xE)
- uint32_t SystemCoreClock = 24000000; /*!< System Clock Frequency (Core Clock) */
+ uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */
#else /*!< HSI Selected as System Clock source */
- uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */
+ uint32_t SystemCoreClock = 72000000U; /*!< System Clock Frequency (Core Clock) */
#endif
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
@@ -176,42 +176,42 @@
{
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
+ RCC->CR |= 0x00000001U;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC)
- RCC->CFGR &= (uint32_t)0xF8FF0000;
+ RCC->CFGR &= 0xF8FF0000U;
#else
- RCC->CFGR &= (uint32_t)0xF0FF0000;
+ RCC->CFGR &= 0xF0FF0000U;
#endif /* STM32F105xC */
/* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
+ RCC->CR &= 0xFEF6FFFFU;
/* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
+ RCC->CR &= 0xFFFBFFFFU;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
- RCC->CFGR &= (uint32_t)0xFF80FFFF;
+ RCC->CFGR &= 0xFF80FFFFU;
#if defined(STM32F105xC) || defined(STM32F107xC)
/* Reset PLL2ON and PLL3ON bits */
- RCC->CR &= (uint32_t)0xEBFFFFFF;
+ RCC->CR &= 0xEBFFFFFFU;
/* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x00FF0000;
+ RCC->CIR = 0x00FF0000U;
/* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000;
+ RCC->CFGR2 = 0x00000000U;
#elif defined(STM32F100xB) || defined(STM32F100xE)
/* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000;
+ RCC->CIR = 0x009F0000U;
/* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000;
+ RCC->CFGR2 = 0x00000000U;
#else
/* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000;
+ RCC->CIR = 0x009F0000U;
#endif /* STM32F105xC */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
@@ -264,14 +264,14 @@
*/
void SystemCoreClockUpdate (void)
{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+ uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
#if defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
+ uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
#endif /* STM32F105xC */
#if defined(STM32F100xB) || defined(STM32F100xE)
- uint32_t prediv1factor = 0;
+ uint32_t prediv1factor = 0U;
#endif /* STM32F100xB or STM32F100xE */
/* Get SYSCLK source -------------------------------------------------------*/
@@ -279,37 +279,37 @@
switch (tmp)
{
- case 0x00: /* HSI used as system clock */
+ case 0x00U: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
- case 0x04: /* HSE used as system clock */
+ case 0x04U: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
- case 0x08: /* PLL used as system clock */
+ case 0x08U: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
#if !defined(STM32F105xC) && !defined(STM32F107xC)
- pllmull = ( pllmull >> 18) + 2;
+ pllmull = ( pllmull >> 18U) + 2U;
- if (pllsource == 0x00)
+ if (pllsource == 0x00U)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
}
else
{
#if defined(STM32F100xB) || defined(STM32F100xE)
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
#else
/* HSE selected as PLL clock entry */
if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
{/* HSE oscillator clock divided by 2 */
- SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+ SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
}
else
{
@@ -318,30 +318,30 @@
#endif
}
#else
- pllmull = pllmull >> 18;
+ pllmull = pllmull >> 18U;
- if (pllmull != 0x0D)
+ if (pllmull != 0x0DU)
{
- pllmull += 2;
+ pllmull += 2U;
}
else
{ /* PLL multiplication factor = PLL input clock * 6.5 */
- pllmull = 13 / 2;
+ pllmull = 13U / 2U;
}
- if (pllsource == 0x00)
+ if (pllsource == 0x00U)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
}
else
{/* PREDIV1 selected as PLL clock entry */
/* Get PREDIV1 clock source and division factor */
prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
- if (prediv1source == 0)
+ if (prediv1source == 0U)
{
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
@@ -350,8 +350,8 @@
{/* PLL2 clock selected as PREDIV1 clock entry */
/* Get PREDIV2 division factor and PLL2 multiplication factor */
- prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
- pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
+ prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
+ pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
}
}
@@ -365,7 +365,7 @@
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
@@ -394,13 +394,13 @@
required, then adjust the Register Addresses */
/* Enable FSMC clock */
- RCC->AHBENR = 0x00000114;
+ RCC->AHBENR = 0x00000114U;
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
- RCC->APB2ENR = 0x000001E0;
+ RCC->APB2ENR = 0x000001E0U;
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
@@ -413,23 +413,23 @@
/*---------------- NE3 configuration ----------------------------------------*/
/*---------------- NBL0, NBL1 configuration ---------------------------------*/
- GPIOD->CRL = 0x44BB44BB;
- GPIOD->CRH = 0xBBBBBBBB;
+ GPIOD->CRL = 0x44BB44BBU;
+ GPIOD->CRH = 0xBBBBBBBBU;
- GPIOE->CRL = 0xB44444BB;
- GPIOE->CRH = 0xBBBBBBBB;
+ GPIOE->CRL = 0xB44444BBU;
+ GPIOE->CRH = 0xBBBBBBBBU;
- GPIOF->CRL = 0x44BBBBBB;
- GPIOF->CRH = 0xBBBB4444;
+ GPIOF->CRL = 0x44BBBBBBU;
+ GPIOF->CRH = 0xBBBB4444U;
- GPIOG->CRL = 0x44BBBBBB;
- GPIOG->CRH = 0x444B4B44;
+ GPIOG->CRL = 0x44BBBBBBU;
+ GPIOG->CRH = 0x444B4B44U;
/*---------------- FSMC Configuration ---------------------------------------*/
/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
- FSMC_Bank1->BTCR[4] = 0x00001091;
- FSMC_Bank1->BTCR[5] = 0x00110212;
+ FSMC_Bank1->BTCR[4U] = 0x00001091U;
+ FSMC_Bank1->BTCR[5U] = 0x00110212U;
}
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
diff --git a/ext/hal/st/stm32cube/stm32f1xx/soc/system_stm32f1xx.h b/ext/hal/st/stm32cube/stm32f1xx/soc/system_stm32f1xx.h
index 3587015..3652ff5 100644
--- a/ext/hal/st/stm32cube/stm32f1xx/soc/system_stm32f1xx.h
+++ b/ext/hal/st/stm32cube/stm32f1xx/soc/system_stm32f1xx.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f10x.h
* @author MCD Application Team
- * @version V4.1.0
- * @date 29-April-2016
+ * @version V4.2.0
+ * @date 31-March-2017
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -67,8 +67,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
-extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
+extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */
/**
* @}
