| commit | b18309c0d7124b4090e68dec4813b60c45c64ffd | [log] [tgz] |
|---|---|---|
| author | Robert Winkler <rwinkler@antmicro.com> | Wed Dec 02 15:06:49 2020 +0100 |
| committer | Anas Nashif <anas.nashif@intel.com> | Wed Dec 16 12:49:16 2020 -0500 |
| tree | 1537e9d4dd08da6f4336c8a63b90b396f99a0b8e | |
| parent | b827f4d37f33b295d46bd6688a03388313f1a1f9 [diff] |
boards: doc: Add information about generating litex_vexriscv SoC This commit adds more information about the litex_vexrscv board target, including references to related projects and instruction about generating bitstream for the Digilent Arty A7-35T Board. Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
