b6bbc46610bafab4c441f1decd7d01b981a26aef - third_party/github/zephyrproject-rtos/zephyr

commit: b6bbc46610bafab4c441f1decd7d01b981a26aef
[log]
author: Etienne Carriere <etienne.carriere@st.com>
Mon Feb 03 17:33:43 2025 +0100
committer: Benjamin Cabé <kartben@gmail.com>
Wed Mar 26 16:19:09 2025 +0100
tree: e16cbc849152a6e7c1adbb3152eacbfd5c217625
parent: a4e00505dc33ab51044eef7d4e49dce3937f0837 [diff]

tests: drivers: core clock controls for stm32n6 series

Add core clock configuration tests for STM32N6 series boards.
These tests covers CPU clock, system clock, PERCLK and LSE/HSE CSS
configuration.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/CMakeLists.txt[Added - diff]
tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/clear_clocks.overlay[Added - diff]
tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/hse_48.overlay[Added - diff]
tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/hsi_64.overlay[Added - diff]
tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/pll_hse_200.overlay[Added - diff]
tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/pll_hse_600_400.overlay[Added - diff]
tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/pll_hsi_600_400.overlay[Added - diff]
tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/prj.conf[Added - diff]
tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/src/test_stm32_clock_configuration.c[Added - diff]
tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/testcase.yaml[Added - diff]

10 files changed