soc: esp32_net: added esp32_net as an option
to use esp32 core 1 as a separate CPU, also
provide infrastructure to load firmware to
that CPU
Signed-off-by: Felipe Neves <felipe.neves@linaro.org>
diff --git a/soc/xtensa/esp32/esp32-mp.c b/soc/xtensa/esp32/esp32-mp.c
index 4d1c528..fd3b2f1 100644
--- a/soc/xtensa/esp32/esp32-mp.c
+++ b/soc/xtensa/esp32/esp32-mp.c
@@ -60,6 +60,7 @@
*/
void smp_log(const char *msg)
{
+#ifndef CONFIG_ESP32_NETWORK_CORE
k_spinlock_key_t key = k_spin_lock(&loglock);
while (*msg) {
@@ -69,6 +70,7 @@
esp_rom_uart_tx_one_char('\n');
k_spin_unlock(&loglock, key);
+#endif
}
static void appcpu_entry2(void)
@@ -169,7 +171,7 @@
* calls or registers shown are documented, so treat this code with
* extreme caution.
*/
-static void appcpu_start(void)
+void esp_appcpu_start(void *entry_point)
{
smp_log("ESP32: starting APPCPU");
@@ -193,21 +195,11 @@
/* Seems weird that you set the boot address AFTER starting
* the CPU, but this is how they do it...
*/
- esp_rom_ets_set_appcpu_boot_addr((void *)appcpu_entry1);
+ esp_rom_ets_set_appcpu_boot_addr((void *)entry_point);
smp_log("ESP32: APPCPU start sequence complete");
}
-IRAM_ATTR static inline uint32_t prid(void)
-{
- uint32_t id;
-
- __asm__ volatile (
- "rsr.prid %0\n"
- "extui %0,%0,13,1" : "=r" (id));
- return id;
-}
-
IRAM_ATTR static void esp_crosscore_isr(void *arg)
{
ARG_UNUSED(arg);
@@ -217,7 +209,7 @@
z_sched_ipi();
#endif
- const int core_id = prid();
+ const int core_id = esp_core_id();
if (core_id == 0) {
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
@@ -250,7 +242,7 @@
start_rec = &sr;
- appcpu_start();
+ esp_appcpu_start(appcpu_entry1);
while (!alive_flag) {
}
@@ -275,7 +267,7 @@
void arch_sched_ipi(void)
{
- const int core_id = prid();
+ const int core_id = esp_core_id();
if (core_id == 0) {
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
