dts: arm: gigadevice: support gd32f405xx soc
Add support for GD32F405xx series SOCs.
Signed-off-by: HaiLong Yang <cameledyang@pm.me>
diff --git a/dts/arm/gigadevice/gd32f4xx/gd32f405.dtsi b/dts/arm/gigadevice/gd32f4xx/gd32f405.dtsi
new file mode 100644
index 0000000..dd31946
--- /dev/null
+++ b/dts/arm/gigadevice/gd32f4xx/gd32f405.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2021, BrainCo Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <gigadevice/gd32f4xx/gd32f4xx.dtsi>
+
+&cpu0 {
+ clock-frequency = <168000000>;
+};
diff --git a/dts/arm/gigadevice/gd32f4xx/gd32f405vg.dtsi b/dts/arm/gigadevice/gd32f4xx/gd32f405vg.dtsi
new file mode 100644
index 0000000..cccfbff
--- /dev/null
+++ b/dts/arm/gigadevice/gd32f4xx/gd32f405vg.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <gigadevice/gd32f4xx/gd32f405.dtsi>
+
+/ {
+ soc {
+ flash-controller@40023c00 {
+ flash0: flash@8000000 {
+ reg = <0x08000000 DT_SIZE_K(1024)>;
+ };
+ };
+
+ sram1: memory@2001c000 {
+ compatible = "mmio-sram";
+ reg = <0x2001c000 DT_SIZE_K(16)>;
+ };
+ };
+};
