| commit | bc69500b0e101087d5c9f7261c2e729882aee88a | [log] [tgz] |
|---|---|---|
| author | Henrik Brix Andersen <hebad@vestas.com> | Tue Jan 09 11:23:17 2024 +0100 |
| committer | Anas Nashif <anas.nashif@intel.com> | Wed Jan 10 20:59:55 2024 -0500 |
| tree | a2ff9f6ef50f7f36abf488643f451a4d58dcc2d7 | |
| parent | 0f73e8fd3e2f9594dd223b93b891808891e83929 [diff] |
drivers: can: stm32h7: fdcan: add support for domain clock and divider Add support for specifying the domain/kernel clock along with a common clock divider for the STM32H7 CAN controller driver via devicetree. Previously, the driver only supported using the PLL1_Q clock for domain/kernel clock, but now the driver defaults to the HSE clock, which is the chip default. Update existing boards to continue to use the PLL1_Q clock. Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>