| commit | be881d4cf269d3126722ce42e3c198b5960a3f3b | [log] [tgz] |
|---|---|---|
| author | Kai Vehmanen <kai.vehmanen@linux.intel.com> | Wed Feb 14 15:23:52 2024 +0200 |
| committer | Anas Nashif <anas.nashif@intel.com> | Fri Mar 15 21:45:57 2024 -0400 |
| tree | dbf943c8feca545ca0b8716176b5490090fc6863 | |
| parent | d89e8052da79f9542a18cb14d53d5d2e00976ef1 [diff] |
arch: xtensa: add isync to interrupt vector On Intel ADSP platforms, additional "isync" is needed in interrupt vector to synchronize icache when core is woken up from deeper sleep state by an interrupt. This is only needed if DSP clock gating is enabled. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>