soc: xlnx: versal*: add cache line size defaults for APU

Set DCACHE_LINE_SIZE and ICACHE_LINE_SIZE configdefaults to 64 bytes
for the APU (Cortex-A) configurations on Versal, Versal2, and
Versalnet SoCs.

Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>