| commit | c723d8b8d3ac5e0c103c66f82e0b320435d24929 | [log] [tgz] |
|---|---|---|
| author | Flavio Ceolin <flavio.ceolin@intel.com> | Wed Feb 15 23:49:15 2023 +0000 |
| committer | Anas Nashif <anas.nashif@intel.com> | Sat Aug 26 16:50:40 2023 -0400 |
| tree | 9a17d30a3e7cf6367a750e09e1d0e13ca78389a3 | |
| parent | 24148718fc6e8f36d7465d374a3b8f06e8543c22 [diff] |
xtensa: Add missing synchronization rsync after writing MISC0..3 or EXCSAVE1..7 registers is needed before reading them. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>