kconfig: Make the CPU_HAS_FPU_DOUBLE_PRECISION option global. This option now applies to the RISC-V architecture and is no longer a ARM only configuration. Signed-off-by: Corey Wharton <coreyw7@fb.com>
diff --git a/arch/Kconfig b/arch/Kconfig index e94c740..4a4102a 100644 --- a/arch/Kconfig +++ b/arch/Kconfig
@@ -464,6 +464,13 @@ This option is enabled when the CPU has hardware floating point unit. +config CPU_HAS_FPU_DOUBLE_PRECISION + bool + select CPU_HAS_FPU + help + When enabled, this indicates that the CPU has a double floating point + precision unit. + config CPU_HAS_MPU bool help @@ -531,13 +538,6 @@ This option allows multiple threads to use the floating point registers. -config FLOAT_64BIT - bool "Double precision floating point" - depends on FLOAT - depends on RISCV - help - This option means that floating point registers are 64bit width. - config ARCH string help
diff --git a/cmake/compiler/gcc/target_riscv.cmake b/cmake/compiler/gcc/target_riscv.cmake index 94b8d1f..7d758a9 100644 --- a/cmake/compiler/gcc/target_riscv.cmake +++ b/cmake/compiler/gcc/target_riscv.cmake
@@ -12,16 +12,18 @@ string(CONCAT riscv_march ${riscv_march} "32ima") endif() -if(CONFIG_FLOAT_64BIT) - if(CONFIG_FLOAT_HARD) - string(CONCAT riscv_mabi ${riscv_mabi} "d") +if(CONFIG_FLOAT) + if(CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION) + if(CONFIG_FLOAT_HARD) + string(CONCAT riscv_mabi ${riscv_mabi} "d") + endif() + string(CONCAT riscv_march ${riscv_march} "fd") + else() + if(CONFIG_FLOAT_HARD) + string(CONCAT riscv_mabi ${riscv_mabi} "f") + endif() + string(CONCAT riscv_march ${riscv_march} "f") endif() - string(CONCAT riscv_march ${riscv_march} "fd") -elseif(CONFIG_FLOAT) - if(CONFIG_FLOAT_HARD) - string(CONCAT riscv_mabi ${riscv_mabi} "f") - endif() - string(CONCAT riscv_march ${riscv_march} "f") endif() if(CONFIG_COMPRESSED_ISA)
diff --git a/include/arch/riscv/arch.h b/include/arch/riscv/arch.h index c136a57..a264d28 100644 --- a/include/arch/riscv/arch.h +++ b/include/arch/riscv/arch.h
@@ -40,7 +40,7 @@ #define RV_REGSHIFT 2 #endif -#ifdef CONFIG_FLOAT_64BIT +#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION #define RV_OP_LOADFPREG fld #define RV_OP_STOREFPREG fsd #else
diff --git a/include/arch/riscv/exp.h b/include/arch/riscv/exp.h index 487889d..03c7e7b 100644 --- a/include/arch/riscv/exp.h +++ b/include/arch/riscv/exp.h
@@ -42,7 +42,7 @@ #endif #if !defined(RV_FP_TYPE) && defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING) -#ifdef CONFIG_FLOAT_64BIT +#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION #define RV_FP_TYPE u64_t #else #define RV_FP_TYPE u32_t
diff --git a/include/arch/riscv/thread.h b/include/arch/riscv/thread.h index 6190a10..7068e28 100644 --- a/include/arch/riscv/thread.h +++ b/include/arch/riscv/thread.h
@@ -23,7 +23,7 @@ #include <zephyr/types.h> #if !defined(RV_FP_TYPE) && defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING) -#ifdef CONFIG_FLOAT_64BIT +#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION #define RV_FP_TYPE u64_t #else #define RV_FP_TYPE u32_t
diff --git a/soc/arm/Kconfig b/soc/arm/Kconfig index 3043d08..5855b84 100644 --- a/soc/arm/Kconfig +++ b/soc/arm/Kconfig
@@ -57,14 +57,6 @@ RAM region size for the NRF_SPU peripheral endif -config CPU_HAS_FPU_DOUBLE_PRECISION - bool - depends on CPU_CORTEX_M7 - select CPU_HAS_FPU - help - When enabled, indicates that the SoC has a double - floating point precision unit. - config HAS_SWO bool help
diff --git a/tests/kernel/fp_sharing/float_disable/src/k_float_disable.c b/tests/kernel/fp_sharing/float_disable/src/k_float_disable.c index aade43a..421a038 100644 --- a/tests/kernel/fp_sharing/float_disable/src/k_float_disable.c +++ b/tests/kernel/fp_sharing/float_disable/src/k_float_disable.c
@@ -78,7 +78,7 @@ "usr_fp_thread FP options not set (0x%0x)", usr_fp_thread.base.user_options); -#if defined(CONFIG_ARM) || defined(RISCV) +#if defined(CONFIG_ARM) || defined(CONFIG_RISCV) /* Verify FP mode can only be disabled for current thread */ zassert_true((k_float_disable(&usr_fp_thread) == -EINVAL), "k_float_disable() successful on thread other than current!");
diff --git a/tests/kernel/fp_sharing/generic/src/float_context.h b/tests/kernel/fp_sharing/generic/src/float_context.h index 988958f..87cf796 100644 --- a/tests/kernel/fp_sharing/generic/src/float_context.h +++ b/tests/kernel/fp_sharing/generic/src/float_context.h
@@ -109,7 +109,7 @@ #elif defined(CONFIG_RISCV) struct fp_volatile_register_set { -#ifdef CONFIG_FLOAT_64BIT +#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION u64_t fp[32]; #else u32_t fp[32];
diff --git a/tests/kernel/fp_sharing/generic/src/float_regs_riscv_gcc.h b/tests/kernel/fp_sharing/generic/src/float_regs_riscv_gcc.h index 316d1aa..3b6651e 100644 --- a/tests/kernel/fp_sharing/generic/src/float_regs_riscv_gcc.h +++ b/tests/kernel/fp_sharing/generic/src/float_regs_riscv_gcc.h
@@ -19,7 +19,7 @@ #include <toolchain.h> #include "float_context.h" -#ifdef CONFIG_FLOAT_64BIT +#ifdef CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION #define RV_FPREG_WIDTH 8 #define RV_FPREG_SAVE "fsd " #define RV_FPREG_LOAD "fld "
diff --git a/tests/kernel/fp_sharing/generic/src/test_common.h b/tests/kernel/fp_sharing/generic/src/test_common.h index 24ebe05..7088998 100644 --- a/tests/kernel/fp_sharing/generic/src/test_common.h +++ b/tests/kernel/fp_sharing/generic/src/test_common.h
@@ -9,7 +9,7 @@ /* * Test Thread Parameters */ -#define THREAD_STACK_SIZE 2048 +#define THREAD_STACK_SIZE 1024 #define THREAD_HIGH_PRIORITY 5 #define THREAD_LOW_PRIORITY 10