arch: riscv: imply XIP config pushed to SoC level
'imply XIP' pushed from arch/Kconfig/'config RISCV' to riscv SoCs Kconfig
files to allow riscv SoCs having XIP enabled (or not) at SoC level
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
diff --git a/arch/Kconfig b/arch/Kconfig
index 8b3e80f..5a7ceae 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -122,7 +122,6 @@
select ARCH_HAS_DIRECTED_IPIS
select BARRIER_OPERATIONS_BUILTIN
select ARCH_HAS_THREAD_PRIV_STACK_SPACE_GET if USERSPACE
- imply XIP
help
RISCV architecture
diff --git a/soc/andestech/ae350/Kconfig b/soc/andestech/ae350/Kconfig
index d184845..bfe3805 100644
--- a/soc/andestech/ae350/Kconfig
+++ b/soc/andestech/ae350/Kconfig
@@ -5,6 +5,7 @@
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
+ imply XIP
config SOC_ANDES_AE350
select ATOMIC_OPERATIONS_BUILTIN
diff --git a/soc/efinix/sapphire/Kconfig b/soc/efinix/sapphire/Kconfig
index 4617e73..5c639e1 100644
--- a/soc/efinix/sapphire/Kconfig
+++ b/soc/efinix/sapphire/Kconfig
@@ -12,3 +12,4 @@
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
+ imply XIP
diff --git a/soc/intel/intel_niosv/niosv/Kconfig b/soc/intel/intel_niosv/niosv/Kconfig
index 6d47923..8e21016 100644
--- a/soc/intel/intel_niosv/niosv/Kconfig
+++ b/soc/intel/intel_niosv/niosv/Kconfig
@@ -11,6 +11,7 @@
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
+ imply XIP
config SOC_NIOSV_M
help
diff --git a/soc/ite/ec/it8xxx2/Kconfig b/soc/ite/ec/it8xxx2/Kconfig
index 0dafce0..a7cf5b7 100644
--- a/soc/ite/ec/it8xxx2/Kconfig
+++ b/soc/ite/ec/it8xxx2/Kconfig
@@ -20,6 +20,7 @@
select RISCV_ISA_EXT_M if !(SOC_IT81302BX || SOC_IT81202BX)
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
+ imply XIP
config SOC_IT8XXX2_REG_SET_V1
bool
diff --git a/soc/litex/litex_vexriscv/Kconfig b/soc/litex/litex_vexriscv/Kconfig
index b841a1d..60f0cb3 100644
--- a/soc/litex/litex_vexriscv/Kconfig
+++ b/soc/litex/litex_vexriscv/Kconfig
@@ -9,6 +9,7 @@
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
+ imply XIP
if SOC_LITEX_VEXRISCV
diff --git a/soc/lowrisc/opentitan/Kconfig b/soc/lowrisc/opentitan/Kconfig
index 25670a9..e4a6082 100644
--- a/soc/lowrisc/opentitan/Kconfig
+++ b/soc/lowrisc/opentitan/Kconfig
@@ -19,3 +19,4 @@
# OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode.
select RISCV_VECTORED_MODE
select GEN_IRQ_VECTOR_TABLE
+ imply XIP
diff --git a/soc/microchip/miv/miv/Kconfig b/soc/microchip/miv/miv/Kconfig
index 132818d..58e04c0 100644
--- a/soc/microchip/miv/miv/Kconfig
+++ b/soc/microchip/miv/miv/Kconfig
@@ -7,6 +7,7 @@
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
+ imply XIP
config SOC_MIV
select ATOMIC_OPERATIONS_BUILTIN
diff --git a/soc/microchip/miv/polarfire/Kconfig b/soc/microchip/miv/polarfire/Kconfig
index c096759..a39e34d 100644
--- a/soc/microchip/miv/polarfire/Kconfig
+++ b/soc/microchip/miv/polarfire/Kconfig
@@ -7,6 +7,7 @@
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
+ imply XIP
config SOC_POLARFIRE
select 64BIT
diff --git a/soc/neorv32/Kconfig b/soc/neorv32/Kconfig
index 6df6c6d..c4725545 100644
--- a/soc/neorv32/Kconfig
+++ b/soc/neorv32/Kconfig
@@ -9,6 +9,7 @@
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select RISCV_PRIVILEGED
+ imply XIP
if SOC_NEORV32
diff --git a/soc/nordic/common/vpr/Kconfig b/soc/nordic/common/vpr/Kconfig
index e51c31c..59550da 100644
--- a/soc/nordic/common/vpr/Kconfig
+++ b/soc/nordic/common/vpr/Kconfig
@@ -20,5 +20,6 @@
select ARCH_HAS_CUSTOM_CPU_IDLE
select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
select INCLUDE_RESET_VECTOR
+ imply XIP
help
Enable support for the RISC-V Nordic VPR core.
diff --git a/soc/qemu/virt_riscv/Kconfig b/soc/qemu/virt_riscv/Kconfig
index 1c33823..0145f14 100644
--- a/soc/qemu/virt_riscv/Kconfig
+++ b/soc/qemu/virt_riscv/Kconfig
@@ -10,6 +10,7 @@
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
+ imply XIP
if SOC_FAMILY_QEMU_VIRT_RISCV
diff --git a/soc/renode/riscv_virtual/Kconfig b/soc/renode/riscv_virtual/Kconfig
index 37c4578..8fb2a2f 100644
--- a/soc/renode/riscv_virtual/Kconfig
+++ b/soc/renode/riscv_virtual/Kconfig
@@ -13,3 +13,4 @@
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select RISCV_HAS_PLIC
+ imply XIP
diff --git a/soc/sifive/sifive_freedom/fe300/Kconfig b/soc/sifive/sifive_freedom/fe300/Kconfig
index cde775a..61fe4f5 100644
--- a/soc/sifive/sifive_freedom/fe300/Kconfig
+++ b/soc/sifive/sifive_freedom/fe300/Kconfig
@@ -20,3 +20,5 @@
select ATOMIC_OPERATIONS_C
select INCLUDE_RESET_VECTOR
+
+ imply XIP
diff --git a/soc/sifive/sifive_freedom/fu500/Kconfig b/soc/sifive/sifive_freedom/fu500/Kconfig
index dbe9e07..741bae4 100644
--- a/soc/sifive/sifive_freedom/fu500/Kconfig
+++ b/soc/sifive/sifive_freedom/fu500/Kconfig
@@ -15,6 +15,7 @@
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
+ imply XIP
select 64BIT
select INCLUDE_RESET_VECTOR
diff --git a/soc/sifive/sifive_freedom/fu700/Kconfig b/soc/sifive/sifive_freedom/fu700/Kconfig
index 11804e5..7ebbbd9 100644
--- a/soc/sifive/sifive_freedom/fu700/Kconfig
+++ b/soc/sifive/sifive_freedom/fu700/Kconfig
@@ -14,6 +14,7 @@
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
+ imply XIP
select INCLUDE_RESET_VECTOR
select 64BIT
diff --git a/soc/snps/nsim/arc_v/rmx/Kconfig b/soc/snps/nsim/arc_v/rmx/Kconfig
index 5152b81..2e0ae39 100644
--- a/soc/snps/nsim/arc_v/rmx/Kconfig
+++ b/soc/snps/nsim/arc_v/rmx/Kconfig
@@ -14,3 +14,4 @@
select RISCV_ISA_EXT_ZIFENCEI
select INCLUDE_RESET_VECTOR
select ATOMIC_OPERATIONS_BUILTIN
+ imply XIP
diff --git a/soc/starfive/jh71xx/Kconfig b/soc/starfive/jh71xx/Kconfig
index 823ffe0..7d04259 100644
--- a/soc/starfive/jh71xx/Kconfig
+++ b/soc/starfive/jh71xx/Kconfig
@@ -5,6 +5,7 @@
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
+ imply XIP
config SOC_JH7100
select ATOMIC_OPERATIONS_BUILTIN
diff --git a/soc/telink/tlsr/tlsr951x/Kconfig b/soc/telink/tlsr/tlsr951x/Kconfig
index 80fa44e..82a8c7d 100644
--- a/soc/telink/tlsr/tlsr951x/Kconfig
+++ b/soc/telink/tlsr/tlsr951x/Kconfig
@@ -16,6 +16,7 @@
select ATOMIC_OPERATIONS_BUILTIN
select CPU_HAS_FPU
select INCLUDE_RESET_VECTOR
+ imply XIP
if SOC_SERIES_TLSR951X
