it8xxx2: intc: protect interrupt enable registers of soc

Because these two functions are called from threads and ISR.
And they run a bit-wise OR operation on the interrupt registers.
So protect them to prevent race condition between thread and ISR
context where causing an interrupt won't enable as expected.

eg.
- Pseudo code of thread enable IER1's bit1:
1. load word from IER1 (0x40) and write into CPU register S1
   => S1=0x40
2. Or S1's bit1
   => S1=0x42
(But if an interrupt is triggered here)
3. Store word to IER1 from S1
   => IER1=0x42
(IER1 will be 0x42 not 0x43, IER1's bit0 is disable again due to the
race condition above)

-Pseudo code of ISR enable IER1's bit0
1. load word from IER1 (0x40) write into CPU register S2
   => S2=0x40
2. Or S2's bit0
   => S2=0x41
3. Store word to IER1 from S2
   => IER1=0x41
4. Go back to thread.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
1 file changed