esp32: drivers: clock_control: code refactoring
code refactoring.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
diff --git a/drivers/clock_control/clock_control_esp32.c b/drivers/clock_control/clock_control_esp32.c
index 6c91f12..d895de8 100644
--- a/drivers/clock_control/clock_control_esp32.c
+++ b/drivers/clock_control/clock_control_esp32.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2020 Mohamed ElShahawi.
+ * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,21 +8,16 @@
#define DT_DRV_COMPAT espressif_esp32_rtc
#include <dt-bindings/clock/esp32_clock.h>
-#include <esp_bit_defs.h>
-#include <soc/dport_reg.h>
-#include <esp32/rom/uart.h>
-#include <esp32/rom/rtc.h>
#include <soc/rtc.h>
-#include <soc/rtc_cntl_reg.h>
-#include <drivers/uart.h>
#include <soc/apb_ctrl_reg.h>
+#include <soc/timer_group_reg.h>
+#include <regi2c_ctrl.h>
+#include <hal/clk_gate_ll.h>
#include <soc.h>
#include <drivers/clock_control.h>
-#include <sys/util.h>
+#include <driver/periph_ctrl.h>
#include "clock_control_esp32.h"
-#include "driver/periph_ctrl.h"
-#include <xtensa/core-macros.h>
struct esp32_clock_config {
uint32_t clk_src_sel;
@@ -30,239 +26,119 @@
uint32_t xtal_div;
};
-struct control_regs {
- /** Peripheral control register */
- uint32_t clk;
- /** Peripheral reset register */
- uint32_t rst;
-};
-
-struct bbpll_cfg {
- uint8_t div_ref;
- uint8_t div7_0;
- uint8_t div10_8;
- uint8_t lref;
- uint8_t dcur;
- uint8_t bw;
-};
-
-struct pll_cfg {
- uint8_t dbias_wak;
- uint8_t endiv5;
- uint8_t bbadc_dsmp;
- struct bbpll_cfg bbpll[2];
-};
-
-
-#define PLL_APB_CLK_FREQ 80
-
-#define RTC_PLL_FREQ_320M 0
-#define RTC_PLL_FREQ_480M 1
-
-#define DPORT_CPUPERIOD_SEL_80 0
-#define DPORT_CPUPERIOD_SEL_160 1
-#define DPORT_CPUPERIOD_SEL_240 2
-
#define DEV_CFG(dev) ((struct esp32_clock_config *)(dev->config))
-#define GET_REG_BANK(module_id) ((uint32_t)module_id / 32U)
-#define GET_REG_OFFSET(module_id) ((uint32_t)module_id % 32U)
-
-#define CLOCK_REGS_BANK_COUNT 3
-
-const struct control_regs clock_control_regs[CLOCK_REGS_BANK_COUNT] = {
- [0] = { .clk = DPORT_PERIP_CLK_EN_REG, .rst = DPORT_PERIP_RST_EN_REG },
- [1] = { .clk = DPORT_PERI_CLK_EN_REG, .rst = DPORT_PERI_RST_EN_REG },
- [2] = { .clk = DPORT_WIFI_CLK_EN_REG, .rst = DPORT_CORE_RST_EN_REG }
-};
static uint32_t const xtal_freq[] = {
+ [ESP32_CLK_XTAL_24M] = 24,
+ [ESP32_CLK_XTAL_26M] = 26,
[ESP32_CLK_XTAL_40M] = 40,
- [ESP32_CLK_XTAL_26M] = 26
+ [ESP32_CLK_XTAL_AUTO] = 0
};
-const struct pll_cfg pll_config[] = {
- [RTC_PLL_FREQ_320M] = {
- .dbias_wak = 0,
- .endiv5 = BBPLL_ENDIV5_VAL_320M,
- .bbadc_dsmp = BBPLL_BBADC_DSMP_VAL_320M,
- .bbpll[ESP32_CLK_XTAL_40M] = {
- /* 40mhz */
- .div_ref = 0,
- .div7_0 = 32,
- .div10_8 = 0,
- .lref = 0,
- .dcur = 6,
- .bw = 3,
- },
- .bbpll[ESP32_CLK_XTAL_26M] = {
- /* 26mhz */
- .div_ref = 12,
- .div7_0 = 224,
- .div10_8 = 4,
- .lref = 1,
- .dcur = 0,
- .bw = 1,
- }
- },
- [RTC_PLL_FREQ_480M] = {
- .dbias_wak = 0,
- .endiv5 = BBPLL_ENDIV5_VAL_480M,
- .bbadc_dsmp = BBPLL_BBADC_DSMP_VAL_480M,
- .bbpll[ESP32_CLK_XTAL_40M] = {
- /* 40mhz */
- .div_ref = 0,
- .div7_0 = 28,
- .div10_8 = 0,
- .lref = 0,
- .dcur = 6,
- .bw = 3,
- },
- .bbpll[ESP32_CLK_XTAL_26M] = {
- /* 26mhz */
- .div_ref = 12,
- .div7_0 = 144,
- .div10_8 = 4,
- .lref = 1,
- .dcur = 0,
- .bw = 1,
- }
- }
-};
-
-static void bbpll_configure(rtc_xtal_freq_t xtal_freq, uint32_t pll_freq)
-{
- uint8_t dbias_wak = 0;
-
- const struct pll_cfg *cfg = &pll_config[pll_freq];
- const struct bbpll_cfg *bb_cfg = &pll_config[pll_freq].bbpll[xtal_freq];
-
- /* Enable PLL, Clear PowerDown (_PD) flags */
- CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
- RTC_CNTL_BIAS_I2C_FORCE_PD |
- RTC_CNTL_BB_I2C_FORCE_PD |
- RTC_CNTL_BBPLL_FORCE_PD |
- RTC_CNTL_BBPLL_I2C_FORCE_PD);
-
- /* reset BBPLL configuration */
- I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
- I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
- I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
- I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
- I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
-
- /* voltage needs to be changed for CPU@240MHz or
- * 80MHz Flash (because of internal flash regulator)
- */
- if (pll_freq == RTC_PLL_FREQ_320M) {
- dbias_wak = DIG_DBIAS_80M_160M;
- } else { /* RTC_PLL_FREQ_480M */
- dbias_wak = DIG_DBIAS_240M;
- }
-
- /* Configure the voltage */
- REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias_wak);
- esp32_rom_ets_delay_us(DELAY_PLL_DBIAS_RAISE);
-
- I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, cfg->endiv5);
- I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, cfg->bbadc_dsmp);
-
- uint8_t i2c_bbpll_lref = (bb_cfg->lref << 7) | (bb_cfg->div10_8 << 4) | (bb_cfg->div_ref);
-
- I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref);
- I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, bb_cfg->div7_0);
- I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, ((bb_cfg->bw << 6) | bb_cfg->dcur));
-}
+/* function prototypes */
+extern void rtc_clk_cpu_freq_to_xtal(int freq, int div);
+extern void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq);
static inline uint32_t clk_val_to_reg_val(uint32_t val)
{
return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16);
}
-int IRAM_ATTR esp_clk_cpu_freq(void)
+static void esp_clk_cpu_freq_to_8m(void)
{
- return MHZ(esp32_rom_g_ticks_per_us_pro);
+ ets_update_cpu_frequency(8);
+ REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
+ REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0);
+ REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M);
+ rtc_clk_apb_freq_update(ESP32_FAST_CLK_FREQ_8M);
}
-int IRAM_ATTR esp_clk_apb_freq(void)
+static void esp_clk_bbpll_disable(void)
{
- return MHZ(MIN(esp32_rom_g_ticks_per_us_pro, 80));
+ SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
+ RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
+ RTC_CNTL_BBPLL_I2C_FORCE_PD);
+
+ /* is APLL under force power down? */
+ uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
+
+ if (apll_fpd) {
+ /* then also power down the internal I2C bus */
+ SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
+ }
+}
+
+static void esp_clk_bbpll_enable(void)
+{
+ CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
+ RTC_CNTL_BIAS_I2C_FORCE_PD |
+ RTC_CNTL_BB_I2C_FORCE_PD |
+ RTC_CNTL_BBPLL_FORCE_PD |
+ RTC_CNTL_BBPLL_I2C_FORCE_PD);
+
+ /* reset BBPLL configuration */
+ REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
+ REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
+ REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
+ REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
+ REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
}
void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
{
/* Update scale factors used by ets_delay_us */
- esp32_rom_g_ticks_per_us_pro = ticks_per_us;
- esp32_rom_g_ticks_per_us_app = ticks_per_us;
+ esp_rom_g_ticks_per_us_pro = ticks_per_us;
+#if defined(CONFIG_SMP)
+ esp_rom_g_ticks_per_us_app = ticks_per_us;
+#endif
}
-static void esp32_cpu_freq_to_xtal(int freq, int div)
+static void esp_clk_wait_for_slow_cycle(void)
{
- ets_update_cpu_frequency(freq);
-
- uint32_t apb_freq = MHZ(freq);
- WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
- /* set divider from XTAL to APB clock */
- REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, div - 1);
- /* adjust ref_tick */
- REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, MHZ(freq) / REF_CLK_FREQ - 1);
- /* switch clock source */
- REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
-
- /* lower the voltage */
- if (freq <= 2) {
- REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M);
- } else {
- REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
- }
-}
-
-static void cpuclk_pll_configure(uint32_t xtal_freq, uint32_t cpu_freq)
-{
- uint32_t pll_freq = RTC_PLL_FREQ_320M;
- uint32_t cpu_period_sel = DPORT_CPUPERIOD_SEL_80;
-
- switch (cpu_freq) {
- case ESP32_CLK_CPU_80M:
- pll_freq = RTC_PLL_FREQ_320M;
- cpu_period_sel = DPORT_CPUPERIOD_SEL_80;
- break;
- case ESP32_CLK_CPU_160M:
- pll_freq = RTC_PLL_FREQ_320M;
- cpu_period_sel = DPORT_CPUPERIOD_SEL_160;
- break;
- case ESP32_CLK_CPU_240M:
- pll_freq = RTC_PLL_FREQ_480M;
- cpu_period_sel = DPORT_CPUPERIOD_SEL_240;
- break;
- }
-
- /* Configure PLL based on XTAL Value */
- bbpll_configure(xtal_freq, pll_freq);
- /* Set CPU Speed (80,160,240) */
- DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, cpu_period_sel);
- /* Set PLL as CPU Clock Source */
- REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
-
- ets_update_cpu_frequency(cpu_freq);
-
+ REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING | TIMG_RTC_CALI_START);
+ REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY);
+ REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, RTC_CAL_RTC_MUX);
/*
- * Update REF_Tick,
- * if PLL is the cpu clock source, APB frequency is always 80MHz
+ * Request to run calibration for 0 slow clock cycles.
+ * RDY bit will be set on the nearest slow clock cycle.
*/
- REG_WRITE(APB_CTRL_PLL_TICK_CONF_REG, PLL_APB_CLK_FREQ - 1);
+ REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, 0);
+ REG_SET_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
+ esp_rom_ets_delay_us(1); /* RDY needs some time to go low */
+ while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
+ esp_rom_ets_delay_us(1);
+ }
+}
+
+static int esp_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
+{
+ int dbias = DIG_DBIAS_80M_160M;
+ int per_conf = DPORT_CPUPERIOD_SEL_80;
+
+ if (cpu_freq_mhz == 80) {
+ /* nothing to do */
+ } else if (cpu_freq_mhz == 160) {
+ per_conf = DPORT_CPUPERIOD_SEL_160;
+ } else if (cpu_freq_mhz == 240) {
+ dbias = DIG_DBIAS_240M;
+ per_conf = DPORT_CPUPERIOD_SEL_240;
+ } else {
+ return -EINVAL;
+ }
+ DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, per_conf);
+ REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
+ REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
+ rtc_clk_apb_freq_update(MHZ(80));
+ ets_update_cpu_frequency(cpu_freq_mhz);
+ esp_clk_wait_for_slow_cycle();
+ return 0;
}
static int clock_control_esp32_on(const struct device *dev,
clock_control_subsys_t sys)
{
ARG_UNUSED(dev);
- uint32_t bank = GET_REG_BANK(sys);
- uint32_t offset = GET_REG_OFFSET(sys);
-
- __ASSERT_NO_MSG(bank < CLOCK_REGS_BANK_COUNT);
-
- esp32_set_mask32(BIT(offset), clock_control_regs[bank].clk);
- esp32_clear_mask32(BIT(offset), clock_control_regs[bank].rst);
+ periph_module_enable((periph_module_t)sys);
return 0;
}
@@ -270,24 +146,30 @@
clock_control_subsys_t sys)
{
ARG_UNUSED(dev);
- uint32_t bank = GET_REG_BANK(sys);
- uint32_t offset = GET_REG_OFFSET(sys);
-
- __ASSERT_NO_MSG(bank < CLOCK_REGS_BANK_COUNT);
-
- esp32_clear_mask32(BIT(offset), clock_control_regs[bank].clk);
- esp32_set_mask32(BIT(offset), clock_control_regs[bank].rst);
+ periph_module_disable((periph_module_t)sys);
return 0;
}
+static int clock_control_esp32_async_on(const struct device *dev,
+ clock_control_subsys_t sys,
+ clock_control_cb_t cb,
+ void *user_data)
+{
+ ARG_UNUSED(dev);
+ ARG_UNUSED(sys);
+ ARG_UNUSED(cb);
+ ARG_UNUSED(user_data);
+ return -ENOTSUP;
+}
+
static enum clock_control_status clock_control_esp32_get_status(const struct device *dev,
clock_control_subsys_t sys)
{
ARG_UNUSED(dev);
- uint32_t bank = GET_REG_BANK(sys);
- uint32_t offset = GET_REG_OFFSET(sys);
+ uint32_t clk_en_reg = periph_ll_get_clk_en_reg((periph_module_t)sys);
+ uint32_t clk_en_mask = periph_ll_get_clk_en_mask((periph_module_t)sys);
- if (DPORT_GET_PERI_REG_MASK(clock_control_regs[bank].clk, BIT(offset))) {
+ if (DPORT_GET_PERI_REG_MASK(clk_en_reg, clk_en_mask)) {
return CLOCK_CONTROL_STATUS_ON;
}
return CLOCK_CONTROL_STATUS_OFF;
@@ -318,21 +200,31 @@
static int clock_control_esp32_init(const struct device *dev)
{
struct esp32_clock_config *cfg = DEV_CFG(dev);
+ uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
- /* Wait for UART first before changing freq to avoid garbage on console */
- esp32_rom_uart_tx_wait_idle(0);
+ if (soc_clk_sel != RTC_CNTL_SOC_CLK_SEL_XTL) {
+ rtc_clk_cpu_freq_to_xtal(xtal_freq[cfg->xtal_freq_sel], 1);
+ esp_clk_wait_for_slow_cycle();
+ }
+
+ if (soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_PLL) {
+ esp_clk_bbpll_disable();
+ }
switch (cfg->clk_src_sel) {
case ESP32_CLK_SRC_XTAL:
- REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, cfg->xtal_div);
- /* adjust ref_tick */
- REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, xtal_freq[cfg->xtal_freq_sel] - 1);
- /* switch clock source */
- REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
+ if (cfg->xtal_div > 1) {
+ rtc_clk_cpu_freq_to_xtal(xtal_freq[cfg->xtal_freq_sel], cfg->xtal_div);
+ }
break;
case ESP32_CLK_SRC_PLL:
- esp32_cpu_freq_to_xtal(xtal_freq[cfg->xtal_freq_sel], 1);
- cpuclk_pll_configure(cfg->xtal_freq_sel, cfg->cpu_freq);
+ esp_clk_bbpll_enable();
+ esp_clk_wait_for_slow_cycle();
+ rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), cfg->cpu_freq);
+ esp_clk_cpu_freq_to_pll_mhz(cfg->cpu_freq);
+ break;
+ case ESP32_CLK_SRC_RTC8M:
+ esp_clk_cpu_freq_to_8m();
break;
default:
return -EINVAL;
@@ -341,17 +233,13 @@
/* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE);
- /* Re-calculate the CCOUNT register value to make time calculation correct.
- * This should be updated on each frequency change
- * New CCOUNT = Current CCOUNT * (new freq / old freq)
- */
- XTHAL_SET_CCOUNT((uint64_t)XTHAL_GET_CCOUNT() * cfg->cpu_freq / xtal_freq[cfg->xtal_freq_sel]);
return 0;
}
static const struct clock_control_driver_api clock_control_esp32_api = {
.on = clock_control_esp32_on,
.off = clock_control_esp32_off,
+ .async_on = clock_control_esp32_async_on,
.get_rate = clock_control_esp32_get_rate,
.get_status = clock_control_esp32_get_status,
};
@@ -360,15 +248,17 @@
.clk_src_sel = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_source),
.cpu_freq = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_frequency),
.xtal_freq_sel = DT_INST_PROP(0, xtal_freq),
- .xtal_div = DT_INST_PROP(0, xtal_div),
+ .xtal_div = DT_INST_PROP(0, xtal_div)
};
-DEVICE_DT_INST_DEFINE(0,
- &clock_control_esp32_init,
- NULL,
- NULL, &esp32_clock_config0,
- PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,
- &clock_control_esp32_api);
+DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
+ &clock_control_esp32_init,
+ NULL,
+ NULL,
+ &esp32_clock_config0,
+ PRE_KERNEL_1,
+ CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,
+ &clock_control_esp32_api);
BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) ==
MHZ(DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_frequency)),
diff --git a/drivers/clock_control/clock_control_esp32.h b/drivers/clock_control/clock_control_esp32.h
index 76da35a..5201d05 100644
--- a/drivers/clock_control/clock_control_esp32.h
+++ b/drivers/clock_control/clock_control_esp32.h
@@ -63,8 +63,10 @@
#define BBPLL_OC_ENB_VCON_VAL 0x00
#define BBPLL_BBADC_CAL_7_0_VAL 0x00
-extern uint32_t esp32_rom_g_ticks_per_us_pro;
-extern uint32_t esp32_rom_g_ticks_per_us_app;
-extern void esp32_rom_ets_delay_us(uint32_t us);
+#define ESP32_FAST_CLK_FREQ_8M 8500000
+
+extern uint32_t esp_rom_g_ticks_per_us_pro;
+extern uint32_t esp_rom_g_ticks_per_us_app;
+extern void esp_rom_ets_delay_us(uint32_t us);
#endif /* ZEPHYR_DRIVERS_CLOCK_CONTROL_ESP32_CLOCK_H_ */
diff --git a/include/dt-bindings/clock/esp32_clock.h b/include/dt-bindings/clock/esp32_clock.h
index bcf1f11..4e3ff70 100644
--- a/include/dt-bindings/clock/esp32_clock.h
+++ b/include/dt-bindings/clock/esp32_clock.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2020 Mohamed ElShahawi
+ * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,6 +12,7 @@
#define ESP32_CLK_SRC_XTAL 0U
#define ESP32_CLK_SRC_PLL 1U
#define ESP32_CLK_SRC_RTC8M 2U
+#define ESP32_CLK_SRC_APLL 3U
/* Supported CPU Frequencies */
#define ESP32_CLK_CPU_26M 26U
@@ -20,8 +22,10 @@
#define ESP32_CLK_CPU_240M 240U
/* Supported XTAL Frequencies */
-#define ESP32_CLK_XTAL_40M 0U
+#define ESP32_CLK_XTAL_24M 0U
#define ESP32_CLK_XTAL_26M 1U
+#define ESP32_CLK_XTAL_40M 2U
+#define ESP32_CLK_XTAL_AUTO 3U
/* Modules IDs
* These IDs are actually offsets in CLK and RST Control registers.
@@ -31,54 +35,42 @@
* Basic Modules
* Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG
*/
-#define ESP32_TIMERS_MODULE 0
-#define ESP32_SPI1_MODULE 1
-#define ESP32_UART0_MODULE 2
-#define ESP32_WDG_MODULE 3
-#define ESP32_I2S0_MODULE 4
-#define ESP32_UART1_MODULE 5
-#define ESP32_SPI2_MODULE 6
-#define ESP32_I2C_EXT0_MODULE 7
-#define ESP32_UHCI0_MODULE 8
-#define ESP32_RMT_MODULE 9
-#define ESP32_PCNT_MODULE 10
-#define ESP32_LEDC_MODULE 11
-#define ESP32_UHCI1_MODULE 12
-#define ESP32_TIMERGROUP_MODULE 13
-#define ESP32_EFUSE_MODULE 14
-#define ESP32_TIMERGROUP1_MODULE 15
-#define ESP32_SPI3_MODULE 16
-#define ESP32_PWM0_MODULE 17
-#define ESP32_I2C_EXT1_MODULE 18
-#define ESP32_CAN_MODULE 19
-#define ESP32_PWM1_MODULE 20
-#define ESP32_I2S1_MODULE 21
-#define ESP32_SPI_DMA_MODULE 22
-#define ESP32_UART2_MODULE 23
-#define ESP32_UART_MEM_MODULE 24
-#define ESP32_PWM2_MODULE 25
-#define ESP32_PWM3_MODULE 26
-
-/* HW Security Modules
- * Registers: DPORT_PERI_CLK_EN_REG, DPORT_PERI_RST_EN_REG
- */
-#define ESP32_AES_MODULE 32
-#define ESP32_SHA_MODULE 33
-#define ESP32_RSA_MODULE 34
-#define ESP32_SECUREBOOT_MODULE 35 /* Secure boot reset will hold SHA & AES in reset */
-#define ESP32_DIGITAL_SIGNATURE_MODULE 36 /* Digital signature reset will hold AES & RSA in reset */
-
-/* WiFi/BT
- * Registers: DPORT_WIFI_CLK_EN_REG, DPORT_CORE_RST_EN_REG
- */
-#define ESP32_SDMMC_MODULE 64
-#define ESP32_SDIO_SLAVE_MODULE 65
-#define ESP32_EMAC_MODULE 66
-#define ESP32_RNG_MODULE 67
-#define ESP32_WIFI_MODULE 68
-#define ESP32_BT_MODULE 69
-#define ESP32_WIFI_BT_COMMON_MODULE 70
-#define ESP32_BT_BASEBAND_MODULE 71
-#define ESP32_BT_LC_MODULE 72
+#define ESP32_LEDC_MODULE 0
+#define ESP32_UART0_MODULE 1
+#define ESP32_UART1_MODULE 2
+#define ESP32_UART2_MODULE 3
+#define ESP32_I2C0_MODULE 4
+#define ESP32_I2C1_MODULE 5
+#define ESP32_I2S0_MODULE 6
+#define ESP32_I2S1_MODULE 7
+#define ESP32_TIMG0_MODULE 8
+#define ESP32_TIMG1_MODULE 9
+#define ESP32_PWM0_MODULE 10
+#define ESP32_PWM1_MODULE 11
+#define ESP32_PWM2_MODULE 12
+#define ESP32_PWM3_MODULE 13
+#define ESP32_UHCI0_MODULE 14
+#define ESP32_UHCI1_MODULE 15
+#define ESP32_RMT_MODULE 16
+#define ESP32_PCNT_MODULE 17
+#define ESP32_SPI_MODULE 18
+#define ESP32_HSPI_MODULE 19
+#define ESP32_VSPI_MODULE 20
+#define ESP32_SPI_DMA_MODULE 21
+#define ESP32_SDMMC_MODULE 22
+#define ESP32_SDIO_SLAVE_MODULE 23
+#define ESP32_TWAI_MODULE 24
+#define ESP32_CAN_MODULE ESP32_TWAI_MODULE
+#define ESP32_EMAC_MODULE 25
+#define ESP32_RNG_MODULE 26
+#define ESP32_WIFI_MODULE 27
+#define ESP32_BT_MODULE 28
+#define ESP32_WIFI_BT_COMMON_MODULE 29
+#define ESP32_BT_BASEBAND_MODULE 30
+#define ESP32_BT_LC_MODULE 31
+#define ESP32_AES_MODULE 32
+#define ESP32_SHA_MODULE 33
+#define ESP32_RSA_MODULE 34
+#define ESP32_MODULE_MAX 35
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32_H_ */
