dts: arm:st: stm32h5: fix dma phandle lists
Correct STM32H5xx SoCs DMA lists that were not split by phandle and
seemed to form unique phandles. This is not currently as issue with
existing DT parsing macros and tools but may generate build errors
if tools are more strict on the DTS implementation formats.
Clean indentation by the ways for the modified DTSI file lines.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
diff --git a/dts/arm/st/h5/stm32h5.dtsi b/dts/arm/st/h5/stm32h5.dtsi
index da8f4d6..a40802b 100644
--- a/dts/arm/st/h5/stm32h5.dtsi
+++ b/dts/arm/st/h5/stm32h5.dtsi
@@ -581,9 +581,9 @@
clocks = <&rcc STM32_CLOCK(APB2, 12)>,
<&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
dmas = <&gpdma1 0 7 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS |
- STM32_DMA_PRIORITY_HIGH)
- &gpdma1 1 6 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS |
- STM32_DMA_PRIORITY_HIGH)>;
+ STM32_DMA_PRIORITY_HIGH)>,
+ <&gpdma1 1 6 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS |
+ STM32_DMA_PRIORITY_HIGH)>;
dma-names = "tx", "rx";
interrupts = <55 3>;
status = "disabled";
@@ -597,9 +597,9 @@
clocks = <&rcc STM32_CLOCK(APB1, 14)>,
<&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>;
dmas = <&gpdma1 2 9 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS |
- STM32_DMA_PRIORITY_HIGH)
- &gpdma1 3 8 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS |
- STM32_DMA_PRIORITY_HIGH)>;
+ STM32_DMA_PRIORITY_HIGH)>,
+ <&gpdma1 3 8 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS |
+ STM32_DMA_PRIORITY_HIGH)>;
dma-names = "tx", "rx";
interrupts = <56 3>;
status = "disabled";
@@ -613,9 +613,9 @@
clocks = <&rcc STM32_CLOCK(APB1, 15)>,
<&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>;
dmas = <&gpdma1 4 11 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS |
- STM32_DMA_PRIORITY_HIGH)
- &gpdma1 5 10 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS |
- STM32_DMA_PRIORITY_HIGH)>;
+ STM32_DMA_PRIORITY_HIGH)>,
+ <&gpdma1 5 10 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS |
+ STM32_DMA_PRIORITY_HIGH)>;
dma-names = "tx", "rx";
interrupts = <57 3>;
status = "disabled";
