| commit | d6cbdace78517045538f2f471989c362fc1b8879 | [log] [tgz] |
|---|---|---|
| author | Daniel Leung <daniel.leung@intel.com> | Tue Apr 27 10:07:13 2021 -0700 |
| committer | Anas Nashif <anas.nashif@intel.com> | Thu Apr 29 16:49:17 2021 -0400 |
| tree | ee0a37f2f9dd531543da8e0967e19bf5d2def91f | |
| parent | 08c750a3978176d1a7cf7908925d2ae94e1d899d [diff] |
x86: timing: fix potential divide by zero There is a possibility that the TSC frequency calculation is divided by zero. So this fixes the issue by repeatedly trying to get the delta clock cycles and delta TSC cycles until they both are not zero. Signed-off-by: Daniel Leung <daniel.leung@intel.com>