arch: arm: aarch32: add ARMv8 timer
This is mostly a copy of the existing arm64 implementation,
at the difference that the AArch32 registers do not mention the
execution level.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
diff --git a/include/arch/arm/aarch32/arch.h b/include/arch/arm/aarch32/arch.h
index 2f46e68e..c273aa1 100644
--- a/include/arch/arm/aarch32/arch.h
+++ b/include/arch/arm/aarch32/arch.h
@@ -40,8 +40,13 @@
#elif defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
#include <arch/arm/aarch32/cortex_a_r/cpu.h>
#include <arch/arm/aarch32/cortex_a_r/sys_io.h>
+#if defined(CONFIG_AARCH32_ARMV8_R)
+#include <arch/arm/aarch32/cortex_a_r/lib_helpers.h>
+#include <arch/arm/aarch32/cortex_a_r/armv8_timer.h>
+#else
#include <arch/arm/aarch32/cortex_a_r/timer.h>
#endif
+#endif
#ifdef __cplusplus
extern "C" {
diff --git a/include/arch/arm/aarch32/cortex_a_r/armv8_timer.h b/include/arch/arm/aarch32/cortex_a_r/armv8_timer.h
new file mode 100644
index 0000000..05599bb
--- /dev/null
+++ b/include/arch/arm/aarch32/cortex_a_r/armv8_timer.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ * Copyright (c) 2022 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_ARMV8_TIMER_H_
+#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_ARMV8_TIMER_H_
+
+#ifndef _ASMLANGUAGE
+
+#include <drivers/timer/arm_arch_timer.h>
+#include <zephyr/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ARM_ARCH_TIMER_IRQ ARM_TIMER_VIRTUAL_IRQ
+#define ARM_ARCH_TIMER_PRIO ARM_TIMER_VIRTUAL_PRIO
+#define ARM_ARCH_TIMER_FLAGS ARM_TIMER_VIRTUAL_FLAGS
+
+static ALWAYS_INLINE void arm_arch_timer_init(void)
+{
+}
+
+static ALWAYS_INLINE void arm_arch_timer_set_compare(uint64_t val)
+{
+ write_cntv_cval(val);
+}
+
+static ALWAYS_INLINE void arm_arch_timer_enable(unsigned char enable)
+{
+ uint64_t cntv_ctl;
+
+ cntv_ctl = read_cntv_ctl();
+
+ if (enable) {
+ cntv_ctl |= CNTV_CTL_ENABLE_BIT;
+ } else {
+ cntv_ctl &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_cntv_ctl(cntv_ctl);
+}
+
+static ALWAYS_INLINE void arm_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t cntv_ctl;
+
+ cntv_ctl = read_cntv_ctl();
+
+ if (mask) {
+ cntv_ctl |= CNTV_CTL_IMASK_BIT;
+ } else {
+ cntv_ctl &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_cntv_ctl(cntv_ctl);
+}
+
+static ALWAYS_INLINE uint64_t arm_arch_timer_count(void)
+{
+ return read_cntvct();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_ARMV8_TIMER_H_ */
diff --git a/include/arch/arm/aarch32/cortex_a_r/cpu.h b/include/arch/arm/aarch32/cortex_a_r/cpu.h
index 04bdb72..8fa248c 100644
--- a/include/arch/arm/aarch32/cortex_a_r/cpu.h
+++ b/include/arch/arm/aarch32/cortex_a_r/cpu.h
@@ -72,4 +72,8 @@
HACTLR_BUSTIMEOUTR_BIT | HACTLR_QOSR_BIT | \
HACTLR_PERIPHPREGIONR | HACTLR_FLASHIFREGIONR | \
HACTLR_CDBGDCI | HACTLR_CPUACTLR)
+/* ARMv8 Timer */
+#define CNTV_CTL_ENABLE_BIT BIT(0)
+#define CNTV_CTL_IMASK_BIT BIT(1)
+
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CPU_H_ */
