d7b53226d1185482c571d3827fb029a3197c68da - third_party/github/zephyrproject-rtos/zephyr

commit	d7b53226d1185482c571d3827fb029a3197c68da	[log] [tgz]
author	Jim Shu <cwshu@andestech.com>	Thu Jul 29 12:39:27 2021 +0800
committer	Anas Nashif <anas.nashif@intel.com>	Mon Aug 30 13:40:14 2021 -0400
tree	065e9db263941c5ea5949fc5c99383ce423f804f
parent	3b7221363a6d31993cb40829de3edd2ffffd8b41 [diff]

soc: riscv: andes_v5: initial support of Andes L2 cache controller

This initial support of L2C driver only contains cache enable and HW
capability checking. Cache management operation isn't supported yet
in this driver.

Signed-off-by: Jim Shu <cwshu@andestech.com>

soc/riscv/riscv-privilege/andes_v5/CMakeLists.txt[diff]
soc/riscv/riscv-privilege/andes_v5/Kconfig.soc[diff]
soc/riscv/riscv-privilege/andes_v5/l2_cache.c[Added - diff]

3 files changed