| commit | dd74db46e43b663f89c1b2e96409a79a3224359a | [log] [tgz] |
|---|---|---|
| author | Julien Massot <julien.massot@iot.bzh> | Thu Jan 27 14:37:41 2022 +0100 |
| committer | Carles Cufí <carles.cufi@nordicsemi.no> | Fri Mar 11 10:59:48 2022 +0100 |
| tree | 86d299b9a631cd2a24673995c765382b6dec2077 | |
| parent | d70a6ef72678caf1e998727a8f6c4e4191a4d440 [diff] |
arch: arm: cortex_a_r: add MPIDR and SG1R definition These definitions are required to be able to use GICv3 interrupts controller on an ARMv8 AArch32 processor. Signed-off-by: Julien Massot <julien.massot@iot.bzh>