dts: arm: Kinetis: Add base support for Kinetis
This patch adds DTS support and related files for the NXP Kinetis
platform. The DTS files contain the base definitions for the hardware
nodes on Kinetis platforms. The YAML files provide the definitions of
the contents of the DTS nodes.
The Kconfig changes were put in place to allow for the conversion of
existing drivers. Once those drivers are modified, the Kconfig options
that are replaced by the DTS information will be removed.
Change-Id: If110fffa99c0b12471cf2df206da6687277e4756
Signed-off-by: Andy Gross <andy.gross@linaro.org>
diff --git a/arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.series b/arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.series
index 7cb1e41..a472216 100644
--- a/arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.series
+++ b/arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.series
@@ -11,6 +11,8 @@
config SOC_SERIES
default k6x
+if !HAS_DTS
+
config SRAM_BASE_ADDRESS
default 0x20000000
@@ -26,6 +28,8 @@
# must be >= the highest interrupt number used
default 86
+endif # !HAS_DTS
+
source "arch/arm/soc/nxp_kinetis/k6x/Kconfig.defconfig.mk*"
endif # SOC_SERIES_KINETIS_K6X
diff --git a/boards/arm/frdm_k64f/Kconfig.defconfig b/boards/arm/frdm_k64f/Kconfig.defconfig
index d90a0f6..aac7f60 100644
--- a/boards/arm/frdm_k64f/Kconfig.defconfig
+++ b/boards/arm/frdm_k64f/Kconfig.defconfig
@@ -10,12 +10,16 @@
config BOARD
default frdm_k64f
+if !HAS_DTS
+
config FLASH_SIZE
default 1024
config SRAM_SIZE
default 192
+endif # !HAS_DTS
+
config OSC_XTAL0_FREQ
default 50000000
diff --git a/drivers/serial/Kconfig.mcux b/drivers/serial/Kconfig.mcux
index 69f96cd..6ddd8b0 100644
--- a/drivers/serial/Kconfig.mcux
+++ b/drivers/serial/Kconfig.mcux
@@ -27,6 +27,8 @@
string "UART 0 driver name"
default "UART_0"
+if !HAS_DTS
+
config UART_MCUX_0_IRQ_PRI
int "UART 0 interrupt priority"
default 0
@@ -35,6 +37,8 @@
int "UART 0 baud rate"
default 115200
+endif # !HAS_DTS
+
endif # UART_MCUX_0
menuconfig UART_MCUX_1
@@ -49,6 +53,8 @@
string "UART 1 driver name"
default "UART_1"
+if !HAS_DTS
+
config UART_MCUX_1_IRQ_PRI
int "UART 1 interrupt priority"
default 0
@@ -57,6 +63,8 @@
int "UART 1 baud rate"
default 115200
+endif # !HAS_DTS
+
endif # UART_MCUX_1
menuconfig UART_MCUX_2
@@ -71,6 +79,8 @@
string "UART 2 driver name"
default "UART_2"
+if !HAS_DTS
+
config UART_MCUX_2_IRQ_PRI
int "UART 2 interrupt priority"
default 0
@@ -79,6 +89,8 @@
int "UART 2 baud rate"
default 115200
+endif # !HAS_DTS
+
endif # UART_MCUX_2
menuconfig UART_MCUX_3
@@ -93,6 +105,8 @@
string "UART 3 driver name"
default "UART_3"
+if !HAS_DTS
+
config UART_MCUX_3_IRQ_PRI
int "UART 3 interrupt priority"
default 0
@@ -101,6 +115,8 @@
int "UART 3 baud rate"
default 115200
+endif # !HAS_DTS
+
endif # UART_MCUX_3
menuconfig UART_MCUX_4
@@ -115,6 +131,8 @@
string "UART 4 driver name"
default "UART_4"
+if !HAS_DTS
+
config UART_MCUX_4_IRQ_PRI
int "UART 4 interrupt priority"
default 0
@@ -123,6 +141,8 @@
int "UART 4 baud rate"
default 115200
+endif # !HAS_DTS
+
endif # UART_MCUX_4
menuconfig UART_MCUX_5
@@ -137,6 +157,8 @@
string "UART 5 driver name"
default "UART_5"
+if !HAS_DTS
+
config UART_MCUX_5_IRQ_PRI
int "UART 5 interrupt priority"
default 0
@@ -145,6 +167,8 @@
int "UART 5 baud rate"
default 115200
+endif # !HAS_DTS
+
endif # UART_MCUX_5
endif # UART_MCUX
diff --git a/dts/arm/nxp_k6x.dtsi b/dts/arm/nxp_k6x.dtsi
new file mode 100644
index 0000000..fdb45ca
--- /dev/null
+++ b/dts/arm/nxp_k6x.dtsi
@@ -0,0 +1,288 @@
+#include "armv7-m.dtsi"
+
+/ {
+ cpus {
+ cpu@0 {
+ compatible = "arm,cortex-m4f";
+ };
+ };
+
+ sram0: memory {
+ compatible = "mmio-sram";
+ reg = <0x20000000 0x30000>;
+ };
+
+ soc {
+
+ mpu@4000d000 {
+ compatible = "nxp,k64f-mpu";
+ reg = <0x4000d000 0x824>;
+
+ status = "disabled";
+ };
+
+ mcg: clock-controller@40064000 {
+ compatible = "nxp,k64f-mcg";
+ reg = <0x40064000 0xd>;
+ system-clock-frequency = <120000000>;
+
+ clock-controller;
+ };
+
+ clock-controller@40065000 {
+ compatible = "nxp,k64f-osc";
+ reg = <0x40065000 0x4>;
+
+ enable-external-reference;
+ };
+
+ rtc@4003d000 {
+ compatible = "nxp,k64f-rtc";
+ reg = <0x4003d000 0x808>;
+ clock-frequency = <32768>;
+ };
+
+ sim: sim@40047000 {
+ compatible = "nxp,k64f-sim";
+ reg = <0x40047000 0x1060>;
+
+ clk-divider-core = <1>;
+ clk-divider-bus = <2>;
+ clk-divider-flexbus = <3>;
+ clk-divider-flash = <5>;
+
+ clock-controller;
+ #clock-cells = <2>;
+ };
+
+ flash-controller@4001f000 {
+ compatible = "nxp,k64f-flash-controller";
+ reg = <0x4001f000 0x27c>;
+ interrupts = <18>, <19>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ flash0: flash@0 {
+ reg = <0 0x100000>;
+ };
+ };
+
+ uart0: uart@4006a000 {
+ compatible = "nxp,k64f-uart";
+ reg = <0x4006a000 0x1000>;
+ interrupts = <31>, <32>;
+ interrupt-names = "status", "error";
+ zephyr,irq-prio = <0>;
+
+ baud-rate = <115200>;
+ pinctrl-0 = <&uart0_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ uart1: uart@4006b000 {
+ compatible = "nxp,k64f-uart";
+ reg = <0x4006b000 0x1000>;
+ interrupts = <33>, <34>;
+ interrupt-names = "status", "error";
+ zephyr,irq-prio = <0>;
+
+ status = "disabled";
+ };
+
+ uart2: uart@4006c000 {
+ compatible = "nxp,k64f-uart";
+ reg = <0x4006c000 0x1000>;
+ interrupts = <35>, <36>;
+ interrupt-names = "status", "error";
+ zephyr,irq-prio = <0>;
+
+ status = "disabled";
+ };
+
+ uart3: uart@4006d000 {
+ compatible = "nxp,k64f-uart";
+ reg = <0x4006d000 0x1000>;
+ interrupts = <37>, <38>;
+ interrupt-names = "status", "error";
+ zephyr,irq-prio = <0>;
+
+ status = "disabled";
+ };
+
+ uart4: uart@400ea000 {
+ compatible = "nxp,k64f-uart";
+ reg = <0x400ea000 0x1000>;
+ interrupts = <66>, <67>;
+ interrupt-names = "status", "error";
+ zephyr,irq-prio = <0>;
+
+ status = "disabled";
+ };
+
+ uart5: uart@400eb000 {
+ compatible = "nxp,k64f-uart";
+ reg = <0x400eb000 0x1000>;
+ interrupts = <68>, <69>;
+ interrupt-names = "status", "error";
+ zephyr,irq-prio = <0>;
+
+ status = "disabled";
+ };
+
+ pinmux_a: pinmux@40049000 {
+ compatible = "nxp,k64f-pinmux";
+ reg = <0x40049000 0xd0>;
+
+ clocks = <&sim 0x1038 9>;
+ };
+
+ pinmux_b: pinmux@4004a000 {
+ compatible = "nxp,k64f-pinmux";
+ reg = <0x4004a000 0xd0>;
+
+ clocks = <&sim 0x1038 10>;
+ uart0_default: uart0_default {
+ rx-tx {
+ pins = <16>, <17>;
+ function = <3>;
+ };
+ };
+
+ uart0_lpm: uart0_lpm {
+ rx-tx {
+ pins = <16>, <17>;
+ function = <0>;
+ };
+ };
+
+ spi0_default: spi0_default {
+ miso-mosi-clk {
+ pins = <10>, <9>;
+ function = <2>;
+ };
+ };
+ };
+
+ pinmux_c: pinmux@4004b000 {
+ compatible = "nxp,k64f-pinmux";
+ reg = <0x4004b000 0xd0>;
+ clocks = <&sim 0x1038 11>;
+ };
+
+ pinmux_d: pinmux@4004c000 {
+ compatible = "nxp,k64f-pinmux";
+ reg = <0x4004c000 0xd0>;
+ clocks = <&sim 0x1038 12>;
+ };
+
+ pinmux_e: pinmux@4004d000 {
+ compatible = "nxp,k64f-pinmux";
+ reg = <0x4004d000 0xd0>;
+ clocks = <&sim 0x1038 13>;
+ };
+
+ gpioa: gpio@400ff000 {
+ compatible = "nxp,k64f-gpio";
+ reg = <0x400ff000 0x40>;
+ interrupts = <59>;
+ zephyr,irq-prio = <2>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpiob: gpio@400ff040 {
+ compatible = "nxp,k64f-gpio";
+ reg = <0x400ff040 0x40>;
+ interrupts = <60>;
+
+ zephyr,irq-prio = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpioc: gpio@400ff080 {
+ compatible = "nxp,k64f-gpio";
+ reg = <0x400ff080 0x40>;
+ interrupts = <61>;
+
+ zephyr,irq-prio = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpiod: gpio@400ff0c0 {
+ compatible = "nxp,k64f-gpio";
+ reg = <0x400ff0c0 0x40>;
+ interrupts = <62>;
+ zephyr,irq-prio = <2>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpioe: gpio@400ff100 {
+ compatible = "nxp,k64f-gpio";
+ reg = <0x400ff100 0x40>;
+ interrupts = <63>;
+ zephyr,irq-prio = <2>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ spi0: spi@4002c000 {
+ compatible = "nxp,k64f-spi";
+ reg = <0x4002c000 0x88>;
+ interrupts = <26>;
+ clocks = <&sim 0x103C 12>; /* clk gate */
+
+ cs = <&gpiob 10 0>, <&gpiob 9 0>;
+ pinctrl-0 = <&spi0_default>;
+ pinctrl-names = "default";
+ };
+
+ spi1: spi@4002d000 {
+ compatible = "nxp,k64f-spi";
+ reg = <0x4002d000 0x88>;
+ interrupts = <0>;
+ clocks = <&sim 0x103C 13>; /* clk gate */
+ status = "disabled";
+ };
+
+ wdog: watchdog@40052000 {
+ compatible = "nxp,k64f-watchdog";
+ reg = <0x40052000 16>;
+ clock-source = <0>; /* LPO 1kHz or other source */
+ reload-counter = <40000>;
+ start-on-boot;
+ prescaler = <2>;
+ };
+
+ pwm0: pwm@40038000{
+ compatible = "nxp,k64f-pwm";
+ reg = <0x40038000 0x98>;
+ prescaler = <2>;
+ period = <1000>;
+ clock-source = <0>;
+ /* channel information needed - fixme */
+ };
+
+ pwm1: pwm@40039000{
+ compatible = "nxp,k64f-pwm";
+ reg = <0x40039000 0x98>;
+ prescaler = <2>;
+ period = <1000>;
+ clock-source = <0>;
+ /* channel information needed - fixme */
+ };
+ };
+};
+
+&nvic {
+ num-irqs = <86>;
+ num-irq-prio-bits = <4>;
+};
diff --git a/dts/arm/yaml/k64gpio.yaml b/dts/arm/yaml/k64gpio.yaml
new file mode 100644
index 0000000..2ab3afd
--- /dev/null
+++ b/dts/arm/yaml/k64gpio.yaml
@@ -0,0 +1,32 @@
+---
+title: K64 GPIO
+version: 0.1
+
+description: >
+ This is a representation of the K64 GPIO nodes
+
+properties:
+ - compatible:
+ type: string
+ category: required
+ description: compatible strings
+ constraint: "nxp,k64f-gpio"
+
+ - reg:
+ type: int
+ description: mmio register space
+ generation: define
+ category: required
+
+ - interrupts:
+ type: compound
+ category: required
+ description: required interrupts
+ generation: define
+
+cell_string: GPIO
+
+"#cells":
+ - pin
+ - flags
+...
diff --git a/dts/arm/yaml/k64pinmux.yaml b/dts/arm/yaml/k64pinmux.yaml
new file mode 100644
index 0000000..b610152
--- /dev/null
+++ b/dts/arm/yaml/k64pinmux.yaml
@@ -0,0 +1,32 @@
+---
+title: K64 Pinmux
+version: 0.1
+
+description: >
+ This is a representation of the K64 Pinmux node
+
+properties:
+ - compatible:
+ type: string
+ category: required
+ description: compatible strings
+ constraint: "nxp,k64f-pinmux"
+
+ - reg:
+ type: int
+ description: mmio register space
+ generation: define
+ category: required
+
+ - clocks:
+ type: array
+ description: clock gate information
+ generation: define
+ category: required
+
+cell_string: PINMUX
+
+"#cells":
+ - pin
+ - function
+...
diff --git a/dts/arm/yaml/k64sim.yaml b/dts/arm/yaml/k64sim.yaml
new file mode 100644
index 0000000..d303e8c
--- /dev/null
+++ b/dts/arm/yaml/k64sim.yaml
@@ -0,0 +1,26 @@
+---
+title: K64 System Integration Module (SIM)
+version: 0.1
+
+description: >
+ This is a representation of the K64 SIM IP node
+
+properties:
+ - compatible:
+ type: string
+ category: required
+ description: compatible strings
+ constraint: "nxp,k64f-sim"
+
+ - reg:
+ type: int
+ description: mmio register space
+ generation: define
+ category: required
+
+cell_string: SIM_CLK
+
+"#cells":
+ - offset
+ - bits
+...
diff --git a/dts/arm/yaml/k64uart.yaml b/dts/arm/yaml/k64uart.yaml
new file mode 100644
index 0000000..f35ad18
--- /dev/null
+++ b/dts/arm/yaml/k64uart.yaml
@@ -0,0 +1,43 @@
+---
+title: K64 Uart
+id: nxp,k64f-uart
+version: 0.1
+
+description: >
+ This binding gives a base representation of the K64 UART
+
+inherits:
+ - !include uart.yaml
+ - !include zephyr_devices.yaml
+
+properties:
+ - compatible:
+ type: string
+ category: required
+ description: compatible strings
+ constraint: "nxp,k64f-uart"
+
+ - reg:
+ type: array
+ description: mmio register space
+ generation: define
+ category: required
+
+ - interrupts:
+ type: array
+ category: required
+ description: required interrupts
+ generation: define
+
+ - pinctrl-\d+:
+ type: array
+ category: optional
+ description: pinmux information for RX, TX, CTS, RTS
+ generation: define
+
+ - clocks:
+ type: array
+ category: required
+ description: Clock gate control information
+ generation: structures
+...
