| commit | deb57e3b859861124706e0c9d00c74dcaabf2aa9 | [log] [tgz] |
|---|---|---|
| author | Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com> | Thu Apr 01 20:36:23 2021 +0200 |
| committer | Anas Nashif <anas.nashif@intel.com> | Mon May 03 17:13:01 2021 -0400 |
| tree | f3d939b4381bb3330f3696435a99306b52ecf942 | |
| parent | aef4edddfa8b048caecfbc234c1a1ababd952baf [diff] |
xtensa: ADSP: fix disabling the IDC interrupt To disable the IDC interrupt on the interrupt controller a bit must be set in the MSD register instead of clearing the bit in the MCD register, which has no effect. Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>