boards: frdm_mcxa344: add frdm_mcxa344 board
enable board support for frdm_mcxa344
Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
diff --git a/boards/nxp/frdm_mcxa344/CMakeLists.txt b/boards/nxp/frdm_mcxa344/CMakeLists.txt
new file mode 100644
index 0000000..c06b927
--- /dev/null
+++ b/boards/nxp/frdm_mcxa344/CMakeLists.txt
@@ -0,0 +1,8 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_sources(board.c)
diff --git a/boards/nxp/frdm_mcxa344/Kconfig b/boards/nxp/frdm_mcxa344/Kconfig
new file mode 100644
index 0000000..9e41ea4
--- /dev/null
+++ b/boards/nxp/frdm_mcxa344/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXA344
+ select BOARD_EARLY_INIT_HOOK
diff --git a/boards/nxp/frdm_mcxa344/Kconfig.frdm_mcxa344 b/boards/nxp/frdm_mcxa344/Kconfig.frdm_mcxa344
new file mode 100644
index 0000000..4d895ff
--- /dev/null
+++ b/boards/nxp/frdm_mcxa344/Kconfig.frdm_mcxa344
@@ -0,0 +1,6 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXA344
+ select SOC_MCXA344
+ select SOC_PART_NUMBER_MCXA344VLL
diff --git a/boards/nxp/frdm_mcxa344/board.c b/boards/nxp/frdm_mcxa344/board.c
new file mode 100644
index 0000000..aeef915
--- /dev/null
+++ b/boards/nxp/frdm_mcxa344/board.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/init.h>
+#include <zephyr/device.h>
+#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
+#include <fsl_clock.h>
+#include <fsl_spc.h>
+#include <soc.h>
+
+/* Core clock frequency: 180MHz */
+#define CLOCK_INIT_CORE_CLOCK 180000000U
+#define BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK 180000000U
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+void board_early_init_hook(void)
+{
+ uint32_t core_freq;
+ spc_active_mode_core_ldo_option_t ldo_option;
+ spc_sram_voltage_config_t sram_option;
+
+ /* Get the CPU Core frequency */
+ core_freq = CLOCK_GetCoreSysClkFreq();
+
+ /* The flow of increasing voltage and frequency */
+ if (core_freq <= BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK) {
+ /* Set the LDO_CORE VDD regulator level */
+ ldo_option.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage;
+ ldo_option.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+ (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo_option);
+ /* Configure Flash to support different voltage level and frequency */
+ FMU0->FCTRL =
+ (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x4U));
+ /* Specifies the operating voltage for the SRAM's read/write timing margin */
+ sram_option.operateVoltage = kSPC_sramOperateAt1P2V;
+ sram_option.requestVoltageUpdate = true;
+ (void)SPC_SetSRAMOperateVoltage(SPC0, &sram_option);
+ }
+
+ /*!< Set up system dividers */
+ CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set SYSCON.AHBCLKDIV divider to value 1 */
+ CLOCK_SetClockDiv(kCLOCK_DivFRO_HF, 1U); /* !< Set SYSCON.FROHFDIV divider to value 1 */
+ CLOCK_SetupFROHFClocking(BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK); /*!< Enable FRO HF */
+ CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
+
+ CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to kFRO_HF */
+
+ /* The flow of decreasing voltage and frequency */
+ if (core_freq > BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK) {
+ /* Configure Flash to support different voltage level and frequency */
+ FMU0->FCTRL =
+ (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x4U));
+ /* Specifies the operating voltage for the SRAM's read/write timing margin */
+ sram_option.operateVoltage = kSPC_sramOperateAt1P2V;
+ sram_option.requestVoltageUpdate = true;
+ (void)SPC_SetSRAMOperateVoltage(SPC0, &sram_option);
+ /* Set the LDO_CORE VDD regulator level */
+ ldo_option.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage;
+ ldo_option.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+ (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo_option);
+ }
+
+ /*!< Set up clock selectors - Attach clocks to the peripheries */
+ CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
+
+ /*!< Set up dividers */
+ CLOCK_SetClockDiv(kCLOCK_DivFRO_LF, 1U); /* !< Set SYSCON.FROLFDIV divider to value 1 */
+ CLOCK_SetClockDiv(kCLOCK_DivTRACE, 2U); /* !< Set MRCC.TRACE_CLKDIV divider to value 2 */
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porta))
+ RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
+ CLOCK_EnableClock(kCLOCK_GatePORT0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portb))
+ RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn);
+ CLOCK_EnableClock(kCLOCK_GatePORT1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portc))
+ RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn);
+ CLOCK_EnableClock(kCLOCK_GatePORT2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portd))
+ RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
+ CLOCK_EnableClock(kCLOCK_GatePORT3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porte))
+ RESET_ReleasePeripheralReset(kPORT4_RST_SHIFT_RSTn);
+ CLOCK_EnableClock(kCLOCK_GatePORT4);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0))
+ RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn);
+ CLOCK_EnableClock(kCLOCK_GateGPIO0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
+ RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn);
+ CLOCK_EnableClock(kCLOCK_GateGPIO1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2))
+ RESET_ReleasePeripheralReset(kGPIO2_RST_SHIFT_RSTn);
+ CLOCK_EnableClock(kCLOCK_GateGPIO2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3))
+ RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
+ CLOCK_EnableClock(kCLOCK_GateGPIO3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4))
+ RESET_ReleasePeripheralReset(kGPIO4_RST_SHIFT_RSTn);
+ CLOCK_EnableClock(kCLOCK_GateGPIO4);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
+ CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+ CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART0);
+ RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1))
+ CLOCK_SetClockDiv(kCLOCK_DivLPUART1, 1u);
+ CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART1);
+ RESET_ReleasePeripheralReset(kLPUART1_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2))
+ CLOCK_SetClockDiv(kCLOCK_DivLPUART2, 1u);
+ CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART2);
+ RESET_ReleasePeripheralReset(kLPUART2_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart3))
+ CLOCK_SetClockDiv(kCLOCK_DivLPUART3, 1u);
+ CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART3);
+ RESET_ReleasePeripheralReset(kLPUART3_RST_SHIFT_RSTn);
+#endif
+
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
+}
diff --git a/boards/nxp/frdm_mcxa344/board.cmake b/boards/nxp/frdm_mcxa344/board.cmake
new file mode 100644
index 0000000..d111b15
--- /dev/null
+++ b/boards/nxp/frdm_mcxa344/board.cmake
@@ -0,0 +1,13 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+board_runner_args(jlink "--device=MCXA344")
+board_runner_args(linkserver "--device=MCXA344:FRDM-MCXA344")
+board_runner_args(pyocd "--target=MCXA344")
+
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/nxp/frdm_mcxa344/board.yml b/boards/nxp/frdm_mcxa344/board.yml
new file mode 100644
index 0000000..20a5876
--- /dev/null
+++ b/boards/nxp/frdm_mcxa344/board.yml
@@ -0,0 +1,6 @@
+board:
+ name: frdm_mcxa344
+ full_name: FRDM-MCXA344
+ vendor: nxp
+ socs:
+ - name: mcxa344
diff --git a/boards/nxp/frdm_mcxa344/doc/frdm_mcxa344.webp b/boards/nxp/frdm_mcxa344/doc/frdm_mcxa344.webp
new file mode 100644
index 0000000..7412adb
--- /dev/null
+++ b/boards/nxp/frdm_mcxa344/doc/frdm_mcxa344.webp
Binary files differ
diff --git a/boards/nxp/frdm_mcxa344/doc/index.rst b/boards/nxp/frdm_mcxa344/doc/index.rst
new file mode 100644
index 0000000..729c69c
--- /dev/null
+++ b/boards/nxp/frdm_mcxa344/doc/index.rst
@@ -0,0 +1,160 @@
+.. zephyr:board:: frdm_mcxa344
+
+Overview
+********
+
+FRDM-MCXA344 is a compact and scalable development board for rapid prototyping of MCX A344
+MCUs. They offer industry standard headers for easy access to the MCUs input/output (I/O),
+integrated open-standard serial interfaces, external flash memory and an onboard MCU-Link
+debugger.
+
+Hardware
+********
+
+- MCX-A344 Arm Cortex-M33 microcontroller running at 180 MHz
+- 256KB dual-bank on chip Flash
+- 64 KB RAM
+- 1x FlexCAN with FD, 1x RGB LED, 3x SW buttons
+- On-board MCU-Link debugger with CMSIS-DAP
+- Arduino Header, SmartDMA/Camera Header, mikroBUS
+
+For more information about the MCX-A344 SoC and FRDM-MCXA344 board, see:
+
+- `MCX-A344 SoC Website`_
+- `FRDM-MCXA344 Website`_
+- `FRDM-MCXA344 User Guide`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+The MCX-A344 SoC has 5 gpio controllers and has pinmux registers which
+can be used to configure the functionality of a pin.
+
++------------+-----------------+----------------------------+
+| Name | Function | Usage |
++============+=================+============================+
+| PIO2_3 | UART | UART RX |
++------------+-----------------+----------------------------+
+| PIO2_2 | UART | UART TX |
++------------+-----------------+----------------------------+
+
+System Clock
+============
+
+The MCX-A344 SoC is configured to use FRO running at 180MHz as a source for
+the system clock.
+
+Serial Port
+===========
+
+The FRDM-MCXA344 SoC has 4 LPUART interfaces for serial communication.
+LPUART 2 is configured as UART for the console.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Configuring a Debug Probe
+=========================
+
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
+
+Using LinkServer
+----------------
+
+Linkserver is the default runner for this board, and supports the factory
+default MCU-Link firmware. Follow the instructions in
+:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
+firmware. This only needs to be done if the default onboard debug circuit
+firmware was changed. To put the board in ``ISP mode`` to program the firmware,
+short jumper JP4.
+
+Using J-Link
+------------
+
+There are two options. The onboard debug circuit can be updated with Segger
+J-Link firmware by following the instructions in
+:ref:`mcu-link-jlink-onboard-debug-probe`.
+To be able to program the firmware, you need to put the board in ``ISP mode``
+by shortening the jumper JP4.
+The second option is to attach a :ref:`jlink-external-debug-probe` to the
+10-pin SWD connector (J11) of the board. Additionally, the jumper JP6 must
+be shorted.
+For both options use the ``-r jlink`` option with west to use the jlink runner.
+
+.. code-block:: console
+
+ west flash -r jlink
+
+Configuring a Console
+=====================
+
+Connect a USB cable from your PC to J13, and use the serial terminal of your choice
+(minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Flashing
+========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: frdm_mcxa344
+ :goals: flash
+
+Open a serial terminal, reset the board (press the RESET button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+ *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
+ Hello World! frdm_mcxa344/mcxa344
+
+Debugging
+=========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+ :zephyr-app: samples/hello_world
+ :board: frdm_mcxa344/mcxa344
+ :goals: debug
+
+Open a serial terminal, step through the application in your debugger, and you
+should see the following message in the terminal:
+
+.. code-block:: console
+
+ *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
+ Hello World! frdm_mcxa344/mcxa344
+
+Troubleshooting
+===============
+
+.. include:: ../../common/segger-ecc-systemview.rst.inc
+
+.. include:: ../../common/board-footer.rst.inc
+
+.. _MCX-A344 SoC Website:
+ https://www.nxp.com/products/MCX-A34X
+
+.. _FRDM-MCXA344 Website:
+ https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA344
+
+.. _FRDM-MCXA344 User Guide:
+ https://www.nxp.com/document/guide/getting-started-with-frdm-mcxa344:GS-FRDM-MCXA344
diff --git a/boards/nxp/frdm_mcxa344/frdm_mcxa344-pinctrl.dtsi b/boards/nxp/frdm_mcxa344/frdm_mcxa344-pinctrl.dtsi
new file mode 100644
index 0000000..0179bb4
--- /dev/null
+++ b/boards/nxp/frdm_mcxa344/frdm_mcxa344-pinctrl.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <nxp/mcx/MCXA344VLL-pinctrl.h>
+
+&pinctrl {
+ pinmux_lpuart2: pinmux_lpuart2 {
+ group0 {
+ pinmux = <LPUART2_RXD_P2_3>,
+ <LPUART2_TXD_P2_2>;
+ drive-strength = "low";
+ slew-rate = "fast";
+ input-enable;
+ };
+ };
+};
diff --git a/boards/nxp/frdm_mcxa344/frdm_mcxa344.dts b/boards/nxp/frdm_mcxa344/frdm_mcxa344.dts
new file mode 100644
index 0000000..8028d7d
--- /dev/null
+++ b/boards/nxp/frdm_mcxa344/frdm_mcxa344.dts
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mcxa344.dtsi>
+#include "frdm_mcxa344-pinctrl.dtsi"
+#include <zephyr/dt-bindings/gpio/arduino-header-r3.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+ model = "NXP FRDM_MCXA344 board";
+ compatible = "nxp,mcxa344", "nxp,mcx";
+
+ aliases{
+ led0 = &red_led;
+ led1 = &green_led;
+ led2 = &blue_led;
+ sw0 = &user_button_2;
+ sw1 = &user_button_3;
+ };
+
+ chosen {
+ zephyr,sram = &sram0;
+ zephyr,flash = &flash;
+ zephyr,flash-controller = &fmu;
+ zephyr,code-partition = &slot0_partition;
+ zephyr,console = &lpuart2;
+ zephyr,shell-uart = &lpuart2;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ red_led: led_0 {
+ gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+ label = "Red LED";
+ };
+
+ green_led: led_1 {
+ gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+ label = "Green LED";
+ };
+
+ blue_led: led_2 {
+ gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
+ label = "Blue LED";
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ user_button_2: button_2 {
+ label = "User SW2";
+ gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ zephyr,code = <INPUT_KEY_0>;
+ };
+
+ user_button_3: button_3 {
+ label = "User SW3";
+ gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+ zephyr,code = <INPUT_KEY_1>;
+ };
+ };
+
+ arduino_header: arduino-connector {
+ compatible = "arduino-header-r3";
+ #gpio-cells = <2>;
+ gpio-map-mask = <0xffffffff 0xffffffc0>;
+ gpio-map-pass-thru = <0 0x3f>;
+ gpio-map = <ARDUINO_HEADER_R3_A0 0 &gpio1 14 0>,
+ <ARDUINO_HEADER_R3_A1 0 &gpio2 5 0>,
+ <ARDUINO_HEADER_R3_A2 0 &gpio2 7 0>,
+ <ARDUINO_HEADER_R3_A3 0 &gpio3 30 0>,
+ <ARDUINO_HEADER_R3_A4 0 &gpio1 0 0>,
+ <ARDUINO_HEADER_R3_A5 0 &gpio1 1 0>,
+ <ARDUINO_HEADER_R3_D0 0 &gpio2 3 0>,
+ <ARDUINO_HEADER_R3_D1 0 &gpio2 2 0>,
+ <ARDUINO_HEADER_R3_D2 0 &gpio3 12 0>,
+ <ARDUINO_HEADER_R3_D3 0 &gpio3 14 0>,
+ <ARDUINO_HEADER_R3_D4 0 &gpio1 15 0>,
+ <ARDUINO_HEADER_R3_D5 0 &gpio3 1 0>,
+ <ARDUINO_HEADER_R3_D6 0 &gpio3 17 0>,
+ <ARDUINO_HEADER_R3_D7 0 &gpio3 22 0>,
+ <ARDUINO_HEADER_R3_D8 0 &gpio4 3 0>,
+ <ARDUINO_HEADER_R3_D9 0 &gpio3 13 0>,
+ <ARDUINO_HEADER_R3_D10 0 &gpio3 11 0>,
+ <ARDUINO_HEADER_R3_D11 0 &gpio3 8 0>,
+ <ARDUINO_HEADER_R3_D12 0 &gpio3 9 0>,
+ <ARDUINO_HEADER_R3_D13 0 &gpio3 10 0>,
+ <ARDUINO_HEADER_R3_D14 0 &gpio1 8 0>,
+ <ARDUINO_HEADER_R3_D15 0 &gpio1 9 0>;
+ };
+};
+
+&cpu0 {
+ clock-frequency = <180000000>;
+};
+
+&edma0 {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&lpuart2 {
+ status = "okay";
+ current-speed = <115200>;
+ pinctrl-0 = <&pinmux_lpuart2>;
+ pinctrl-names = "default";
+};
+
+&flash {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot_partition: partition@0 {
+ label = "mcuboot";
+ reg = <0x00000000 DT_SIZE_K(16)>;
+ read-only;
+ };
+
+ slot0_partition: partition@4000 {
+ label = "image-0";
+ reg = <0x00004000 DT_SIZE_K(100)>;
+ };
+
+ slot1_partition: partition@1D000 {
+ label = "image-1";
+ reg = <0x0001D000 DT_SIZE_K(100)>;
+ };
+
+ storage_partition: partition@36000 {
+ label = "storage";
+ reg = <0x00036000 DT_SIZE_K(28)>;
+ };
+ };
+};
diff --git a/boards/nxp/frdm_mcxa344/frdm_mcxa344.yaml b/boards/nxp/frdm_mcxa344/frdm_mcxa344.yaml
new file mode 100644
index 0000000..5adc5c8
--- /dev/null
+++ b/boards/nxp/frdm_mcxa344/frdm_mcxa344.yaml
@@ -0,0 +1,21 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: frdm_mcxa344
+name: NXP FRDM MCXA344
+type: mcu
+arch: arm
+ram: 48
+flash: 244
+toolchain:
+ - zephyr
+ - gnuarmemb
+supported:
+ - arduino_gpio
+ - flash
+ - gpio
+ - uart
+vendor: nxp
diff --git a/boards/nxp/frdm_mcxa344/frdm_mcxa344_defconfig b/boards/nxp/frdm_mcxa344/frdm_mcxa344_defconfig
new file mode 100644
index 0000000..e006f65
--- /dev/null
+++ b/boards/nxp/frdm_mcxa344/frdm_mcxa344_defconfig
@@ -0,0 +1,12 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y
+CONFIG_LPADC_DO_OFFSET_CALIBRATION=y
