dts: arm: st: stm32l0: remove U suffix from "resets" in DTSI
STM32 reset controller position argument provided to STM32_RESET()
macro sometime uses an unnecessary U suffix. Remove these useless
suffixes for this series for consistency among STM32 SoCs DTSI files.
No functional change.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
diff --git a/dts/arm/st/l0/stm32l0.dtsi b/dts/arm/st/l0/stm32l0.dtsi
index 684e771..1dbd96f 100644
--- a/dts/arm/st/l0/stm32l0.dtsi
+++ b/dts/arm/st/l0/stm32l0.dtsi
@@ -218,7 +218,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 17)>;
- resets = <&rctl STM32_RESET(APB1, 17U)>;
+ resets = <&rctl STM32_RESET(APB1, 17)>;
interrupts = <28 0>;
status = "disabled";
};
@@ -227,7 +227,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 18)>;
- resets = <&rctl STM32_RESET(APB1, 18U)>;
+ resets = <&rctl STM32_RESET(APB1, 18)>;
interrupts = <29 0>;
status = "disabled";
};
@@ -259,7 +259,7 @@
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 0)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 0U)>;
+ resets = <&rctl STM32_RESET(APB1, 0)>;
interrupts = <15 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -288,7 +288,7 @@
reg = <0x40010800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 2)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 2U)>;
+ resets = <&rctl STM32_RESET(APB2, 2)>;
interrupts = <20 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/l0/stm32l010Xb.dtsi b/dts/arm/st/l0/stm32l010Xb.dtsi
index 79e5f8a..16911c6 100644
--- a/dts/arm/st/l0/stm32l010Xb.dtsi
+++ b/dts/arm/st/l0/stm32l010Xb.dtsi
@@ -28,7 +28,7 @@
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 5)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 5U)>;
+ resets = <&rctl STM32_RESET(APB2, 5)>;
interrupts = <22 0>;
interrupt-names = "global";
status = "disabled";
diff --git a/dts/arm/st/l0/stm32l031.dtsi b/dts/arm/st/l0/stm32l031.dtsi
index dfe5582..67f26ef 100644
--- a/dts/arm/st/l0/stm32l031.dtsi
+++ b/dts/arm/st/l0/stm32l031.dtsi
@@ -14,7 +14,7 @@
compatible = "st,stm32-timers";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 5)>;
- resets = <&rctl STM32_RESET(APB2, 5U)>;
+ resets = <&rctl STM32_RESET(APB2, 5)>;
interrupts = <22 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/l0/stm32l051.dtsi b/dts/arm/st/l0/stm32l051.dtsi
index 31ba235..761456a 100644
--- a/dts/arm/st/l0/stm32l051.dtsi
+++ b/dts/arm/st/l0/stm32l051.dtsi
@@ -36,7 +36,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
- resets = <&rctl STM32_RESET(APB2, 14U)>;
+ resets = <&rctl STM32_RESET(APB2, 14)>;
interrupts = <27 0>;
status = "disabled";
};
@@ -46,7 +46,7 @@
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 5)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 5U)>;
+ resets = <&rctl STM32_RESET(APB2, 5)>;
interrupts = <22 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -64,7 +64,7 @@
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 4)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 4U)>;
+ resets = <&rctl STM32_RESET(APB1, 4)>;
interrupts = <17 0>;
interrupt-names = "global";
st,prescaler = <0>;
diff --git a/dts/arm/st/l0/stm32l071.dtsi b/dts/arm/st/l0/stm32l071.dtsi
index 8150739..ba98e1c 100644
--- a/dts/arm/st/l0/stm32l071.dtsi
+++ b/dts/arm/st/l0/stm32l071.dtsi
@@ -59,7 +59,7 @@
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 1)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 1U)>;
+ resets = <&rctl STM32_RESET(APB1, 1)>;
interrupts = <16 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -88,7 +88,7 @@
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 4)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 4U)>;
+ resets = <&rctl STM32_RESET(APB1, 4)>;
interrupts = <17 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -105,7 +105,7 @@
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 5)>,
<&rcc STM32_SRC_TIMPCLK1 NO_SEL>;
- resets = <&rctl STM32_RESET(APB1, 5U)>;
+ resets = <&rctl STM32_RESET(APB1, 5)>;
interrupts = <18 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -122,7 +122,7 @@
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 5)>,
<&rcc STM32_SRC_TIMPCLK2 NO_SEL>;
- resets = <&rctl STM32_RESET(APB2, 5U)>;
+ resets = <&rctl STM32_RESET(APB2, 5)>;
interrupts = <22 0>;
interrupt-names = "global";
st,prescaler = <0>;
@@ -144,7 +144,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK(APB2, 14)>;
- resets = <&rctl STM32_RESET(APB2, 14U)>;
+ resets = <&rctl STM32_RESET(APB2, 14)>;
interrupts = <27 0>;
status = "disabled";
};
@@ -153,7 +153,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 19)>;
- resets = <&rctl STM32_RESET(APB1, 19U)>;
+ resets = <&rctl STM32_RESET(APB1, 19)>;
interrupts = <14 0>;
status = "disabled";
};
@@ -162,7 +162,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK(APB1, 20)>;
- resets = <&rctl STM32_RESET(APB1, 20U)>;
+ resets = <&rctl STM32_RESET(APB1, 20)>;
interrupts = <14 0>;
status = "disabled";
};
