soc: microchip: mec172x: Add CPU barriers during low power entry/exit
Follow ARM architecture recommendations:
* Use Data Synchronization Barrier (DSB) instruction before WFI,
to ensure that pending memory transactions complete before
changing state.
* To guarantee pend interrupts are recognized before subsequent
operation, use ISB after CPSIE (__irq_enable)
This prevents sporadicy delayed ISRs due to continous MEC172x
entering/exiting deep sleep.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
1 file changed
